atw.c revision 1.169
1 /* $NetBSD: atw.c,v 1.169 2019/11/10 21:16:35 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.169 2019/11/10 21:16:35 chs Exp $"); 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/kauth.h> 51 #include <sys/time.h> 52 #include <sys/proc.h> 53 #include <sys/atomic.h> 54 #include <lib/libkern/libkern.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <net/bpf.h> 68 69 #include <sys/bus.h> 70 #include <sys/intr.h> 71 72 #include <dev/ic/atwreg.h> 73 #include <dev/ic/rf3000reg.h> 74 #include <dev/ic/si4136reg.h> 75 #include <dev/ic/atwvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* XXX TBD open questions 79 * 80 * 81 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 82 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 83 * handle this for me? 84 * 85 */ 86 /* device attachment 87 * 88 * print TOFS[012] 89 * 90 * device initialization 91 * 92 * clear ATW_FRCTL_MAXPSP to disable max power saving 93 * set ATW_TXBR_ALCUPDATE to enable ALC 94 * set TOFS[012]? (hope not) 95 * disable rx/tx 96 * set ATW_PAR_SWR (software reset) 97 * wait for ATW_PAR_SWR clear 98 * disable interrupts 99 * ack status register 100 * enable interrupts 101 * 102 * rx/tx initialization 103 * 104 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 105 * allocate and init descriptor rings 106 * write ATW_PAR_DSL (descriptor skip length) 107 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 108 * write ATW_NAR_SQ for one/both transmit descriptor rings 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * 112 * rx/tx end 113 * 114 * stop DMA 115 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * flush tx w/ ATW_NAR_HF 117 * 118 * scan 119 * 120 * initialize rx/tx 121 * 122 * BSS join: (re)association response 123 * 124 * set ATW_FRCTL_AID 125 * 126 * optimizations ??? 127 * 128 */ 129 130 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 131 132 int atw_pseudo_milli = 1; 133 int atw_magic_delay1 = 100 * 1000; 134 int atw_magic_delay2 = 100 * 1000; 135 /* more magic multi-millisecond delays (units: microseconds) */ 136 int atw_nar_delay = 20 * 1000; 137 int atw_magic_delay4 = 10 * 1000; 138 int atw_rf_delay1 = 10 * 1000; 139 int atw_rf_delay2 = 5 * 1000; 140 int atw_plcphd_delay = 2 * 1000; 141 int atw_bbp_io_enable_delay = 20 * 1000; 142 int atw_bbp_io_disable_delay = 2 * 1000; 143 int atw_writewep_delay = 1000; 144 int atw_beacon_len_adjust = 4; 145 int atw_dwelltime = 200; 146 int atw_xindiv2 = 0; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 159 static void atw_print_regs(struct atw_softc *, const char *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static void atw_rf3000_print(struct atw_softc *); 164 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static void atw_si4126_print(struct atw_softc *); 169 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 170 # endif /* ATW_SYNDEBUG */ 171 #define __atwdebugused /* empty */ 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #define __atwdebugused __unused 180 #endif 181 182 /* ifnet methods */ 183 int atw_init(struct ifnet *); 184 int atw_ioctl(struct ifnet *, u_long, void *); 185 void atw_start(struct ifnet *); 186 void atw_stop(struct ifnet *, int); 187 void atw_watchdog(struct ifnet *); 188 189 /* Device attachment */ 190 void atw_attach(struct atw_softc *); 191 int atw_detach(struct atw_softc *); 192 static void atw_evcnt_attach(struct atw_softc *); 193 static void atw_evcnt_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 int atw_add_rxbuf(struct atw_softc *, int); 197 void atw_idle(struct atw_softc *, uint32_t); 198 void atw_rxdrain(struct atw_softc *); 199 void atw_txdrain(struct atw_softc *); 200 201 /* Device (de)activation and power state */ 202 void atw_reset(struct atw_softc *); 203 204 /* Interrupt handlers */ 205 void atw_softintr(void *); 206 void atw_linkintr(struct atw_softc *, uint32_t); 207 void atw_rxintr(struct atw_softc *); 208 void atw_txintr(struct atw_softc *, uint32_t); 209 210 /* 802.11 state machine */ 211 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 212 static void atw_next_scan(void *); 213 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 214 struct ieee80211_node *, int, int, uint32_t); 215 static int atw_tune(struct atw_softc *); 216 217 /* Device initialization */ 218 static void atw_bbp_io_init(struct atw_softc *); 219 static void atw_cfp_init(struct atw_softc *); 220 static void atw_cmdr_init(struct atw_softc *); 221 static void atw_ifs_init(struct atw_softc *); 222 static void atw_nar_init(struct atw_softc *); 223 static void atw_response_times_init(struct atw_softc *); 224 static void atw_rf_reset(struct atw_softc *); 225 static void atw_test1_init(struct atw_softc *); 226 static void atw_tofs0_init(struct atw_softc *); 227 static void atw_tofs2_init(struct atw_softc *); 228 static void atw_txlmt_init(struct atw_softc *); 229 static void atw_wcsr_init(struct atw_softc *); 230 231 /* Key management */ 232 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 233 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 234 const uint8_t[IEEE80211_ADDR_LEN]); 235 static void atw_key_update_begin(struct ieee80211com *); 236 static void atw_key_update_end(struct ieee80211com *); 237 238 /* RAM/ROM utilities */ 239 static void atw_clear_sram(struct atw_softc *); 240 static void atw_write_sram(struct atw_softc *, u_int, uint8_t *, u_int); 241 static int atw_read_srom(struct atw_softc *); 242 243 /* BSS setup */ 244 static void atw_predict_beacon(struct atw_softc *); 245 static void atw_start_beacon(struct atw_softc *, int); 246 static void atw_write_bssid(struct atw_softc *); 247 static void atw_write_ssid(struct atw_softc *); 248 static void atw_write_sup_rates(struct atw_softc *); 249 static void atw_write_wep(struct atw_softc *); 250 251 /* Media */ 252 static int atw_media_change(struct ifnet *); 253 254 static void atw_filter_setup(struct atw_softc *); 255 256 /* 802.11 utilities */ 257 static uint64_t atw_get_tsft(struct atw_softc *); 258 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 259 uint32_t); 260 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 261 static void atw_node_free(struct ieee80211_node *); 262 263 /* 264 * Tuner/transceiver/modem 265 */ 266 static void atw_bbp_io_enable(struct atw_softc *, int); 267 268 /* RFMD RF3000 Baseband Processor */ 269 static int atw_rf3000_init(struct atw_softc *); 270 static int atw_rf3000_tune(struct atw_softc *, u_int); 271 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 272 273 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 274 static void atw_si4126_tune(struct atw_softc *, u_int); 275 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 276 277 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 278 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 279 280 const char *atw_tx_state[] = { 281 "STOPPED", 282 "RUNNING - read descriptor", 283 "RUNNING - transmitting", 284 "RUNNING - filling fifo", /* XXX */ 285 "SUSPENDED", 286 "RUNNING -- write descriptor", 287 "RUNNING -- write last descriptor", 288 "RUNNING - fifo full" 289 }; 290 291 const char *atw_rx_state[] = { 292 "STOPPED", 293 "RUNNING - read descriptor", 294 "RUNNING - check this packet, pre-fetch next", 295 "RUNNING - wait for reception", 296 "SUSPENDED", 297 "RUNNING - write descriptor", 298 "RUNNING - flush fifo", 299 "RUNNING - fifo drain" 300 }; 301 302 static inline int 303 is_running(struct ifnet *ifp) 304 { 305 return (ifp->if_flags & (IFF_RUNNING | IFF_UP)) 306 == (IFF_RUNNING | IFF_UP); 307 } 308 309 int 310 atw_activate(device_t self, enum devact act) 311 { 312 struct atw_softc *sc = device_private(self); 313 314 switch (act) { 315 case DVACT_DEACTIVATE: 316 if_deactivate(&sc->sc_if); 317 return 0; 318 default: 319 return EOPNOTSUPP; 320 } 321 } 322 323 bool 324 atw_suspend(device_t self, const pmf_qual_t *qual) 325 { 326 struct atw_softc *sc = device_private(self); 327 328 atw_rxdrain(sc); 329 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 330 331 return true; 332 } 333 334 /* Returns -1 on failure. */ 335 static int 336 atw_read_srom(struct atw_softc *sc) 337 { 338 struct seeprom_descriptor sd; 339 uint32_t test0, fail_bits; 340 341 (void)memset(&sd, 0, sizeof(sd)); 342 343 test0 = ATW_READ(sc, ATW_TEST0); 344 345 switch (sc->sc_rev) { 346 case ATW_REVISION_BA: 347 case ATW_REVISION_CA: 348 fail_bits = ATW_TEST0_EPNE; 349 break; 350 default: 351 fail_bits = ATW_TEST0_EPNE | ATW_TEST0_EPSNM; 352 break; 353 } 354 if ((test0 & fail_bits) != 0) { 355 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 356 return -1; 357 } 358 359 switch (test0 & ATW_TEST0_EPTYP_MASK) { 360 case ATW_TEST0_EPTYP_93c66: 361 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 362 sc->sc_sromsz = 512; 363 sd.sd_chip = C56_66; 364 break; 365 case ATW_TEST0_EPTYP_93c46: 366 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 367 sc->sc_sromsz = 128; 368 sd.sd_chip = C46; 369 break; 370 default: 371 printf("%s: unknown SROM type %" __PRIuBITS "\n", 372 device_xname(sc->sc_dev), 373 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 374 return -1; 375 } 376 377 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_WAITOK | M_ZERO); 378 379 /* ADM8211 has a single 32-bit register for controlling the 380 * 93cx6 SROM. Bit SRS enables the serial port. There is no 381 * "ready" bit. The ADM8211 input/output sense is the reverse 382 * of read_seeprom's. 383 */ 384 sd.sd_tag = sc->sc_st; 385 sd.sd_bsh = sc->sc_sh; 386 sd.sd_regsize = 4; 387 sd.sd_control_offset = ATW_SPR; 388 sd.sd_status_offset = ATW_SPR; 389 sd.sd_dataout_offset = ATW_SPR; 390 sd.sd_CK = ATW_SPR_SCLK; 391 sd.sd_CS = ATW_SPR_SCS; 392 sd.sd_DI = ATW_SPR_SDO; 393 sd.sd_DO = ATW_SPR_SDI; 394 sd.sd_MS = ATW_SPR_SRS; 395 sd.sd_RDY = 0; 396 397 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 398 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 399 free(sc->sc_srom, M_DEVBUF); 400 return -1; 401 } 402 #ifdef ATW_DEBUG 403 { 404 int i; 405 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 406 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 407 if (((i % 8) == 0) && (i != 0)) { 408 ATW_DPRINTF(("\n\t")); 409 } 410 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 411 } 412 ATW_DPRINTF(("\n")); 413 } 414 #endif /* ATW_DEBUG */ 415 return 0; 416 } 417 418 #ifdef ATW_DEBUG 419 static void 420 atw_print_regs(struct atw_softc *sc, const char *where) 421 { 422 #define PRINTREG(sc, reg) \ 423 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 424 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 425 426 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 427 428 PRINTREG(sc, ATW_PAR); 429 PRINTREG(sc, ATW_FRCTL); 430 PRINTREG(sc, ATW_TDR); 431 PRINTREG(sc, ATW_WTDP); 432 PRINTREG(sc, ATW_RDR); 433 PRINTREG(sc, ATW_WRDP); 434 PRINTREG(sc, ATW_RDB); 435 PRINTREG(sc, ATW_CSR3A); 436 PRINTREG(sc, ATW_TDBD); 437 PRINTREG(sc, ATW_TDBP); 438 PRINTREG(sc, ATW_STSR); 439 PRINTREG(sc, ATW_CSR5A); 440 PRINTREG(sc, ATW_NAR); 441 PRINTREG(sc, ATW_CSR6A); 442 PRINTREG(sc, ATW_IER); 443 PRINTREG(sc, ATW_CSR7A); 444 PRINTREG(sc, ATW_LPC); 445 PRINTREG(sc, ATW_TEST1); 446 PRINTREG(sc, ATW_SPR); 447 PRINTREG(sc, ATW_TEST0); 448 PRINTREG(sc, ATW_WCSR); 449 PRINTREG(sc, ATW_WPDR); 450 PRINTREG(sc, ATW_GPTMR); 451 PRINTREG(sc, ATW_GPIO); 452 PRINTREG(sc, ATW_BBPCTL); 453 PRINTREG(sc, ATW_SYNCTL); 454 PRINTREG(sc, ATW_PLCPHD); 455 PRINTREG(sc, ATW_MMIWADDR); 456 PRINTREG(sc, ATW_MMIRADDR1); 457 PRINTREG(sc, ATW_MMIRADDR2); 458 PRINTREG(sc, ATW_TXBR); 459 PRINTREG(sc, ATW_CSR15A); 460 PRINTREG(sc, ATW_ALCSTAT); 461 PRINTREG(sc, ATW_TOFS2); 462 PRINTREG(sc, ATW_CMDR); 463 PRINTREG(sc, ATW_PCIC); 464 PRINTREG(sc, ATW_PMCSR); 465 PRINTREG(sc, ATW_PAR0); 466 PRINTREG(sc, ATW_PAR1); 467 PRINTREG(sc, ATW_MAR0); 468 PRINTREG(sc, ATW_MAR1); 469 PRINTREG(sc, ATW_ATIMDA0); 470 PRINTREG(sc, ATW_ABDA1); 471 PRINTREG(sc, ATW_BSSID0); 472 PRINTREG(sc, ATW_TXLMT); 473 PRINTREG(sc, ATW_MIBCNT); 474 PRINTREG(sc, ATW_BCNT); 475 PRINTREG(sc, ATW_TSFTH); 476 PRINTREG(sc, ATW_TSC); 477 PRINTREG(sc, ATW_SYNRF); 478 PRINTREG(sc, ATW_BPLI); 479 PRINTREG(sc, ATW_CAP0); 480 PRINTREG(sc, ATW_CAP1); 481 PRINTREG(sc, ATW_RMD); 482 PRINTREG(sc, ATW_CFPP); 483 PRINTREG(sc, ATW_TOFS0); 484 PRINTREG(sc, ATW_TOFS1); 485 PRINTREG(sc, ATW_IFST); 486 PRINTREG(sc, ATW_RSPT); 487 PRINTREG(sc, ATW_TSFTL); 488 PRINTREG(sc, ATW_WEPCTL); 489 PRINTREG(sc, ATW_WESK); 490 PRINTREG(sc, ATW_WEPCNT); 491 PRINTREG(sc, ATW_MACTEST); 492 PRINTREG(sc, ATW_FER); 493 PRINTREG(sc, ATW_FEMR); 494 PRINTREG(sc, ATW_FPSR); 495 PRINTREG(sc, ATW_FFER); 496 #undef PRINTREG 497 } 498 #endif /* ATW_DEBUG */ 499 500 /* 501 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 502 */ 503 void 504 atw_attach(struct atw_softc *sc) 505 { 506 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 507 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 508 }; 509 struct ieee80211com *ic = &sc->sc_ic; 510 struct ifnet *ifp = &sc->sc_if; 511 int country_code, error, i, srom_major; 512 uint32_t reg; 513 static const char *type_strings[] = {"Intersil (not supported)", 514 "RFMD", "Marvel (not supported)"}; 515 516 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 517 518 sc->sc_soft_ih = softint_establish(SOFTINT_NET, atw_softintr, sc); 519 if (sc->sc_soft_ih == NULL) { 520 aprint_error_dev(sc->sc_dev, "unable to establish softint\n"); 521 goto fail_0; 522 } 523 524 sc->sc_txth = atw_txthresh_tab_lo; 525 526 SIMPLEQ_INIT(&sc->sc_txfreeq); 527 SIMPLEQ_INIT(&sc->sc_txdirtyq); 528 529 #ifdef ATW_DEBUG 530 atw_print_regs(sc, "atw_attach"); 531 #endif /* ATW_DEBUG */ 532 533 /* 534 * Allocate the control data structures, and create and load the 535 * DMA map for it. 536 */ 537 if ((error = bus_dmamem_alloc(sc->sc_dmat, 538 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 539 1, &sc->sc_cdnseg, 0)) != 0) { 540 aprint_error_dev(sc->sc_dev, 541 "unable to allocate control data, error = %d\n", 542 error); 543 goto fail_0; 544 } 545 546 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 547 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 548 BUS_DMA_COHERENT)) != 0) { 549 aprint_error_dev(sc->sc_dev, 550 "unable to map control data, error = %d\n", 551 error); 552 goto fail_1; 553 } 554 555 if ((error = bus_dmamap_create(sc->sc_dmat, 556 sizeof(struct atw_control_data), 1, 557 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 558 aprint_error_dev(sc->sc_dev, 559 "unable to create control data DMA map, error = %d\n", 560 error); 561 goto fail_2; 562 } 563 564 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 565 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 566 0)) != 0) { 567 aprint_error_dev(sc->sc_dev, 568 "unable to load control data DMA map, error = %d\n", error); 569 goto fail_3; 570 } 571 572 /* 573 * Create the transmit buffer DMA maps. 574 */ 575 sc->sc_ntxsegs = ATW_NTXSEGS; 576 for (i = 0; i < ATW_TXQUEUELEN; i++) { 577 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 578 sc->sc_ntxsegs, MCLBYTES, 0, 0, 579 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 580 aprint_error_dev(sc->sc_dev, 581 "unable to create tx DMA map %d, error = %d\n", i, 582 error); 583 goto fail_4; 584 } 585 } 586 587 /* 588 * Create the receive buffer DMA maps. 589 */ 590 for (i = 0; i < ATW_NRXDESC; i++) { 591 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 592 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 593 aprint_error_dev(sc->sc_dev, 594 "unable to create rx DMA map %d, error = %d\n", i, 595 error); 596 goto fail_5; 597 } 598 } 599 for (i = 0; i < ATW_NRXDESC; i++) { 600 sc->sc_rxsoft[i].rxs_mbuf = NULL; 601 } 602 603 switch (sc->sc_rev) { 604 case ATW_REVISION_AB: 605 case ATW_REVISION_AF: 606 sc->sc_sramlen = ATW_SRAM_A_SIZE; 607 break; 608 case ATW_REVISION_BA: 609 case ATW_REVISION_CA: 610 sc->sc_sramlen = ATW_SRAM_B_SIZE; 611 break; 612 } 613 614 /* Reset the chip to a known state. */ 615 atw_reset(sc); 616 617 if (atw_read_srom(sc) == -1) 618 goto fail_5; 619 620 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 621 ATW_SR_RFTYPE_MASK); 622 623 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 624 ATW_SR_BBPTYPE_MASK); 625 626 if (sc->sc_rftype >= __arraycount(type_strings)) { 627 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 628 goto fail_5; 629 } 630 if (sc->sc_bbptype >= __arraycount(type_strings)) { 631 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 632 goto fail_5; 633 } 634 635 aprint_normal_dev(sc->sc_dev, "%s RF, %s BBP", 636 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 637 638 /* XXX There exists a Linux driver which seems to use RFType = 0 for 639 * MARVEL. My bug, or theirs? 640 */ 641 642 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 643 644 switch (sc->sc_rftype) { 645 case ATW_RFTYPE_INTERSIL: 646 reg |= ATW_SYNCTL_CS1; 647 break; 648 case ATW_RFTYPE_RFMD: 649 reg |= ATW_SYNCTL_CS0; 650 break; 651 case ATW_RFTYPE_MARVEL: 652 break; 653 } 654 655 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 656 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 657 658 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 659 660 switch (sc->sc_bbptype) { 661 case ATW_BBPTYPE_INTERSIL: 662 reg |= ATW_BBPCTL_TWI; 663 break; 664 case ATW_BBPTYPE_RFMD: 665 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 666 ATW_BBPCTL_CCA_ACTLO; 667 break; 668 case ATW_BBPTYPE_MARVEL: 669 break; 670 case ATW_C_BBPTYPE_RFMD: 671 aprint_error_dev(sc->sc_dev, 672 "ADM8211C MAC/RFMD BBP not supported yet.\n"); 673 break; 674 } 675 676 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 677 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 678 679 /* 680 * From this point forward, the attachment cannot fail. A failure 681 * before this point releases all resources that may have been 682 * allocated. 683 */ 684 sc->sc_flags |= ATWF_ATTACHED; 685 686 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 687 htole16(sc->sc_srom[ATW_SR_MAC00]), 688 htole16(sc->sc_srom[ATW_SR_MAC01]), 689 htole16(sc->sc_srom[ATW_SR_MAC10]))); 690 691 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 692 ATW_SR_MAJOR_MASK); 693 694 if (srom_major < 2) 695 sc->sc_rf3000_options1 = 0; 696 else if (sc->sc_rev == ATW_REVISION_BA) { 697 sc->sc_rf3000_options1 = 698 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 699 ATW_SR_CR28_MASK); 700 } else 701 sc->sc_rf3000_options1 = 0; 702 703 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 704 ATW_SR_CR29_MASK); 705 706 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 707 ATW_SR_CTRY_MASK); 708 709 #define ADD_CHANNEL(_ic, _chan) do { \ 710 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 711 _ic->ic_channels[_chan].ic_freq = \ 712 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 713 } while (0) 714 715 /* Find available channels */ 716 switch (country_code) { 717 case COUNTRY_MMK2: /* 1-14 */ 718 ADD_CHANNEL(ic, 14); 719 /*FALLTHROUGH*/ 720 case COUNTRY_ETSI: /* 1-13 */ 721 for (i = 1; i <= 13; i++) 722 ADD_CHANNEL(ic, i); 723 break; 724 case COUNTRY_FCC: /* 1-11 */ 725 case COUNTRY_IC: /* 1-11 */ 726 for (i = 1; i <= 11; i++) 727 ADD_CHANNEL(ic, i); 728 break; 729 case COUNTRY_MMK: /* 14 */ 730 ADD_CHANNEL(ic, 14); 731 break; 732 case COUNTRY_FRANCE: /* 10-13 */ 733 for (i = 10; i <= 13; i++) 734 ADD_CHANNEL(ic, i); 735 break; 736 default: /* assume channels 10-11 */ 737 case COUNTRY_SPAIN: /* 10-11 */ 738 for (i = 10; i <= 11; i++) 739 ADD_CHANNEL(ic, i); 740 break; 741 } 742 743 /* Read the MAC address. */ 744 reg = ATW_READ(sc, ATW_PAR0); 745 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 746 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 747 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 748 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 749 reg = ATW_READ(sc, ATW_PAR1); 750 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 751 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 752 753 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 754 aprint_error_dev(sc->sc_dev, 755 "could not get mac address, attach failed\n"); 756 goto fail_5; 757 } 758 759 aprint_normal(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 760 761 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 762 ifp->if_softc = sc; 763 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 764 ifp->if_ioctl = atw_ioctl; 765 ifp->if_start = atw_start; 766 ifp->if_watchdog = atw_watchdog; 767 ifp->if_init = atw_init; 768 ifp->if_stop = atw_stop; 769 IFQ_SET_READY(&ifp->if_snd); 770 771 ic->ic_ifp = ifp; 772 ic->ic_phytype = IEEE80211_T_DS; 773 ic->ic_opmode = IEEE80211_M_STA; 774 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 775 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 776 777 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 778 779 /* 780 * Call MI attach routines. 781 */ 782 783 error = if_initialize(ifp); 784 if (error != 0) { 785 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 786 error); 787 goto fail_5; 788 } 789 ieee80211_ifattach(ic); 790 /* Use common softint-based if_input */ 791 ifp->if_percpuq = if_percpuq_create(ifp); 792 if_register(ifp); 793 794 atw_evcnt_attach(sc); 795 796 sc->sc_newstate = ic->ic_newstate; 797 ic->ic_newstate = atw_newstate; 798 799 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 800 ic->ic_recv_mgmt = atw_recv_mgmt; 801 802 sc->sc_node_free = ic->ic_node_free; 803 ic->ic_node_free = atw_node_free; 804 805 sc->sc_node_alloc = ic->ic_node_alloc; 806 ic->ic_node_alloc = atw_node_alloc; 807 808 ic->ic_crypto.cs_key_delete = atw_key_delete; 809 ic->ic_crypto.cs_key_set = atw_key_set; 810 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 811 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 812 813 /* possibly we should fill in our own sc_send_prresp, since 814 * the ADM8211 is probably sending probe responses in ad hoc 815 * mode. 816 */ 817 818 /* complete initialization */ 819 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 820 callout_init(&sc->sc_scan_ch, 0); 821 822 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 823 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 824 825 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 826 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 827 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 828 829 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 830 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 831 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 832 833 ieee80211_announce(ic); 834 return; 835 836 /* 837 * Free any resources we've allocated during the failed attach 838 * attempt. Do this in reverse order and fall through. 839 */ 840 fail_5: 841 for (i = 0; i < ATW_NRXDESC; i++) { 842 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 843 continue; 844 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 845 } 846 fail_4: 847 for (i = 0; i < ATW_TXQUEUELEN; i++) { 848 if (sc->sc_txsoft[i].txs_dmamap == NULL) 849 continue; 850 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 851 } 852 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 853 fail_3: 854 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 855 fail_2: 856 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 857 sizeof(struct atw_control_data)); 858 fail_1: 859 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 860 fail_0: 861 if (sc->sc_soft_ih != NULL) { 862 softint_disestablish(sc->sc_soft_ih); 863 sc->sc_soft_ih = NULL; 864 } 865 } 866 867 static struct ieee80211_node * 868 atw_node_alloc(struct ieee80211_node_table *nt) 869 { 870 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 871 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 872 873 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 874 return ni; 875 } 876 877 static void 878 atw_node_free(struct ieee80211_node *ni) 879 { 880 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 881 882 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 883 ether_sprintf(ni->ni_bssid))); 884 (*sc->sc_node_free)(ni); 885 } 886 887 888 static void 889 atw_test1_reset(struct atw_softc *sc) 890 { 891 switch (sc->sc_rev) { 892 case ATW_REVISION_BA: 893 if (1 /* XXX condition on transceiver type */) { 894 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 895 } 896 break; 897 case ATW_REVISION_CA: 898 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 899 break; 900 default: 901 break; 902 } 903 } 904 905 /* 906 * atw_reset: 907 * 908 * Perform a soft reset on the ADM8211. 909 */ 910 void 911 atw_reset(struct atw_softc *sc) 912 { 913 int i; 914 uint32_t lpc __atwdebugused; 915 916 ATW_WRITE(sc, ATW_NAR, 0x0); 917 DELAY(atw_nar_delay); 918 919 /* Reference driver has a cryptic remark indicating that this might 920 * power-on the chip. I know that it turns off power-saving.... 921 */ 922 ATW_WRITE(sc, ATW_FRCTL, 0x0); 923 924 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 925 926 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 927 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 928 break; 929 DELAY(atw_pseudo_milli); 930 } 931 932 /* ... and then pause 100ms longer for good measure. */ 933 DELAY(atw_magic_delay1); 934 935 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 936 937 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 938 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 939 940 /* 941 * Initialize the PCI Access Register. 942 */ 943 sc->sc_busmode = ATW_PAR_PBL_8DW; 944 945 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 946 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 947 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 948 949 atw_test1_reset(sc); 950 951 /* Turn off maximum power saving, etc. */ 952 ATW_WRITE(sc, ATW_FRCTL, 0x0); 953 954 DELAY(atw_magic_delay2); 955 956 /* Recall EEPROM. */ 957 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 958 959 DELAY(atw_magic_delay4); 960 961 lpc = ATW_READ(sc, ATW_LPC); 962 963 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 964 965 /* A reset seems to affect the SRAM contents, so put them into 966 * a known state. 967 */ 968 atw_clear_sram(sc); 969 970 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 971 } 972 973 static void 974 atw_clear_sram(struct atw_softc *sc) 975 { 976 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 977 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 978 /* XXX not for revision 0x20. */ 979 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 980 } 981 982 /* TBD atw_init 983 * 984 * set MAC based on ic->ic_bss->myaddr 985 * write WEP keys 986 * set TX rate 987 */ 988 989 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 990 * without receiving a beacon with the preferred BSSID & SSID. 991 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 992 */ 993 static void 994 atw_wcsr_init(struct atw_softc *sc) 995 { 996 uint32_t wcsr; 997 998 wcsr = ATW_READ(sc, ATW_WCSR); 999 wcsr &= ~ATW_WCSR_BLN_MASK; 1000 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1001 /* We always want to wake up on link loss or TSFT out of range */ 1002 wcsr |= ATW_WCSR_LSOE | ATW_WCSR_TSFTWE; 1003 ATW_WRITE(sc, ATW_WCSR, wcsr); 1004 1005 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1006 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1007 } 1008 1009 /* Turn off power management. Set Rx store-and-forward mode. */ 1010 static void 1011 atw_cmdr_init(struct atw_softc *sc) 1012 { 1013 uint32_t cmdr; 1014 cmdr = ATW_READ(sc, ATW_CMDR); 1015 cmdr &= ~ATW_CMDR_APM; 1016 cmdr |= ATW_CMDR_RTE; 1017 cmdr &= ~ATW_CMDR_DRT_MASK; 1018 cmdr |= ATW_CMDR_DRT_SF; 1019 1020 ATW_WRITE(sc, ATW_CMDR, cmdr); 1021 } 1022 1023 static void 1024 atw_tofs2_init(struct atw_softc *sc) 1025 { 1026 uint32_t tofs2; 1027 /* XXX this magic can probably be figured out from the RFMD docs */ 1028 #ifndef ATW_REFSLAVE 1029 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1030 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1031 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1032 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1033 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1034 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1035 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1036 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1037 #else 1038 /* XXX new magic from reference driver source */ 1039 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1040 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1041 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1042 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1043 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1044 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1045 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1046 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1047 #endif 1048 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1049 } 1050 1051 static void 1052 atw_nar_init(struct atw_softc *sc) 1053 { 1054 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF | ATW_NAR_PB); 1055 } 1056 1057 static void 1058 atw_txlmt_init(struct atw_softc *sc) 1059 { 1060 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1061 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1062 } 1063 1064 static void 1065 atw_test1_init(struct atw_softc *sc) 1066 { 1067 uint32_t test1; 1068 1069 test1 = ATW_READ(sc, ATW_TEST1); 1070 test1 &= ~(ATW_TEST1_DBGREAD_MASK | ATW_TEST1_CONTROL); 1071 /* XXX magic 0x1 */ 1072 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1073 ATW_WRITE(sc, ATW_TEST1, test1); 1074 } 1075 1076 static void 1077 atw_rf_reset(struct atw_softc *sc) 1078 { 1079 /* XXX this resets an Intersil RF front-end? */ 1080 /* TBD condition on Intersil RFType? */ 1081 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1082 DELAY(atw_rf_delay1); 1083 ATW_WRITE(sc, ATW_SYNRF, 0); 1084 DELAY(atw_rf_delay2); 1085 } 1086 1087 /* Set 16 TU max duration for the contention-free period (CFP). */ 1088 static void 1089 atw_cfp_init(struct atw_softc *sc) 1090 { 1091 uint32_t cfpp; 1092 1093 cfpp = ATW_READ(sc, ATW_CFPP); 1094 cfpp &= ~ATW_CFPP_CFPMD; 1095 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1096 ATW_WRITE(sc, ATW_CFPP, cfpp); 1097 } 1098 1099 static void 1100 atw_tofs0_init(struct atw_softc *sc) 1101 { 1102 /* XXX I guess that the Cardbus clock is 22 MHz? 1103 * I am assuming that the role of ATW_TOFS0_USCNT is 1104 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1105 * very clear on this point. It says in the datasheet that it is 1106 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1107 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1108 * these values. These values are also the power-on default. 1109 */ 1110 ATW_WRITE(sc, ATW_TOFS0, 1111 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1112 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1113 } 1114 1115 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1116 static void 1117 atw_ifs_init(struct atw_softc *sc) 1118 { 1119 uint32_t ifst; 1120 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1121 * Go figure. 1122 */ 1123 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1124 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1125 ATW_IFST_SIFS_MASK) | 1126 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1127 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1128 1129 ATW_WRITE(sc, ATW_IFST, ifst); 1130 } 1131 1132 static void 1133 atw_response_times_init(struct atw_softc *sc) 1134 { 1135 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1136 * indicate that the MAC expects at least SIFS + MIRT microseconds 1137 * to pass after it transmits a frame that requires a response; 1138 * it waits at most SIFS + MART microseconds for the response. 1139 * Surely this is not the ACK timeout? 1140 */ 1141 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1142 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1143 } 1144 1145 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1146 * engines read and write baseband registers after Rx and before 1147 * Tx, respectively. 1148 */ 1149 static void 1150 atw_bbp_io_init(struct atw_softc *sc) 1151 { 1152 uint32_t mmiraddr2; 1153 1154 /* XXX The reference driver does this, but is it *really* 1155 * necessary? 1156 */ 1157 switch (sc->sc_rev) { 1158 case ATW_REVISION_AB: 1159 case ATW_REVISION_AF: 1160 mmiraddr2 = 0x0; 1161 break; 1162 default: 1163 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1164 mmiraddr2 &= 1165 ~(ATW_MMIRADDR2_PROREXT | ATW_MMIRADDR2_PRORLEN_MASK); 1166 break; 1167 } 1168 1169 switch (sc->sc_bbptype) { 1170 case ATW_BBPTYPE_INTERSIL: 1171 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1172 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1173 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1174 break; 1175 case ATW_BBPTYPE_MARVEL: 1176 /* TBD find out the Marvel settings. */ 1177 break; 1178 case ATW_BBPTYPE_RFMD: 1179 default: 1180 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1181 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1182 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1183 break; 1184 } 1185 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1186 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1187 } 1188 1189 /* 1190 * atw_init: [ ifnet interface function ] 1191 * 1192 * Initialize the interface. Must be called at splnet(). 1193 */ 1194 int 1195 atw_init(struct ifnet *ifp) 1196 { 1197 struct atw_softc *sc = ifp->if_softc; 1198 struct ieee80211com *ic = &sc->sc_ic; 1199 struct atw_txsoft *txs; 1200 struct atw_rxsoft *rxs; 1201 int i, error = 0; 1202 1203 if (device_is_active(sc->sc_dev)) { 1204 /* 1205 * Cancel any pending I/O. 1206 */ 1207 atw_stop(ifp, 0); 1208 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1209 !device_is_active(sc->sc_dev)) 1210 return 0; 1211 1212 /* 1213 * Reset the chip to a known state. 1214 */ 1215 atw_reset(sc); 1216 1217 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1218 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1219 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1220 1221 atw_wcsr_init(sc); 1222 1223 atw_cmdr_init(sc); 1224 1225 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1226 * 1227 * XXX Set transmit power for ATIM, RTS, Beacon. 1228 */ 1229 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1230 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1231 1232 atw_tofs2_init(sc); 1233 1234 atw_nar_init(sc); 1235 1236 atw_txlmt_init(sc); 1237 1238 atw_test1_init(sc); 1239 1240 atw_rf_reset(sc); 1241 1242 atw_cfp_init(sc); 1243 1244 atw_tofs0_init(sc); 1245 1246 atw_ifs_init(sc); 1247 1248 /* XXX Fall asleep after one second of inactivity. 1249 * XXX A frame may only dribble in for 65536us. 1250 */ 1251 ATW_WRITE(sc, ATW_RMD, 1252 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1253 1254 atw_response_times_init(sc); 1255 1256 atw_bbp_io_init(sc); 1257 1258 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1259 1260 if ((error = atw_rf3000_init(sc)) != 0) 1261 goto out; 1262 1263 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1264 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1265 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1266 1267 /* 1268 * Initialize the transmit descriptor ring. 1269 */ 1270 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1271 for (i = 0; i < ATW_NTXDESC; i++) { 1272 sc->sc_txdescs[i].at_ctl = 0; 1273 /* no transmit chaining */ 1274 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1275 sc->sc_txdescs[i].at_buf2 = 1276 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1277 } 1278 /* use ring mode */ 1279 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1280 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1281 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1282 sc->sc_txfree = ATW_NTXDESC; 1283 sc->sc_txnext = 0; 1284 1285 /* 1286 * Initialize the transmit job descriptors. 1287 */ 1288 SIMPLEQ_INIT(&sc->sc_txfreeq); 1289 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1290 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1291 txs = &sc->sc_txsoft[i]; 1292 txs->txs_mbuf = NULL; 1293 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1294 } 1295 1296 /* 1297 * Initialize the receive descriptor and receive job 1298 * descriptor rings. 1299 */ 1300 for (i = 0; i < ATW_NRXDESC; i++) { 1301 rxs = &sc->sc_rxsoft[i]; 1302 if (rxs->rxs_mbuf == NULL) { 1303 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1304 aprint_error_dev(sc->sc_dev, 1305 "unable to allocate or map rx buffer %d, " 1306 "error = %d\n", i, error); 1307 /* 1308 * XXX Should attempt to run with fewer receive 1309 * XXX buffers instead of just failing. 1310 */ 1311 atw_rxdrain(sc); 1312 goto out; 1313 } 1314 } else 1315 atw_init_rxdesc(sc, i); 1316 } 1317 sc->sc_rxptr = 0; 1318 1319 /* 1320 * Initialize the interrupt mask and enable interrupts. 1321 */ 1322 /* normal interrupts */ 1323 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1324 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1325 1326 /* abnormal interrupts */ 1327 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1328 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1329 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1330 1331 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1332 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1333 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1334 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1335 ATW_INTR_TRT; 1336 1337 sc->sc_linkint_mask &= sc->sc_inten; 1338 sc->sc_rxint_mask &= sc->sc_inten; 1339 sc->sc_txint_mask &= sc->sc_inten; 1340 1341 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1342 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1343 1344 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1345 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1346 1347 /* 1348 * Give the transmit and receive rings to the ADM8211. 1349 */ 1350 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1351 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1352 1353 sc->sc_txthresh = 0; 1354 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1355 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1356 1357 /* common 802.11 configuration */ 1358 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1359 switch (ic->ic_opmode) { 1360 case IEEE80211_M_STA: 1361 break; 1362 case IEEE80211_M_AHDEMO: /* XXX */ 1363 case IEEE80211_M_IBSS: 1364 ic->ic_flags |= IEEE80211_F_IBSSON; 1365 /*FALLTHROUGH*/ 1366 case IEEE80211_M_HOSTAP: /* XXX */ 1367 break; 1368 case IEEE80211_M_MONITOR: /* XXX */ 1369 break; 1370 } 1371 1372 switch (ic->ic_opmode) { 1373 case IEEE80211_M_AHDEMO: 1374 case IEEE80211_M_HOSTAP: 1375 #ifndef IEEE80211_NO_HOSTAP 1376 ic->ic_bss->ni_intval = ic->ic_lintval; 1377 ic->ic_bss->ni_rssi = 0; 1378 ic->ic_bss->ni_rstamp = 0; 1379 #endif /* !IEEE80211_NO_HOSTAP */ 1380 break; 1381 default: /* XXX */ 1382 break; 1383 } 1384 1385 sc->sc_wepctl = 0; 1386 1387 atw_write_ssid(sc); 1388 atw_write_sup_rates(sc); 1389 atw_write_wep(sc); 1390 1391 ic->ic_state = IEEE80211_S_INIT; 1392 1393 /* 1394 * Set the receive filter. This will start the transmit and 1395 * receive processes. 1396 */ 1397 atw_filter_setup(sc); 1398 1399 /* 1400 * Start the receive process. 1401 */ 1402 ATW_WRITE(sc, ATW_RDR, 0x1); 1403 1404 /* 1405 * Note that the interface is now running. 1406 */ 1407 ifp->if_flags |= IFF_RUNNING; 1408 1409 /* send no beacons, yet. */ 1410 atw_start_beacon(sc, 0); 1411 1412 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1413 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1414 else 1415 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1416 out: 1417 if (error) { 1418 ifp->if_flags &= ~IFF_RUNNING; 1419 sc->sc_tx_timer = 0; 1420 ifp->if_timer = 0; 1421 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1422 } 1423 #ifdef ATW_DEBUG 1424 atw_print_regs(sc, "end of init"); 1425 #endif /* ATW_DEBUG */ 1426 1427 return (error); 1428 } 1429 1430 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1431 * 0: MAC control of RF3000/Si4126. 1432 * 1433 * Applies power, or selects RF front-end? Sets reset condition. 1434 * 1435 * TBD support non-RFMD BBP, non-SiLabs synth. 1436 */ 1437 static void 1438 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1439 { 1440 if (enable) { 1441 ATW_WRITE(sc, ATW_SYNRF, 1442 ATW_SYNRF_SELRF | ATW_SYNRF_PE1 | ATW_SYNRF_PHYRST); 1443 DELAY(atw_bbp_io_enable_delay); 1444 } else { 1445 ATW_WRITE(sc, ATW_SYNRF, 0); 1446 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1447 } 1448 } 1449 1450 static int 1451 atw_tune(struct atw_softc *sc) 1452 { 1453 int rc; 1454 u_int chan; 1455 struct ieee80211com *ic = &sc->sc_ic; 1456 1457 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1458 if (chan == IEEE80211_CHAN_ANY) 1459 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1460 1461 if (chan == sc->sc_cur_chan) 1462 return 0; 1463 1464 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1465 sc->sc_cur_chan, chan)); 1466 1467 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 1468 1469 atw_si4126_tune(sc, chan); 1470 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1471 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1472 chan); 1473 1474 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1475 DELAY(atw_nar_delay); 1476 ATW_WRITE(sc, ATW_RDR, 0x1); 1477 1478 if (rc == 0) { 1479 sc->sc_cur_chan = chan; 1480 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1481 htole16(ic->ic_curchan->ic_freq); 1482 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1483 htole16(ic->ic_curchan->ic_flags); 1484 } 1485 1486 return rc; 1487 } 1488 1489 #ifdef ATW_SYNDEBUG 1490 static void 1491 atw_si4126_print(struct atw_softc *sc) 1492 { 1493 struct ifnet *ifp = &sc->sc_if; 1494 u_int addr, val; 1495 1496 val = 0; 1497 1498 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1499 return; 1500 1501 for (addr = 0; addr <= 8; addr++) { 1502 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1503 if (atw_si4126_read(sc, addr, &val) == 0) { 1504 printf("<unknown> (quitting print-out)\n"); 1505 break; 1506 } 1507 printf("%05x\n", val); 1508 } 1509 } 1510 #endif /* ATW_SYNDEBUG */ 1511 1512 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1513 * 1514 * The RF/IF synthesizer produces two reference frequencies for 1515 * the RF2948B transceiver. The first frequency the RF2948B requires 1516 * is two times the so-called "intermediate frequency" (IF). Since 1517 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1518 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1519 * frequency required by the transceiver is the radio frequency 1520 * (RF). This is a superheterodyne transceiver; for f(chan) the 1521 * center frequency of the channel we are tuning, RF = f(chan) - 1522 * IF. 1523 * 1524 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1525 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1526 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1527 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1528 */ 1529 static void 1530 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1531 { 1532 u_int mhz; 1533 u_int R; 1534 uint32_t gpio; 1535 uint16_t gain; 1536 1537 #ifdef ATW_SYNDEBUG 1538 atw_si4126_print(sc); 1539 #endif /* ATW_SYNDEBUG */ 1540 1541 if (chan == 14) 1542 mhz = 2484; 1543 else 1544 mhz = 2412 + 5 * (chan - 1); 1545 1546 /* Tune IF to 748 MHz to suit the IF LO input of the 1547 * RF2494B, which is 2 x IF. No need to set an IF divider 1548 * because an IF in 526 MHz - 952 MHz is allowed. 1549 * 1550 * XIN is 44.000 MHz, so divide it by two to get allowable 1551 * range of 2-25 MHz. SiLabs tells me that this is not 1552 * strictly necessary. 1553 */ 1554 1555 if (atw_xindiv2) 1556 R = 44; 1557 else 1558 R = 88; 1559 1560 /* Power-up RF, IF synthesizers. */ 1561 atw_si4126_write(sc, SI4126_POWER, 1562 SI4126_POWER_PDIB | SI4126_POWER_PDRB); 1563 1564 /* set LPWR, too? */ 1565 atw_si4126_write(sc, SI4126_MAIN, 1566 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1567 1568 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1569 * set KP2 to 1. 1570 * 1571 * REFDIF This is different from the reference driver, which 1572 * always sets SI4126_GAIN to 0. 1573 */ 1574 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1575 1576 atw_si4126_write(sc, SI4126_GAIN, gain); 1577 1578 /* XIN = 44 MHz. 1579 * 1580 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1581 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1582 * 1583 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1584 * so that 1496/88 * 44 MHz = 748 MHz. 1585 */ 1586 atw_si4126_write(sc, SI4126_IFN, 1496); 1587 1588 atw_si4126_write(sc, SI4126_IFR, R); 1589 1590 #ifndef ATW_REFSLAVE 1591 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1592 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1593 * which has no RF1! 1594 */ 1595 atw_si4126_write(sc, SI4126_RF1R, R); 1596 1597 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1598 #endif 1599 1600 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1601 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1602 * Now let's multiply it to mhz. So mhz - IF = N. 1603 */ 1604 atw_si4126_write(sc, SI4126_RF2R, R); 1605 1606 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1607 1608 /* wait 100us from power-up for RF, IF to settle */ 1609 DELAY(100); 1610 1611 gpio = ATW_READ(sc, ATW_GPIO); 1612 gpio &= ~(ATW_GPIO_EN_MASK | ATW_GPIO_O_MASK | ATW_GPIO_I_MASK); 1613 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1614 1615 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1616 /* Set a Prism RF front-end to a special mode for channel 14? 1617 * 1618 * Apparently the SMC2635W needs this, although I don't think 1619 * it has a Prism RF. 1620 */ 1621 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1622 } 1623 ATW_WRITE(sc, ATW_GPIO, gpio); 1624 1625 #ifdef ATW_SYNDEBUG 1626 atw_si4126_print(sc); 1627 #endif /* ATW_SYNDEBUG */ 1628 } 1629 1630 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1631 * diversity. 1632 * 1633 * !!! 1634 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1635 * !!! 1636 */ 1637 static int 1638 atw_rf3000_init(struct atw_softc *sc) 1639 { 1640 int rc = 0; 1641 1642 atw_bbp_io_enable(sc, 1); 1643 1644 /* CCA is acquisition sensitive */ 1645 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1646 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1647 1648 if (rc != 0) 1649 goto out; 1650 1651 /* enable diversity */ 1652 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1653 1654 if (rc != 0) 1655 goto out; 1656 1657 /* sensible setting from a binary-only driver */ 1658 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1659 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1660 1661 if (rc != 0) 1662 goto out; 1663 1664 /* magic from a binary-only driver */ 1665 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1666 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1667 1668 if (rc != 0) 1669 goto out; 1670 1671 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1672 1673 if (rc != 0) 1674 goto out; 1675 1676 /* XXX Reference driver remarks that Abocom sets this to 50. 1677 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1678 * in the "reserved" area of register RF3000_OPTIONS1. 1679 */ 1680 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1681 1682 if (rc != 0) 1683 goto out; 1684 1685 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1686 1687 if (rc != 0) 1688 goto out; 1689 1690 out: 1691 atw_bbp_io_enable(sc, 0); 1692 return rc; 1693 } 1694 1695 #ifdef ATW_BBPDEBUG 1696 static void 1697 atw_rf3000_print(struct atw_softc *sc) 1698 { 1699 struct ifnet *ifp = &sc->sc_if; 1700 u_int addr, val; 1701 1702 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1703 return; 1704 1705 for (addr = 0x01; addr <= 0x15; addr++) { 1706 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1707 if (atw_rf3000_read(sc, addr, &val) != 0) { 1708 printf("<unknown> (quitting print-out)\n"); 1709 break; 1710 } 1711 printf("%08x\n", val); 1712 } 1713 } 1714 #endif /* ATW_BBPDEBUG */ 1715 1716 /* Set the power settings on the BBP for channel `chan'. */ 1717 static int 1718 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1719 { 1720 int rc = 0; 1721 uint32_t reg; 1722 uint16_t txpower, lpf_cutoff, lna_gs_thresh; 1723 1724 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1725 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1726 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1727 1728 /* odd channels: LSB, even channels: MSB */ 1729 if (chan % 2 == 1) { 1730 txpower &= 0xFF; 1731 lpf_cutoff &= 0xFF; 1732 lna_gs_thresh &= 0xFF; 1733 } else { 1734 txpower >>= 8; 1735 lpf_cutoff >>= 8; 1736 lna_gs_thresh >>= 8; 1737 } 1738 1739 #ifdef ATW_BBPDEBUG 1740 atw_rf3000_print(sc); 1741 #endif /* ATW_BBPDEBUG */ 1742 1743 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1744 "lna_gs_thresh %02x\n", 1745 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1746 1747 atw_bbp_io_enable(sc, 1); 1748 1749 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1750 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1751 goto out; 1752 1753 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1754 goto out; 1755 1756 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1757 goto out; 1758 1759 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1760 1761 if (rc != 0) 1762 goto out; 1763 1764 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1765 1766 if (rc != 0) 1767 goto out; 1768 1769 #ifdef ATW_BBPDEBUG 1770 atw_rf3000_print(sc); 1771 #endif /* ATW_BBPDEBUG */ 1772 1773 out: 1774 atw_bbp_io_enable(sc, 0); 1775 1776 /* set beacon, rts, atim transmit power */ 1777 reg = ATW_READ(sc, ATW_PLCPHD); 1778 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1779 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1780 ATW_PLCPHD_SERVICE_MASK); 1781 ATW_WRITE(sc, ATW_PLCPHD, reg); 1782 DELAY(atw_plcphd_delay); 1783 1784 return rc; 1785 } 1786 1787 /* Write a register on the RF3000 baseband processor using the 1788 * registers provided by the ADM8211 for this purpose. 1789 * 1790 * Return 0 on success. 1791 */ 1792 static int 1793 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1794 { 1795 uint32_t reg; 1796 int i; 1797 1798 reg = sc->sc_bbpctl_wr | 1799 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1800 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1801 1802 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1803 ATW_WRITE(sc, ATW_BBPCTL, reg); 1804 DELAY(2 * atw_pseudo_milli); 1805 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1806 break; 1807 } 1808 1809 if (i < 0) { 1810 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1811 return ETIMEDOUT; 1812 } 1813 return 0; 1814 } 1815 1816 /* Read a register on the RF3000 baseband processor using the registers 1817 * the ADM8211 provides for this purpose. 1818 * 1819 * The 7-bit register address is addr. Record the 8-bit data in the register 1820 * in *val. 1821 * 1822 * Return 0 on success. 1823 * 1824 * XXX This does not seem to work. The ADM8211 must require more or 1825 * different magic to read the chip than to write it. Possibly some 1826 * of the magic I have derived from a binary-only driver concerns 1827 * the "chip address" (see the RF3000 manual). 1828 */ 1829 #ifdef ATW_BBPDEBUG 1830 static int 1831 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1832 { 1833 uint32_t reg; 1834 int i; 1835 1836 for (i = 1000; --i >= 0; ) { 1837 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD | ATW_BBPCTL_WR) 1838 == 0) 1839 break; 1840 DELAY(100); 1841 } 1842 1843 if (i < 0) { 1844 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1845 device_xname(sc->sc_dev)); 1846 return ETIMEDOUT; 1847 } 1848 1849 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1850 1851 ATW_WRITE(sc, ATW_BBPCTL, reg); 1852 1853 for (i = 1000; --i >= 0; ) { 1854 DELAY(100); 1855 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1856 break; 1857 } 1858 1859 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1860 1861 if (i < 0) { 1862 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1863 device_xname(sc->sc_dev), reg); 1864 return ETIMEDOUT; 1865 } 1866 if (val != NULL) 1867 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1868 return 0; 1869 } 1870 #endif /* ATW_BBPDEBUG */ 1871 1872 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1873 * provided by the ADM8211 for that purpose. 1874 * 1875 * val is 18 bits of data, and val is the 4-bit address of the register. 1876 * 1877 * Return 0 on success. 1878 */ 1879 static void 1880 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1881 { 1882 uint32_t bits, mask, reg; 1883 const int nbits = 22; 1884 1885 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1886 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1887 1888 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1889 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1890 1891 reg = ATW_SYNRF_SELSYN; 1892 /* reference driver: reset Si4126 serial bus to initial 1893 * conditions? 1894 */ 1895 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1896 ATW_WRITE(sc, ATW_SYNRF, reg); 1897 1898 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1899 if ((bits & mask) != 0) 1900 reg |= ATW_SYNRF_SYNDATA; 1901 else 1902 reg &= ~ATW_SYNRF_SYNDATA; 1903 ATW_WRITE(sc, ATW_SYNRF, reg); 1904 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1905 ATW_WRITE(sc, ATW_SYNRF, reg); 1906 } 1907 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1908 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1909 } 1910 1911 /* Read 18-bit data from the 4-bit address addr in Si4126 1912 * RF synthesizer and write the data to *val. Return 0 on success. 1913 * 1914 * XXX This does not seem to work. The ADM8211 must require more or 1915 * different magic to read the chip than to write it. 1916 */ 1917 #ifdef ATW_SYNDEBUG 1918 static int 1919 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1920 { 1921 uint32_t reg; 1922 int i; 1923 1924 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1925 1926 for (i = 1000; --i >= 0; ) { 1927 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD | ATW_SYNCTL_WR) 1928 == 0) 1929 break; 1930 DELAY(100); 1931 } 1932 1933 if (i < 0) { 1934 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1935 device_xname(sc->sc_dev)); 1936 return ETIMEDOUT; 1937 } 1938 1939 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1940 1941 ATW_WRITE(sc, ATW_SYNCTL, reg); 1942 1943 for (i = 1000; --i >= 0; ) { 1944 DELAY(100); 1945 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1946 break; 1947 } 1948 1949 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1950 1951 if (i < 0) { 1952 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1953 device_xname(sc->sc_dev), reg); 1954 return ETIMEDOUT; 1955 } 1956 if (val != NULL) 1957 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1958 ATW_SYNCTL_DATA_MASK); 1959 return 0; 1960 } 1961 #endif /* ATW_SYNDEBUG */ 1962 1963 /* XXX is the endianness correct? test. */ 1964 #define atw_calchash(addr) \ 1965 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1966 1967 /* 1968 * atw_filter_setup: 1969 * 1970 * Set the ADM8211's receive filter. 1971 */ 1972 static void 1973 atw_filter_setup(struct atw_softc *sc) 1974 { 1975 struct ieee80211com *ic = &sc->sc_ic; 1976 struct ethercom *ec = &sc->sc_ec; 1977 struct ifnet *ifp = &sc->sc_if; 1978 int hash; 1979 uint32_t hashes[2]; 1980 struct ether_multi *enm; 1981 struct ether_multistep step; 1982 1983 /* According to comments in tlp_al981_filter_setup 1984 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1985 * multicast filter to be set while it is running. Hopefully 1986 * the ADM8211 is not the same! 1987 */ 1988 if ((ifp->if_flags & IFF_RUNNING) != 0) 1989 atw_idle(sc, ATW_NAR_SR); 1990 1991 sc->sc_opmode &= ~(ATW_NAR_PB | ATW_NAR_PR | ATW_NAR_MM); 1992 ifp->if_flags &= ~IFF_ALLMULTI; 1993 1994 /* XXX in scan mode, do not filter packets. Maybe this is 1995 * unnecessary. 1996 */ 1997 if (ic->ic_state == IEEE80211_S_SCAN || 1998 (ifp->if_flags & IFF_PROMISC) != 0) { 1999 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2000 goto allmulti; 2001 } 2002 2003 hashes[0] = hashes[1] = 0x0; 2004 2005 /* 2006 * Program the 64-bit multicast hash filter. 2007 */ 2008 ETHER_LOCK(ec); 2009 ETHER_FIRST_MULTI(step, ec, enm); 2010 while (enm != NULL) { 2011 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2012 ETHER_ADDR_LEN) != 0) { 2013 ETHER_UNLOCK(ec); 2014 goto allmulti; 2015 } 2016 2017 hash = atw_calchash(enm->enm_addrlo); 2018 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2019 ETHER_NEXT_MULTI(step, enm); 2020 sc->sc_opmode |= ATW_NAR_MM; 2021 } 2022 ETHER_UNLOCK(ec); 2023 ifp->if_flags &= ~IFF_ALLMULTI; 2024 goto setit; 2025 2026 allmulti: 2027 sc->sc_opmode |= ATW_NAR_MM; 2028 ifp->if_flags |= IFF_ALLMULTI; 2029 hashes[0] = hashes[1] = 0xffffffff; 2030 2031 setit: 2032 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2033 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2034 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2035 DELAY(atw_nar_delay); 2036 ATW_WRITE(sc, ATW_RDR, 0x1); 2037 2038 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2039 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2040 } 2041 2042 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2043 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2044 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2045 * no beacon with the preferred BSSID and SSID in the number of 2046 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2047 */ 2048 static void 2049 atw_write_bssid(struct atw_softc *sc) 2050 { 2051 struct ieee80211com *ic = &sc->sc_ic; 2052 uint8_t *bssid; 2053 2054 bssid = ic->ic_bss->ni_bssid; 2055 2056 ATW_WRITE(sc, ATW_BSSID0, 2057 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2058 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2059 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2060 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2061 2062 ATW_WRITE(sc, ATW_ABDA1, 2063 (ATW_READ(sc, ATW_ABDA1) & 2064 ~(ATW_ABDA1_BSSIDB4_MASK | ATW_ABDA1_BSSIDB5_MASK)) | 2065 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2066 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2067 2068 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2069 ether_sprintf(sc->sc_bssid))); 2070 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2071 2072 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2073 } 2074 2075 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2076 * 16-bit word. 2077 */ 2078 static void 2079 atw_write_sram(struct atw_softc *sc, u_int ofs, uint8_t *buf, u_int buflen) 2080 { 2081 u_int i; 2082 uint8_t *ptr; 2083 2084 memcpy(&sc->sc_sram[ofs], buf, buflen); 2085 2086 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2087 2088 KASSERT(buflen + ofs <= sc->sc_sramlen); 2089 2090 ptr = &sc->sc_sram[ofs]; 2091 2092 for (i = 0; i < buflen; i += 2) { 2093 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2094 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2095 DELAY(atw_writewep_delay); 2096 2097 ATW_WRITE(sc, ATW_WESK, 2098 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2099 DELAY(atw_writewep_delay); 2100 } 2101 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2102 2103 if (sc->sc_if.if_flags & IFF_DEBUG) { 2104 int n_octets = 0; 2105 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2106 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2107 for (i = 0; i < buflen; i++) { 2108 printf(" %02x", ptr[i]); 2109 if (++n_octets % 24 == 0) 2110 printf("\n"); 2111 } 2112 if (n_octets % 24 != 0) 2113 printf("\n"); 2114 } 2115 } 2116 2117 static int 2118 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2119 { 2120 struct atw_softc *sc = ic->ic_ifp->if_softc; 2121 u_int keyix = k->wk_keyix; 2122 2123 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2124 2125 if (keyix >= IEEE80211_WEP_NKID) 2126 return 0; 2127 if (k->wk_keylen != 0) 2128 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2129 2130 return 1; 2131 } 2132 2133 static int 2134 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2135 const uint8_t mac[IEEE80211_ADDR_LEN]) 2136 { 2137 struct atw_softc *sc = ic->ic_ifp->if_softc; 2138 2139 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2140 2141 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2142 return 0; 2143 2144 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2145 2146 return 1; 2147 } 2148 2149 static void 2150 atw_key_update_begin(struct ieee80211com *ic) 2151 { 2152 #ifdef ATW_DEBUG 2153 struct ifnet *ifp = ic->ic_ifp; 2154 struct atw_softc *sc = ifp->if_softc; 2155 #endif 2156 2157 DPRINTF(sc, ("%s:\n", __func__)); 2158 } 2159 2160 static void 2161 atw_key_update_end(struct ieee80211com *ic) 2162 { 2163 struct ifnet *ifp = ic->ic_ifp; 2164 struct atw_softc *sc = ifp->if_softc; 2165 2166 DPRINTF(sc, ("%s:\n", __func__)); 2167 2168 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2169 return; 2170 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2171 return; 2172 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2173 atw_write_wep(sc); 2174 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2175 DELAY(atw_nar_delay); 2176 ATW_WRITE(sc, ATW_RDR, 0x1); 2177 } 2178 2179 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2180 static void 2181 atw_write_wep(struct atw_softc *sc) 2182 { 2183 #if 0 2184 struct ieee80211com *ic = &sc->sc_ic; 2185 uint32_t reg; 2186 int i; 2187 #endif 2188 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2189 uint8_t buf[IEEE80211_WEP_NKID] 2190 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2191 2192 sc->sc_wepctl = 0; 2193 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2194 2195 memset(&buf[0][0], 0, sizeof(buf)); 2196 2197 #if 0 2198 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2199 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2200 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2201 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2202 buf[i][1] = ATW_WEP_ENABLED; 2203 } else { 2204 buf[i][1] = 0; 2205 continue; 2206 } 2207 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2208 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2209 ic->ic_nw_keys[i].wk_keylen - 1); 2210 } 2211 2212 reg = ATW_READ(sc, ATW_MACTEST); 2213 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2214 reg &= ~ATW_MACTEST_KEYID_MASK; 2215 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2216 ATW_WRITE(sc, ATW_MACTEST, reg); 2217 2218 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2219 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2220 2221 switch (sc->sc_rev) { 2222 case ATW_REVISION_AB: 2223 case ATW_REVISION_AF: 2224 /* Bypass WEP on Rx. */ 2225 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2226 break; 2227 default: 2228 break; 2229 } 2230 #endif 2231 2232 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (uint8_t*)&buf[0][0], 2233 sizeof(buf)); 2234 2235 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2236 } 2237 2238 static void 2239 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2240 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp) 2241 { 2242 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2243 2244 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2245 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2246 return; 2247 2248 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2249 2250 switch (subtype) { 2251 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2252 case IEEE80211_FC0_SUBTYPE_BEACON: 2253 if (ic->ic_opmode == IEEE80211_M_IBSS && 2254 ic->ic_state == IEEE80211_S_RUN) { 2255 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2256 (void)ieee80211_ibss_merge(ni); 2257 } 2258 break; 2259 default: 2260 break; 2261 } 2262 return; 2263 } 2264 2265 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2266 * In ad hoc mode, the SSID is written to the beacons sent by the 2267 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2268 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2269 * indications. 2270 */ 2271 static void 2272 atw_write_ssid(struct atw_softc *sc) 2273 { 2274 struct ieee80211com *ic = &sc->sc_ic; 2275 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2276 * it only expects the element length, not its ID. 2277 */ 2278 uint8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2279 2280 memset(buf, 0, sizeof(buf)); 2281 buf[0] = ic->ic_bss->ni_esslen; 2282 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2283 2284 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2285 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2286 } 2287 2288 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2289 * In ad hoc mode, the supported rates are written to beacons sent by the 2290 * ADM8211. 2291 */ 2292 static void 2293 atw_write_sup_rates(struct atw_softc *sc) 2294 { 2295 struct ieee80211com *ic = &sc->sc_ic; 2296 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2297 * supported rates 2298 */ 2299 uint8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2300 2301 memset(buf, 0, sizeof(buf)); 2302 2303 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2304 2305 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2306 ic->ic_bss->ni_rates.rs_nrates); 2307 2308 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2309 } 2310 2311 /* Start/stop sending beacons. */ 2312 void 2313 atw_start_beacon(struct atw_softc *sc, int start) 2314 { 2315 struct ieee80211com *ic = &sc->sc_ic; 2316 uint16_t chan; 2317 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2318 size_t len; 2319 2320 if (!device_is_active(sc->sc_dev)) 2321 return; 2322 2323 /* start beacons */ 2324 len = sizeof(struct ieee80211_frame) + 2325 8 /* timestamp */ + 2 /* beacon interval */ + 2326 2 /* capability info */ + 2327 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2328 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2329 3 /* DS parameters */ + 2330 IEEE80211_CRC_LEN; 2331 2332 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2333 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2334 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2335 2336 ATW_WRITE(sc, ATW_BCNT, bcnt); 2337 ATW_WRITE(sc, ATW_CAP1, cap1); 2338 2339 if (!start) 2340 return; 2341 2342 /* TBD use ni_capinfo */ 2343 2344 capinfo = 0; 2345 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2346 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2347 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2348 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2349 2350 switch (ic->ic_opmode) { 2351 case IEEE80211_M_IBSS: 2352 len += 4; /* IBSS parameters */ 2353 capinfo |= IEEE80211_CAPINFO_IBSS; 2354 break; 2355 case IEEE80211_M_HOSTAP: 2356 /* XXX 6-byte minimum TIM */ 2357 len += atw_beacon_len_adjust; 2358 capinfo |= IEEE80211_CAPINFO_ESS; 2359 break; 2360 default: 2361 return; 2362 } 2363 2364 /* set listen interval 2365 * XXX do software units agree w/ hardware? 2366 */ 2367 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2368 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2369 2370 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2371 2372 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2373 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2374 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2375 2376 ATW_WRITE(sc, ATW_BCNT, bcnt); 2377 ATW_WRITE(sc, ATW_BPLI, bpli); 2378 ATW_WRITE(sc, ATW_CAP0, cap0); 2379 ATW_WRITE(sc, ATW_CAP1, cap1); 2380 2381 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2382 device_xname(sc->sc_dev), bcnt)); 2383 2384 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2385 device_xname(sc->sc_dev), cap1)); 2386 } 2387 2388 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2389 static inline uint32_t 2390 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2391 { 2392 /* Following the reference driver's lead, I compute 2393 * 2394 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2395 * 2396 * without using 64-bit arithmetic, using the following 2397 * relationship: 2398 * 2399 * (0x100000000 * H + L) % m 2400 * = ((0x100000000 % m) * H + L) % m 2401 * = (((0xffffffff + 1) % m) * H + L) % m 2402 * = ((0xffffffff % m + 1 % m) * H + L) % m 2403 * = ((0xffffffff % m + 1) * H + L) % m 2404 */ 2405 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2406 } 2407 2408 static uint64_t 2409 atw_get_tsft(struct atw_softc *sc) 2410 { 2411 int i; 2412 uint32_t tsfth, tsftl; 2413 for (i = 0; i < 2; i++) { 2414 tsfth = ATW_READ(sc, ATW_TSFTH); 2415 tsftl = ATW_READ(sc, ATW_TSFTL); 2416 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2417 break; 2418 } 2419 return ((uint64_t)tsfth << 32) | tsftl; 2420 } 2421 2422 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2423 * the ieee80211com. 2424 * 2425 * Predict the next target beacon transmission time (TBTT) and 2426 * write it to the ADM8211. 2427 */ 2428 static void 2429 atw_predict_beacon(struct atw_softc *sc) 2430 { 2431 #define TBTTOFS 20 /* TU */ 2432 2433 struct ieee80211com *ic = &sc->sc_ic; 2434 uint64_t tsft; 2435 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2436 union { 2437 uint64_t word; 2438 uint8_t tstamp[8]; 2439 } u; 2440 2441 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2442 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2443 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2444 tsft = atw_get_tsft(sc); 2445 u.word = htole64(tsft); 2446 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2447 sizeof(ic->ic_bss->ni_tstamp)); 2448 } else 2449 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2450 2451 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2452 2453 tsftl = tsft & 0xFFFFFFFF; 2454 tsfth = tsft >> 32; 2455 2456 /* We sent/received the last beacon `past' microseconds 2457 * after the interval divided the TSF timer. 2458 */ 2459 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2460 2461 /* Skip ten beacons so that the TBTT cannot pass before 2462 * we've programmed it. Ten is an arbitrary number. 2463 */ 2464 tbtt = past_even + ival * 10; 2465 2466 ATW_WRITE(sc, ATW_TOFS1, 2467 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2468 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2469 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2470 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2471 #undef TBTTOFS 2472 } 2473 2474 static void 2475 atw_next_scan(void *arg) 2476 { 2477 struct atw_softc *sc = arg; 2478 struct ieee80211com *ic = &sc->sc_ic; 2479 int s; 2480 2481 /* don't call atw_start w/o network interrupts blocked */ 2482 s = splnet(); 2483 if (ic->ic_state == IEEE80211_S_SCAN) 2484 ieee80211_next_scan(ic); 2485 splx(s); 2486 } 2487 2488 /* Synchronize the hardware state with the software state. */ 2489 static int 2490 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2491 { 2492 struct ifnet *ifp = ic->ic_ifp; 2493 struct atw_softc *sc = ifp->if_softc; 2494 int error = 0; 2495 2496 callout_stop(&sc->sc_scan_ch); 2497 2498 switch (nstate) { 2499 case IEEE80211_S_AUTH: 2500 case IEEE80211_S_ASSOC: 2501 atw_write_bssid(sc); 2502 error = atw_tune(sc); 2503 break; 2504 case IEEE80211_S_INIT: 2505 callout_stop(&sc->sc_scan_ch); 2506 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2507 atw_start_beacon(sc, 0); 2508 break; 2509 case IEEE80211_S_SCAN: 2510 error = atw_tune(sc); 2511 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2512 atw_next_scan, sc); 2513 break; 2514 case IEEE80211_S_RUN: 2515 error = atw_tune(sc); 2516 atw_write_bssid(sc); 2517 atw_write_ssid(sc); 2518 atw_write_sup_rates(sc); 2519 2520 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2521 ic->ic_opmode == IEEE80211_M_MONITOR) 2522 break; 2523 2524 /* set listen interval 2525 * XXX do software units agree w/ hardware? 2526 */ 2527 ATW_WRITE(sc, ATW_BPLI, 2528 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2529 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2530 ATW_BPLI_LI_MASK)); 2531 2532 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2533 ATW_READ(sc, ATW_BPLI))); 2534 2535 atw_predict_beacon(sc); 2536 2537 switch (ic->ic_opmode) { 2538 case IEEE80211_M_AHDEMO: 2539 case IEEE80211_M_HOSTAP: 2540 case IEEE80211_M_IBSS: 2541 atw_start_beacon(sc, 1); 2542 break; 2543 case IEEE80211_M_MONITOR: 2544 case IEEE80211_M_STA: 2545 break; 2546 } 2547 2548 break; 2549 } 2550 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2551 } 2552 2553 /* 2554 * atw_add_rxbuf: 2555 * 2556 * Add a receive buffer to the indicated descriptor. 2557 */ 2558 int 2559 atw_add_rxbuf(struct atw_softc *sc, int idx) 2560 { 2561 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2562 struct mbuf *m; 2563 int error; 2564 2565 MGETHDR(m, M_DONTWAIT, MT_DATA); 2566 if (m == NULL) 2567 return (ENOBUFS); 2568 2569 MCLGET(m, M_DONTWAIT); 2570 if ((m->m_flags & M_EXT) == 0) { 2571 m_freem(m); 2572 return (ENOBUFS); 2573 } 2574 2575 if (rxs->rxs_mbuf != NULL) 2576 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2577 2578 rxs->rxs_mbuf = m; 2579 2580 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2581 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2582 BUS_DMA_READ | BUS_DMA_NOWAIT); 2583 if (error) { 2584 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2585 idx, error); 2586 panic("atw_add_rxbuf"); /* XXX */ 2587 } 2588 2589 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2590 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2591 2592 atw_init_rxdesc(sc, idx); 2593 2594 return (0); 2595 } 2596 2597 /* 2598 * Release any queued transmit buffers. 2599 */ 2600 void 2601 atw_txdrain(struct atw_softc *sc) 2602 { 2603 struct atw_txsoft *txs; 2604 2605 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2606 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2607 if (txs->txs_mbuf != NULL) { 2608 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2609 m_freem(txs->txs_mbuf); 2610 txs->txs_mbuf = NULL; 2611 } 2612 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2613 sc->sc_txfree += txs->txs_ndescs; 2614 } 2615 2616 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2617 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2618 sc->sc_txfree != ATW_NTXDESC)); 2619 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2620 sc->sc_tx_timer = 0; 2621 } 2622 2623 /* 2624 * atw_stop: [ ifnet interface function ] 2625 * 2626 * Stop transmission on the interface. 2627 */ 2628 void 2629 atw_stop(struct ifnet *ifp, int disable) 2630 { 2631 struct atw_softc *sc = ifp->if_softc; 2632 struct ieee80211com *ic = &sc->sc_ic; 2633 2634 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2635 2636 if (device_is_active(sc->sc_dev)) { 2637 /* Disable interrupts. */ 2638 ATW_WRITE(sc, ATW_IER, 0); 2639 2640 /* Stop the transmit and receive processes. */ 2641 ATW_WRITE(sc, ATW_NAR, 0); 2642 DELAY(atw_nar_delay); 2643 ATW_WRITE(sc, ATW_TDBD, 0); 2644 ATW_WRITE(sc, ATW_TDBP, 0); 2645 ATW_WRITE(sc, ATW_RDB, 0); 2646 } 2647 2648 sc->sc_opmode = 0; 2649 2650 atw_txdrain(sc); 2651 2652 /* 2653 * Mark the interface down and cancel the watchdog timer. 2654 */ 2655 ifp->if_flags &= ~IFF_RUNNING; 2656 ifp->if_timer = 0; 2657 2658 if (disable) 2659 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2660 } 2661 2662 /* 2663 * atw_rxdrain: 2664 * 2665 * Drain the receive queue. 2666 */ 2667 void 2668 atw_rxdrain(struct atw_softc *sc) 2669 { 2670 struct atw_rxsoft *rxs; 2671 int i; 2672 2673 for (i = 0; i < ATW_NRXDESC; i++) { 2674 rxs = &sc->sc_rxsoft[i]; 2675 if (rxs->rxs_mbuf == NULL) 2676 continue; 2677 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2678 m_freem(rxs->rxs_mbuf); 2679 rxs->rxs_mbuf = NULL; 2680 } 2681 } 2682 2683 /* 2684 * atw_detach: 2685 * 2686 * Detach an ADM8211 interface. 2687 */ 2688 int 2689 atw_detach(struct atw_softc *sc) 2690 { 2691 struct ifnet *ifp = &sc->sc_if; 2692 struct atw_rxsoft *rxs; 2693 struct atw_txsoft *txs; 2694 int i; 2695 2696 /* 2697 * Succeed now if there isn't any work to do. 2698 */ 2699 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2700 return (0); 2701 2702 pmf_device_deregister(sc->sc_dev); 2703 2704 callout_stop(&sc->sc_scan_ch); 2705 2706 ieee80211_ifdetach(&sc->sc_ic); 2707 if_detach(ifp); 2708 2709 for (i = 0; i < ATW_NRXDESC; i++) { 2710 rxs = &sc->sc_rxsoft[i]; 2711 if (rxs->rxs_mbuf != NULL) { 2712 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2713 m_freem(rxs->rxs_mbuf); 2714 rxs->rxs_mbuf = NULL; 2715 } 2716 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2717 } 2718 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2719 txs = &sc->sc_txsoft[i]; 2720 if (txs->txs_mbuf != NULL) { 2721 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2722 m_freem(txs->txs_mbuf); 2723 txs->txs_mbuf = NULL; 2724 } 2725 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2726 } 2727 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2728 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2729 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2730 sizeof(struct atw_control_data)); 2731 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2732 2733 if (sc->sc_srom) 2734 free(sc->sc_srom, M_DEVBUF); 2735 2736 atw_evcnt_detach(sc); 2737 2738 if (sc->sc_soft_ih != NULL) { 2739 softint_disestablish(sc->sc_soft_ih); 2740 sc->sc_soft_ih = NULL; 2741 } 2742 2743 return (0); 2744 } 2745 2746 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2747 bool 2748 atw_shutdown(device_t self, int flags) 2749 { 2750 struct atw_softc *sc = device_private(self); 2751 2752 atw_stop(&sc->sc_if, 1); 2753 return true; 2754 } 2755 2756 #if 0 2757 static void 2758 atw_workaround1(struct atw_softc *sc) 2759 { 2760 uint32_t test1; 2761 2762 test1 = ATW_READ(sc, ATW_TEST1); 2763 2764 sc->sc_misc_ev.ev_count++; 2765 2766 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2767 sc->sc_rxpkt1in_ev.ev_count++; 2768 return; 2769 } 2770 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2771 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2772 sc->sc_rxamatch_ev.ev_count++; 2773 return; 2774 } 2775 sc->sc_workaround1_ev.ev_count++; 2776 (void)atw_init(&sc->sc_if); 2777 } 2778 #endif 2779 2780 int 2781 atw_intr(void *arg) 2782 { 2783 struct atw_softc *sc = arg; 2784 struct ifnet *ifp = &sc->sc_if; 2785 uint32_t status; 2786 2787 #ifdef DEBUG 2788 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2789 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2790 #endif 2791 2792 /* 2793 * If the interface isn't running, the interrupt couldn't 2794 * possibly have come from us. 2795 */ 2796 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2797 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2798 return (0); 2799 2800 status = ATW_READ(sc, ATW_STSR); 2801 if (status == 0) 2802 return 0; 2803 2804 if ((status & sc->sc_inten) == 0) { 2805 ATW_WRITE(sc, ATW_STSR, status); 2806 return 0; 2807 } 2808 2809 /* Disable interrupts */ 2810 ATW_WRITE(sc, ATW_IER, 0); 2811 2812 softint_schedule(sc->sc_soft_ih); 2813 return 1; 2814 } 2815 2816 void 2817 atw_softintr(void *arg) 2818 { 2819 struct atw_softc *sc = arg; 2820 struct ifnet *ifp = &sc->sc_if; 2821 uint32_t status, rxstatus, txstatus, linkstatus; 2822 int txthresh, s; 2823 2824 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2825 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2826 return; 2827 2828 for (;;) { 2829 status = ATW_READ(sc, ATW_STSR); 2830 2831 if (status) 2832 ATW_WRITE(sc, ATW_STSR, status); 2833 2834 #ifdef ATW_DEBUG 2835 #define PRINTINTR(flag) do { \ 2836 if ((status & flag) != 0) { \ 2837 printf("%s" #flag, delim); \ 2838 delim = ","; \ 2839 } \ 2840 } while (0) 2841 2842 if (atw_debug > 1 && status) { 2843 const char *delim = "<"; 2844 2845 printf("%s: reg[STSR] = %x", 2846 device_xname(sc->sc_dev), status); 2847 2848 PRINTINTR(ATW_INTR_FBE); 2849 PRINTINTR(ATW_INTR_LINKOFF); 2850 PRINTINTR(ATW_INTR_LINKON); 2851 PRINTINTR(ATW_INTR_RCI); 2852 PRINTINTR(ATW_INTR_RDU); 2853 PRINTINTR(ATW_INTR_REIS); 2854 PRINTINTR(ATW_INTR_RPS); 2855 PRINTINTR(ATW_INTR_TCI); 2856 PRINTINTR(ATW_INTR_TDU); 2857 PRINTINTR(ATW_INTR_TLT); 2858 PRINTINTR(ATW_INTR_TPS); 2859 PRINTINTR(ATW_INTR_TRT); 2860 PRINTINTR(ATW_INTR_TUF); 2861 PRINTINTR(ATW_INTR_BCNTC); 2862 PRINTINTR(ATW_INTR_ATIME); 2863 PRINTINTR(ATW_INTR_TBTT); 2864 PRINTINTR(ATW_INTR_TSCZ); 2865 PRINTINTR(ATW_INTR_TSFTF); 2866 printf(">\n"); 2867 } 2868 #undef PRINTINTR 2869 #endif /* ATW_DEBUG */ 2870 2871 if ((status & sc->sc_inten) == 0) 2872 break; 2873 2874 rxstatus = status & sc->sc_rxint_mask; 2875 txstatus = status & sc->sc_txint_mask; 2876 linkstatus = status & sc->sc_linkint_mask; 2877 2878 if (linkstatus) { 2879 atw_linkintr(sc, linkstatus); 2880 } 2881 2882 if (rxstatus) { 2883 /* Grab any new packets. */ 2884 atw_rxintr(sc); 2885 2886 if (rxstatus & ATW_INTR_RDU) { 2887 printf("%s: receive ring overrun\n", 2888 device_xname(sc->sc_dev)); 2889 /* Get the receive process going again. */ 2890 ATW_WRITE(sc, ATW_RDR, 0x1); 2891 } 2892 } 2893 2894 if (txstatus) { 2895 /* Sweep up transmit descriptors. */ 2896 atw_txintr(sc, txstatus); 2897 2898 if (txstatus & ATW_INTR_TLT) { 2899 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2900 device_xname(sc->sc_dev))); 2901 (void)atw_init(&sc->sc_if); 2902 } 2903 2904 if (txstatus & ATW_INTR_TRT) { 2905 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2906 device_xname(sc->sc_dev))); 2907 } 2908 2909 /* If Tx under-run, increase our transmit threshold 2910 * if another is available. 2911 */ 2912 txthresh = sc->sc_txthresh + 1; 2913 if ((txstatus & ATW_INTR_TUF) && 2914 sc->sc_txth[txthresh].txth_name != NULL) { 2915 /* Idle the transmit process. */ 2916 atw_idle(sc, ATW_NAR_ST); 2917 2918 sc->sc_txthresh = txthresh; 2919 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2920 sc->sc_opmode |= 2921 sc->sc_txth[txthresh].txth_opmode; 2922 printf("%s: transmit underrun; new " 2923 "threshold: %s\n", device_xname(sc->sc_dev), 2924 sc->sc_txth[txthresh].txth_name); 2925 2926 /* Set the new threshold and restart 2927 * the transmit process. 2928 */ 2929 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2930 DELAY(atw_nar_delay); 2931 ATW_WRITE(sc, ATW_TDR, 0x1); 2932 /* XXX Log every Nth underrun from 2933 * XXX now on? 2934 */ 2935 } 2936 } 2937 2938 if (status & (ATW_INTR_TPS | ATW_INTR_RPS)) { 2939 if (status & ATW_INTR_TPS) 2940 printf("%s: transmit process stopped\n", 2941 device_xname(sc->sc_dev)); 2942 if (status & ATW_INTR_RPS) 2943 printf("%s: receive process stopped\n", 2944 device_xname(sc->sc_dev)); 2945 s = splnet(); 2946 (void)atw_init(ifp); 2947 splx(s); 2948 break; 2949 } 2950 2951 if (status & ATW_INTR_FBE) { 2952 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2953 s = splnet(); 2954 (void)atw_init(ifp); 2955 splx(s); 2956 break; 2957 } 2958 2959 /* 2960 * Not handled: 2961 * 2962 * Transmit buffer unavailable -- normal 2963 * condition, nothing to do, really. 2964 * 2965 * Early receive interrupt -- not available on 2966 * all chips, we just use RI. We also only 2967 * use single-segment receive DMA, so this 2968 * is mostly useless. 2969 * 2970 * TBD others 2971 */ 2972 } 2973 2974 /* Try to get more packets going. */ 2975 s = splnet(); 2976 atw_start(ifp); 2977 splx(s); 2978 2979 /* Enable interrupts */ 2980 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 2981 } 2982 2983 /* 2984 * atw_idle: 2985 * 2986 * Cause the transmit and/or receive processes to go idle. 2987 * 2988 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2989 * process in STSR if I clear SR or ST after the process has already 2990 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2991 * do not seem to be too reliable. Perhaps I have the sense of the 2992 * Rx bits switched with the Tx bits? 2993 */ 2994 void 2995 atw_idle(struct atw_softc *sc, uint32_t bits) 2996 { 2997 uint32_t ackmask = 0, opmode, stsr, test0; 2998 int i, s; 2999 3000 s = splnet(); 3001 3002 opmode = sc->sc_opmode & ~bits; 3003 3004 if (bits & ATW_NAR_SR) 3005 ackmask |= ATW_INTR_RPS; 3006 3007 if (bits & ATW_NAR_ST) { 3008 ackmask |= ATW_INTR_TPS; 3009 /* set ATW_NAR_HF to flush TX FIFO. */ 3010 opmode |= ATW_NAR_HF; 3011 } 3012 3013 ATW_WRITE(sc, ATW_NAR, opmode); 3014 DELAY(atw_nar_delay); 3015 3016 for (i = 0; i < 1000; i++) { 3017 stsr = ATW_READ(sc, ATW_STSR); 3018 if ((stsr & ackmask) == ackmask) 3019 break; 3020 DELAY(10); 3021 } 3022 3023 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3024 3025 if ((stsr & ackmask) == ackmask) 3026 goto out; 3027 3028 test0 = ATW_READ(sc, ATW_TEST0); 3029 3030 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3031 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3032 printf("%s: transmit process not idle [%s]\n", 3033 device_xname(sc->sc_dev), 3034 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3035 printf("%s: bits %08x test0 %08x stsr %08x\n", 3036 device_xname(sc->sc_dev), bits, test0, stsr); 3037 } 3038 3039 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3040 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3041 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3042 device_xname(sc->sc_dev), 3043 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3044 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3045 device_xname(sc->sc_dev), bits, test0, stsr)); 3046 } 3047 out: 3048 if ((bits & ATW_NAR_ST) != 0) 3049 atw_txdrain(sc); 3050 splx(s); 3051 return; 3052 } 3053 3054 /* 3055 * atw_linkintr: 3056 * 3057 * Helper; handle link-status interrupts. 3058 */ 3059 void 3060 atw_linkintr(struct atw_softc *sc, uint32_t linkstatus) 3061 { 3062 struct ieee80211com *ic = &sc->sc_ic; 3063 3064 if (ic->ic_state != IEEE80211_S_RUN) 3065 return; 3066 3067 if (linkstatus & ATW_INTR_LINKON) { 3068 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3069 sc->sc_rescan_timer = 0; 3070 } else if (linkstatus & ATW_INTR_LINKOFF) { 3071 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3072 if (ic->ic_opmode != IEEE80211_M_STA) 3073 return; 3074 sc->sc_rescan_timer = 3; 3075 sc->sc_if.if_timer = 1; 3076 } 3077 } 3078 3079 #if 0 3080 static inline int 3081 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3082 { 3083 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3084 return 0; 3085 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3086 return 0; 3087 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3088 } 3089 #endif 3090 3091 /* 3092 * atw_rxintr: 3093 * 3094 * Helper; handle receive interrupts. 3095 */ 3096 void 3097 atw_rxintr(struct atw_softc *sc) 3098 { 3099 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3100 struct ieee80211com *ic = &sc->sc_ic; 3101 struct ieee80211_node *ni; 3102 struct ieee80211_frame_min *wh; 3103 struct ifnet *ifp = &sc->sc_if; 3104 struct atw_rxsoft *rxs; 3105 struct mbuf *m; 3106 uint32_t rxstat; 3107 int i, s, len, rate, rate0; 3108 uint32_t rssi, ctlrssi; 3109 3110 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3111 rxs = &sc->sc_rxsoft[i]; 3112 3113 ATW_CDRXSYNC(sc, i, 3114 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3115 3116 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3117 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3118 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3119 3120 if (rxstat & ATW_RXSTAT_OWN) { 3121 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3122 break; 3123 } 3124 3125 sc->sc_rxptr = ATW_NEXTRX(i); 3126 3127 DPRINTF3(sc, 3128 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3129 device_xname(sc->sc_dev), 3130 rxstat, ctlrssi, 3131 le32toh(sc->sc_rxdescs[i].ar_buf1), 3132 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3133 3134 /* 3135 * Make sure the packet fits in one buffer. This should 3136 * always be the case. 3137 */ 3138 if ((rxstat & (ATW_RXSTAT_FS | ATW_RXSTAT_LS)) != 3139 (ATW_RXSTAT_FS | ATW_RXSTAT_LS)) { 3140 printf("%s: incoming packet spilled, resetting\n", 3141 device_xname(sc->sc_dev)); 3142 (void)atw_init(ifp); 3143 return; 3144 } 3145 3146 /* 3147 * If an error occurred, update stats, clear the status 3148 * word, and leave the packet buffer in place. It will 3149 * simply be reused the next time the ring comes around. 3150 */ 3151 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3152 #define PRINTERR(bit, str) \ 3153 if (rxstat & (bit)) \ 3154 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3155 str) 3156 ifp->if_ierrors++; 3157 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3158 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3159 #if 0 3160 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3161 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3162 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3163 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3164 #endif 3165 #undef PRINTERR 3166 atw_init_rxdesc(sc, i); 3167 continue; 3168 } 3169 3170 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3171 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3172 3173 /* 3174 * No errors; receive the packet. Note the ADM8211 3175 * includes the CRC in promiscuous mode. 3176 */ 3177 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3178 3179 /* 3180 * Allocate a new mbuf cluster. If that fails, we are 3181 * out of memory, and must drop the packet and recycle 3182 * the buffer that's already attached to this descriptor. 3183 */ 3184 m = rxs->rxs_mbuf; 3185 if (atw_add_rxbuf(sc, i) != 0) { 3186 ifp->if_ierrors++; 3187 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3188 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3189 atw_init_rxdesc(sc, i); 3190 continue; 3191 } 3192 3193 ifp->if_ipackets++; 3194 m_set_rcvif(m, ifp); 3195 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3196 3197 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3198 3199 /* The RSSI comes straight from a register in the 3200 * baseband processor. I know that for the RF3000, 3201 * the RSSI register also contains the antenna-selection 3202 * bits. Mask those off. 3203 * 3204 * TBD Treat other basebands. 3205 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3206 */ 3207 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3208 rssi = ctlrssi & RF3000_RSSI_MASK; 3209 else 3210 rssi = ctlrssi; 3211 3212 s = splnet(); 3213 3214 /* Pass this up to any BPF listeners. */ 3215 if (sc->sc_radiobpf != NULL) { 3216 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3217 3218 tap->ar_rate = rate; 3219 3220 /* TBD verify units are dB */ 3221 tap->ar_antsignal = (int)rssi; 3222 if (sc->sc_opmode & ATW_NAR_PR) 3223 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3224 else 3225 tap->ar_flags = 0; 3226 3227 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3228 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3229 3230 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), 3231 m, BPF_D_IN); 3232 } 3233 3234 sc->sc_recv_ev.ev_count++; 3235 3236 if ((rxstat & (ATW_RXSTAT_CRC16E | ATW_RXSTAT_CRC32E | 3237 ATW_RXSTAT_ICVE | ATW_RXSTAT_SFDE | ATW_RXSTAT_SIGE)) 3238 != 0) { 3239 if (rxstat & ATW_RXSTAT_CRC16E) 3240 sc->sc_crc16e_ev.ev_count++; 3241 if (rxstat & ATW_RXSTAT_CRC32E) 3242 sc->sc_crc32e_ev.ev_count++; 3243 if (rxstat & ATW_RXSTAT_ICVE) 3244 sc->sc_icve_ev.ev_count++; 3245 if (rxstat & ATW_RXSTAT_SFDE) 3246 sc->sc_sfde_ev.ev_count++; 3247 if (rxstat & ATW_RXSTAT_SIGE) 3248 sc->sc_sige_ev.ev_count++; 3249 ifp->if_ierrors++; 3250 m_freem(m); 3251 splx(s); 3252 continue; 3253 } 3254 3255 if (sc->sc_opmode & ATW_NAR_PR) 3256 m_adj(m, -IEEE80211_CRC_LEN); 3257 3258 wh = mtod(m, struct ieee80211_frame_min *); 3259 ni = ieee80211_find_rxnode(ic, wh); 3260 #if 0 3261 if (atw_hw_decrypted(sc, wh)) { 3262 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3263 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3264 } 3265 #endif 3266 ieee80211_input(ic, m, ni, (int)rssi, 0); 3267 ieee80211_free_node(ni); 3268 splx(s); 3269 } 3270 } 3271 3272 /* 3273 * atw_txintr: 3274 * 3275 * Helper; handle transmit interrupts. 3276 */ 3277 void 3278 atw_txintr(struct atw_softc *sc, uint32_t status) 3279 { 3280 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3281 struct ifnet *ifp = &sc->sc_if; 3282 struct atw_txsoft *txs; 3283 uint32_t txstat; 3284 int s; 3285 3286 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3287 device_xname(sc->sc_dev), sc->sc_flags)); 3288 3289 s = splnet(); 3290 3291 /* 3292 * Go through our Tx list and free mbufs for those 3293 * frames that have been transmitted. 3294 */ 3295 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3296 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3298 3299 #ifdef ATW_DEBUG 3300 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3301 int i; 3302 printf(" txsoft %p transmit chain:\n", txs); 3303 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3304 txs->txs_ndescs - 1, 3305 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3306 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3307 printf(" descriptor %d:\n", i); 3308 printf(" at_status: 0x%08x\n", 3309 le32toh(sc->sc_txdescs[i].at_stat)); 3310 printf(" at_flags: 0x%08x\n", 3311 le32toh(sc->sc_txdescs[i].at_flags)); 3312 printf(" at_buf1: 0x%08x\n", 3313 le32toh(sc->sc_txdescs[i].at_buf1)); 3314 printf(" at_buf2: 0x%08x\n", 3315 le32toh(sc->sc_txdescs[i].at_buf2)); 3316 if (i == txs->txs_lastdesc) 3317 break; 3318 } 3319 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3320 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3321 } 3322 #endif 3323 3324 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3325 if (txstat & ATW_TXSTAT_OWN) { 3326 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3327 BUS_DMASYNC_PREREAD); 3328 break; 3329 } 3330 3331 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3332 3333 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3334 0, txs->txs_dmamap->dm_mapsize, 3335 BUS_DMASYNC_POSTWRITE); 3336 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3337 m_freem(txs->txs_mbuf); 3338 txs->txs_mbuf = NULL; 3339 3340 sc->sc_txfree += txs->txs_ndescs; 3341 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3342 3343 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3344 sc->sc_tx_timer = 0; 3345 ifp->if_flags &= ~IFF_OACTIVE; 3346 3347 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3348 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3349 snprintb(txstat_buf, sizeof(txstat_buf), 3350 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3351 printf("%s: txstat %s %" __PRIuBITS "\n", 3352 device_xname(sc->sc_dev), txstat_buf, 3353 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3354 } 3355 3356 sc->sc_xmit_ev.ev_count++; 3357 3358 /* 3359 * Check for errors and collisions. 3360 */ 3361 if (txstat & ATW_TXSTAT_TUF) 3362 sc->sc_tuf_ev.ev_count++; 3363 if (txstat & ATW_TXSTAT_TLT) 3364 sc->sc_tlt_ev.ev_count++; 3365 if (txstat & ATW_TXSTAT_TRT) 3366 sc->sc_trt_ev.ev_count++; 3367 if (txstat & ATW_TXSTAT_TRO) 3368 sc->sc_tro_ev.ev_count++; 3369 if (txstat & ATW_TXSTAT_SOFBR) 3370 sc->sc_sofbr_ev.ev_count++; 3371 3372 if ((txstat & ATW_TXSTAT_ES) == 0) 3373 ifp->if_collisions += 3374 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3375 else 3376 ifp->if_oerrors++; 3377 3378 ifp->if_opackets++; 3379 } 3380 3381 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3382 3383 splx(s); 3384 } 3385 3386 /* 3387 * atw_watchdog: [ifnet interface function] 3388 * 3389 * Watchdog timer handler. 3390 */ 3391 void 3392 atw_watchdog(struct ifnet *ifp) 3393 { 3394 struct atw_softc *sc = ifp->if_softc; 3395 struct ieee80211com *ic = &sc->sc_ic; 3396 3397 ifp->if_timer = 0; 3398 if (!device_is_active(sc->sc_dev)) 3399 return; 3400 3401 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3402 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3403 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3404 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3405 printf("%s: transmit timeout\n", ifp->if_xname); 3406 ifp->if_oerrors++; 3407 (void)atw_init(ifp); 3408 atw_start(ifp); 3409 } 3410 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3411 ifp->if_timer = 1; 3412 ieee80211_watchdog(ic); 3413 } 3414 3415 static void 3416 atw_evcnt_detach(struct atw_softc *sc) 3417 { 3418 evcnt_detach(&sc->sc_sige_ev); 3419 evcnt_detach(&sc->sc_sfde_ev); 3420 evcnt_detach(&sc->sc_icve_ev); 3421 evcnt_detach(&sc->sc_crc32e_ev); 3422 evcnt_detach(&sc->sc_crc16e_ev); 3423 evcnt_detach(&sc->sc_recv_ev); 3424 3425 evcnt_detach(&sc->sc_tuf_ev); 3426 evcnt_detach(&sc->sc_tro_ev); 3427 evcnt_detach(&sc->sc_trt_ev); 3428 evcnt_detach(&sc->sc_tlt_ev); 3429 evcnt_detach(&sc->sc_sofbr_ev); 3430 evcnt_detach(&sc->sc_xmit_ev); 3431 3432 evcnt_detach(&sc->sc_rxpkt1in_ev); 3433 evcnt_detach(&sc->sc_rxamatch_ev); 3434 evcnt_detach(&sc->sc_workaround1_ev); 3435 evcnt_detach(&sc->sc_misc_ev); 3436 } 3437 3438 static void 3439 atw_evcnt_attach(struct atw_softc *sc) 3440 { 3441 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3442 NULL, sc->sc_if.if_xname, "recv"); 3443 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3444 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3445 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3446 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3447 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3448 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3449 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3450 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3451 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3452 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3453 3454 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3455 NULL, sc->sc_if.if_xname, "xmit"); 3456 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3457 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3458 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3459 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3460 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3461 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3462 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3463 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3464 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3465 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3466 3467 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3468 NULL, sc->sc_if.if_xname, "misc"); 3469 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3470 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3471 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3472 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3473 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3474 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3475 } 3476 3477 #ifdef ATW_DEBUG 3478 static void 3479 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3480 { 3481 struct atw_softc *sc = ifp->if_softc; 3482 struct mbuf *m; 3483 int i, noctets = 0; 3484 3485 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3486 m0->m_pkthdr.len); 3487 3488 for (m = m0; m; m = m->m_next) { 3489 if (m->m_len == 0) 3490 continue; 3491 for (i = 0; i < m->m_len; i++) { 3492 printf(" %02x", ((uint8_t*)m->m_data)[i]); 3493 if (++noctets % 24 == 0) 3494 printf("\n"); 3495 } 3496 } 3497 printf("%s%s: %d bytes emitted\n", 3498 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3499 } 3500 #endif /* ATW_DEBUG */ 3501 3502 /* 3503 * atw_start: [ifnet interface function] 3504 * 3505 * Start packet transmission on the interface. 3506 */ 3507 void 3508 atw_start(struct ifnet *ifp) 3509 { 3510 struct atw_softc *sc = ifp->if_softc; 3511 struct ieee80211_key *k; 3512 struct ieee80211com *ic = &sc->sc_ic; 3513 struct ieee80211_node *ni; 3514 struct ieee80211_frame_min *whm; 3515 struct ieee80211_frame *wh; 3516 struct atw_frame *hh; 3517 uint16_t hdrctl; 3518 struct mbuf *m0, *m; 3519 struct atw_txsoft *txs; 3520 struct atw_txdesc *txd; 3521 int npkt, rate; 3522 bus_dmamap_t dmamap; 3523 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3524 3525 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3526 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3527 3528 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3529 return; 3530 3531 /* 3532 * Remember the previous number of free descriptors and 3533 * the first descriptor we'll use. 3534 */ 3535 ofree = sc->sc_txfree; 3536 firsttx = lasttx = sc->sc_txnext; 3537 3538 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3539 device_xname(sc->sc_dev), ofree, firsttx)); 3540 3541 /* 3542 * Loop through the send queue, setting up transmit descriptors 3543 * until we drain the queue, or use up all available transmit 3544 * descriptors. 3545 */ 3546 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3547 sc->sc_txfree != 0) { 3548 3549 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3550 3551 /* 3552 * Grab a packet off the management queue, if it 3553 * is not empty. Otherwise, from the data queue. 3554 */ 3555 IF_DEQUEUE(&ic->ic_mgtq, m0); 3556 if (m0 != NULL) { 3557 ni = M_GETCTX(m0, struct ieee80211_node *); 3558 M_CLEARCTX(m0); 3559 } else if (ic->ic_state != IEEE80211_S_RUN) 3560 break; /* send no data until associated */ 3561 else { 3562 IFQ_DEQUEUE(&ifp->if_snd, m0); 3563 if (m0 == NULL) 3564 break; 3565 bpf_mtap(ifp, m0, BPF_D_OUT); 3566 ni = ieee80211_find_txnode(ic, 3567 mtod(m0, struct ether_header *)->ether_dhost); 3568 if (ni == NULL) { 3569 ifp->if_oerrors++; 3570 break; 3571 } 3572 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3573 ieee80211_free_node(ni); 3574 ifp->if_oerrors++; 3575 break; 3576 } 3577 } 3578 3579 rate = MAX(ieee80211_get_rate(ni), 2); 3580 3581 whm = mtod(m0, struct ieee80211_frame_min *); 3582 3583 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3584 k = NULL; 3585 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3586 m_freem(m0); 3587 ieee80211_free_node(ni); 3588 ifp->if_oerrors++; 3589 break; 3590 } 3591 #if 0 3592 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3593 m0->m_pkthdr.len > ic->ic_fragthreshold) 3594 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3595 #endif 3596 3597 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3598 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3599 3600 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3601 ic->ic_flags, ic->ic_fragthreshold, rate, 3602 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3603 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3604 m_freem(m0); 3605 break; 3606 } 3607 3608 /* XXX Misleading if fragmentation is enabled. Better 3609 * to fragment in software? 3610 */ 3611 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3612 3613 /* 3614 * Pass the packet to any BPF listeners. 3615 */ 3616 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3617 3618 if (sc->sc_radiobpf != NULL) { 3619 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3620 3621 tap->at_rate = rate; 3622 3623 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), 3624 m0, BPF_D_OUT); 3625 } 3626 3627 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3628 3629 if (ni != NULL) 3630 ieee80211_free_node(ni); 3631 3632 if (m0 == NULL) { 3633 ifp->if_oerrors++; 3634 break; 3635 } 3636 3637 /* just to make sure. */ 3638 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3639 3640 if (m0 == NULL) { 3641 ifp->if_oerrors++; 3642 break; 3643 } 3644 3645 hh = mtod(m0, struct atw_frame *); 3646 wh = &hh->atw_ihdr; 3647 3648 /* Copy everything we need from the 802.11 header: 3649 * Frame Control; address 1, address 3, or addresses 3650 * 3 and 4. NIC fills in BSSID, SA. 3651 */ 3652 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3653 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3654 panic("%s: illegal WDS frame", 3655 device_xname(sc->sc_dev)); 3656 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3657 } else 3658 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3659 3660 *(uint16_t*)hh->atw_fc = *(uint16_t*)wh->i_fc; 3661 3662 /* initialize remaining Tx parameters */ 3663 memset(&hh->u, 0, sizeof(hh->u)); 3664 3665 hh->atw_rate = rate * 5; 3666 /* XXX this could be incorrect if M_FCS. _encap should 3667 * probably strip FCS just in case it sticks around in 3668 * bridged packets. 3669 */ 3670 hh->atw_service = 0x00; /* XXX guess */ 3671 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3672 sizeof(struct atw_frame)); 3673 3674 /* never fragment multicast frames */ 3675 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3676 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3677 else { 3678 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3679 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3680 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3681 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3682 } 3683 3684 hh->atw_rtylmt = 3; 3685 #if 0 3686 if (do_encrypt) { 3687 hdrctl |= htole16(ATW_HDRCTL_WEP); 3688 hh->atw_keyid = ic->ic_def_txkey; 3689 } 3690 #endif 3691 3692 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3693 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3694 if (txs->txs_d0.d_residue) 3695 hh->atw_head_plcplen |= htole16(0x8000); 3696 if (txs->txs_dn.d_residue) 3697 hh->atw_tail_plcplen |= htole16(0x8000); 3698 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3699 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3700 3701 hh->atw_hdrctl = hdrctl; 3702 hh->atw_fragnum = npkt << 4; 3703 #ifdef ATW_DEBUG 3704 3705 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3706 printf("%s: dst = %s, rate = 0x%02x, " 3707 "service = 0x%02x, paylen = 0x%04x\n", 3708 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3709 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3710 3711 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3712 "dur1 = 0x%04x, dur2 = 0x%04x, " 3713 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3714 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3715 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3716 hh->atw_tail_dur, hh->atw_head_dur); 3717 3718 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3719 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3720 device_xname(sc->sc_dev), hh->atw_hdrctl, 3721 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3722 3723 printf("%s: keyid = %d\n", 3724 device_xname(sc->sc_dev), hh->atw_keyid); 3725 3726 atw_dump_pkt(ifp, m0); 3727 } 3728 #endif /* ATW_DEBUG */ 3729 3730 dmamap = txs->txs_dmamap; 3731 3732 /* 3733 * Load the DMA map. Copy and try (once) again if the packet 3734 * didn't fit in the alloted number of segments. 3735 */ 3736 for (first = 1; 3737 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3738 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 && first; 3739 first = 0) { 3740 MGETHDR(m, M_DONTWAIT, MT_DATA); 3741 if (m == NULL) { 3742 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3743 break; 3744 } 3745 if (m0->m_pkthdr.len > MHLEN) { 3746 MCLGET(m, M_DONTWAIT); 3747 if ((m->m_flags & M_EXT) == 0) { 3748 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3749 "cluster\n"); 3750 m_freem(m); 3751 break; 3752 } 3753 } 3754 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3755 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3756 m_freem(m0); 3757 m0 = m; 3758 m = NULL; 3759 } 3760 if (error != 0) { 3761 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3762 "error = %d\n", error); 3763 m_freem(m0); 3764 break; 3765 } 3766 3767 /* 3768 * Ensure we have enough descriptors free to describe 3769 * the packet. 3770 */ 3771 if (dmamap->dm_nsegs > sc->sc_txfree) { 3772 /* 3773 * Not enough free descriptors to transmit 3774 * this packet. Unload the DMA map and 3775 * drop the packet. Notify the upper layer 3776 * that there are no more slots left. 3777 * 3778 * XXX We could allocate an mbuf and copy, but 3779 * XXX it is worth it? 3780 */ 3781 bus_dmamap_unload(sc->sc_dmat, dmamap); 3782 m_freem(m0); 3783 break; 3784 } 3785 3786 /* 3787 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3788 */ 3789 3790 /* Sync the DMA map. */ 3791 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3792 BUS_DMASYNC_PREWRITE); 3793 3794 /* XXX arbitrary retry limit; 8 because I have seen it in 3795 * use already and maybe 0 means "no tries" ! 3796 */ 3797 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3798 3799 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3800 device_xname(sc->sc_dev), rate * 5)); 3801 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3802 3803 /* 3804 * Initialize the transmit descriptors. 3805 */ 3806 for (nexttx = sc->sc_txnext, seg = 0; 3807 seg < dmamap->dm_nsegs; 3808 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3809 /* 3810 * If this is the first descriptor we're 3811 * enqueueing, don't set the OWN bit just 3812 * yet. That could cause a race condition. 3813 * We'll do it below. 3814 */ 3815 txd = &sc->sc_txdescs[nexttx]; 3816 txd->at_ctl = ctl | 3817 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3818 3819 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3820 txd->at_flags = 3821 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3822 ATW_TXFLAG_TBS1_MASK)) | 3823 ((nexttx == (ATW_NTXDESC - 1)) 3824 ? htole32(ATW_TXFLAG_TER) : 0); 3825 lasttx = nexttx; 3826 } 3827 3828 /* Set `first segment' and `last segment' appropriately. */ 3829 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3830 htole32(ATW_TXFLAG_FS); 3831 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3832 3833 #ifdef ATW_DEBUG 3834 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3835 printf(" txsoft %p transmit chain:\n", txs); 3836 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3837 printf(" descriptor %d:\n", seg); 3838 printf(" at_ctl: 0x%08x\n", 3839 le32toh(sc->sc_txdescs[seg].at_ctl)); 3840 printf(" at_flags: 0x%08x\n", 3841 le32toh(sc->sc_txdescs[seg].at_flags)); 3842 printf(" at_buf1: 0x%08x\n", 3843 le32toh(sc->sc_txdescs[seg].at_buf1)); 3844 printf(" at_buf2: 0x%08x\n", 3845 le32toh(sc->sc_txdescs[seg].at_buf2)); 3846 if (seg == lasttx) 3847 break; 3848 } 3849 } 3850 #endif 3851 3852 /* Sync the descriptors we're using. */ 3853 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3854 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3855 3856 /* 3857 * Store a pointer to the packet so we can free it later, 3858 * and remember what txdirty will be once the packet is 3859 * done. 3860 */ 3861 txs->txs_mbuf = m0; 3862 txs->txs_firstdesc = sc->sc_txnext; 3863 txs->txs_lastdesc = lasttx; 3864 txs->txs_ndescs = dmamap->dm_nsegs; 3865 3866 /* Advance the tx pointer. */ 3867 sc->sc_txfree -= dmamap->dm_nsegs; 3868 sc->sc_txnext = nexttx; 3869 3870 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3871 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3872 } 3873 3874 if (sc->sc_txfree != ofree) { 3875 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3876 device_xname(sc->sc_dev), lasttx, firsttx)); 3877 /* 3878 * Cause a transmit interrupt to happen on the 3879 * last packet we enqueued. 3880 */ 3881 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3882 ATW_CDTXSYNC(sc, lasttx, 1, 3883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3884 3885 /* 3886 * The entire packet chain is set up. Give the 3887 * first descriptor to the chip now. 3888 */ 3889 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3890 ATW_CDTXSYNC(sc, firsttx, 1, 3891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3892 3893 /* Wake up the transmitter. */ 3894 ATW_WRITE(sc, ATW_TDR, 0x1); 3895 3896 if (txs == NULL || sc->sc_txfree == 0) 3897 ifp->if_flags |= IFF_OACTIVE; 3898 3899 /* Set a watchdog timer in case the chip flakes out. */ 3900 sc->sc_tx_timer = 5; 3901 ifp->if_timer = 1; 3902 } 3903 } 3904 3905 /* 3906 * atw_ioctl: [ifnet interface function] 3907 * 3908 * Handle control requests from the operator. 3909 */ 3910 int 3911 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3912 { 3913 struct atw_softc *sc = ifp->if_softc; 3914 struct ieee80211req *ireq; 3915 int s, error = 0; 3916 3917 s = splnet(); 3918 3919 switch (cmd) { 3920 case SIOCSIFFLAGS: 3921 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3922 break; 3923 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3924 case IFF_UP | IFF_RUNNING: 3925 /* 3926 * To avoid rescanning another access point, 3927 * do not call atw_init() here. Instead, 3928 * only reflect media settings. 3929 */ 3930 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3931 atw_filter_setup(sc); 3932 break; 3933 case IFF_UP: 3934 error = atw_init(ifp); 3935 break; 3936 case IFF_RUNNING: 3937 atw_stop(ifp, 1); 3938 break; 3939 case 0: 3940 break; 3941 } 3942 break; 3943 case SIOCADDMULTI: 3944 case SIOCDELMULTI: 3945 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3946 if (ifp->if_flags & IFF_RUNNING) 3947 atw_filter_setup(sc); /* do not rescan */ 3948 error = 0; 3949 } 3950 break; 3951 case SIOCS80211: 3952 ireq = data; 3953 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3954 if ((error = kauth_authorize_network(curlwp->l_cred, 3955 KAUTH_NETWORK_INTERFACE, 3956 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3957 (void *)cmd, NULL)) != 0) 3958 break; 3959 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3960 ireq->i_val <= IEEE80211_FRAG_MAX)) 3961 error = EINVAL; 3962 else 3963 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3964 break; 3965 } 3966 /*FALLTHROUGH*/ 3967 default: 3968 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3969 if (error == ENETRESET || error == ERESTART) { 3970 if (is_running(ifp)) 3971 error = atw_init(ifp); 3972 else 3973 error = 0; 3974 } 3975 break; 3976 } 3977 3978 /* Try to get more packets going. */ 3979 if (device_is_active(sc->sc_dev)) 3980 atw_start(ifp); 3981 3982 splx(s); 3983 return (error); 3984 } 3985 3986 static int 3987 atw_media_change(struct ifnet *ifp) 3988 { 3989 int error; 3990 3991 error = ieee80211_media_change(ifp); 3992 if (error == ENETRESET) { 3993 if (is_running(ifp)) 3994 error = atw_init(ifp); 3995 else 3996 error = 0; 3997 } 3998 return error; 3999 } 4000
Indexes created Sun Sep 21 20:09:37 GMT 2025