atw.c revision 1.23
1 /* $NetBSD: atw.c,v 1.23 2004/01/29 10:25:49 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.23 2004/01/29 10:25:49 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/atwvar.h> 82 #include <dev/ic/smc93cx6var.h> 83 84 /* XXX TBD open questions 85 * 86 * 87 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 88 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 89 * handle this for me? 90 * 91 */ 92 /* device attachment 93 * 94 * print TOFS[012] 95 * 96 * device initialization 97 * 98 * clear ATW_FRCTL_MAXPSP to disable max power saving 99 * set ATW_TXBR_ALCUPDATE to enable ALC 100 * set TOFS[012]? (hope not) 101 * disable rx/tx 102 * set ATW_PAR_SWR (software reset) 103 * wait for ATW_PAR_SWR clear 104 * disable interrupts 105 * ack status register 106 * enable interrupts 107 * 108 * rx/tx initialization 109 * 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * allocate and init descriptor rings 112 * write ATW_PAR_DSL (descriptor skip length) 113 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * write ATW_NAR_SQ for one/both transmit descriptor rings 116 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * 118 * rx/tx end 119 * 120 * stop DMA 121 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 122 * flush tx w/ ATW_NAR_HF 123 * 124 * scan 125 * 126 * initialize rx/tx 127 * 128 * IBSS join/create 129 * 130 * set ATW_NAR_EA (is set by ASIC?) 131 * 132 * BSS join: (re)association response 133 * 134 * set ATW_FRCTL_AID 135 * 136 * optimizations ??? 137 * 138 */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_rfio_enable_delay = 20 * 1000; 145 int atw_rfio_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 5; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 150 #ifdef ATW_DEBUG 151 int atw_xhdrctl = 0; 152 int atw_xrtylmt = ~0; 153 int atw_xservice = IEEE80211_PLCP_SERVICE; 154 int atw_xpaylen = 0; 155 156 int atw_debug = 0; 157 158 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 159 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 160 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 161 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 162 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 163 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 164 static void atw_print_regs(struct atw_softc *, const char *); 165 static void atw_rf3000_print(struct atw_softc *); 166 static void atw_si4126_print(struct atw_softc *); 167 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 168 #else 169 #define ATW_DPRINTF(x) 170 #define ATW_DPRINTF2(x) 171 #define ATW_DPRINTF3(x) 172 #define DPRINTF(sc, x) /* nothing */ 173 #define DPRINTF2(sc, x) /* nothing */ 174 #define DPRINTF3(sc, x) /* nothing */ 175 #endif 176 177 #ifdef ATW_STATS 178 void atw_print_stats(struct atw_softc *); 179 #endif 180 181 void atw_start(struct ifnet *); 182 void atw_watchdog(struct ifnet *); 183 int atw_ioctl(struct ifnet *, u_long, caddr_t); 184 int atw_init(struct ifnet *); 185 void atw_stop(struct ifnet *, int); 186 187 void atw_reset(struct atw_softc *); 188 int atw_read_srom(struct atw_softc *); 189 190 void atw_shutdown(void *); 191 192 void atw_rxdrain(struct atw_softc *); 193 int atw_add_rxbuf(struct atw_softc *, int); 194 void atw_idle(struct atw_softc *, u_int32_t); 195 196 int atw_enable(struct atw_softc *); 197 void atw_disable(struct atw_softc *); 198 void atw_power(int, void *); 199 200 void atw_rxintr(struct atw_softc *); 201 void atw_txintr(struct atw_softc *); 202 void atw_linkintr(struct atw_softc *, u_int32_t); 203 204 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 205 static void atw_tsf(struct atw_softc *); 206 static void atw_start_beacon(struct atw_softc *, int); 207 static void atw_write_wep(struct atw_softc *); 208 static void atw_write_bssid(struct atw_softc *); 209 static void atw_write_bcn_thresh(struct atw_softc *); 210 static void atw_write_ssid(struct atw_softc *); 211 static void atw_write_sup_rates(struct atw_softc *); 212 static void atw_clear_sram(struct atw_softc *); 213 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 214 static int atw_media_change(struct ifnet *); 215 static void atw_media_status(struct ifnet *, struct ifmediareq *); 216 static void atw_filter_setup(struct atw_softc *); 217 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 218 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 219 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 224 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 225 226 static int atw_tune(struct atw_softc *); 227 228 static void atw_rfio_enable(struct atw_softc *, int); 229 230 /* RFMD RF3000 Baseband Processor */ 231 static int atw_rf3000_init(struct atw_softc *); 232 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 233 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 234 #ifdef ATW_DEBUG 235 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 236 #endif /* ATW_DEBUG */ 237 238 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 239 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 240 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 241 #ifdef ATW_DEBUG 242 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 243 #endif /* ATW_DEBUG */ 244 245 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 246 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 247 248 const char *atw_tx_state[] = { 249 "STOPPED", 250 "RUNNING - FETCH", 251 "RUNNING - WAIT", 252 "RUNNING - READING", 253 "-- RESERVED1 --", 254 "-- RESERVED2 --", 255 "SUSPENDED", 256 "RUNNING - CLOSE" 257 }; 258 259 const char *atw_rx_state[] = { 260 "STOPPED", 261 "RUNNING - FETCH", 262 "RUNNING - CHECK", 263 "RUNNING - WAIT", 264 "SUSPENDED", 265 "RUNNING - CLOSE", 266 "RUNNING - FLUSH", 267 "RUNNING - QUEUE" 268 }; 269 270 int 271 atw_activate(struct device *self, enum devact act) 272 { 273 struct atw_softc *sc = (struct atw_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 282 case DVACT_DEACTIVATE: 283 if_deactivate(&sc->sc_ic.ic_if); 284 break; 285 } 286 splx(s); 287 return rv; 288 } 289 290 /* 291 * atw_enable: 292 * 293 * Enable the ADM8211 chip. 294 */ 295 int 296 atw_enable(struct atw_softc *sc) 297 { 298 299 if (ATW_IS_ENABLED(sc) == 0) { 300 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 301 printf("%s: device enable failed\n", 302 sc->sc_dev.dv_xname); 303 return (EIO); 304 } 305 sc->sc_flags |= ATWF_ENABLED; 306 } 307 return (0); 308 } 309 310 /* 311 * atw_disable: 312 * 313 * Disable the ADM8211 chip. 314 */ 315 void 316 atw_disable(struct atw_softc *sc) 317 { 318 if (!ATW_IS_ENABLED(sc)) 319 return; 320 if (sc->sc_disable != NULL) 321 (*sc->sc_disable)(sc); 322 sc->sc_flags &= ~ATWF_ENABLED; 323 } 324 325 /* Returns -1 on failure. */ 326 int 327 atw_read_srom(struct atw_softc *sc) 328 { 329 struct seeprom_descriptor sd; 330 u_int32_t reg; 331 332 (void)memset(&sd, 0, sizeof(sd)); 333 334 reg = ATW_READ(sc, ATW_TEST0); 335 336 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 337 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 338 return -1; 339 } 340 341 switch (reg & ATW_TEST0_EPTYP_MASK) { 342 case ATW_TEST0_EPTYP_93c66: 343 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 344 sc->sc_sromsz = 512; 345 sd.sd_chip = C56_66; 346 break; 347 case ATW_TEST0_EPTYP_93c46: 348 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 349 sc->sc_sromsz = 128; 350 sd.sd_chip = C46; 351 break; 352 default: 353 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 354 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 355 return -1; 356 } 357 358 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 359 360 if (sc->sc_srom == NULL) { 361 printf("%s: unable to allocate SROM buffer\n", 362 sc->sc_dev.dv_xname); 363 return -1; 364 } 365 366 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 367 368 /* ADM8211 has a single 32-bit register for controlling the 369 * 93cx6 SROM. Bit SRS enables the serial port. There is no 370 * "ready" bit. The ADM8211 input/output sense is the reverse 371 * of read_seeprom's. 372 */ 373 sd.sd_tag = sc->sc_st; 374 sd.sd_bsh = sc->sc_sh; 375 sd.sd_regsize = 4; 376 sd.sd_control_offset = ATW_SPR; 377 sd.sd_status_offset = ATW_SPR; 378 sd.sd_dataout_offset = ATW_SPR; 379 sd.sd_CK = ATW_SPR_SCLK; 380 sd.sd_CS = ATW_SPR_SCS; 381 sd.sd_DI = ATW_SPR_SDO; 382 sd.sd_DO = ATW_SPR_SDI; 383 sd.sd_MS = ATW_SPR_SRS; 384 sd.sd_RDY = 0; 385 386 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 387 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 388 free(sc->sc_srom, M_DEVBUF); 389 return -1; 390 } 391 #ifdef ATW_DEBUG 392 { 393 int i; 394 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 395 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 396 if (((i % 8) == 0) && (i != 0)) { 397 ATW_DPRINTF(("\n\t")); 398 } 399 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 400 } 401 ATW_DPRINTF(("\n")); 402 } 403 #endif /* ATW_DEBUG */ 404 return 0; 405 } 406 407 #ifdef ATW_DEBUG 408 static void 409 atw_print_regs(struct atw_softc *sc, const char *where) 410 { 411 #define PRINTREG(sc, reg) \ 412 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 413 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 414 415 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 416 417 PRINTREG(sc, ATW_PAR); 418 PRINTREG(sc, ATW_FRCTL); 419 PRINTREG(sc, ATW_TDR); 420 PRINTREG(sc, ATW_WTDP); 421 PRINTREG(sc, ATW_RDR); 422 PRINTREG(sc, ATW_WRDP); 423 PRINTREG(sc, ATW_RDB); 424 PRINTREG(sc, ATW_CSR3A); 425 PRINTREG(sc, ATW_TDBD); 426 PRINTREG(sc, ATW_TDBP); 427 PRINTREG(sc, ATW_STSR); 428 PRINTREG(sc, ATW_CSR5A); 429 PRINTREG(sc, ATW_NAR); 430 PRINTREG(sc, ATW_CSR6A); 431 PRINTREG(sc, ATW_IER); 432 PRINTREG(sc, ATW_CSR7A); 433 PRINTREG(sc, ATW_LPC); 434 PRINTREG(sc, ATW_TEST1); 435 PRINTREG(sc, ATW_SPR); 436 PRINTREG(sc, ATW_TEST0); 437 PRINTREG(sc, ATW_WCSR); 438 PRINTREG(sc, ATW_WPDR); 439 PRINTREG(sc, ATW_GPTMR); 440 PRINTREG(sc, ATW_GPIO); 441 PRINTREG(sc, ATW_BBPCTL); 442 PRINTREG(sc, ATW_SYNCTL); 443 PRINTREG(sc, ATW_PLCPHD); 444 PRINTREG(sc, ATW_MMIWADDR); 445 PRINTREG(sc, ATW_MMIRADDR1); 446 PRINTREG(sc, ATW_MMIRADDR2); 447 PRINTREG(sc, ATW_TXBR); 448 PRINTREG(sc, ATW_CSR15A); 449 PRINTREG(sc, ATW_ALCSTAT); 450 PRINTREG(sc, ATW_TOFS2); 451 PRINTREG(sc, ATW_CMDR); 452 PRINTREG(sc, ATW_PCIC); 453 PRINTREG(sc, ATW_PMCSR); 454 PRINTREG(sc, ATW_PAR0); 455 PRINTREG(sc, ATW_PAR1); 456 PRINTREG(sc, ATW_MAR0); 457 PRINTREG(sc, ATW_MAR1); 458 PRINTREG(sc, ATW_ATIMDA0); 459 PRINTREG(sc, ATW_ABDA1); 460 PRINTREG(sc, ATW_BSSID0); 461 PRINTREG(sc, ATW_TXLMT); 462 PRINTREG(sc, ATW_MIBCNT); 463 PRINTREG(sc, ATW_BCNT); 464 PRINTREG(sc, ATW_TSFTH); 465 PRINTREG(sc, ATW_TSC); 466 PRINTREG(sc, ATW_SYNRF); 467 PRINTREG(sc, ATW_BPLI); 468 PRINTREG(sc, ATW_CAP0); 469 PRINTREG(sc, ATW_CAP1); 470 PRINTREG(sc, ATW_RMD); 471 PRINTREG(sc, ATW_CFPP); 472 PRINTREG(sc, ATW_TOFS0); 473 PRINTREG(sc, ATW_TOFS1); 474 PRINTREG(sc, ATW_IFST); 475 PRINTREG(sc, ATW_RSPT); 476 PRINTREG(sc, ATW_TSFTL); 477 PRINTREG(sc, ATW_WEPCTL); 478 PRINTREG(sc, ATW_WESK); 479 PRINTREG(sc, ATW_WEPCNT); 480 PRINTREG(sc, ATW_MACTEST); 481 PRINTREG(sc, ATW_FER); 482 PRINTREG(sc, ATW_FEMR); 483 PRINTREG(sc, ATW_FPSR); 484 PRINTREG(sc, ATW_FFER); 485 #undef PRINTREG 486 } 487 #endif /* ATW_DEBUG */ 488 489 /* 490 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 491 */ 492 void 493 atw_attach(struct atw_softc *sc) 494 { 495 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 496 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 497 }; 498 struct ieee80211com *ic = &sc->sc_ic; 499 struct ifnet *ifp = &ic->ic_if; 500 int country_code, error, i, nrate; 501 u_int32_t reg; 502 static const char *type_strings[] = {"Intersil (not supported)", 503 "RFMD", "Marvel (not supported)"}; 504 505 sc->sc_txth = atw_txthresh_tab_lo; 506 507 SIMPLEQ_INIT(&sc->sc_txfreeq); 508 SIMPLEQ_INIT(&sc->sc_txdirtyq); 509 510 #ifdef ATW_DEBUG 511 atw_print_regs(sc, "atw_attach"); 512 #endif /* ATW_DEBUG */ 513 514 /* 515 * Allocate the control data structures, and create and load the 516 * DMA map for it. 517 */ 518 if ((error = bus_dmamem_alloc(sc->sc_dmat, 519 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 520 1, &sc->sc_cdnseg, 0)) != 0) { 521 printf("%s: unable to allocate control data, error = %d\n", 522 sc->sc_dev.dv_xname, error); 523 goto fail_0; 524 } 525 526 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 527 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 528 BUS_DMA_COHERENT)) != 0) { 529 printf("%s: unable to map control data, error = %d\n", 530 sc->sc_dev.dv_xname, error); 531 goto fail_1; 532 } 533 534 if ((error = bus_dmamap_create(sc->sc_dmat, 535 sizeof(struct atw_control_data), 1, 536 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 537 printf("%s: unable to create control data DMA map, " 538 "error = %d\n", sc->sc_dev.dv_xname, error); 539 goto fail_2; 540 } 541 542 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 543 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 544 0)) != 0) { 545 printf("%s: unable to load control data DMA map, error = %d\n", 546 sc->sc_dev.dv_xname, error); 547 goto fail_3; 548 } 549 550 /* 551 * Create the transmit buffer DMA maps. 552 */ 553 sc->sc_ntxsegs = ATW_NTXSEGS; 554 for (i = 0; i < ATW_TXQUEUELEN; i++) { 555 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 556 sc->sc_ntxsegs, MCLBYTES, 0, 0, 557 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 558 printf("%s: unable to create tx DMA map %d, " 559 "error = %d\n", sc->sc_dev.dv_xname, i, error); 560 goto fail_4; 561 } 562 } 563 564 /* 565 * Create the receive buffer DMA maps. 566 */ 567 for (i = 0; i < ATW_NRXDESC; i++) { 568 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 569 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 570 printf("%s: unable to create rx DMA map %d, " 571 "error = %d\n", sc->sc_dev.dv_xname, i, error); 572 goto fail_5; 573 } 574 } 575 for (i = 0; i < ATW_NRXDESC; i++) { 576 sc->sc_rxsoft[i].rxs_mbuf = NULL; 577 } 578 579 /* Reset the chip to a known state. */ 580 atw_reset(sc); 581 582 if (atw_read_srom(sc) == -1) 583 return; 584 585 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 586 ATW_SR_RFTYPE_MASK); 587 588 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 589 ATW_SR_BBPTYPE_MASK); 590 591 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 592 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 600 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 601 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 602 603 /* XXX There exists a Linux driver which seems to use RFType = 0 for 604 * MARVEL. My bug, or theirs? 605 */ 606 607 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 608 609 switch (sc->sc_rftype) { 610 case ATW_RFTYPE_INTERSIL: 611 reg |= ATW_SYNCTL_CS1; 612 break; 613 case ATW_RFTYPE_RFMD: 614 reg |= ATW_SYNCTL_CS0; 615 break; 616 case ATW_RFTYPE_MARVEL: 617 break; 618 } 619 620 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 621 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 622 623 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 624 625 switch (sc->sc_bbptype) { 626 case ATW_RFTYPE_INTERSIL: 627 reg |= ATW_BBPCTL_TWI; 628 break; 629 case ATW_RFTYPE_RFMD: 630 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 631 ATW_BBPCTL_CCA_ACTLO; 632 break; 633 case ATW_RFTYPE_MARVEL: 634 break; 635 } 636 637 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 638 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 639 640 /* 641 * From this point forward, the attachment cannot fail. A failure 642 * before this point releases all resources that may have been 643 * allocated. 644 */ 645 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 646 647 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 648 htole16(sc->sc_srom[ATW_SR_MAC00]), 649 htole16(sc->sc_srom[ATW_SR_MAC01]), 650 htole16(sc->sc_srom[ATW_SR_MAC10]))); 651 652 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 653 ATW_SR_CTRY_MASK); 654 655 #define ADD_CHANNEL(_ic, _chan) do { \ 656 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 657 _ic->ic_channels[_chan].ic_freq = \ 658 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 659 } while (0) 660 661 /* Find available channels */ 662 switch (country_code) { 663 case COUNTRY_MMK2: /* 1-14 */ 664 ADD_CHANNEL(ic, 14); 665 /*FALLTHROUGH*/ 666 case COUNTRY_ETSI: /* 1-13 */ 667 for (i = 1; i <= 13; i++) 668 ADD_CHANNEL(ic, i); 669 break; 670 case COUNTRY_FCC: /* 1-11 */ 671 case COUNTRY_IC: /* 1-11 */ 672 for (i = 1; i <= 11; i++) 673 ADD_CHANNEL(ic, i); 674 break; 675 case COUNTRY_MMK: /* 14 */ 676 ADD_CHANNEL(ic, 14); 677 break; 678 case COUNTRY_FRANCE: /* 10-13 */ 679 for (i = 10; i <= 13; i++) 680 ADD_CHANNEL(ic, i); 681 break; 682 default: /* assume channels 10-11 */ 683 case COUNTRY_SPAIN: /* 10-11 */ 684 for (i = 10; i <= 11; i++) 685 ADD_CHANNEL(ic, i); 686 break; 687 } 688 689 /* Read the MAC address. */ 690 reg = ATW_READ(sc, ATW_PAR0); 691 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 692 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 693 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 694 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 695 reg = ATW_READ(sc, ATW_PAR1); 696 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 697 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 698 699 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 700 printf(" could not get mac address, attach failed\n"); 701 return; 702 } 703 704 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 705 706 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 707 ifp->if_softc = sc; 708 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 709 IFF_NOTRAILERS; 710 ifp->if_ioctl = atw_ioctl; 711 ifp->if_start = atw_start; 712 ifp->if_watchdog = atw_watchdog; 713 ifp->if_init = atw_init; 714 ifp->if_stop = atw_stop; 715 IFQ_SET_READY(&ifp->if_snd); 716 717 ic->ic_phytype = IEEE80211_T_DS; 718 ic->ic_opmode = IEEE80211_M_STA; 719 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 720 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 721 722 nrate = 0; 723 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 724 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 728 729 /* 730 * Call MI attach routines. 731 */ 732 733 if_attach(ifp); 734 ieee80211_ifattach(ifp); 735 736 sc->sc_newstate = ic->ic_newstate; 737 ic->ic_newstate = atw_newstate; 738 739 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 740 ic->ic_recv_mgmt = atw_recv_mgmt; 741 742 sc->sc_node_free = ic->ic_node_free; 743 ic->ic_node_free = atw_node_free; 744 745 sc->sc_node_alloc = ic->ic_node_alloc; 746 ic->ic_node_alloc = atw_node_alloc; 747 748 /* possibly we should fill in our own sc_send_prresp, since 749 * the ADM8211 is probably sending probe responses in ad hoc 750 * mode. 751 */ 752 753 /* complete initialization */ 754 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 755 callout_init(&sc->sc_scan_ch); 756 757 #if NBPFILTER > 0 758 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 759 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 760 #endif 761 762 /* 763 * Make sure the interface is shutdown during reboot. 764 */ 765 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 766 if (sc->sc_sdhook == NULL) 767 printf("%s: WARNING: unable to establish shutdown hook\n", 768 sc->sc_dev.dv_xname); 769 770 /* 771 * Add a suspend hook to make sure we come back up after a 772 * resume. 773 */ 774 sc->sc_powerhook = powerhook_establish(atw_power, sc); 775 if (sc->sc_powerhook == NULL) 776 printf("%s: WARNING: unable to establish power hook\n", 777 sc->sc_dev.dv_xname); 778 779 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 780 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 781 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 782 783 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 784 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 785 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 786 787 return; 788 789 /* 790 * Free any resources we've allocated during the failed attach 791 * attempt. Do this in reverse order and fall through. 792 */ 793 fail_5: 794 for (i = 0; i < ATW_NRXDESC; i++) { 795 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 796 continue; 797 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 798 } 799 fail_4: 800 for (i = 0; i < ATW_TXQUEUELEN; i++) { 801 if (sc->sc_txsoft[i].txs_dmamap == NULL) 802 continue; 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 804 } 805 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 806 fail_3: 807 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 808 fail_2: 809 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 810 sizeof(struct atw_control_data)); 811 fail_1: 812 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 813 fail_0: 814 return; 815 } 816 817 static struct ieee80211_node * 818 atw_node_alloc(struct ieee80211com *ic) 819 { 820 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 821 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 822 823 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 824 return ni; 825 } 826 827 static void 828 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 829 { 830 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 831 832 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 833 ether_sprintf(ni->ni_bssid))); 834 (*sc->sc_node_free)(ic, ni); 835 } 836 837 /* 838 * atw_reset: 839 * 840 * Perform a soft reset on the ADM8211. 841 */ 842 void 843 atw_reset(struct atw_softc *sc) 844 { 845 int i; 846 847 if (ATW_IS_ENABLED(sc) == 0) 848 return; 849 850 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 851 852 for (i = 0; i < 10000; i++) { 853 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 854 break; 855 DELAY(1); 856 } 857 858 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 859 860 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 861 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 862 863 /* Turn off maximum power saving. */ 864 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 865 866 /* Recall EEPROM. */ 867 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 868 869 DELAY(10 * 1000); 870 871 /* A reset seems to affect the SRAM contents, so put them into 872 * a known state. 873 */ 874 atw_clear_sram(sc); 875 876 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 877 878 sc->sc_lost_bcn_thresh = 0; 879 } 880 881 static void 882 atw_clear_sram(struct atw_softc *sc) 883 { 884 #if 0 885 for (addr = 0; addr < 448; addr++) { 886 ATW_WRITE(sc, ATW_WEPCTL, 887 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 888 DELAY(1000); 889 ATW_WRITE(sc, ATW_WESK, 0); 890 DELAY(1000); /* paranoia */ 891 } 892 return; 893 #endif 894 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 895 /* XXX not for revision 0x20. */ 896 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 897 } 898 899 /* TBD atw_init 900 * 901 * set MAC based on ic->ic_bss->myaddr 902 * write WEP keys 903 * set TX rate 904 */ 905 906 /* 907 * atw_init: [ ifnet interface function ] 908 * 909 * Initialize the interface. Must be called at splnet(). 910 */ 911 int 912 atw_init(struct ifnet *ifp) 913 { 914 struct atw_softc *sc = ifp->if_softc; 915 struct ieee80211com *ic = &sc->sc_ic; 916 struct atw_txsoft *txs; 917 struct atw_rxsoft *rxs; 918 u_int32_t reg; 919 int i, error = 0; 920 921 if ((error = atw_enable(sc)) != 0) 922 goto out; 923 924 /* 925 * Cancel any pending I/O. This also resets. 926 */ 927 atw_stop(ifp, 0); 928 929 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 930 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 931 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 932 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 933 934 /* Turn off APM??? (A binary-only driver does this.) 935 * 936 * Set Rx store-and-forward mode. 937 */ 938 reg = ATW_READ(sc, ATW_CMDR); 939 reg &= ~ATW_CMDR_APM; 940 reg &= ~ATW_CMDR_DRT_MASK; 941 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 942 943 ATW_WRITE(sc, ATW_CMDR, reg); 944 945 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 946 * 947 * XXX a binary-only driver sets a different service field than 948 * 0. why? 949 */ 950 reg = ATW_READ(sc, ATW_PLCPHD); 951 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 952 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 953 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 954 ATW_WRITE(sc, ATW_PLCPHD, reg); 955 956 /* XXX this magic can probably be figured out from the RFMD docs */ 957 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 958 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 959 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 960 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 961 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 962 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 963 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 964 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 965 ATW_WRITE(sc, ATW_TOFS2, reg); 966 967 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 968 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 969 970 /* XXX this resets an Intersil RF front-end? */ 971 /* TBD condition on Intersil RFType? */ 972 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 973 DELAY(10 * 1000); 974 ATW_WRITE(sc, ATW_SYNRF, 0); 975 DELAY(5 * 1000); 976 977 /* 16 TU max duration for contention-free period */ 978 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 979 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 980 981 /* XXX I guess that the Cardbus clock is 22MHz? 982 * I am assuming that the role of ATW_TOFS0_USCNT is 983 * to divide the bus clock to get a 1MHz clock---the datasheet is not 984 * very clear on this point. It says in the datasheet that it is 985 * possible for the ADM8211 to accomodate bus speeds between 22MHz 986 * and 33MHz; maybe this is the way? I see a binary-only driver write 987 * these values. These values are also the power-on default. 988 */ 989 ATW_WRITE(sc, ATW_TOFS0, 990 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 991 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 992 993 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 994 * driver. Go figure. 995 */ 996 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 997 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 998 ATW_IFST_SIFS_MASK) | 999 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1000 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1001 1002 ATW_WRITE(sc, ATW_IFST, reg); 1003 1004 /* XXX More magic. Might relate to ACK timing. */ 1005 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1006 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1007 1008 /* Set up the MMI read/write addresses for the BBP. 1009 * 1010 * TBD find out the Marvel settings. 1011 */ 1012 switch (sc->sc_bbptype) { 1013 case ATW_BBPTYPE_INTERSIL: 1014 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1015 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1016 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1017 break; 1018 case ATW_BBPTYPE_MARVEL: 1019 break; 1020 case ATW_BBPTYPE_RFMD: 1021 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1022 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1023 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1024 default: 1025 break; 1026 } 1027 1028 sc->sc_wepctl = 0; 1029 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1030 1031 if ((error = atw_rf3000_init(sc)) != 0) 1032 goto out; 1033 1034 /* 1035 * Initialize the PCI Access Register. 1036 */ 1037 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1038 1039 /* 1040 * If we're allowed to do so, use Memory Read Line 1041 * and Memory Read Multiple. 1042 * 1043 * XXX Should we use Memory Write and Invalidate? 1044 */ 1045 if (sc->sc_flags & ATWF_MRL) 1046 sc->sc_busmode |= ATW_PAR_MRLE; 1047 if (sc->sc_flags & ATWF_MRM) 1048 sc->sc_busmode |= ATW_PAR_MRME; 1049 if (sc->sc_flags & ATWF_MWI) 1050 sc->sc_busmode |= ATW_PAR_MWIE; 1051 if (sc->sc_maxburst == 0) 1052 sc->sc_maxburst = 8; /* ADM8211 default */ 1053 1054 switch (sc->sc_cacheline) { 1055 default: 1056 /* Use burst length. */ 1057 break; 1058 case 8: 1059 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1060 break; 1061 case 16: 1062 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1063 break; 1064 case 32: 1065 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1066 break; 1067 } 1068 switch (sc->sc_maxburst) { 1069 case 1: 1070 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1071 break; 1072 case 2: 1073 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1074 break; 1075 case 4: 1076 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1077 break; 1078 case 8: 1079 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1080 break; 1081 case 16: 1082 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1083 break; 1084 case 32: 1085 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1086 break; 1087 default: 1088 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1089 break; 1090 } 1091 1092 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1093 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1094 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1095 1096 /* 1097 * Initialize the OPMODE register. We don't write it until 1098 * we're ready to begin the transmit and receive processes. 1099 */ 1100 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1101 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1102 1103 /* 1104 * Initialize the transmit descriptor ring. 1105 */ 1106 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1107 for (i = 0; i < ATW_NTXDESC; i++) { 1108 /* no transmit chaining */ 1109 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1110 sc->sc_txdescs[i].at_buf2 = 1111 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1112 } 1113 /* use ring mode */ 1114 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1115 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1116 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1117 sc->sc_txfree = ATW_NTXDESC; 1118 sc->sc_txnext = 0; 1119 1120 /* 1121 * Initialize the transmit job descriptors. 1122 */ 1123 SIMPLEQ_INIT(&sc->sc_txfreeq); 1124 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1125 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1126 txs = &sc->sc_txsoft[i]; 1127 txs->txs_mbuf = NULL; 1128 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1129 } 1130 1131 /* 1132 * Initialize the receive descriptor and receive job 1133 * descriptor rings. 1134 */ 1135 for (i = 0; i < ATW_NRXDESC; i++) { 1136 rxs = &sc->sc_rxsoft[i]; 1137 if (rxs->rxs_mbuf == NULL) { 1138 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1139 printf("%s: unable to allocate or map rx " 1140 "buffer %d, error = %d\n", 1141 sc->sc_dev.dv_xname, i, error); 1142 /* 1143 * XXX Should attempt to run with fewer receive 1144 * XXX buffers instead of just failing. 1145 */ 1146 atw_rxdrain(sc); 1147 goto out; 1148 } 1149 } else 1150 ATW_INIT_RXDESC(sc, i); 1151 } 1152 sc->sc_rxptr = 0; 1153 1154 /* disable all wake-up events */ 1155 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1156 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1157 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1158 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1159 1160 /* ack all wake-up events */ 1161 ATW_SET(sc, ATW_WCSR, 0); 1162 1163 /* 1164 * Initialize the interrupt mask and enable interrupts. 1165 */ 1166 /* normal interrupts */ 1167 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1168 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1169 1170 /* abnormal interrupts */ 1171 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1172 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1173 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1174 1175 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1176 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1177 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1178 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1179 ATW_INTR_TRT; 1180 1181 sc->sc_linkint_mask &= sc->sc_inten; 1182 sc->sc_rxint_mask &= sc->sc_inten; 1183 sc->sc_txint_mask &= sc->sc_inten; 1184 1185 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1186 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1187 if (sc->sc_intr_ack != NULL) 1188 (*sc->sc_intr_ack)(sc); 1189 1190 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1191 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1192 1193 /* 1194 * Give the transmit and receive rings to the ADM8211. 1195 */ 1196 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1197 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1198 1199 /* common 802.11 configuration */ 1200 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1201 switch (ic->ic_opmode) { 1202 case IEEE80211_M_STA: 1203 sc->sc_opmode &= ~ATW_NAR_EA; 1204 break; 1205 case IEEE80211_M_AHDEMO: /* XXX */ 1206 case IEEE80211_M_IBSS: 1207 ic->ic_flags |= IEEE80211_F_IBSSON; 1208 /*FALLTHROUGH*/ 1209 case IEEE80211_M_HOSTAP: /* XXX */ 1210 /* EA bit seems important for ad hoc reception. */ 1211 sc->sc_opmode |= ATW_NAR_EA; 1212 break; 1213 case IEEE80211_M_MONITOR: /* XXX */ 1214 break; 1215 } 1216 1217 atw_start_beacon(sc, 0); 1218 1219 switch (ic->ic_opmode) { 1220 case IEEE80211_M_AHDEMO: 1221 case IEEE80211_M_HOSTAP: 1222 ic->ic_bss->ni_intval = ic->ic_lintval; 1223 ic->ic_bss->ni_rssi = 0; 1224 ic->ic_bss->ni_rstamp = 0; 1225 break; 1226 default: /* XXX */ 1227 break; 1228 } 1229 1230 atw_write_ssid(sc); 1231 atw_write_sup_rates(sc); 1232 if (ic->ic_caps & IEEE80211_C_WEP) 1233 atw_write_wep(sc); 1234 1235 /* 1236 * Set the receive filter. This will start the transmit and 1237 * receive processes. 1238 */ 1239 atw_filter_setup(sc); 1240 1241 /* 1242 * Start the receive process. 1243 */ 1244 ATW_WRITE(sc, ATW_RDR, 0x1); 1245 1246 /* 1247 * Note that the interface is now running. 1248 */ 1249 ifp->if_flags |= IFF_RUNNING; 1250 ifp->if_flags &= ~IFF_OACTIVE; 1251 ic->ic_state = IEEE80211_S_INIT; 1252 1253 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1254 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1255 else 1256 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1257 out: 1258 if (error) { 1259 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1260 ifp->if_timer = 0; 1261 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1262 } 1263 #ifdef ATW_DEBUG 1264 atw_print_regs(sc, "end of init"); 1265 #endif /* ATW_DEBUG */ 1266 1267 return (error); 1268 } 1269 1270 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1271 * 0: MAC control of RF3000/Si4126. 1272 * 1273 * Applies power, or selects RF front-end? Sets reset condition. 1274 * 1275 * TBD support non-RFMD BBP, non-SiLabs synth. 1276 */ 1277 static void 1278 atw_rfio_enable(struct atw_softc *sc, int enable) 1279 { 1280 if (enable) { 1281 ATW_WRITE(sc, ATW_SYNRF, 1282 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1283 DELAY(atw_rfio_enable_delay); 1284 } else { 1285 ATW_WRITE(sc, ATW_SYNRF, 0); 1286 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1287 } 1288 } 1289 1290 static int 1291 atw_tune(struct atw_softc *sc) 1292 { 1293 int rc; 1294 u_int32_t reg; 1295 int chan; 1296 struct ieee80211com *ic = &sc->sc_ic; 1297 1298 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1299 if (chan == IEEE80211_CHAN_ANY) 1300 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1301 1302 if (chan == sc->sc_cur_chan) 1303 return 0; 1304 1305 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1306 sc->sc_cur_chan, chan)); 1307 1308 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1309 1310 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1311 (rc = atw_rf3000_tune(sc, chan)) != 0) 1312 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1313 chan); 1314 1315 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1316 ATW_WRITE(sc, ATW_CAP0, 1317 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1318 1319 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1320 1321 if (rc == 0) 1322 sc->sc_cur_chan = chan; 1323 1324 return rc; 1325 } 1326 1327 #ifdef ATW_DEBUG 1328 static void 1329 atw_si4126_print(struct atw_softc *sc) 1330 { 1331 struct ifnet *ifp = &sc->sc_ic.ic_if; 1332 u_int addr, val; 1333 1334 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1335 return; 1336 1337 for (addr = 0; addr <= 8; addr++) { 1338 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1339 if (atw_si4126_read(sc, addr, &val) == 0) { 1340 printf("<unknown> (quitting print-out)\n"); 1341 break; 1342 } 1343 printf("%05x\n", val); 1344 } 1345 } 1346 #endif /* ATW_DEBUG */ 1347 1348 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1349 * 1350 * The RF/IF synthesizer produces two reference frequencies for 1351 * the RF2948B transceiver. The first frequency the RF2948B requires 1352 * is two times the so-called "intermediate frequency" (IF). Since 1353 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1354 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1355 * frequency required by the transceiver is the radio frequency 1356 * (RF). This is a superheterodyne transceiver; for f(chan) the 1357 * center frequency of the channel we are tuning, RF = f(chan) - 1358 * IF. 1359 * 1360 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1361 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1362 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1363 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1364 */ 1365 static int 1366 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1367 { 1368 int rc = 0; 1369 u_int mhz; 1370 u_int R; 1371 u_int32_t reg; 1372 u_int16_t gain; 1373 1374 #ifdef ATW_DEBUG 1375 atw_si4126_print(sc); 1376 #endif /* ATW_DEBUG */ 1377 1378 if (chan == 14) 1379 mhz = 2484; 1380 else 1381 mhz = 2412 + 5 * (chan - 1); 1382 1383 /* Tune IF to 748MHz to suit the IF LO input of the 1384 * RF2494B, which is 2 x IF. No need to set an IF divider 1385 * because an IF in 526MHz - 952MHz is allowed. 1386 * 1387 * XIN is 44.000MHz, so divide it by two to get allowable 1388 * range of 2-25MHz. SiLabs tells me that this is not 1389 * strictly necessary. 1390 */ 1391 1392 R = 44; 1393 1394 atw_rfio_enable(sc, 1); 1395 1396 /* Power-up RF, IF synthesizers. */ 1397 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1398 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1399 goto out; 1400 1401 /* If RF2 N > 2047, then set KP2 to 1. */ 1402 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1403 1404 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1405 goto out; 1406 1407 /* set LPWR, too? */ 1408 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1409 SI4126_MAIN_XINDIV2)) != 0) 1410 goto out; 1411 1412 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1413 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1414 */ 1415 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1416 goto out; 1417 1418 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1419 goto out; 1420 1421 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1422 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1423 * which has no RF1! 1424 */ 1425 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1426 goto out; 1427 1428 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1429 goto out; 1430 1431 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1432 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1433 * Now let's multiply it to mhz. So mhz - IF = N. 1434 */ 1435 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1436 goto out; 1437 1438 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1439 goto out; 1440 1441 /* wait 100us from power-up for RF, IF to settle */ 1442 DELAY(100); 1443 1444 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1445 /* XXX there is a binary driver which sends 1446 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1447 * that this enables the Si4126 by raising its PWDN#, but I 1448 * think that it actually sets the Prism RF front-end 1449 * to a special mode for channel 14. 1450 */ 1451 reg = ATW_READ(sc, ATW_GPIO); 1452 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1453 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1454 ATW_WRITE(sc, ATW_GPIO, reg); 1455 } 1456 1457 #ifdef ATW_DEBUG 1458 atw_si4126_print(sc); 1459 #endif /* ATW_DEBUG */ 1460 1461 out: 1462 atw_rfio_enable(sc, 0); 1463 1464 return rc; 1465 } 1466 1467 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1468 * diversity. 1469 * 1470 * Call this w/ Tx/Rx suspended. 1471 */ 1472 static int 1473 atw_rf3000_init(struct atw_softc *sc) 1474 { 1475 int rc = 0; 1476 1477 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1478 1479 atw_rfio_enable(sc, 1); 1480 1481 /* enable diversity */ 1482 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1483 1484 if (rc != 0) 1485 goto out; 1486 1487 /* sensible setting from a binary-only driver */ 1488 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1489 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1490 1491 if (rc != 0) 1492 goto out; 1493 1494 /* magic from a binary-only driver */ 1495 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1496 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1502 1503 if (rc != 0) 1504 goto out; 1505 1506 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1507 1508 if (rc != 0) 1509 goto out; 1510 1511 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1512 1513 if (rc != 0) 1514 goto out; 1515 1516 /* CCA is acquisition sensitive */ 1517 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1518 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1519 1520 if (rc != 0) 1521 goto out; 1522 1523 out: 1524 atw_rfio_enable(sc, 0); 1525 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1526 return rc; 1527 } 1528 1529 #ifdef ATW_DEBUG 1530 static void 1531 atw_rf3000_print(struct atw_softc *sc) 1532 { 1533 struct ifnet *ifp = &sc->sc_ic.ic_if; 1534 u_int addr, val; 1535 1536 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1537 return; 1538 1539 for (addr = 0x01; addr <= 0x15; addr++) { 1540 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1541 if (atw_rf3000_read(sc, addr, &val) != 0) { 1542 printf("<unknown> (quitting print-out)\n"); 1543 break; 1544 } 1545 printf("%08x\n", val); 1546 } 1547 } 1548 #endif /* ATW_DEBUG */ 1549 1550 /* Set the power settings on the BBP for channel `chan'. */ 1551 static int 1552 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1553 { 1554 int rc = 0; 1555 u_int32_t reg; 1556 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1557 1558 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1559 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1560 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1561 1562 /* odd channels: LSB, even channels: MSB */ 1563 if (chan % 2 == 1) { 1564 txpower &= 0xFF; 1565 lpf_cutoff &= 0xFF; 1566 lna_gs_thresh &= 0xFF; 1567 } else { 1568 txpower >>= 8; 1569 lpf_cutoff >>= 8; 1570 lna_gs_thresh >>= 8; 1571 } 1572 1573 #ifdef ATW_DEBUG 1574 atw_rf3000_print(sc); 1575 #endif /* ATW_DEBUG */ 1576 1577 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1578 "lna_gs_thresh %02x\n", 1579 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1580 1581 atw_rfio_enable(sc, 1); 1582 1583 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1584 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1585 goto out; 1586 1587 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1588 goto out; 1589 1590 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1591 goto out; 1592 1593 /* from a binary-only driver. */ 1594 reg = ATW_READ(sc, ATW_PLCPHD); 1595 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1596 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1597 ATW_WRITE(sc, ATW_PLCPHD, reg); 1598 1599 #ifdef ATW_DEBUG 1600 atw_rf3000_print(sc); 1601 #endif /* ATW_DEBUG */ 1602 1603 out: 1604 atw_rfio_enable(sc, 0); 1605 1606 return rc; 1607 } 1608 1609 /* Write a register on the RF3000 baseband processor using the 1610 * registers provided by the ADM8211 for this purpose. 1611 * 1612 * Return 0 on success. 1613 */ 1614 static int 1615 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1616 { 1617 u_int32_t reg; 1618 int i; 1619 1620 for (i = 1000; --i >= 0; ) { 1621 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1622 break; 1623 DELAY(100); 1624 } 1625 1626 if (i < 0) { 1627 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1628 return ETIMEDOUT; 1629 } 1630 1631 reg = sc->sc_bbpctl_wr | 1632 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1633 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1634 1635 ATW_WRITE(sc, ATW_BBPCTL, reg); 1636 1637 for (i = 1000; --i >= 0; ) { 1638 DELAY(100); 1639 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1640 break; 1641 } 1642 1643 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1644 1645 if (i < 0) { 1646 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1647 return ETIMEDOUT; 1648 } 1649 return 0; 1650 } 1651 1652 /* Read a register on the RF3000 baseband processor using the registers 1653 * the ADM8211 provides for this purpose. 1654 * 1655 * The 7-bit register address is addr. Record the 8-bit data in the register 1656 * in *val. 1657 * 1658 * Return 0 on success. 1659 * 1660 * XXX This does not seem to work. The ADM8211 must require more or 1661 * different magic to read the chip than to write it. Possibly some 1662 * of the magic I have derived from a binary-only driver concerns 1663 * the "chip address" (see the RF3000 manual). 1664 */ 1665 #ifdef ATW_DEBUG 1666 static int 1667 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1668 { 1669 u_int32_t reg; 1670 int i; 1671 1672 for (i = 1000; --i >= 0; ) { 1673 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1674 break; 1675 DELAY(100); 1676 } 1677 1678 if (i < 0) { 1679 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1680 sc->sc_dev.dv_xname); 1681 return ETIMEDOUT; 1682 } 1683 1684 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1685 1686 ATW_WRITE(sc, ATW_BBPCTL, reg); 1687 1688 for (i = 1000; --i >= 0; ) { 1689 DELAY(100); 1690 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1691 break; 1692 } 1693 1694 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1695 1696 if (i < 0) { 1697 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1698 sc->sc_dev.dv_xname, reg); 1699 return ETIMEDOUT; 1700 } 1701 if (val != NULL) 1702 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1703 return 0; 1704 } 1705 #endif /* ATW_DEBUG */ 1706 1707 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1708 * provided by the ADM8211 for that purpose. 1709 * 1710 * val is 18 bits of data, and val is the 4-bit address of the register. 1711 * 1712 * Return 0 on success. 1713 */ 1714 static int 1715 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1716 { 1717 u_int32_t reg; 1718 int i; 1719 1720 for (i = 1000; --i >= 0; ) { 1721 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1722 break; 1723 DELAY(100); 1724 } 1725 1726 if (i < 0) { 1727 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1728 sc->sc_dev.dv_xname); 1729 return ETIMEDOUT; 1730 } 1731 1732 reg = sc->sc_synctl_wr | 1733 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1734 1735 ATW_WRITE(sc, ATW_SYNCTL, reg); 1736 1737 for (i = 1000; --i >= 0; ) { 1738 DELAY(100); 1739 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1740 break; 1741 } 1742 1743 /* restore to acceptable starting condition */ 1744 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1745 1746 if (i < 0) { 1747 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1748 sc->sc_dev.dv_xname, reg); 1749 return ETIMEDOUT; 1750 } 1751 return 0; 1752 } 1753 1754 /* Read 18-bit data from the 4-bit address addr in Si4126 1755 * RF synthesizer and write the data to *val. Return 0 on success. 1756 * 1757 * XXX This does not seem to work. The ADM8211 must require more or 1758 * different magic to read the chip than to write it. 1759 */ 1760 #ifdef ATW_DEBUG 1761 static int 1762 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1763 { 1764 u_int32_t reg; 1765 int i; 1766 1767 for (i = 1000; --i >= 0; ) { 1768 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1769 break; 1770 DELAY(100); 1771 } 1772 1773 if (i < 0) { 1774 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1775 sc->sc_dev.dv_xname); 1776 return ETIMEDOUT; 1777 } 1778 1779 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1780 1781 ATW_WRITE(sc, ATW_SYNCTL, reg); 1782 1783 for (i = 1000; --i >= 0; ) { 1784 DELAY(100); 1785 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1786 break; 1787 } 1788 1789 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1790 1791 if (i < 0) { 1792 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1793 sc->sc_dev.dv_xname, reg); 1794 return ETIMEDOUT; 1795 } 1796 if (val != NULL) 1797 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1798 ATW_SYNCTL_DATA_MASK); 1799 return 0; 1800 } 1801 #endif /* ATW_DEBUG */ 1802 1803 /* XXX is the endianness correct? test. */ 1804 #define atw_calchash(addr) \ 1805 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1806 1807 /* 1808 * atw_filter_setup: 1809 * 1810 * Set the ADM8211's receive filter. 1811 */ 1812 static void 1813 atw_filter_setup(struct atw_softc *sc) 1814 { 1815 struct ieee80211com *ic = &sc->sc_ic; 1816 struct ethercom *ec = &ic->ic_ec; 1817 struct ifnet *ifp = &sc->sc_ic.ic_if; 1818 int hash; 1819 u_int32_t hashes[2] = { 0, 0 }; 1820 struct ether_multi *enm; 1821 struct ether_multistep step; 1822 1823 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1824 sc->sc_dev.dv_xname, sc->sc_flags)); 1825 1826 /* 1827 * If we're running, idle the receive engine. If we're NOT running, 1828 * we're being called from atw_init(), and our writing ATW_NAR will 1829 * start the transmit and receive processes in motion. 1830 */ 1831 if (ifp->if_flags & IFF_RUNNING) 1832 atw_idle(sc, ATW_NAR_SR); 1833 1834 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1835 1836 ifp->if_flags &= ~IFF_ALLMULTI; 1837 1838 if (ifp->if_flags & IFF_PROMISC) { 1839 sc->sc_opmode |= ATW_NAR_PR; 1840 allmulti: 1841 ifp->if_flags |= IFF_ALLMULTI; 1842 goto setit; 1843 } 1844 1845 /* 1846 * Program the 64-bit multicast hash filter. 1847 */ 1848 ETHER_FIRST_MULTI(step, ec, enm); 1849 while (enm != NULL) { 1850 /* XXX */ 1851 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1852 ETHER_ADDR_LEN) != 0) 1853 goto allmulti; 1854 1855 hash = atw_calchash(enm->enm_addrlo); 1856 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1857 ETHER_NEXT_MULTI(step, enm); 1858 } 1859 1860 if (ifp->if_flags & IFF_BROADCAST) { 1861 hash = atw_calchash(etherbroadcastaddr); 1862 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1863 } 1864 1865 /* all bits set => hash is useless */ 1866 if (~(hashes[0] & hashes[1]) == 0) 1867 goto allmulti; 1868 1869 setit: 1870 if (ifp->if_flags & IFF_ALLMULTI) 1871 sc->sc_opmode |= ATW_NAR_MM; 1872 1873 /* XXX in scan mode, do not filter packets. maybe this is 1874 * unnecessary. 1875 */ 1876 if (ic->ic_state == IEEE80211_S_SCAN) 1877 sc->sc_opmode |= ATW_NAR_PR; 1878 1879 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1880 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1881 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1882 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1883 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1884 1885 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1886 } 1887 1888 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1889 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1890 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1891 * no beacon with the preferred BSSID and SSID in the number of 1892 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1893 */ 1894 static void 1895 atw_write_bssid(struct atw_softc *sc) 1896 { 1897 struct ieee80211com *ic = &sc->sc_ic; 1898 u_int8_t *bssid; 1899 1900 bssid = ic->ic_bss->ni_bssid; 1901 1902 ATW_WRITE(sc, ATW_ABDA1, 1903 (ATW_READ(sc, ATW_ABDA1) & 1904 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1905 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1906 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1907 1908 ATW_WRITE(sc, ATW_BSSID0, 1909 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1910 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1911 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1912 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1913 1914 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1915 ether_sprintf(sc->sc_bssid))); 1916 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1917 1918 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1919 } 1920 1921 /* Tell the ADM8211 how many beacon intervals must pass without 1922 * receiving a beacon with the preferred BSSID & SSID set by 1923 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1924 * raised. 1925 */ 1926 static void 1927 atw_write_bcn_thresh(struct atw_softc *sc) 1928 { 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 int lost_bcn_thresh; 1931 1932 /* Lose link after one second or 7 beacons, whichever comes 1933 * first, but do not lose link before 2 beacons are lost. 1934 * 1935 * In host AP mode, set the lost-beacon threshold to 0. 1936 */ 1937 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1938 lost_bcn_thresh = 0; 1939 else { 1940 int beacons_per_second = 1941 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1942 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1943 } 1944 1945 /* XXX resets wake-up status bits */ 1946 ATW_WRITE(sc, ATW_WCSR, 1947 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1948 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1949 1950 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1951 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1952 1953 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1954 1955 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1956 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1957 } 1958 1959 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1960 * 16-bit word. 1961 */ 1962 static void 1963 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1964 { 1965 u_int i; 1966 u_int8_t *ptr; 1967 1968 memcpy(&sc->sc_sram[ofs], buf, buflen); 1969 1970 if (ofs % 2 != 0) { 1971 ofs--; 1972 buflen++; 1973 } 1974 1975 if (buflen % 2 != 0) 1976 buflen++; 1977 1978 assert(buflen + ofs <= ATW_SRAM_SIZE); 1979 1980 ptr = &sc->sc_sram[ofs]; 1981 1982 for (i = 0; i < buflen; i += 2) { 1983 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1984 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1985 DELAY(atw_writewep_delay); 1986 1987 ATW_WRITE(sc, ATW_WESK, 1988 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1989 DELAY(atw_writewep_delay); 1990 } 1991 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1992 1993 if (sc->sc_if.if_flags & IFF_DEBUG) { 1994 int n_octets = 0; 1995 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1996 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1997 for (i = 0; i < buflen; i++) { 1998 printf(" %02x", ptr[i]); 1999 if (++n_octets % 24 == 0) 2000 printf("\n"); 2001 } 2002 if (n_octets % 24 != 0) 2003 printf("\n"); 2004 } 2005 } 2006 2007 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2008 static void 2009 atw_write_wep(struct atw_softc *sc) 2010 { 2011 struct ieee80211com *ic = &sc->sc_ic; 2012 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2013 u_int8_t buf[IEEE80211_WEP_NKID] 2014 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2015 u_int32_t reg; 2016 int i; 2017 2018 sc->sc_wepctl = 0; 2019 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2020 2021 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2022 return; 2023 2024 memset(&buf[0][0], 0, sizeof(buf)); 2025 2026 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2027 if (ic->ic_nw_keys[i].wk_len > 5) { 2028 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2029 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2030 buf[i][1] = ATW_WEP_ENABLED; 2031 } else { 2032 buf[i][1] = 0; 2033 continue; 2034 } 2035 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2036 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2037 ic->ic_nw_keys[i].wk_len - 1); 2038 } 2039 2040 reg = ATW_READ(sc, ATW_MACTEST); 2041 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2042 reg &= ~ATW_MACTEST_KEYID_MASK; 2043 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2044 ATW_WRITE(sc, ATW_MACTEST, reg); 2045 2046 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2047 * throughout.) 2048 */ 2049 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2050 if (sc->sc_if.if_flags & IFF_LINK2) 2051 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2052 2053 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2054 sizeof(buf)); 2055 } 2056 2057 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2058 2059 static void 2060 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2061 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2062 { 2063 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2064 2065 switch (subtype) { 2066 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2067 /* do nothing: hardware answers probe request */ 2068 break; 2069 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2070 case IEEE80211_FC0_SUBTYPE_BEACON: 2071 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2072 break; 2073 default: 2074 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2075 break; 2076 } 2077 return; 2078 } 2079 2080 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2081 * of IBSSs with like SSID/channel but different BSSID. It joins the 2082 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2083 * convention. Possibly the ADMtek chip does this for us; I will have 2084 * to test to find out. 2085 * 2086 * XXX we should add the duration field of the received beacon to 2087 * the TSF time it contains before comparing it with the ADM8211's 2088 * TSF. 2089 */ 2090 static void 2091 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2092 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2093 { 2094 struct atw_softc *sc; 2095 struct ieee80211_frame *wh; 2096 u_int64_t tsft, bcn_tsft; 2097 u_int32_t tsftl, tsfth; 2098 int do_print = 0; 2099 2100 sc = (struct atw_softc*)ic->ic_if.if_softc; 2101 2102 if (ic->ic_if.if_flags & IFF_DEBUG) 2103 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2104 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2105 2106 wh = mtod(m0, struct ieee80211_frame *); 2107 2108 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2109 2110 if (ic->ic_state != IEEE80211_S_RUN) { 2111 if (do_print) 2112 printf("%s: atw_recv_beacon: not running\n", 2113 sc->sc_dev.dv_xname); 2114 return; 2115 } 2116 2117 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2118 ic->ic_bss->ni_chan)) == NULL) { 2119 if (do_print) 2120 printf("%s: atw_recv_beacon: no node %s\n", 2121 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2122 return; 2123 } 2124 2125 if (ieee80211_match_bss(ic, ni) != 0) { 2126 if (do_print) 2127 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2128 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2129 return; 2130 } 2131 2132 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2133 return; 2134 2135 if (do_print) 2136 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2137 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2138 2139 if (ic->ic_opmode != IEEE80211_M_IBSS) 2140 return; 2141 2142 /* If we read TSFTL right before rollover, we read a TSF timer 2143 * that is too high rather than too low. This prevents a spurious 2144 * synchronization down the line, however, our IBSS could suffer 2145 * from a creeping TSF.... 2146 */ 2147 tsftl = ATW_READ(sc, ATW_TSFTL); 2148 tsfth = ATW_READ(sc, ATW_TSFTH); 2149 2150 tsft = (u_int64_t)tsfth << 32 | tsftl; 2151 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2152 2153 if (do_print) 2154 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2155 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2156 2157 /* we are faster, let the other guy catch up */ 2158 if (bcn_tsft < tsft) 2159 return; 2160 2161 if (do_print) 2162 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2163 ether_sprintf(wh->i_addr2)); 2164 2165 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2166 2167 #if 0 2168 atw_tsf(sc); 2169 #endif 2170 2171 /* negotiate rates with new IBSS */ 2172 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2173 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2174 if (ni->ni_rates.rs_nrates == 0) { 2175 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2176 ether_sprintf(ni->ni_bssid)); 2177 return; 2178 } 2179 2180 if (do_print) { 2181 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2182 ether_sprintf(ic->ic_bss->ni_bssid)); 2183 printf("%s ", ether_sprintf(ni->ni_bssid)); 2184 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2185 } 2186 2187 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2188 2189 atw_write_bssid(sc); 2190 atw_write_bcn_thresh(sc); 2191 atw_start_beacon(sc, 1); 2192 } 2193 2194 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2195 * In ad hoc mode, the SSID is written to the beacons sent by the 2196 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2197 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2198 * indications. 2199 */ 2200 static void 2201 atw_write_ssid(struct atw_softc *sc) 2202 { 2203 struct ieee80211com *ic = &sc->sc_ic; 2204 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2205 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2206 2207 memset(buf, 0, sizeof(buf)); 2208 buf[0] = ic->ic_bss->ni_esslen; 2209 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2210 2211 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2212 } 2213 2214 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2215 * In ad hoc mode, the supported rates are written to beacons sent by the 2216 * ADM8211. 2217 */ 2218 static void 2219 atw_write_sup_rates(struct atw_softc *sc) 2220 { 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2223 * supported rates 2224 */ 2225 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2226 2227 memset(buf, 0, sizeof(buf)); 2228 2229 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2230 2231 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2232 ic->ic_bss->ni_rates.rs_nrates); 2233 2234 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2235 } 2236 2237 /* Start/stop sending beacons. */ 2238 void 2239 atw_start_beacon(struct atw_softc *sc, int start) 2240 { 2241 struct ieee80211com *ic = &sc->sc_ic; 2242 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2243 2244 if (ATW_IS_ENABLED(sc) == 0) 2245 return; 2246 2247 len = capinfo = 0; 2248 2249 /* start beacons */ 2250 len = sizeof(struct ieee80211_frame) + 2251 8 /* timestamp */ + 2 /* beacon interval */ + 2252 2 /* capability info */ + 2253 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2254 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2255 3 /* DS parameters */ + 2256 IEEE80211_CRC_LEN; 2257 2258 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2259 2260 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2261 2262 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2263 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2264 2265 if (!start) 2266 return; 2267 2268 /* TBD use ni_capinfo */ 2269 2270 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2271 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2272 if (ic->ic_flags & IEEE80211_F_WEPON) 2273 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2274 2275 switch (ic->ic_opmode) { 2276 case IEEE80211_M_IBSS: 2277 len += 4; /* IBSS parameters */ 2278 capinfo |= IEEE80211_CAPINFO_IBSS; 2279 break; 2280 case IEEE80211_M_HOSTAP: 2281 /* XXX 6-byte minimum TIM */ 2282 len += atw_beacon_len_adjust; 2283 capinfo |= IEEE80211_CAPINFO_ESS; 2284 break; 2285 default: 2286 return; 2287 } 2288 2289 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2290 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2291 2292 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2293 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2294 2295 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2296 sc->sc_dev.dv_xname, reg_bcnt)); 2297 2298 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2299 sc->sc_dev.dv_xname, reg_cap1)); 2300 } 2301 2302 /* First beacon was sent at time 0 microseconds, current time is 2303 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2304 * microseconds. Return the expected time in microseconds for the 2305 * beacon after next. 2306 */ 2307 static __inline u_int64_t 2308 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2309 { 2310 return tsft + (tbtt - tsft % tbtt); 2311 } 2312 2313 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2314 * the ieee80211com. 2315 * 2316 * Predict the next target beacon transmission time (TBTT) and 2317 * write it to the ADM8211. 2318 */ 2319 static void 2320 atw_tsf(struct atw_softc *sc) 2321 { 2322 #define TBTTOFS 20 /* TU */ 2323 2324 struct ieee80211com *ic = &sc->sc_ic; 2325 u_int64_t tsft, tbtt; 2326 2327 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2328 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2329 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2330 tsft = ATW_READ(sc, ATW_TSFTH); 2331 tsft <<= 32; 2332 tsft |= ATW_READ(sc, ATW_TSFTL); 2333 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2334 } else 2335 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2336 2337 tbtt = atw_predict_beacon(tsft, 2338 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2339 2340 /* skip one more beacon so that the TBTT cannot pass before 2341 * we've programmed it, and also so that we can subtract a 2342 * few TU so that we wake a little before TBTT. 2343 */ 2344 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2345 2346 /* wake up a little early */ 2347 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2348 2349 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2350 sc->sc_dev.dv_xname, tsft, tbtt)); 2351 2352 ATW_WRITE(sc, ATW_TOFS1, 2353 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2354 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2355 LSHIFT( 2356 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2357 ATW_TOFS1_TBTTPRE_MASK)); 2358 #undef TBTTOFS 2359 } 2360 2361 static void 2362 atw_next_scan(void *arg) 2363 { 2364 struct atw_softc *sc = arg; 2365 struct ieee80211com *ic = &sc->sc_ic; 2366 struct ifnet *ifp = &ic->ic_if; 2367 int s; 2368 2369 /* don't call atw_start w/o network interrupts blocked */ 2370 s = splnet(); 2371 if (ic->ic_state == IEEE80211_S_SCAN) 2372 ieee80211_next_scan(ifp); 2373 splx(s); 2374 } 2375 2376 /* Synchronize the hardware state with the software state. */ 2377 static int 2378 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2379 { 2380 struct ifnet *ifp = &ic->ic_if; 2381 struct atw_softc *sc = ifp->if_softc; 2382 enum ieee80211_state ostate; 2383 int error; 2384 2385 ostate = ic->ic_state; 2386 2387 if (nstate == IEEE80211_S_INIT) { 2388 callout_stop(&sc->sc_scan_ch); 2389 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2390 atw_start_beacon(sc, 0); 2391 return (*sc->sc_newstate)(ic, nstate, arg); 2392 } 2393 2394 if ((error = atw_tune(sc)) != 0) 2395 return error; 2396 2397 switch (nstate) { 2398 case IEEE80211_S_ASSOC: 2399 break; 2400 case IEEE80211_S_INIT: 2401 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2402 break; 2403 case IEEE80211_S_SCAN: 2404 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2405 atw_write_bssid(sc); 2406 2407 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2408 atw_next_scan, sc); 2409 2410 break; 2411 case IEEE80211_S_RUN: 2412 if (ic->ic_opmode == IEEE80211_M_STA) 2413 break; 2414 /*FALLTHROUGH*/ 2415 case IEEE80211_S_AUTH: 2416 atw_write_bssid(sc); 2417 atw_write_bcn_thresh(sc); 2418 atw_write_ssid(sc); 2419 atw_write_sup_rates(sc); 2420 2421 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2422 ic->ic_opmode == IEEE80211_M_MONITOR) 2423 break; 2424 2425 /* set listen interval 2426 * XXX do software units agree w/ hardware? 2427 */ 2428 ATW_WRITE(sc, ATW_BPLI, 2429 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2430 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2431 ATW_BPLI_LI_MASK)); 2432 2433 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2434 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2435 2436 atw_tsf(sc); 2437 break; 2438 } 2439 2440 if (nstate != IEEE80211_S_SCAN) 2441 callout_stop(&sc->sc_scan_ch); 2442 2443 if (nstate == IEEE80211_S_RUN && 2444 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2445 ic->ic_opmode == IEEE80211_M_IBSS)) 2446 atw_start_beacon(sc, 1); 2447 else 2448 atw_start_beacon(sc, 0); 2449 2450 return (*sc->sc_newstate)(ic, nstate, arg); 2451 } 2452 2453 /* 2454 * atw_add_rxbuf: 2455 * 2456 * Add a receive buffer to the indicated descriptor. 2457 */ 2458 int 2459 atw_add_rxbuf(struct atw_softc *sc, int idx) 2460 { 2461 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2462 struct mbuf *m; 2463 int error; 2464 2465 MGETHDR(m, M_DONTWAIT, MT_DATA); 2466 if (m == NULL) 2467 return (ENOBUFS); 2468 2469 MCLGET(m, M_DONTWAIT); 2470 if ((m->m_flags & M_EXT) == 0) { 2471 m_freem(m); 2472 return (ENOBUFS); 2473 } 2474 2475 if (rxs->rxs_mbuf != NULL) 2476 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2477 2478 rxs->rxs_mbuf = m; 2479 2480 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2481 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2482 BUS_DMA_READ|BUS_DMA_NOWAIT); 2483 if (error) { 2484 printf("%s: can't load rx DMA map %d, error = %d\n", 2485 sc->sc_dev.dv_xname, idx, error); 2486 panic("atw_add_rxbuf"); /* XXX */ 2487 } 2488 2489 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2490 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2491 2492 ATW_INIT_RXDESC(sc, idx); 2493 2494 return (0); 2495 } 2496 2497 /* 2498 * atw_stop: [ ifnet interface function ] 2499 * 2500 * Stop transmission on the interface. 2501 */ 2502 void 2503 atw_stop(struct ifnet *ifp, int disable) 2504 { 2505 struct atw_softc *sc = ifp->if_softc; 2506 struct ieee80211com *ic = &sc->sc_ic; 2507 struct atw_txsoft *txs; 2508 2509 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2510 2511 /* Disable interrupts. */ 2512 ATW_WRITE(sc, ATW_IER, 0); 2513 2514 /* Stop the transmit and receive processes. */ 2515 sc->sc_opmode = 0; 2516 ATW_WRITE(sc, ATW_NAR, 0); 2517 ATW_WRITE(sc, ATW_TDBD, 0); 2518 ATW_WRITE(sc, ATW_TDBP, 0); 2519 ATW_WRITE(sc, ATW_RDB, 0); 2520 2521 /* 2522 * Release any queued transmit buffers. 2523 */ 2524 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2525 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2526 if (txs->txs_mbuf != NULL) { 2527 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2528 m_freem(txs->txs_mbuf); 2529 txs->txs_mbuf = NULL; 2530 } 2531 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2532 } 2533 2534 if (disable) { 2535 atw_rxdrain(sc); 2536 atw_disable(sc); 2537 } 2538 2539 /* 2540 * Mark the interface down and cancel the watchdog timer. 2541 */ 2542 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2543 ifp->if_timer = 0; 2544 2545 /* XXX */ 2546 atw_reset(sc); 2547 } 2548 2549 /* 2550 * atw_rxdrain: 2551 * 2552 * Drain the receive queue. 2553 */ 2554 void 2555 atw_rxdrain(struct atw_softc *sc) 2556 { 2557 struct atw_rxsoft *rxs; 2558 int i; 2559 2560 for (i = 0; i < ATW_NRXDESC; i++) { 2561 rxs = &sc->sc_rxsoft[i]; 2562 if (rxs->rxs_mbuf == NULL) 2563 continue; 2564 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2565 m_freem(rxs->rxs_mbuf); 2566 rxs->rxs_mbuf = NULL; 2567 } 2568 } 2569 2570 /* 2571 * atw_detach: 2572 * 2573 * Detach an ADM8211 interface. 2574 */ 2575 int 2576 atw_detach(struct atw_softc *sc) 2577 { 2578 struct ifnet *ifp = &sc->sc_ic.ic_if; 2579 struct atw_rxsoft *rxs; 2580 struct atw_txsoft *txs; 2581 int i; 2582 2583 /* 2584 * Succeed now if there isn't any work to do. 2585 */ 2586 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2587 return (0); 2588 2589 ieee80211_ifdetach(ifp); 2590 if_detach(ifp); 2591 2592 for (i = 0; i < ATW_NRXDESC; i++) { 2593 rxs = &sc->sc_rxsoft[i]; 2594 if (rxs->rxs_mbuf != NULL) { 2595 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2596 m_freem(rxs->rxs_mbuf); 2597 rxs->rxs_mbuf = NULL; 2598 } 2599 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2600 } 2601 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2602 txs = &sc->sc_txsoft[i]; 2603 if (txs->txs_mbuf != NULL) { 2604 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2605 m_freem(txs->txs_mbuf); 2606 txs->txs_mbuf = NULL; 2607 } 2608 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2609 } 2610 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2611 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2612 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2613 sizeof(struct atw_control_data)); 2614 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2615 2616 shutdownhook_disestablish(sc->sc_sdhook); 2617 powerhook_disestablish(sc->sc_powerhook); 2618 2619 if (sc->sc_srom) 2620 free(sc->sc_srom, M_DEVBUF); 2621 2622 return (0); 2623 } 2624 2625 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2626 void 2627 atw_shutdown(void *arg) 2628 { 2629 struct atw_softc *sc = arg; 2630 2631 atw_stop(&sc->sc_ic.ic_if, 1); 2632 } 2633 2634 int 2635 atw_intr(void *arg) 2636 { 2637 struct atw_softc *sc = arg; 2638 struct ifnet *ifp = &sc->sc_ic.ic_if; 2639 u_int32_t status, rxstatus, txstatus, linkstatus; 2640 int handled = 0, txthresh; 2641 2642 #ifdef DEBUG 2643 if (ATW_IS_ENABLED(sc) == 0) 2644 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2645 #endif 2646 2647 /* 2648 * If the interface isn't running, the interrupt couldn't 2649 * possibly have come from us. 2650 */ 2651 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2652 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2653 return (0); 2654 2655 for (;;) { 2656 status = ATW_READ(sc, ATW_STSR); 2657 2658 if (status) 2659 ATW_WRITE(sc, ATW_STSR, status); 2660 2661 if (sc->sc_intr_ack != NULL) 2662 (*sc->sc_intr_ack)(sc); 2663 2664 #ifdef ATW_DEBUG 2665 #define PRINTINTR(flag) do { \ 2666 if ((status & flag) != 0) { \ 2667 printf("%s" #flag, delim); \ 2668 delim = ","; \ 2669 } \ 2670 } while (0) 2671 2672 if (atw_debug > 1 && status) { 2673 const char *delim = "<"; 2674 2675 printf("%s: reg[STSR] = %x", 2676 sc->sc_dev.dv_xname, status); 2677 2678 PRINTINTR(ATW_INTR_FBE); 2679 PRINTINTR(ATW_INTR_LINKOFF); 2680 PRINTINTR(ATW_INTR_LINKON); 2681 PRINTINTR(ATW_INTR_RCI); 2682 PRINTINTR(ATW_INTR_RDU); 2683 PRINTINTR(ATW_INTR_REIS); 2684 PRINTINTR(ATW_INTR_RPS); 2685 PRINTINTR(ATW_INTR_TCI); 2686 PRINTINTR(ATW_INTR_TDU); 2687 PRINTINTR(ATW_INTR_TLT); 2688 PRINTINTR(ATW_INTR_TPS); 2689 PRINTINTR(ATW_INTR_TRT); 2690 PRINTINTR(ATW_INTR_TUF); 2691 PRINTINTR(ATW_INTR_BCNTC); 2692 PRINTINTR(ATW_INTR_ATIME); 2693 PRINTINTR(ATW_INTR_TBTT); 2694 PRINTINTR(ATW_INTR_TSCZ); 2695 PRINTINTR(ATW_INTR_TSFTF); 2696 printf(">\n"); 2697 } 2698 #undef PRINTINTR 2699 #endif /* ATW_DEBUG */ 2700 2701 if ((status & sc->sc_inten) == 0) 2702 break; 2703 2704 handled = 1; 2705 2706 rxstatus = status & sc->sc_rxint_mask; 2707 txstatus = status & sc->sc_txint_mask; 2708 linkstatus = status & sc->sc_linkint_mask; 2709 2710 if (linkstatus) { 2711 atw_linkintr(sc, linkstatus); 2712 } 2713 2714 if (rxstatus) { 2715 /* Grab any new packets. */ 2716 atw_rxintr(sc); 2717 2718 if (rxstatus & ATW_INTR_RDU) { 2719 printf("%s: receive ring overrun\n", 2720 sc->sc_dev.dv_xname); 2721 /* Get the receive process going again. */ 2722 ATW_WRITE(sc, ATW_RDR, 0x1); 2723 break; 2724 } 2725 } 2726 2727 if (txstatus) { 2728 /* Sweep up transmit descriptors. */ 2729 atw_txintr(sc); 2730 2731 if (txstatus & ATW_INTR_TLT) 2732 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2733 sc->sc_dev.dv_xname)); 2734 2735 if (txstatus & ATW_INTR_TRT) 2736 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2737 sc->sc_dev.dv_xname)); 2738 2739 /* If Tx under-run, increase our transmit threshold 2740 * if another is available. 2741 */ 2742 txthresh = sc->sc_txthresh + 1; 2743 if ((txstatus & ATW_INTR_TUF) && 2744 sc->sc_txth[txthresh].txth_name != NULL) { 2745 /* Idle the transmit process. */ 2746 atw_idle(sc, ATW_NAR_ST); 2747 2748 sc->sc_txthresh = txthresh; 2749 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2750 sc->sc_opmode |= 2751 sc->sc_txth[txthresh].txth_opmode; 2752 printf("%s: transmit underrun; new " 2753 "threshold: %s\n", sc->sc_dev.dv_xname, 2754 sc->sc_txth[txthresh].txth_name); 2755 2756 /* Set the new threshold and restart 2757 * the transmit process. 2758 */ 2759 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2760 /* XXX Log every Nth underrun from 2761 * XXX now on? 2762 */ 2763 } 2764 } 2765 2766 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2767 if (status & ATW_INTR_TPS) 2768 printf("%s: transmit process stopped\n", 2769 sc->sc_dev.dv_xname); 2770 if (status & ATW_INTR_RPS) 2771 printf("%s: receive process stopped\n", 2772 sc->sc_dev.dv_xname); 2773 (void)atw_init(ifp); 2774 break; 2775 } 2776 2777 if (status & ATW_INTR_FBE) { 2778 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2779 (void)atw_init(ifp); 2780 break; 2781 } 2782 2783 /* 2784 * Not handled: 2785 * 2786 * Transmit buffer unavailable -- normal 2787 * condition, nothing to do, really. 2788 * 2789 * Early receive interrupt -- not available on 2790 * all chips, we just use RI. We also only 2791 * use single-segment receive DMA, so this 2792 * is mostly useless. 2793 * 2794 * TBD others 2795 */ 2796 } 2797 2798 /* Try to get more packets going. */ 2799 atw_start(ifp); 2800 2801 return (handled); 2802 } 2803 2804 /* 2805 * atw_idle: 2806 * 2807 * Cause the transmit and/or receive processes to go idle. 2808 * 2809 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2810 * process in STSR if I clear SR or ST after the process has already 2811 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2812 * do not seem to be too reliable. Perhaps I have the sense of the 2813 * Rx bits switched with the Tx bits? 2814 */ 2815 void 2816 atw_idle(struct atw_softc *sc, u_int32_t bits) 2817 { 2818 u_int32_t ackmask = 0, opmode, stsr, test0; 2819 int i, s; 2820 2821 /* without this, somehow we run concurrently w/ interrupt handler */ 2822 s = splnet(); 2823 2824 opmode = sc->sc_opmode & ~bits; 2825 2826 if (bits & ATW_NAR_SR) 2827 ackmask |= ATW_INTR_RPS; 2828 2829 if (bits & ATW_NAR_ST) { 2830 ackmask |= ATW_INTR_TPS; 2831 /* set ATW_NAR_HF to flush TX FIFO. */ 2832 opmode |= ATW_NAR_HF; 2833 } 2834 2835 ATW_WRITE(sc, ATW_NAR, opmode); 2836 2837 for (i = 0; i < 1000; i++) { 2838 stsr = ATW_READ(sc, ATW_STSR); 2839 if ((stsr & ackmask) == ackmask) 2840 break; 2841 DELAY(10); 2842 } 2843 2844 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2845 2846 if ((stsr & ackmask) == ackmask) 2847 goto out; 2848 2849 test0 = ATW_READ(sc, ATW_TEST0); 2850 2851 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2852 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2853 printf("%s: transmit process not idle [%s]\n", 2854 sc->sc_dev.dv_xname, 2855 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2856 printf("%s: bits %08x test0 %08x stsr %08x\n", 2857 sc->sc_dev.dv_xname, bits, test0, stsr); 2858 } 2859 2860 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2861 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2862 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2863 sc->sc_dev.dv_xname, 2864 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2865 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2866 sc->sc_dev.dv_xname, bits, test0, stsr)); 2867 } 2868 out: 2869 splx(s); 2870 return; 2871 } 2872 2873 /* 2874 * atw_linkintr: 2875 * 2876 * Helper; handle link-status interrupts. 2877 */ 2878 void 2879 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2880 { 2881 struct ieee80211com *ic = &sc->sc_ic; 2882 2883 if (ic->ic_state != IEEE80211_S_RUN) 2884 return; 2885 2886 if (linkstatus & ATW_INTR_LINKON) { 2887 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2888 sc->sc_rescan_timer = 0; 2889 } else if (linkstatus & ATW_INTR_LINKOFF) { 2890 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2891 switch (ic->ic_opmode) { 2892 case IEEE80211_M_HOSTAP: 2893 return; 2894 case IEEE80211_M_IBSS: 2895 if (ic->ic_flags & IEEE80211_F_SIBSS) 2896 return; 2897 /*FALLTHROUGH*/ 2898 case IEEE80211_M_STA: 2899 sc->sc_rescan_timer = 3; 2900 ic->ic_if.if_timer = 1; 2901 break; 2902 default: 2903 break; 2904 } 2905 } 2906 } 2907 2908 /* 2909 * atw_rxintr: 2910 * 2911 * Helper; handle receive interrupts. 2912 */ 2913 void 2914 atw_rxintr(struct atw_softc *sc) 2915 { 2916 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2917 struct ieee80211com *ic = &sc->sc_ic; 2918 struct ieee80211_node *ni; 2919 struct ieee80211_frame *wh; 2920 struct ifnet *ifp = &ic->ic_if; 2921 struct atw_rxsoft *rxs; 2922 struct mbuf *m; 2923 u_int32_t rxstat; 2924 int i, len, rate, rate0; 2925 u_int32_t rssi; 2926 2927 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2928 rxs = &sc->sc_rxsoft[i]; 2929 2930 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2931 2932 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2933 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2934 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2935 2936 if (rxstat & ATW_RXSTAT_OWN) 2937 break; /* We have processed all receive buffers. */ 2938 2939 DPRINTF3(sc, 2940 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2941 sc->sc_dev.dv_xname, 2942 sc->sc_rxdescs[i].ar_stat, 2943 sc->sc_rxdescs[i].ar_rssi, 2944 sc->sc_rxdescs[i].ar_buf1, 2945 sc->sc_rxdescs[i].ar_buf2)); 2946 2947 /* 2948 * Make sure the packet fit in one buffer. This should 2949 * always be the case. 2950 */ 2951 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2952 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2953 printf("%s: incoming packet spilled, resetting\n", 2954 sc->sc_dev.dv_xname); 2955 (void)atw_init(ifp); 2956 return; 2957 } 2958 2959 /* 2960 * If an error occurred, update stats, clear the status 2961 * word, and leave the packet buffer in place. It will 2962 * simply be reused the next time the ring comes around. 2963 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2964 * error. 2965 */ 2966 2967 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2968 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2969 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2970 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2971 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2972 ATW_RXSTAT_ICVE)) != 0)) { 2973 #define PRINTERR(bit, str) \ 2974 if (rxstat & (bit)) \ 2975 printf("%s: receive error: %s\n", \ 2976 sc->sc_dev.dv_xname, str) 2977 ifp->if_ierrors++; 2978 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2979 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2980 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2981 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2982 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2983 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2984 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2985 #undef PRINTERR 2986 ATW_INIT_RXDESC(sc, i); 2987 continue; 2988 } 2989 2990 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2991 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2992 2993 /* 2994 * No errors; receive the packet. Note the ADM8211 2995 * includes the CRC in promiscuous mode. 2996 */ 2997 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2998 2999 /* 3000 * Allocate a new mbuf cluster. If that fails, we are 3001 * out of memory, and must drop the packet and recycle 3002 * the buffer that's already attached to this descriptor. 3003 */ 3004 m = rxs->rxs_mbuf; 3005 if (atw_add_rxbuf(sc, i) != 0) { 3006 ifp->if_ierrors++; 3007 ATW_INIT_RXDESC(sc, i); 3008 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3009 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3010 continue; 3011 } 3012 3013 ifp->if_ipackets++; 3014 if (sc->sc_opmode & ATW_NAR_PR) 3015 m->m_flags |= M_HASFCS; 3016 m->m_pkthdr.rcvif = ifp; 3017 m->m_pkthdr.len = m->m_len = len; 3018 3019 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3020 rate = 0; 3021 else 3022 rate = rate_tbl[rate0]; 3023 3024 #if NBPFILTER > 0 3025 /* Pass this up to any BPF listeners. */ 3026 if (sc->sc_radiobpf != NULL) { 3027 struct mbuf mb; 3028 3029 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3030 3031 tap->ar_rate = rate; 3032 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3033 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3034 3035 /* TBD verify units are dB */ 3036 tap->ar_antsignal = (int)rssi; 3037 /* TBD tap->ar_flags */ 3038 3039 M_COPY_PKTHDR(&mb, m); 3040 mb.m_data = (caddr_t)tap; 3041 mb.m_len = tap->ar_ihdr.it_len; 3042 mb.m_next = m; 3043 mb.m_pkthdr.len += mb.m_len; 3044 bpf_mtap(sc->sc_radiobpf, &mb); 3045 } 3046 #endif /* NPBFILTER > 0 */ 3047 3048 wh = mtod(m, struct ieee80211_frame *); 3049 ni = ieee80211_find_rxnode(ic, wh); 3050 if (m->m_pkthdr.len >= sizeof(struct ieee80211_frame_min) || 3051 ic->ic_opmode == IEEE80211_M_MONITOR) 3052 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3053 /* 3054 * The frame may have caused the node to be marked for 3055 * reclamation (e.g. in response to a DEAUTH message) 3056 * so use free_node here instead of unref_node. 3057 */ 3058 if (ni == ic->ic_bss) 3059 ieee80211_unref_node(&ni); 3060 else 3061 ieee80211_free_node(ic, ni); 3062 } 3063 3064 /* Update the receive pointer. */ 3065 sc->sc_rxptr = i; 3066 } 3067 3068 /* 3069 * atw_txintr: 3070 * 3071 * Helper; handle transmit interrupts. 3072 */ 3073 void 3074 atw_txintr(struct atw_softc *sc) 3075 { 3076 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3077 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3078 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3079 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3080 3081 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3082 struct ifnet *ifp = &sc->sc_ic.ic_if; 3083 struct atw_txsoft *txs; 3084 u_int32_t txstat; 3085 3086 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3087 sc->sc_dev.dv_xname, sc->sc_flags)); 3088 3089 ifp->if_flags &= ~IFF_OACTIVE; 3090 3091 /* 3092 * Go through our Tx list and free mbufs for those 3093 * frames that have been transmitted. 3094 */ 3095 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3096 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3097 txs->txs_ndescs, 3098 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3099 3100 #ifdef ATW_DEBUG 3101 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3102 int i; 3103 printf(" txsoft %p transmit chain:\n", txs); 3104 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3105 printf(" descriptor %d:\n", i); 3106 printf(" at_status: 0x%08x\n", 3107 le32toh(sc->sc_txdescs[i].at_stat)); 3108 printf(" at_flags: 0x%08x\n", 3109 le32toh(sc->sc_txdescs[i].at_flags)); 3110 printf(" at_buf1: 0x%08x\n", 3111 le32toh(sc->sc_txdescs[i].at_buf1)); 3112 printf(" at_buf2: 0x%08x\n", 3113 le32toh(sc->sc_txdescs[i].at_buf2)); 3114 if (i == txs->txs_lastdesc) 3115 break; 3116 } 3117 } 3118 #endif 3119 3120 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3121 if (txstat & ATW_TXSTAT_OWN) 3122 break; 3123 3124 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3125 3126 sc->sc_txfree += txs->txs_ndescs; 3127 3128 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3129 0, txs->txs_dmamap->dm_mapsize, 3130 BUS_DMASYNC_POSTWRITE); 3131 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3132 m_freem(txs->txs_mbuf); 3133 txs->txs_mbuf = NULL; 3134 3135 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3136 3137 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3138 (txstat & TXSTAT_ERRMASK) != 0) { 3139 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3140 txstat_buf, sizeof(txstat_buf)); 3141 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3142 txstat_buf, 3143 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3144 } 3145 3146 /* 3147 * Check for errors and collisions. 3148 */ 3149 if (txstat & ATW_TXSTAT_TUF) 3150 sc->sc_stats.ts_tx_tuf++; 3151 if (txstat & ATW_TXSTAT_TLT) 3152 sc->sc_stats.ts_tx_tlt++; 3153 if (txstat & ATW_TXSTAT_TRT) 3154 sc->sc_stats.ts_tx_trt++; 3155 if (txstat & ATW_TXSTAT_TRO) 3156 sc->sc_stats.ts_tx_tro++; 3157 if (txstat & ATW_TXSTAT_SOFBR) { 3158 sc->sc_stats.ts_tx_sofbr++; 3159 } 3160 3161 if ((txstat & ATW_TXSTAT_ES) == 0) 3162 ifp->if_collisions += 3163 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3164 else 3165 ifp->if_oerrors++; 3166 3167 ifp->if_opackets++; 3168 } 3169 3170 /* 3171 * If there are no more pending transmissions, cancel the watchdog 3172 * timer. 3173 */ 3174 if (txs == NULL) 3175 sc->sc_tx_timer = 0; 3176 #undef TXSTAT_ERRMASK 3177 #undef TXSTAT_FMT 3178 } 3179 3180 /* 3181 * atw_watchdog: [ifnet interface function] 3182 * 3183 * Watchdog timer handler. 3184 */ 3185 void 3186 atw_watchdog(struct ifnet *ifp) 3187 { 3188 struct atw_softc *sc = ifp->if_softc; 3189 struct ieee80211com *ic = &sc->sc_ic; 3190 3191 ifp->if_timer = 0; 3192 if (ATW_IS_ENABLED(sc) == 0) 3193 return; 3194 3195 if (sc->sc_rescan_timer) { 3196 if (--sc->sc_rescan_timer == 0) 3197 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3198 } 3199 if (sc->sc_tx_timer) { 3200 if (--sc->sc_tx_timer == 0 && 3201 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3202 printf("%s: transmit timeout\n", ifp->if_xname); 3203 ifp->if_oerrors++; 3204 (void)atw_init(ifp); 3205 atw_start(ifp); 3206 } 3207 } 3208 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3209 ifp->if_timer = 1; 3210 ieee80211_watchdog(ifp); 3211 } 3212 3213 /* Compute the 802.11 Duration field and the PLCP Length fields for 3214 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3215 * Write the fields to the ADM8211 Tx header, frm. 3216 * 3217 * TBD use the fragmentation threshold to find the right duration for 3218 * the first & last fragments. 3219 * 3220 * TBD make certain of the duration fields applied by the ADM8211 to each 3221 * fragment. I think that the ADM8211 knows how to subtract the CTS 3222 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3223 * I also think that the ADM8211 does *some* arithmetic for us, because 3224 * otherwise I think we would have to set a first duration for CTS/first 3225 * fragment, a second duration for fragments between the first and the 3226 * last, and a third duration for the last fragment. 3227 * 3228 * TBD make certain that duration fields reflect addition of FCS/WEP 3229 * and correct duration arithmetic as necessary. 3230 */ 3231 static void 3232 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3233 int len) 3234 { 3235 int remainder; 3236 3237 /* deal also with encrypted fragments */ 3238 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3239 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3240 sc->sc_dev.dv_xname)); 3241 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3242 IEEE80211_WEP_CRCLEN; 3243 } 3244 3245 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3246 * duration (XXX added by MAC?). 3247 */ 3248 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3249 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3250 3251 if (rate <= 4) 3252 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3253 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3254 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3255 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3256 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3257 else 3258 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3259 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3260 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3261 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3262 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3263 3264 /* lengthen duration if long preamble */ 3265 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3266 frm->atw_head_dur += 3267 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3268 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3269 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3270 IEEE80211_DUR_DS_FAST_PLCPHDR); 3271 3272 if (remainder != 0) 3273 frm->atw_head_dur++; 3274 3275 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3276 (rate == 2 || rate == 4)) { 3277 /* derived from Linux: how could this be right? */ 3278 frm->atw_head_plcplen = frm->atw_head_dur; 3279 } else { 3280 frm->atw_head_plcplen = (16 * len) / rate; 3281 remainder = (80 * len) % (rate * 5); 3282 3283 if (remainder != 0) { 3284 frm->atw_head_plcplen++; 3285 3286 /* XXX magic */ 3287 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3288 rate == 22 && remainder <= 30) 3289 frm->atw_head_plcplen |= 0x8000; 3290 } 3291 } 3292 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3293 htole16(frm->atw_head_plcplen); 3294 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3295 } 3296 3297 #ifdef ATW_DEBUG 3298 static void 3299 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3300 { 3301 struct atw_softc *sc = ifp->if_softc; 3302 struct mbuf *m; 3303 int i, noctets = 0; 3304 3305 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3306 m0->m_pkthdr.len); 3307 3308 for (m = m0; m; m = m->m_next) { 3309 if (m->m_len == 0) 3310 continue; 3311 for (i = 0; i < m->m_len; i++) { 3312 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3313 if (++noctets % 24 == 0) 3314 printf("\n"); 3315 } 3316 } 3317 printf("%s%s: %d bytes emitted\n", 3318 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3319 } 3320 #endif /* ATW_DEBUG */ 3321 3322 /* 3323 * atw_start: [ifnet interface function] 3324 * 3325 * Start packet transmission on the interface. 3326 */ 3327 void 3328 atw_start(struct ifnet *ifp) 3329 { 3330 struct atw_softc *sc = ifp->if_softc; 3331 struct ieee80211com *ic = &sc->sc_ic; 3332 struct ieee80211_node *ni; 3333 struct ieee80211_frame *wh; 3334 struct atw_frame *hh; 3335 struct mbuf *m0, *m; 3336 struct atw_txsoft *txs, *last_txs; 3337 struct atw_txdesc *txd; 3338 int do_encrypt, rate; 3339 bus_dmamap_t dmamap; 3340 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3341 3342 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3343 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3344 3345 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3346 return; 3347 3348 #if 0 /* TBD ??? */ 3349 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3350 return; 3351 #endif 3352 3353 /* 3354 * Remember the previous number of free descriptors and 3355 * the first descriptor we'll use. 3356 */ 3357 ofree = sc->sc_txfree; 3358 firsttx = sc->sc_txnext; 3359 3360 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3361 sc->sc_dev.dv_xname, ofree, firsttx)); 3362 3363 /* 3364 * Loop through the send queue, setting up transmit descriptors 3365 * until we drain the queue, or use up all available transmit 3366 * descriptors. 3367 */ 3368 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3369 sc->sc_txfree != 0) { 3370 3371 do_encrypt = 0; 3372 /* 3373 * Grab a packet off the management queue, if it 3374 * is not empty. Otherwise, from the data queue. 3375 */ 3376 IF_DEQUEUE(&ic->ic_mgtq, m0); 3377 if (m0 != NULL) { 3378 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3379 m0->m_pkthdr.rcvif = NULL; 3380 } else { 3381 IFQ_DEQUEUE(&ifp->if_snd, m0); 3382 if (m0 == NULL) 3383 break; 3384 #if NBPFILTER > 0 3385 if (ifp->if_bpf != NULL) 3386 bpf_mtap(ifp->if_bpf, m0); 3387 #endif /* NBPFILTER > 0 */ 3388 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3389 ifp->if_oerrors++; 3390 break; 3391 } 3392 } 3393 3394 rate = MAX(ieee80211_get_rate(ic), 2); 3395 3396 #if NBPFILTER > 0 3397 /* 3398 * Pass the packet to any BPF listeners. 3399 */ 3400 if (ic->ic_rawbpf != NULL) 3401 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3402 3403 if (sc->sc_radiobpf != NULL) { 3404 struct mbuf mb; 3405 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3406 3407 tap->at_rate = rate; 3408 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3409 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3410 3411 /* TBD tap->at_flags */ 3412 3413 M_COPY_PKTHDR(&mb, m0); 3414 mb.m_data = (caddr_t)tap; 3415 mb.m_len = tap->at_ihdr.it_len; 3416 mb.m_next = m0; 3417 mb.m_pkthdr.len += mb.m_len; 3418 bpf_mtap(sc->sc_radiobpf, &mb); 3419 } 3420 #endif /* NBPFILTER > 0 */ 3421 3422 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3423 3424 if (ni != NULL && ni != ic->ic_bss) 3425 ieee80211_free_node(ic, ni); 3426 3427 if (m0 == NULL) { 3428 ifp->if_oerrors++; 3429 break; 3430 } 3431 3432 /* just to make sure. */ 3433 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3434 3435 if (m0 == NULL) { 3436 ifp->if_oerrors++; 3437 break; 3438 } 3439 3440 hh = mtod(m0, struct atw_frame *); 3441 wh = &hh->atw_ihdr; 3442 3443 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3444 3445 /* Copy everything we need from the 802.11 header: 3446 * Frame Control; address 1, address 3, or addresses 3447 * 3 and 4. NIC fills in BSSID, SA. 3448 */ 3449 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3450 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3451 panic("%s: illegal WDS frame", 3452 sc->sc_dev.dv_xname); 3453 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3454 } else 3455 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3456 3457 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3458 3459 /* initialize remaining Tx parameters */ 3460 memset(&hh->u, 0, sizeof(hh->u)); 3461 3462 hh->atw_rate = rate * 5; 3463 /* XXX this could be incorrect if M_FCS. _encap should 3464 * probably strip FCS just in case it sticks around in 3465 * bridged packets. 3466 */ 3467 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3468 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3469 sizeof(struct atw_frame)); 3470 3471 #if 0 3472 /* this virtually guaranteed that WEP-encrypted frames 3473 * are fragmented. oops. 3474 */ 3475 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3476 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3477 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3478 #else 3479 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3480 #endif 3481 3482 hh->atw_rtylmt = 3; 3483 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3484 if (do_encrypt) { 3485 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3486 hh->atw_keyid = ic->ic_wep_txkey; 3487 } 3488 3489 /* TBD 4-addr frames */ 3490 atw_frame_setdurs(sc, hh, rate, 3491 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3492 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3493 3494 /* never fragment multicast frames */ 3495 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3496 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3497 } else if (sc->sc_flags & ATWF_RTSCTS) { 3498 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3499 } 3500 3501 #ifdef ATW_DEBUG 3502 /* experimental stuff */ 3503 if (atw_xrtylmt != ~0) 3504 hh->atw_rtylmt = atw_xrtylmt; 3505 if (atw_xhdrctl != 0) 3506 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3507 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3508 hh->atw_service = atw_xservice; 3509 if (atw_xpaylen != 0) 3510 hh->atw_paylen = htole16(atw_xpaylen); 3511 hh->atw_fragnum = 0; 3512 3513 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3514 printf("%s: dst = %s, rate = 0x%02x, " 3515 "service = 0x%02x, paylen = 0x%04x\n", 3516 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3517 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3518 3519 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3520 "dur1 = 0x%04x, dur2 = 0x%04x, " 3521 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3522 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3523 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3524 hh->atw_tail_dur, hh->atw_head_dur); 3525 3526 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3527 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3528 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3529 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3530 3531 printf("%s: keyid = %d\n", 3532 sc->sc_dev.dv_xname, hh->atw_keyid); 3533 3534 atw_dump_pkt(ifp, m0); 3535 } 3536 #endif /* ATW_DEBUG */ 3537 3538 dmamap = txs->txs_dmamap; 3539 3540 /* 3541 * Load the DMA map. Copy and try (once) again if the packet 3542 * didn't fit in the alloted number of segments. 3543 */ 3544 for (first = 1; 3545 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3546 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3547 first = 0) { 3548 MGETHDR(m, M_DONTWAIT, MT_DATA); 3549 if (m == NULL) { 3550 printf("%s: unable to allocate Tx mbuf\n", 3551 sc->sc_dev.dv_xname); 3552 break; 3553 } 3554 if (m0->m_pkthdr.len > MHLEN) { 3555 MCLGET(m, M_DONTWAIT); 3556 if ((m->m_flags & M_EXT) == 0) { 3557 printf("%s: unable to allocate Tx " 3558 "cluster\n", sc->sc_dev.dv_xname); 3559 m_freem(m); 3560 break; 3561 } 3562 } 3563 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3564 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3565 m_freem(m0); 3566 m0 = m; 3567 m = NULL; 3568 } 3569 if (error != 0) { 3570 printf("%s: unable to load Tx buffer, " 3571 "error = %d\n", sc->sc_dev.dv_xname, error); 3572 m_freem(m0); 3573 break; 3574 } 3575 3576 /* 3577 * Ensure we have enough descriptors free to describe 3578 * the packet. 3579 */ 3580 if (dmamap->dm_nsegs > sc->sc_txfree) { 3581 /* 3582 * Not enough free descriptors to transmit 3583 * this packet. Unload the DMA map and 3584 * drop the packet. Notify the upper layer 3585 * that there are no more slots left. 3586 * 3587 * XXX We could allocate an mbuf and copy, but 3588 * XXX it is worth it? 3589 */ 3590 ifp->if_flags |= IFF_OACTIVE; 3591 bus_dmamap_unload(sc->sc_dmat, dmamap); 3592 m_freem(m0); 3593 break; 3594 } 3595 3596 /* 3597 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3598 */ 3599 3600 /* Sync the DMA map. */ 3601 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3602 BUS_DMASYNC_PREWRITE); 3603 3604 /* XXX arbitrary retry limit; 8 because I have seen it in 3605 * use already and maybe 0 means "no tries" ! 3606 */ 3607 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3608 3609 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3610 sc->sc_dev.dv_xname, rate * 5)); 3611 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3612 3613 /* 3614 * Initialize the transmit descriptors. 3615 */ 3616 for (nexttx = sc->sc_txnext, seg = 0; 3617 seg < dmamap->dm_nsegs; 3618 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3619 /* 3620 * If this is the first descriptor we're 3621 * enqueueing, don't set the OWN bit just 3622 * yet. That could cause a race condition. 3623 * We'll do it below. 3624 */ 3625 txd = &sc->sc_txdescs[nexttx]; 3626 txd->at_ctl = ctl | 3627 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3628 3629 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3630 txd->at_flags = 3631 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3632 ATW_TXFLAG_TBS1_MASK)) | 3633 ((nexttx == (ATW_NTXDESC - 1)) 3634 ? htole32(ATW_TXFLAG_TER) : 0); 3635 lasttx = nexttx; 3636 } 3637 3638 IASSERT(lasttx != -1, ("bad lastx")); 3639 /* Set `first segment' and `last segment' appropriately. */ 3640 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3641 htole32(ATW_TXFLAG_FS); 3642 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3643 3644 #ifdef ATW_DEBUG 3645 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3646 printf(" txsoft %p transmit chain:\n", txs); 3647 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3648 printf(" descriptor %d:\n", seg); 3649 printf(" at_ctl: 0x%08x\n", 3650 le32toh(sc->sc_txdescs[seg].at_ctl)); 3651 printf(" at_flags: 0x%08x\n", 3652 le32toh(sc->sc_txdescs[seg].at_flags)); 3653 printf(" at_buf1: 0x%08x\n", 3654 le32toh(sc->sc_txdescs[seg].at_buf1)); 3655 printf(" at_buf2: 0x%08x\n", 3656 le32toh(sc->sc_txdescs[seg].at_buf2)); 3657 if (seg == lasttx) 3658 break; 3659 } 3660 } 3661 #endif 3662 3663 /* Sync the descriptors we're using. */ 3664 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3665 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3666 3667 /* 3668 * Store a pointer to the packet so we can free it later, 3669 * and remember what txdirty will be once the packet is 3670 * done. 3671 */ 3672 txs->txs_mbuf = m0; 3673 txs->txs_firstdesc = sc->sc_txnext; 3674 txs->txs_lastdesc = lasttx; 3675 txs->txs_ndescs = dmamap->dm_nsegs; 3676 3677 /* Advance the tx pointer. */ 3678 sc->sc_txfree -= dmamap->dm_nsegs; 3679 sc->sc_txnext = nexttx; 3680 3681 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3682 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3683 3684 last_txs = txs; 3685 } 3686 3687 if (txs == NULL || sc->sc_txfree == 0) { 3688 /* No more slots left; notify upper layer. */ 3689 ifp->if_flags |= IFF_OACTIVE; 3690 } 3691 3692 if (sc->sc_txfree != ofree) { 3693 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3694 sc->sc_dev.dv_xname, lasttx, firsttx)); 3695 /* 3696 * Cause a transmit interrupt to happen on the 3697 * last packet we enqueued. 3698 */ 3699 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3700 ATW_CDTXSYNC(sc, lasttx, 1, 3701 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3702 3703 /* 3704 * The entire packet chain is set up. Give the 3705 * first descriptor to the chip now. 3706 */ 3707 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3708 ATW_CDTXSYNC(sc, firsttx, 1, 3709 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3710 3711 /* Wake up the transmitter. */ 3712 /* XXX USE AUTOPOLLING? */ 3713 ATW_WRITE(sc, ATW_TDR, 0x1); 3714 3715 /* Set a watchdog timer in case the chip flakes out. */ 3716 sc->sc_tx_timer = 5; 3717 ifp->if_timer = 1; 3718 } 3719 } 3720 3721 /* 3722 * atw_power: 3723 * 3724 * Power management (suspend/resume) hook. 3725 */ 3726 void 3727 atw_power(int why, void *arg) 3728 { 3729 struct atw_softc *sc = arg; 3730 struct ifnet *ifp = &sc->sc_ic.ic_if; 3731 int s; 3732 3733 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3734 3735 s = splnet(); 3736 switch (why) { 3737 case PWR_STANDBY: 3738 /* XXX do nothing. */ 3739 break; 3740 case PWR_SUSPEND: 3741 atw_stop(ifp, 0); 3742 if (sc->sc_power != NULL) 3743 (*sc->sc_power)(sc, why); 3744 break; 3745 case PWR_RESUME: 3746 if (ifp->if_flags & IFF_UP) { 3747 if (sc->sc_power != NULL) 3748 (*sc->sc_power)(sc, why); 3749 atw_init(ifp); 3750 } 3751 break; 3752 case PWR_SOFTSUSPEND: 3753 case PWR_SOFTSTANDBY: 3754 case PWR_SOFTRESUME: 3755 break; 3756 } 3757 splx(s); 3758 } 3759 3760 /* 3761 * atw_ioctl: [ifnet interface function] 3762 * 3763 * Handle control requests from the operator. 3764 */ 3765 int 3766 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3767 { 3768 struct atw_softc *sc = ifp->if_softc; 3769 struct ifreq *ifr = (struct ifreq *)data; 3770 int s, error = 0; 3771 3772 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3773 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3774 return ENXIO; 3775 3776 s = splnet(); 3777 3778 switch (cmd) { 3779 case SIOCSIFFLAGS: 3780 if (ifp->if_flags & IFF_UP) { 3781 if (ATW_IS_ENABLED(sc)) { 3782 /* 3783 * To avoid rescanning another access point, 3784 * do not call atw_init() here. Instead, 3785 * only reflect media settings. 3786 */ 3787 atw_filter_setup(sc); 3788 } else 3789 error = atw_init(ifp); 3790 } else if (ATW_IS_ENABLED(sc)) 3791 atw_stop(ifp, 1); 3792 break; 3793 case SIOCADDMULTI: 3794 case SIOCDELMULTI: 3795 error = (cmd == SIOCADDMULTI) ? 3796 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3797 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3798 if (error == ENETRESET) { 3799 if (ATW_IS_ENABLED(sc)) 3800 atw_filter_setup(sc); /* do not rescan */ 3801 error = 0; 3802 } 3803 break; 3804 default: 3805 error = ieee80211_ioctl(ifp, cmd, data); 3806 if (error == ENETRESET) { 3807 if (ATW_IS_ENABLED(sc)) 3808 error = atw_init(ifp); 3809 else 3810 error = 0; 3811 } 3812 break; 3813 } 3814 3815 /* Try to get more packets going. */ 3816 if (ATW_IS_ENABLED(sc)) 3817 atw_start(ifp); 3818 3819 splx(s); 3820 return (error); 3821 } 3822 3823 static int 3824 atw_media_change(struct ifnet *ifp) 3825 { 3826 int error; 3827 3828 error = ieee80211_media_change(ifp); 3829 if (error == ENETRESET) { 3830 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3831 (IFF_RUNNING|IFF_UP)) 3832 atw_init(ifp); /* XXX lose error */ 3833 error = 0; 3834 } 3835 return error; 3836 } 3837 3838 static void 3839 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3840 { 3841 struct atw_softc *sc = ifp->if_softc; 3842 3843 if (ATW_IS_ENABLED(sc) == 0) { 3844 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3845 imr->ifm_status = 0; 3846 return; 3847 } 3848 ieee80211_media_status(ifp, imr); 3849 } 3850
Indexes created Thu Sep 25 16:09:42 GMT 2025