atw.c revision 1.24.2.1
1 /* $NetBSD: atw.c,v 1.24.2.1 2004/06/27 08:25:58 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.24.2.1 2004/06/27 08:25:58 jdc Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * IBSS join/create 131 * 132 * set ATW_NAR_EA (is set by ASIC?) 133 * 134 * BSS join: (re)association response 135 * 136 * set ATW_FRCTL_AID 137 * 138 * optimizations ??? 139 * 140 */ 141 142 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 143 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 144 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 145 146 int atw_rfio_enable_delay = 20 * 1000; 147 int atw_rfio_disable_delay = 2 * 1000; 148 int atw_writewep_delay = 5; 149 int atw_beacon_len_adjust = 4; 150 int atw_dwelltime = 200; 151 152 #ifdef ATW_DEBUG 153 int atw_xhdrctl = 0; 154 int atw_xrtylmt = ~0; 155 int atw_xservice = IEEE80211_PLCP_SERVICE; 156 int atw_xpaylen = 0; 157 158 int atw_debug = 0; 159 160 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 161 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 162 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 163 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 164 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 165 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 166 static void atw_print_regs(struct atw_softc *, const char *); 167 static void atw_rf3000_print(struct atw_softc *); 168 static void atw_si4126_print(struct atw_softc *); 169 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 170 #else 171 #define ATW_DPRINTF(x) 172 #define ATW_DPRINTF2(x) 173 #define ATW_DPRINTF3(x) 174 #define DPRINTF(sc, x) /* nothing */ 175 #define DPRINTF2(sc, x) /* nothing */ 176 #define DPRINTF3(sc, x) /* nothing */ 177 #endif 178 179 #ifdef ATW_STATS 180 void atw_print_stats(struct atw_softc *); 181 #endif 182 183 void atw_start(struct ifnet *); 184 void atw_watchdog(struct ifnet *); 185 int atw_ioctl(struct ifnet *, u_long, caddr_t); 186 int atw_init(struct ifnet *); 187 void atw_stop(struct ifnet *, int); 188 189 void atw_reset(struct atw_softc *); 190 int atw_read_srom(struct atw_softc *); 191 192 void atw_shutdown(void *); 193 194 void atw_rxdrain(struct atw_softc *); 195 int atw_add_rxbuf(struct atw_softc *, int); 196 void atw_idle(struct atw_softc *, u_int32_t); 197 198 int atw_enable(struct atw_softc *); 199 void atw_disable(struct atw_softc *); 200 void atw_power(int, void *); 201 202 void atw_rxintr(struct atw_softc *); 203 void atw_txintr(struct atw_softc *); 204 void atw_linkintr(struct atw_softc *, u_int32_t); 205 206 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 207 static void atw_tsf(struct atw_softc *); 208 static void atw_start_beacon(struct atw_softc *, int); 209 static void atw_write_wep(struct atw_softc *); 210 static void atw_write_bssid(struct atw_softc *); 211 static void atw_write_bcn_thresh(struct atw_softc *); 212 static void atw_write_ssid(struct atw_softc *); 213 static void atw_write_sup_rates(struct atw_softc *); 214 static void atw_clear_sram(struct atw_softc *); 215 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 216 static int atw_media_change(struct ifnet *); 217 static void atw_media_status(struct ifnet *, struct ifmediareq *); 218 static void atw_filter_setup(struct atw_softc *); 219 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 220 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 221 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 226 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 227 228 static int atw_tune(struct atw_softc *); 229 230 static void atw_rfio_enable(struct atw_softc *, int); 231 232 /* RFMD RF3000 Baseband Processor */ 233 static int atw_rf3000_init(struct atw_softc *); 234 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 235 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 236 #ifdef ATW_DEBUG 237 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 238 #endif /* ATW_DEBUG */ 239 240 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 241 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 242 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 243 #ifdef ATW_DEBUG 244 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 245 #endif /* ATW_DEBUG */ 246 247 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 248 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 249 250 const char *atw_tx_state[] = { 251 "STOPPED", 252 "RUNNING - FETCH", 253 "RUNNING - WAIT", 254 "RUNNING - READING", 255 "-- RESERVED1 --", 256 "-- RESERVED2 --", 257 "SUSPENDED", 258 "RUNNING - CLOSE" 259 }; 260 261 const char *atw_rx_state[] = { 262 "STOPPED", 263 "RUNNING - FETCH", 264 "RUNNING - CHECK", 265 "RUNNING - WAIT", 266 "SUSPENDED", 267 "RUNNING - CLOSE", 268 "RUNNING - FLUSH", 269 "RUNNING - QUEUE" 270 }; 271 272 int 273 atw_activate(struct device *self, enum devact act) 274 { 275 struct atw_softc *sc = (struct atw_softc *)self; 276 int rv = 0, s; 277 278 s = splnet(); 279 switch (act) { 280 case DVACT_ACTIVATE: 281 rv = EOPNOTSUPP; 282 break; 283 284 case DVACT_DEACTIVATE: 285 if_deactivate(&sc->sc_ic.ic_if); 286 break; 287 } 288 splx(s); 289 return rv; 290 } 291 292 /* 293 * atw_enable: 294 * 295 * Enable the ADM8211 chip. 296 */ 297 int 298 atw_enable(struct atw_softc *sc) 299 { 300 301 if (ATW_IS_ENABLED(sc) == 0) { 302 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 303 printf("%s: device enable failed\n", 304 sc->sc_dev.dv_xname); 305 return (EIO); 306 } 307 sc->sc_flags |= ATWF_ENABLED; 308 } 309 return (0); 310 } 311 312 /* 313 * atw_disable: 314 * 315 * Disable the ADM8211 chip. 316 */ 317 void 318 atw_disable(struct atw_softc *sc) 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF(("\n\t")); 400 } 401 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 499 }; 500 struct ieee80211com *ic = &sc->sc_ic; 501 struct ifnet *ifp = &ic->ic_if; 502 int country_code, error, i, nrate; 503 u_int32_t reg; 504 static const char *type_strings[] = {"Intersil (not supported)", 505 "RFMD", "Marvel (not supported)"}; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 } 577 for (i = 0; i < ATW_NRXDESC; i++) { 578 sc->sc_rxsoft[i].rxs_mbuf = NULL; 579 } 580 581 /* Reset the chip to a known state. */ 582 atw_reset(sc); 583 584 if (atw_read_srom(sc) == -1) 585 return; 586 587 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_RFTYPE_MASK); 589 590 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 591 ATW_SR_BBPTYPE_MASK); 592 593 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 594 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 598 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 599 return; 600 } 601 602 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 603 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 604 605 /* XXX There exists a Linux driver which seems to use RFType = 0 for 606 * MARVEL. My bug, or theirs? 607 */ 608 609 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 610 611 switch (sc->sc_rftype) { 612 case ATW_RFTYPE_INTERSIL: 613 reg |= ATW_SYNCTL_CS1; 614 break; 615 case ATW_RFTYPE_RFMD: 616 reg |= ATW_SYNCTL_CS0; 617 break; 618 case ATW_RFTYPE_MARVEL: 619 break; 620 } 621 622 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 623 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 624 625 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 626 627 switch (sc->sc_bbptype) { 628 case ATW_RFTYPE_INTERSIL: 629 reg |= ATW_BBPCTL_TWI; 630 break; 631 case ATW_RFTYPE_RFMD: 632 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 633 ATW_BBPCTL_CCA_ACTLO; 634 break; 635 case ATW_RFTYPE_MARVEL: 636 break; 637 } 638 639 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 640 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 641 642 /* 643 * From this point forward, the attachment cannot fail. A failure 644 * before this point releases all resources that may have been 645 * allocated. 646 */ 647 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 648 649 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 650 htole16(sc->sc_srom[ATW_SR_MAC00]), 651 htole16(sc->sc_srom[ATW_SR_MAC01]), 652 htole16(sc->sc_srom[ATW_SR_MAC10]))); 653 654 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 655 ATW_SR_CTRY_MASK); 656 657 #define ADD_CHANNEL(_ic, _chan) do { \ 658 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 659 _ic->ic_channels[_chan].ic_freq = \ 660 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 661 } while (0) 662 663 /* Find available channels */ 664 switch (country_code) { 665 case COUNTRY_MMK2: /* 1-14 */ 666 ADD_CHANNEL(ic, 14); 667 /*FALLTHROUGH*/ 668 case COUNTRY_ETSI: /* 1-13 */ 669 for (i = 1; i <= 13; i++) 670 ADD_CHANNEL(ic, i); 671 break; 672 case COUNTRY_FCC: /* 1-11 */ 673 case COUNTRY_IC: /* 1-11 */ 674 for (i = 1; i <= 11; i++) 675 ADD_CHANNEL(ic, i); 676 break; 677 case COUNTRY_MMK: /* 14 */ 678 ADD_CHANNEL(ic, 14); 679 break; 680 case COUNTRY_FRANCE: /* 10-13 */ 681 for (i = 10; i <= 13; i++) 682 ADD_CHANNEL(ic, i); 683 break; 684 default: /* assume channels 10-11 */ 685 case COUNTRY_SPAIN: /* 10-11 */ 686 for (i = 10; i <= 11; i++) 687 ADD_CHANNEL(ic, i); 688 break; 689 } 690 691 /* Read the MAC address. */ 692 reg = ATW_READ(sc, ATW_PAR0); 693 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 694 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 695 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 696 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 697 reg = ATW_READ(sc, ATW_PAR1); 698 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 699 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 700 701 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 702 printf(" could not get mac address, attach failed\n"); 703 return; 704 } 705 706 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 707 708 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 709 ifp->if_softc = sc; 710 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 711 IFF_NOTRAILERS; 712 ifp->if_ioctl = atw_ioctl; 713 ifp->if_start = atw_start; 714 ifp->if_watchdog = atw_watchdog; 715 ifp->if_init = atw_init; 716 ifp->if_stop = atw_stop; 717 IFQ_SET_READY(&ifp->if_snd); 718 719 ic->ic_phytype = IEEE80211_T_DS; 720 ic->ic_opmode = IEEE80211_M_STA; 721 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 722 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 723 724 nrate = 0; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 730 731 /* 732 * Call MI attach routines. 733 */ 734 735 if_attach(ifp); 736 ieee80211_ifattach(ifp); 737 738 sc->sc_newstate = ic->ic_newstate; 739 ic->ic_newstate = atw_newstate; 740 741 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 742 ic->ic_recv_mgmt = atw_recv_mgmt; 743 744 sc->sc_node_free = ic->ic_node_free; 745 ic->ic_node_free = atw_node_free; 746 747 sc->sc_node_alloc = ic->ic_node_alloc; 748 ic->ic_node_alloc = atw_node_alloc; 749 750 /* possibly we should fill in our own sc_send_prresp, since 751 * the ADM8211 is probably sending probe responses in ad hoc 752 * mode. 753 */ 754 755 /* complete initialization */ 756 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 757 callout_init(&sc->sc_scan_ch); 758 759 #if NBPFILTER > 0 760 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 761 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 762 #endif 763 764 /* 765 * Make sure the interface is shutdown during reboot. 766 */ 767 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 768 if (sc->sc_sdhook == NULL) 769 printf("%s: WARNING: unable to establish shutdown hook\n", 770 sc->sc_dev.dv_xname); 771 772 /* 773 * Add a suspend hook to make sure we come back up after a 774 * resume. 775 */ 776 sc->sc_powerhook = powerhook_establish(atw_power, sc); 777 if (sc->sc_powerhook == NULL) 778 printf("%s: WARNING: unable to establish power hook\n", 779 sc->sc_dev.dv_xname); 780 781 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 782 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 783 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 784 785 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 786 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 787 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 788 789 return; 790 791 /* 792 * Free any resources we've allocated during the failed attach 793 * attempt. Do this in reverse order and fall through. 794 */ 795 fail_5: 796 for (i = 0; i < ATW_NRXDESC; i++) { 797 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 798 continue; 799 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 800 } 801 fail_4: 802 for (i = 0; i < ATW_TXQUEUELEN; i++) { 803 if (sc->sc_txsoft[i].txs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 806 } 807 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 808 fail_3: 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 810 fail_2: 811 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 812 sizeof(struct atw_control_data)); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 815 fail_0: 816 return; 817 } 818 819 static struct ieee80211_node * 820 atw_node_alloc(struct ieee80211com *ic) 821 { 822 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 823 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 824 825 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 826 return ni; 827 } 828 829 static void 830 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 831 { 832 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 833 834 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 835 ether_sprintf(ni->ni_bssid))); 836 (*sc->sc_node_free)(ic, ni); 837 } 838 839 /* 840 * atw_reset: 841 * 842 * Perform a soft reset on the ADM8211. 843 */ 844 void 845 atw_reset(struct atw_softc *sc) 846 { 847 int i; 848 849 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 850 851 for (i = 0; i < 10000; i++) { 852 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 853 break; 854 DELAY(1); 855 } 856 857 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 858 859 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 860 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 861 862 /* Turn off maximum power saving. */ 863 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 864 865 /* Recall EEPROM. */ 866 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 867 868 DELAY(10 * 1000); 869 870 /* A reset seems to affect the SRAM contents, so put them into 871 * a known state. 872 */ 873 atw_clear_sram(sc); 874 875 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 876 877 sc->sc_lost_bcn_thresh = 0; 878 } 879 880 static void 881 atw_clear_sram(struct atw_softc *sc) 882 { 883 #if 0 884 for (addr = 0; addr < 448; addr++) { 885 ATW_WRITE(sc, ATW_WEPCTL, 886 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 887 DELAY(1000); 888 ATW_WRITE(sc, ATW_WESK, 0); 889 DELAY(1000); /* paranoia */ 890 } 891 return; 892 #endif 893 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 894 /* XXX not for revision 0x20. */ 895 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 896 } 897 898 /* TBD atw_init 899 * 900 * set MAC based on ic->ic_bss->myaddr 901 * write WEP keys 902 * set TX rate 903 */ 904 905 /* 906 * atw_init: [ ifnet interface function ] 907 * 908 * Initialize the interface. Must be called at splnet(). 909 */ 910 int 911 atw_init(struct ifnet *ifp) 912 { 913 struct atw_softc *sc = ifp->if_softc; 914 struct ieee80211com *ic = &sc->sc_ic; 915 struct atw_txsoft *txs; 916 struct atw_rxsoft *rxs; 917 u_int32_t reg; 918 int i, error = 0; 919 920 if ((error = atw_enable(sc)) != 0) 921 goto out; 922 923 /* 924 * Cancel any pending I/O. This also resets. 925 */ 926 atw_stop(ifp, 0); 927 928 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 929 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 930 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 931 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 932 933 /* Turn off APM??? (A binary-only driver does this.) 934 * 935 * Set Rx store-and-forward mode. 936 */ 937 reg = ATW_READ(sc, ATW_CMDR); 938 reg &= ~ATW_CMDR_APM; 939 reg &= ~ATW_CMDR_DRT_MASK; 940 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 941 942 ATW_WRITE(sc, ATW_CMDR, reg); 943 944 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 945 * 946 * XXX a binary-only driver sets a different service field than 947 * 0. why? 948 */ 949 reg = ATW_READ(sc, ATW_PLCPHD); 950 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 951 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 952 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 953 ATW_WRITE(sc, ATW_PLCPHD, reg); 954 955 /* XXX this magic can probably be figured out from the RFMD docs */ 956 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 957 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 958 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 959 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 960 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 961 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 962 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 963 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 964 ATW_WRITE(sc, ATW_TOFS2, reg); 965 966 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 967 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 968 969 /* XXX this resets an Intersil RF front-end? */ 970 /* TBD condition on Intersil RFType? */ 971 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 972 DELAY(10 * 1000); 973 ATW_WRITE(sc, ATW_SYNRF, 0); 974 DELAY(5 * 1000); 975 976 /* 16 TU max duration for contention-free period */ 977 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 978 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 979 980 /* XXX I guess that the Cardbus clock is 22MHz? 981 * I am assuming that the role of ATW_TOFS0_USCNT is 982 * to divide the bus clock to get a 1MHz clock---the datasheet is not 983 * very clear on this point. It says in the datasheet that it is 984 * possible for the ADM8211 to accomodate bus speeds between 22MHz 985 * and 33MHz; maybe this is the way? I see a binary-only driver write 986 * these values. These values are also the power-on default. 987 */ 988 ATW_WRITE(sc, ATW_TOFS0, 989 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 990 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 991 992 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 993 * driver. Go figure. 994 */ 995 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 996 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 997 ATW_IFST_SIFS_MASK) | 998 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 999 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1000 1001 ATW_WRITE(sc, ATW_IFST, reg); 1002 1003 /* XXX More magic. Might relate to ACK timing. */ 1004 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1005 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1006 1007 /* Set up the MMI read/write addresses for the BBP. 1008 * 1009 * TBD find out the Marvel settings. 1010 */ 1011 switch (sc->sc_bbptype) { 1012 case ATW_BBPTYPE_INTERSIL: 1013 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1014 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1015 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1016 break; 1017 case ATW_BBPTYPE_MARVEL: 1018 break; 1019 case ATW_BBPTYPE_RFMD: 1020 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1021 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1022 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1023 default: 1024 break; 1025 } 1026 1027 sc->sc_wepctl = 0; 1028 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1029 1030 if ((error = atw_rf3000_init(sc)) != 0) 1031 goto out; 1032 1033 /* 1034 * Initialize the PCI Access Register. 1035 */ 1036 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1037 1038 /* 1039 * If we're allowed to do so, use Memory Read Line 1040 * and Memory Read Multiple. 1041 * 1042 * XXX Should we use Memory Write and Invalidate? 1043 */ 1044 if (sc->sc_flags & ATWF_MRL) 1045 sc->sc_busmode |= ATW_PAR_MRLE; 1046 if (sc->sc_flags & ATWF_MRM) 1047 sc->sc_busmode |= ATW_PAR_MRME; 1048 if (sc->sc_flags & ATWF_MWI) 1049 sc->sc_busmode |= ATW_PAR_MWIE; 1050 if (sc->sc_maxburst == 0) 1051 sc->sc_maxburst = 8; /* ADM8211 default */ 1052 1053 switch (sc->sc_cacheline) { 1054 default: 1055 /* Use burst length. */ 1056 break; 1057 case 8: 1058 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1059 break; 1060 case 16: 1061 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1062 break; 1063 case 32: 1064 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1065 break; 1066 } 1067 switch (sc->sc_maxburst) { 1068 case 1: 1069 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1070 break; 1071 case 2: 1072 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1073 break; 1074 case 4: 1075 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1076 break; 1077 case 8: 1078 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1079 break; 1080 case 16: 1081 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1082 break; 1083 case 32: 1084 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1085 break; 1086 default: 1087 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1088 break; 1089 } 1090 1091 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1092 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1093 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1094 1095 /* 1096 * Initialize the OPMODE register. We don't write it until 1097 * we're ready to begin the transmit and receive processes. 1098 */ 1099 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1100 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1101 1102 /* 1103 * Initialize the transmit descriptor ring. 1104 */ 1105 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1106 for (i = 0; i < ATW_NTXDESC; i++) { 1107 /* no transmit chaining */ 1108 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1109 sc->sc_txdescs[i].at_buf2 = 1110 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1111 } 1112 /* use ring mode */ 1113 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1114 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1116 sc->sc_txfree = ATW_NTXDESC; 1117 sc->sc_txnext = 0; 1118 1119 /* 1120 * Initialize the transmit job descriptors. 1121 */ 1122 SIMPLEQ_INIT(&sc->sc_txfreeq); 1123 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1124 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1125 txs = &sc->sc_txsoft[i]; 1126 txs->txs_mbuf = NULL; 1127 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1128 } 1129 1130 /* 1131 * Initialize the receive descriptor and receive job 1132 * descriptor rings. 1133 */ 1134 for (i = 0; i < ATW_NRXDESC; i++) { 1135 rxs = &sc->sc_rxsoft[i]; 1136 if (rxs->rxs_mbuf == NULL) { 1137 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1138 printf("%s: unable to allocate or map rx " 1139 "buffer %d, error = %d\n", 1140 sc->sc_dev.dv_xname, i, error); 1141 /* 1142 * XXX Should attempt to run with fewer receive 1143 * XXX buffers instead of just failing. 1144 */ 1145 atw_rxdrain(sc); 1146 goto out; 1147 } 1148 } else 1149 ATW_INIT_RXDESC(sc, i); 1150 } 1151 sc->sc_rxptr = 0; 1152 1153 /* disable all wake-up events */ 1154 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1155 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1156 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1157 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1158 1159 /* ack all wake-up events */ 1160 ATW_SET(sc, ATW_WCSR, 0); 1161 1162 /* 1163 * Initialize the interrupt mask and enable interrupts. 1164 */ 1165 /* normal interrupts */ 1166 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1167 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1168 1169 /* abnormal interrupts */ 1170 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1171 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1172 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1173 1174 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1175 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1176 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1177 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1178 ATW_INTR_TRT; 1179 1180 sc->sc_linkint_mask &= sc->sc_inten; 1181 sc->sc_rxint_mask &= sc->sc_inten; 1182 sc->sc_txint_mask &= sc->sc_inten; 1183 1184 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1185 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1186 if (sc->sc_intr_ack != NULL) 1187 (*sc->sc_intr_ack)(sc); 1188 1189 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1190 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1191 1192 /* 1193 * Give the transmit and receive rings to the ADM8211. 1194 */ 1195 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1196 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1197 1198 /* common 802.11 configuration */ 1199 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1200 switch (ic->ic_opmode) { 1201 case IEEE80211_M_STA: 1202 sc->sc_opmode &= ~ATW_NAR_EA; 1203 break; 1204 case IEEE80211_M_AHDEMO: /* XXX */ 1205 case IEEE80211_M_IBSS: 1206 ic->ic_flags |= IEEE80211_F_IBSSON; 1207 /*FALLTHROUGH*/ 1208 case IEEE80211_M_HOSTAP: /* XXX */ 1209 /* EA bit seems important for ad hoc reception. */ 1210 sc->sc_opmode |= ATW_NAR_EA; 1211 break; 1212 case IEEE80211_M_MONITOR: /* XXX */ 1213 break; 1214 } 1215 1216 atw_start_beacon(sc, 0); 1217 1218 switch (ic->ic_opmode) { 1219 case IEEE80211_M_AHDEMO: 1220 case IEEE80211_M_HOSTAP: 1221 ic->ic_bss->ni_intval = ic->ic_lintval; 1222 ic->ic_bss->ni_rssi = 0; 1223 ic->ic_bss->ni_rstamp = 0; 1224 break; 1225 default: /* XXX */ 1226 break; 1227 } 1228 1229 atw_write_ssid(sc); 1230 atw_write_sup_rates(sc); 1231 if (ic->ic_caps & IEEE80211_C_WEP) 1232 atw_write_wep(sc); 1233 1234 /* 1235 * Set the receive filter. This will start the transmit and 1236 * receive processes. 1237 */ 1238 atw_filter_setup(sc); 1239 1240 /* 1241 * Start the receive process. 1242 */ 1243 ATW_WRITE(sc, ATW_RDR, 0x1); 1244 1245 /* 1246 * Note that the interface is now running. 1247 */ 1248 ifp->if_flags |= IFF_RUNNING; 1249 ifp->if_flags &= ~IFF_OACTIVE; 1250 ic->ic_state = IEEE80211_S_INIT; 1251 1252 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1253 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1254 else 1255 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1256 out: 1257 if (error) { 1258 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1259 ifp->if_timer = 0; 1260 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1261 } 1262 #ifdef ATW_DEBUG 1263 atw_print_regs(sc, "end of init"); 1264 #endif /* ATW_DEBUG */ 1265 1266 return (error); 1267 } 1268 1269 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1270 * 0: MAC control of RF3000/Si4126. 1271 * 1272 * Applies power, or selects RF front-end? Sets reset condition. 1273 * 1274 * TBD support non-RFMD BBP, non-SiLabs synth. 1275 */ 1276 static void 1277 atw_rfio_enable(struct atw_softc *sc, int enable) 1278 { 1279 if (enable) { 1280 ATW_WRITE(sc, ATW_SYNRF, 1281 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1282 DELAY(atw_rfio_enable_delay); 1283 } else { 1284 ATW_WRITE(sc, ATW_SYNRF, 0); 1285 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1286 } 1287 } 1288 1289 static int 1290 atw_tune(struct atw_softc *sc) 1291 { 1292 int rc; 1293 u_int32_t reg; 1294 int chan; 1295 struct ieee80211com *ic = &sc->sc_ic; 1296 1297 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1298 if (chan == IEEE80211_CHAN_ANY) 1299 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1300 1301 if (chan == sc->sc_cur_chan) 1302 return 0; 1303 1304 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1305 sc->sc_cur_chan, chan)); 1306 1307 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1308 1309 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1310 (rc = atw_rf3000_tune(sc, chan)) != 0) 1311 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1312 chan); 1313 1314 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1315 ATW_WRITE(sc, ATW_CAP0, 1316 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1317 1318 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1319 1320 if (rc == 0) 1321 sc->sc_cur_chan = chan; 1322 1323 return rc; 1324 } 1325 1326 #ifdef ATW_DEBUG 1327 static void 1328 atw_si4126_print(struct atw_softc *sc) 1329 { 1330 struct ifnet *ifp = &sc->sc_ic.ic_if; 1331 u_int addr, val; 1332 1333 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1334 return; 1335 1336 for (addr = 0; addr <= 8; addr++) { 1337 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1338 if (atw_si4126_read(sc, addr, &val) == 0) { 1339 printf("<unknown> (quitting print-out)\n"); 1340 break; 1341 } 1342 printf("%05x\n", val); 1343 } 1344 } 1345 #endif /* ATW_DEBUG */ 1346 1347 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1348 * 1349 * The RF/IF synthesizer produces two reference frequencies for 1350 * the RF2948B transceiver. The first frequency the RF2948B requires 1351 * is two times the so-called "intermediate frequency" (IF). Since 1352 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1353 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1354 * frequency required by the transceiver is the radio frequency 1355 * (RF). This is a superheterodyne transceiver; for f(chan) the 1356 * center frequency of the channel we are tuning, RF = f(chan) - 1357 * IF. 1358 * 1359 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1360 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1361 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1362 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1363 */ 1364 static int 1365 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1366 { 1367 int rc = 0; 1368 u_int mhz; 1369 u_int R; 1370 u_int32_t reg; 1371 u_int16_t gain; 1372 1373 #ifdef ATW_DEBUG 1374 atw_si4126_print(sc); 1375 #endif /* ATW_DEBUG */ 1376 1377 if (chan == 14) 1378 mhz = 2484; 1379 else 1380 mhz = 2412 + 5 * (chan - 1); 1381 1382 /* Tune IF to 748MHz to suit the IF LO input of the 1383 * RF2494B, which is 2 x IF. No need to set an IF divider 1384 * because an IF in 526MHz - 952MHz is allowed. 1385 * 1386 * XIN is 44.000MHz, so divide it by two to get allowable 1387 * range of 2-25MHz. SiLabs tells me that this is not 1388 * strictly necessary. 1389 */ 1390 1391 R = 44; 1392 1393 atw_rfio_enable(sc, 1); 1394 1395 /* Power-up RF, IF synthesizers. */ 1396 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1397 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1398 goto out; 1399 1400 /* If RF2 N > 2047, then set KP2 to 1. */ 1401 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1402 1403 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1404 goto out; 1405 1406 /* set LPWR, too? */ 1407 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1408 SI4126_MAIN_XINDIV2)) != 0) 1409 goto out; 1410 1411 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1412 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1413 */ 1414 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1415 goto out; 1416 1417 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1418 goto out; 1419 1420 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1421 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1422 * which has no RF1! 1423 */ 1424 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1425 goto out; 1426 1427 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1428 goto out; 1429 1430 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1431 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1432 * Now let's multiply it to mhz. So mhz - IF = N. 1433 */ 1434 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1435 goto out; 1436 1437 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1438 goto out; 1439 1440 /* wait 100us from power-up for RF, IF to settle */ 1441 DELAY(100); 1442 1443 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1444 /* XXX there is a binary driver which sends 1445 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1446 * that this enables the Si4126 by raising its PWDN#, but I 1447 * think that it actually sets the Prism RF front-end 1448 * to a special mode for channel 14. 1449 */ 1450 reg = ATW_READ(sc, ATW_GPIO); 1451 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1452 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1453 ATW_WRITE(sc, ATW_GPIO, reg); 1454 } 1455 1456 #ifdef ATW_DEBUG 1457 atw_si4126_print(sc); 1458 #endif /* ATW_DEBUG */ 1459 1460 out: 1461 atw_rfio_enable(sc, 0); 1462 1463 return rc; 1464 } 1465 1466 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1467 * diversity. 1468 * 1469 * Call this w/ Tx/Rx suspended. 1470 */ 1471 static int 1472 atw_rf3000_init(struct atw_softc *sc) 1473 { 1474 int rc = 0; 1475 1476 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1477 1478 atw_rfio_enable(sc, 1); 1479 1480 /* enable diversity */ 1481 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1482 1483 if (rc != 0) 1484 goto out; 1485 1486 /* sensible setting from a binary-only driver */ 1487 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1488 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1489 1490 if (rc != 0) 1491 goto out; 1492 1493 /* magic from a binary-only driver */ 1494 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1495 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1496 1497 if (rc != 0) 1498 goto out; 1499 1500 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1501 1502 if (rc != 0) 1503 goto out; 1504 1505 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1506 1507 if (rc != 0) 1508 goto out; 1509 1510 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1511 1512 if (rc != 0) 1513 goto out; 1514 1515 /* CCA is acquisition sensitive */ 1516 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1517 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1518 1519 if (rc != 0) 1520 goto out; 1521 1522 out: 1523 atw_rfio_enable(sc, 0); 1524 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1525 return rc; 1526 } 1527 1528 #ifdef ATW_DEBUG 1529 static void 1530 atw_rf3000_print(struct atw_softc *sc) 1531 { 1532 struct ifnet *ifp = &sc->sc_ic.ic_if; 1533 u_int addr, val; 1534 1535 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1536 return; 1537 1538 for (addr = 0x01; addr <= 0x15; addr++) { 1539 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1540 if (atw_rf3000_read(sc, addr, &val) != 0) { 1541 printf("<unknown> (quitting print-out)\n"); 1542 break; 1543 } 1544 printf("%08x\n", val); 1545 } 1546 } 1547 #endif /* ATW_DEBUG */ 1548 1549 /* Set the power settings on the BBP for channel `chan'. */ 1550 static int 1551 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1552 { 1553 int rc = 0; 1554 u_int32_t reg; 1555 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1556 1557 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1558 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1559 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1560 1561 /* odd channels: LSB, even channels: MSB */ 1562 if (chan % 2 == 1) { 1563 txpower &= 0xFF; 1564 lpf_cutoff &= 0xFF; 1565 lna_gs_thresh &= 0xFF; 1566 } else { 1567 txpower >>= 8; 1568 lpf_cutoff >>= 8; 1569 lna_gs_thresh >>= 8; 1570 } 1571 1572 #ifdef ATW_DEBUG 1573 atw_rf3000_print(sc); 1574 #endif /* ATW_DEBUG */ 1575 1576 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1577 "lna_gs_thresh %02x\n", 1578 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1579 1580 atw_rfio_enable(sc, 1); 1581 1582 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1583 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1584 goto out; 1585 1586 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1587 goto out; 1588 1589 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1590 goto out; 1591 1592 /* from a binary-only driver. */ 1593 reg = ATW_READ(sc, ATW_PLCPHD); 1594 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1595 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1596 ATW_WRITE(sc, ATW_PLCPHD, reg); 1597 1598 #ifdef ATW_DEBUG 1599 atw_rf3000_print(sc); 1600 #endif /* ATW_DEBUG */ 1601 1602 out: 1603 atw_rfio_enable(sc, 0); 1604 1605 return rc; 1606 } 1607 1608 /* Write a register on the RF3000 baseband processor using the 1609 * registers provided by the ADM8211 for this purpose. 1610 * 1611 * Return 0 on success. 1612 */ 1613 static int 1614 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1615 { 1616 u_int32_t reg; 1617 int i; 1618 1619 for (i = 1000; --i >= 0; ) { 1620 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1621 break; 1622 DELAY(100); 1623 } 1624 1625 if (i < 0) { 1626 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1627 return ETIMEDOUT; 1628 } 1629 1630 reg = sc->sc_bbpctl_wr | 1631 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1632 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1633 1634 ATW_WRITE(sc, ATW_BBPCTL, reg); 1635 1636 for (i = 1000; --i >= 0; ) { 1637 DELAY(100); 1638 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1639 break; 1640 } 1641 1642 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1643 1644 if (i < 0) { 1645 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1646 return ETIMEDOUT; 1647 } 1648 return 0; 1649 } 1650 1651 /* Read a register on the RF3000 baseband processor using the registers 1652 * the ADM8211 provides for this purpose. 1653 * 1654 * The 7-bit register address is addr. Record the 8-bit data in the register 1655 * in *val. 1656 * 1657 * Return 0 on success. 1658 * 1659 * XXX This does not seem to work. The ADM8211 must require more or 1660 * different magic to read the chip than to write it. Possibly some 1661 * of the magic I have derived from a binary-only driver concerns 1662 * the "chip address" (see the RF3000 manual). 1663 */ 1664 #ifdef ATW_DEBUG 1665 static int 1666 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1667 { 1668 u_int32_t reg; 1669 int i; 1670 1671 for (i = 1000; --i >= 0; ) { 1672 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1673 break; 1674 DELAY(100); 1675 } 1676 1677 if (i < 0) { 1678 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1679 sc->sc_dev.dv_xname); 1680 return ETIMEDOUT; 1681 } 1682 1683 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1684 1685 ATW_WRITE(sc, ATW_BBPCTL, reg); 1686 1687 for (i = 1000; --i >= 0; ) { 1688 DELAY(100); 1689 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1690 break; 1691 } 1692 1693 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1694 1695 if (i < 0) { 1696 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1697 sc->sc_dev.dv_xname, reg); 1698 return ETIMEDOUT; 1699 } 1700 if (val != NULL) 1701 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1702 return 0; 1703 } 1704 #endif /* ATW_DEBUG */ 1705 1706 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1707 * provided by the ADM8211 for that purpose. 1708 * 1709 * val is 18 bits of data, and val is the 4-bit address of the register. 1710 * 1711 * Return 0 on success. 1712 */ 1713 static int 1714 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1715 { 1716 u_int32_t bits, reg; 1717 int i; 1718 1719 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1720 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1721 1722 for (i = 1000; --i >= 0; ) { 1723 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1724 break; 1725 DELAY(100); 1726 } 1727 1728 if (i < 0) { 1729 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1730 sc->sc_dev.dv_xname); 1731 return ETIMEDOUT; 1732 } 1733 1734 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1735 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1736 1737 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1738 1739 ATW_WRITE(sc, ATW_SYNCTL, reg); 1740 1741 for (i = 1000; --i >= 0; ) { 1742 DELAY(100); 1743 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1744 break; 1745 } 1746 1747 /* restore to acceptable starting condition */ 1748 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1749 1750 if (i < 0) { 1751 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1752 sc->sc_dev.dv_xname, reg); 1753 return ETIMEDOUT; 1754 } 1755 return 0; 1756 } 1757 1758 /* Read 18-bit data from the 4-bit address addr in Si4126 1759 * RF synthesizer and write the data to *val. Return 0 on success. 1760 * 1761 * XXX This does not seem to work. The ADM8211 must require more or 1762 * different magic to read the chip than to write it. 1763 */ 1764 #ifdef ATW_DEBUG 1765 static int 1766 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1767 { 1768 u_int32_t reg; 1769 int i; 1770 1771 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1772 1773 for (i = 1000; --i >= 0; ) { 1774 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1775 break; 1776 DELAY(100); 1777 } 1778 1779 if (i < 0) { 1780 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1781 sc->sc_dev.dv_xname); 1782 return ETIMEDOUT; 1783 } 1784 1785 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1786 1787 ATW_WRITE(sc, ATW_SYNCTL, reg); 1788 1789 for (i = 1000; --i >= 0; ) { 1790 DELAY(100); 1791 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1792 break; 1793 } 1794 1795 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1796 1797 if (i < 0) { 1798 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1799 sc->sc_dev.dv_xname, reg); 1800 return ETIMEDOUT; 1801 } 1802 if (val != NULL) 1803 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1804 ATW_SYNCTL_DATA_MASK); 1805 return 0; 1806 } 1807 #endif /* ATW_DEBUG */ 1808 1809 /* XXX is the endianness correct? test. */ 1810 #define atw_calchash(addr) \ 1811 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1812 1813 /* 1814 * atw_filter_setup: 1815 * 1816 * Set the ADM8211's receive filter. 1817 */ 1818 static void 1819 atw_filter_setup(struct atw_softc *sc) 1820 { 1821 struct ieee80211com *ic = &sc->sc_ic; 1822 struct ethercom *ec = &ic->ic_ec; 1823 struct ifnet *ifp = &sc->sc_ic.ic_if; 1824 int hash; 1825 u_int32_t hashes[2] = { 0, 0 }; 1826 struct ether_multi *enm; 1827 struct ether_multistep step; 1828 1829 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1830 sc->sc_dev.dv_xname, sc->sc_flags)); 1831 1832 /* 1833 * If we're running, idle the receive engine. If we're NOT running, 1834 * we're being called from atw_init(), and our writing ATW_NAR will 1835 * start the transmit and receive processes in motion. 1836 */ 1837 if (ifp->if_flags & IFF_RUNNING) 1838 atw_idle(sc, ATW_NAR_SR); 1839 1840 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1841 1842 ifp->if_flags &= ~IFF_ALLMULTI; 1843 1844 if (ifp->if_flags & IFF_PROMISC) { 1845 sc->sc_opmode |= ATW_NAR_PR; 1846 allmulti: 1847 ifp->if_flags |= IFF_ALLMULTI; 1848 goto setit; 1849 } 1850 1851 /* 1852 * Program the 64-bit multicast hash filter. 1853 */ 1854 ETHER_FIRST_MULTI(step, ec, enm); 1855 while (enm != NULL) { 1856 /* XXX */ 1857 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1858 ETHER_ADDR_LEN) != 0) 1859 goto allmulti; 1860 1861 hash = atw_calchash(enm->enm_addrlo); 1862 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1863 ETHER_NEXT_MULTI(step, enm); 1864 } 1865 1866 if (ifp->if_flags & IFF_BROADCAST) { 1867 hash = atw_calchash(etherbroadcastaddr); 1868 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1869 } 1870 1871 /* all bits set => hash is useless */ 1872 if (~(hashes[0] & hashes[1]) == 0) 1873 goto allmulti; 1874 1875 setit: 1876 if (ifp->if_flags & IFF_ALLMULTI) 1877 sc->sc_opmode |= ATW_NAR_MM; 1878 1879 /* XXX in scan mode, do not filter packets. maybe this is 1880 * unnecessary. 1881 */ 1882 if (ic->ic_state == IEEE80211_S_SCAN) 1883 sc->sc_opmode |= ATW_NAR_PR; 1884 1885 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1886 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1887 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1888 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1889 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1890 1891 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1892 } 1893 1894 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1895 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1896 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1897 * no beacon with the preferred BSSID and SSID in the number of 1898 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1899 */ 1900 static void 1901 atw_write_bssid(struct atw_softc *sc) 1902 { 1903 struct ieee80211com *ic = &sc->sc_ic; 1904 u_int8_t *bssid; 1905 1906 bssid = ic->ic_bss->ni_bssid; 1907 1908 ATW_WRITE(sc, ATW_ABDA1, 1909 (ATW_READ(sc, ATW_ABDA1) & 1910 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1911 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1912 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1913 1914 ATW_WRITE(sc, ATW_BSSID0, 1915 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1916 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1917 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1918 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1919 1920 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1921 ether_sprintf(sc->sc_bssid))); 1922 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1923 1924 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1925 } 1926 1927 /* Tell the ADM8211 how many beacon intervals must pass without 1928 * receiving a beacon with the preferred BSSID & SSID set by 1929 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1930 * raised. 1931 */ 1932 static void 1933 atw_write_bcn_thresh(struct atw_softc *sc) 1934 { 1935 struct ieee80211com *ic = &sc->sc_ic; 1936 int lost_bcn_thresh; 1937 1938 /* Lose link after one second or 7 beacons, whichever comes 1939 * first, but do not lose link before 2 beacons are lost. 1940 * 1941 * In host AP mode, set the lost-beacon threshold to 0. 1942 */ 1943 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1944 lost_bcn_thresh = 0; 1945 else { 1946 int beacons_per_second = 1947 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1948 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1949 } 1950 1951 /* XXX resets wake-up status bits */ 1952 ATW_WRITE(sc, ATW_WCSR, 1953 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1954 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1955 1956 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1957 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1958 1959 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1960 1961 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1962 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1963 } 1964 1965 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1966 * 16-bit word. 1967 */ 1968 static void 1969 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1970 { 1971 u_int i; 1972 u_int8_t *ptr; 1973 1974 memcpy(&sc->sc_sram[ofs], buf, buflen); 1975 1976 if (ofs % 2 != 0) { 1977 ofs--; 1978 buflen++; 1979 } 1980 1981 if (buflen % 2 != 0) 1982 buflen++; 1983 1984 assert(buflen + ofs <= ATW_SRAM_SIZE); 1985 1986 ptr = &sc->sc_sram[ofs]; 1987 1988 for (i = 0; i < buflen; i += 2) { 1989 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1990 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1991 DELAY(atw_writewep_delay); 1992 1993 ATW_WRITE(sc, ATW_WESK, 1994 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1995 DELAY(atw_writewep_delay); 1996 } 1997 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1998 1999 if (sc->sc_if.if_flags & IFF_DEBUG) { 2000 int n_octets = 0; 2001 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2002 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2003 for (i = 0; i < buflen; i++) { 2004 printf(" %02x", ptr[i]); 2005 if (++n_octets % 24 == 0) 2006 printf("\n"); 2007 } 2008 if (n_octets % 24 != 0) 2009 printf("\n"); 2010 } 2011 } 2012 2013 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2014 static void 2015 atw_write_wep(struct atw_softc *sc) 2016 { 2017 struct ieee80211com *ic = &sc->sc_ic; 2018 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2019 u_int8_t buf[IEEE80211_WEP_NKID] 2020 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2021 u_int32_t reg; 2022 int i; 2023 2024 sc->sc_wepctl = 0; 2025 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2026 2027 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2028 return; 2029 2030 memset(&buf[0][0], 0, sizeof(buf)); 2031 2032 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2033 if (ic->ic_nw_keys[i].wk_len > 5) { 2034 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2035 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2036 buf[i][1] = ATW_WEP_ENABLED; 2037 } else { 2038 buf[i][1] = 0; 2039 continue; 2040 } 2041 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2042 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2043 ic->ic_nw_keys[i].wk_len - 1); 2044 } 2045 2046 reg = ATW_READ(sc, ATW_MACTEST); 2047 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2048 reg &= ~ATW_MACTEST_KEYID_MASK; 2049 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2050 ATW_WRITE(sc, ATW_MACTEST, reg); 2051 2052 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2053 * throughout.) 2054 */ 2055 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2056 if (sc->sc_if.if_flags & IFF_LINK2) 2057 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2058 2059 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2060 sizeof(buf)); 2061 } 2062 2063 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2064 2065 static void 2066 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2067 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2068 { 2069 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2070 2071 switch (subtype) { 2072 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2073 /* do nothing: hardware answers probe request */ 2074 break; 2075 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2076 case IEEE80211_FC0_SUBTYPE_BEACON: 2077 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2078 break; 2079 default: 2080 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2081 break; 2082 } 2083 return; 2084 } 2085 2086 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2087 * of IBSSs with like SSID/channel but different BSSID. It joins the 2088 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2089 * convention. Possibly the ADMtek chip does this for us; I will have 2090 * to test to find out. 2091 * 2092 * XXX we should add the duration field of the received beacon to 2093 * the TSF time it contains before comparing it with the ADM8211's 2094 * TSF. 2095 */ 2096 static void 2097 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2098 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2099 { 2100 struct atw_softc *sc; 2101 struct ieee80211_frame *wh; 2102 u_int64_t tsft, bcn_tsft; 2103 u_int32_t tsftl, tsfth; 2104 int do_print = 0; 2105 2106 sc = (struct atw_softc*)ic->ic_if.if_softc; 2107 2108 if (ic->ic_if.if_flags & IFF_DEBUG) 2109 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2110 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2111 2112 wh = mtod(m0, struct ieee80211_frame *); 2113 2114 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2115 2116 if (ic->ic_state != IEEE80211_S_RUN) { 2117 if (do_print) 2118 printf("%s: atw_recv_beacon: not running\n", 2119 sc->sc_dev.dv_xname); 2120 return; 2121 } 2122 2123 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2124 ic->ic_bss->ni_chan)) == NULL) { 2125 if (do_print) 2126 printf("%s: atw_recv_beacon: no node %s\n", 2127 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2128 return; 2129 } 2130 2131 if (ieee80211_match_bss(ic, ni) != 0) { 2132 if (do_print) 2133 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2134 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2135 return; 2136 } 2137 2138 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2139 return; 2140 2141 if (do_print) 2142 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2143 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2144 2145 if (ic->ic_opmode != IEEE80211_M_IBSS) 2146 return; 2147 2148 /* If we read TSFTL right before rollover, we read a TSF timer 2149 * that is too high rather than too low. This prevents a spurious 2150 * synchronization down the line, however, our IBSS could suffer 2151 * from a creeping TSF.... 2152 */ 2153 tsftl = ATW_READ(sc, ATW_TSFTL); 2154 tsfth = ATW_READ(sc, ATW_TSFTH); 2155 2156 tsft = (u_int64_t)tsfth << 32 | tsftl; 2157 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2158 2159 if (do_print) 2160 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2161 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2162 2163 /* we are faster, let the other guy catch up */ 2164 if (bcn_tsft < tsft) 2165 return; 2166 2167 if (do_print) 2168 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2169 ether_sprintf(wh->i_addr2)); 2170 2171 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2172 2173 #if 0 2174 atw_tsf(sc); 2175 #endif 2176 2177 /* negotiate rates with new IBSS */ 2178 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2179 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2180 if (ni->ni_rates.rs_nrates == 0) { 2181 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2182 ether_sprintf(ni->ni_bssid)); 2183 return; 2184 } 2185 2186 if (do_print) { 2187 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2188 ether_sprintf(ic->ic_bss->ni_bssid)); 2189 printf("%s ", ether_sprintf(ni->ni_bssid)); 2190 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2191 } 2192 2193 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2194 2195 atw_write_bssid(sc); 2196 atw_write_bcn_thresh(sc); 2197 atw_start_beacon(sc, 1); 2198 } 2199 2200 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2201 * In ad hoc mode, the SSID is written to the beacons sent by the 2202 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2203 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2204 * indications. 2205 */ 2206 static void 2207 atw_write_ssid(struct atw_softc *sc) 2208 { 2209 struct ieee80211com *ic = &sc->sc_ic; 2210 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2211 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2212 2213 memset(buf, 0, sizeof(buf)); 2214 buf[0] = ic->ic_bss->ni_esslen; 2215 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2216 2217 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2218 } 2219 2220 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2221 * In ad hoc mode, the supported rates are written to beacons sent by the 2222 * ADM8211. 2223 */ 2224 static void 2225 atw_write_sup_rates(struct atw_softc *sc) 2226 { 2227 struct ieee80211com *ic = &sc->sc_ic; 2228 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2229 * supported rates 2230 */ 2231 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2232 2233 memset(buf, 0, sizeof(buf)); 2234 2235 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2236 2237 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2238 ic->ic_bss->ni_rates.rs_nrates); 2239 2240 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2241 } 2242 2243 /* Start/stop sending beacons. */ 2244 void 2245 atw_start_beacon(struct atw_softc *sc, int start) 2246 { 2247 struct ieee80211com *ic = &sc->sc_ic; 2248 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2249 2250 if (ATW_IS_ENABLED(sc) == 0) 2251 return; 2252 2253 len = capinfo = 0; 2254 2255 /* start beacons */ 2256 len = sizeof(struct ieee80211_frame) + 2257 8 /* timestamp */ + 2 /* beacon interval */ + 2258 2 /* capability info */ + 2259 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2260 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2261 3 /* DS parameters */ + 2262 IEEE80211_CRC_LEN; 2263 2264 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2265 2266 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2267 2268 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2269 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2270 2271 if (!start) 2272 return; 2273 2274 /* TBD use ni_capinfo */ 2275 2276 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2277 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2278 if (ic->ic_flags & IEEE80211_F_WEPON) 2279 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2280 2281 switch (ic->ic_opmode) { 2282 case IEEE80211_M_IBSS: 2283 len += 4; /* IBSS parameters */ 2284 capinfo |= IEEE80211_CAPINFO_IBSS; 2285 break; 2286 case IEEE80211_M_HOSTAP: 2287 /* XXX 6-byte minimum TIM */ 2288 len += atw_beacon_len_adjust; 2289 capinfo |= IEEE80211_CAPINFO_ESS; 2290 break; 2291 default: 2292 return; 2293 } 2294 2295 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2296 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2297 2298 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2299 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2300 2301 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2302 sc->sc_dev.dv_xname, reg_bcnt)); 2303 2304 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2305 sc->sc_dev.dv_xname, reg_cap1)); 2306 } 2307 2308 /* First beacon was sent at time 0 microseconds, current time is 2309 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2310 * microseconds. Return the expected time in microseconds for the 2311 * beacon after next. 2312 */ 2313 static __inline u_int64_t 2314 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2315 { 2316 return tsft + (tbtt - tsft % tbtt); 2317 } 2318 2319 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2320 * the ieee80211com. 2321 * 2322 * Predict the next target beacon transmission time (TBTT) and 2323 * write it to the ADM8211. 2324 */ 2325 static void 2326 atw_tsf(struct atw_softc *sc) 2327 { 2328 #define TBTTOFS 20 /* TU */ 2329 2330 struct ieee80211com *ic = &sc->sc_ic; 2331 u_int64_t tsft, tbtt; 2332 2333 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2334 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2335 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2336 tsft = ATW_READ(sc, ATW_TSFTH); 2337 tsft <<= 32; 2338 tsft |= ATW_READ(sc, ATW_TSFTL); 2339 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2340 } else 2341 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2342 2343 tbtt = atw_predict_beacon(tsft, 2344 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2345 2346 /* skip one more beacon so that the TBTT cannot pass before 2347 * we've programmed it, and also so that we can subtract a 2348 * few TU so that we wake a little before TBTT. 2349 */ 2350 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2351 2352 /* wake up a little early */ 2353 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2354 2355 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2356 sc->sc_dev.dv_xname, tsft, tbtt)); 2357 2358 ATW_WRITE(sc, ATW_TOFS1, 2359 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2360 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2361 LSHIFT( 2362 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2363 ATW_TOFS1_TBTTPRE_MASK)); 2364 #undef TBTTOFS 2365 } 2366 2367 static void 2368 atw_next_scan(void *arg) 2369 { 2370 struct atw_softc *sc = arg; 2371 struct ieee80211com *ic = &sc->sc_ic; 2372 struct ifnet *ifp = &ic->ic_if; 2373 int s; 2374 2375 /* don't call atw_start w/o network interrupts blocked */ 2376 s = splnet(); 2377 if (ic->ic_state == IEEE80211_S_SCAN) 2378 ieee80211_next_scan(ifp); 2379 splx(s); 2380 } 2381 2382 /* Synchronize the hardware state with the software state. */ 2383 static int 2384 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2385 { 2386 struct ifnet *ifp = &ic->ic_if; 2387 struct atw_softc *sc = ifp->if_softc; 2388 enum ieee80211_state ostate; 2389 int error; 2390 2391 ostate = ic->ic_state; 2392 2393 if (nstate == IEEE80211_S_INIT) { 2394 callout_stop(&sc->sc_scan_ch); 2395 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2396 atw_start_beacon(sc, 0); 2397 return (*sc->sc_newstate)(ic, nstate, arg); 2398 } 2399 2400 if ((error = atw_tune(sc)) != 0) 2401 return error; 2402 2403 switch (nstate) { 2404 case IEEE80211_S_ASSOC: 2405 break; 2406 case IEEE80211_S_INIT: 2407 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2408 break; 2409 case IEEE80211_S_SCAN: 2410 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2411 atw_write_bssid(sc); 2412 2413 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2414 atw_next_scan, sc); 2415 2416 break; 2417 case IEEE80211_S_RUN: 2418 if (ic->ic_opmode == IEEE80211_M_STA) 2419 break; 2420 /*FALLTHROUGH*/ 2421 case IEEE80211_S_AUTH: 2422 atw_write_bssid(sc); 2423 atw_write_bcn_thresh(sc); 2424 atw_write_ssid(sc); 2425 atw_write_sup_rates(sc); 2426 2427 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2428 ic->ic_opmode == IEEE80211_M_MONITOR) 2429 break; 2430 2431 /* set listen interval 2432 * XXX do software units agree w/ hardware? 2433 */ 2434 ATW_WRITE(sc, ATW_BPLI, 2435 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2436 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2437 ATW_BPLI_LI_MASK)); 2438 2439 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2440 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2441 2442 atw_tsf(sc); 2443 break; 2444 } 2445 2446 if (nstate != IEEE80211_S_SCAN) 2447 callout_stop(&sc->sc_scan_ch); 2448 2449 if (nstate == IEEE80211_S_RUN && 2450 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2451 ic->ic_opmode == IEEE80211_M_IBSS)) 2452 atw_start_beacon(sc, 1); 2453 else 2454 atw_start_beacon(sc, 0); 2455 2456 return (*sc->sc_newstate)(ic, nstate, arg); 2457 } 2458 2459 /* 2460 * atw_add_rxbuf: 2461 * 2462 * Add a receive buffer to the indicated descriptor. 2463 */ 2464 int 2465 atw_add_rxbuf(struct atw_softc *sc, int idx) 2466 { 2467 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2468 struct mbuf *m; 2469 int error; 2470 2471 MGETHDR(m, M_DONTWAIT, MT_DATA); 2472 if (m == NULL) 2473 return (ENOBUFS); 2474 2475 MCLGET(m, M_DONTWAIT); 2476 if ((m->m_flags & M_EXT) == 0) { 2477 m_freem(m); 2478 return (ENOBUFS); 2479 } 2480 2481 if (rxs->rxs_mbuf != NULL) 2482 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2483 2484 rxs->rxs_mbuf = m; 2485 2486 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2487 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2488 BUS_DMA_READ|BUS_DMA_NOWAIT); 2489 if (error) { 2490 printf("%s: can't load rx DMA map %d, error = %d\n", 2491 sc->sc_dev.dv_xname, idx, error); 2492 panic("atw_add_rxbuf"); /* XXX */ 2493 } 2494 2495 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2496 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2497 2498 ATW_INIT_RXDESC(sc, idx); 2499 2500 return (0); 2501 } 2502 2503 /* 2504 * atw_stop: [ ifnet interface function ] 2505 * 2506 * Stop transmission on the interface. 2507 */ 2508 void 2509 atw_stop(struct ifnet *ifp, int disable) 2510 { 2511 struct atw_softc *sc = ifp->if_softc; 2512 struct ieee80211com *ic = &sc->sc_ic; 2513 struct atw_txsoft *txs; 2514 2515 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2516 2517 /* Disable interrupts. */ 2518 ATW_WRITE(sc, ATW_IER, 0); 2519 2520 /* Stop the transmit and receive processes. */ 2521 sc->sc_opmode = 0; 2522 ATW_WRITE(sc, ATW_NAR, 0); 2523 ATW_WRITE(sc, ATW_TDBD, 0); 2524 ATW_WRITE(sc, ATW_TDBP, 0); 2525 ATW_WRITE(sc, ATW_RDB, 0); 2526 2527 /* 2528 * Release any queued transmit buffers. 2529 */ 2530 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2531 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2532 if (txs->txs_mbuf != NULL) { 2533 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2534 m_freem(txs->txs_mbuf); 2535 txs->txs_mbuf = NULL; 2536 } 2537 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2538 } 2539 2540 if (disable) { 2541 atw_rxdrain(sc); 2542 atw_disable(sc); 2543 } 2544 2545 /* 2546 * Mark the interface down and cancel the watchdog timer. 2547 */ 2548 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2549 ifp->if_timer = 0; 2550 2551 /* XXX */ 2552 atw_reset(sc); 2553 } 2554 2555 /* 2556 * atw_rxdrain: 2557 * 2558 * Drain the receive queue. 2559 */ 2560 void 2561 atw_rxdrain(struct atw_softc *sc) 2562 { 2563 struct atw_rxsoft *rxs; 2564 int i; 2565 2566 for (i = 0; i < ATW_NRXDESC; i++) { 2567 rxs = &sc->sc_rxsoft[i]; 2568 if (rxs->rxs_mbuf == NULL) 2569 continue; 2570 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2571 m_freem(rxs->rxs_mbuf); 2572 rxs->rxs_mbuf = NULL; 2573 } 2574 } 2575 2576 /* 2577 * atw_detach: 2578 * 2579 * Detach an ADM8211 interface. 2580 */ 2581 int 2582 atw_detach(struct atw_softc *sc) 2583 { 2584 struct ifnet *ifp = &sc->sc_ic.ic_if; 2585 struct atw_rxsoft *rxs; 2586 struct atw_txsoft *txs; 2587 int i; 2588 2589 /* 2590 * Succeed now if there isn't any work to do. 2591 */ 2592 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2593 return (0); 2594 2595 ieee80211_ifdetach(ifp); 2596 if_detach(ifp); 2597 2598 for (i = 0; i < ATW_NRXDESC; i++) { 2599 rxs = &sc->sc_rxsoft[i]; 2600 if (rxs->rxs_mbuf != NULL) { 2601 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2602 m_freem(rxs->rxs_mbuf); 2603 rxs->rxs_mbuf = NULL; 2604 } 2605 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2606 } 2607 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2608 txs = &sc->sc_txsoft[i]; 2609 if (txs->txs_mbuf != NULL) { 2610 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2611 m_freem(txs->txs_mbuf); 2612 txs->txs_mbuf = NULL; 2613 } 2614 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2615 } 2616 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2617 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2618 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2619 sizeof(struct atw_control_data)); 2620 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2621 2622 shutdownhook_disestablish(sc->sc_sdhook); 2623 powerhook_disestablish(sc->sc_powerhook); 2624 2625 if (sc->sc_srom) 2626 free(sc->sc_srom, M_DEVBUF); 2627 2628 return (0); 2629 } 2630 2631 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2632 void 2633 atw_shutdown(void *arg) 2634 { 2635 struct atw_softc *sc = arg; 2636 2637 atw_stop(&sc->sc_ic.ic_if, 1); 2638 } 2639 2640 int 2641 atw_intr(void *arg) 2642 { 2643 struct atw_softc *sc = arg; 2644 struct ifnet *ifp = &sc->sc_ic.ic_if; 2645 u_int32_t status, rxstatus, txstatus, linkstatus; 2646 int handled = 0, txthresh; 2647 2648 #ifdef DEBUG 2649 if (ATW_IS_ENABLED(sc) == 0) 2650 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2651 #endif 2652 2653 /* 2654 * If the interface isn't running, the interrupt couldn't 2655 * possibly have come from us. 2656 */ 2657 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2658 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2659 return (0); 2660 2661 for (;;) { 2662 status = ATW_READ(sc, ATW_STSR); 2663 2664 if (status) 2665 ATW_WRITE(sc, ATW_STSR, status); 2666 2667 if (sc->sc_intr_ack != NULL) 2668 (*sc->sc_intr_ack)(sc); 2669 2670 #ifdef ATW_DEBUG 2671 #define PRINTINTR(flag) do { \ 2672 if ((status & flag) != 0) { \ 2673 printf("%s" #flag, delim); \ 2674 delim = ","; \ 2675 } \ 2676 } while (0) 2677 2678 if (atw_debug > 1 && status) { 2679 const char *delim = "<"; 2680 2681 printf("%s: reg[STSR] = %x", 2682 sc->sc_dev.dv_xname, status); 2683 2684 PRINTINTR(ATW_INTR_FBE); 2685 PRINTINTR(ATW_INTR_LINKOFF); 2686 PRINTINTR(ATW_INTR_LINKON); 2687 PRINTINTR(ATW_INTR_RCI); 2688 PRINTINTR(ATW_INTR_RDU); 2689 PRINTINTR(ATW_INTR_REIS); 2690 PRINTINTR(ATW_INTR_RPS); 2691 PRINTINTR(ATW_INTR_TCI); 2692 PRINTINTR(ATW_INTR_TDU); 2693 PRINTINTR(ATW_INTR_TLT); 2694 PRINTINTR(ATW_INTR_TPS); 2695 PRINTINTR(ATW_INTR_TRT); 2696 PRINTINTR(ATW_INTR_TUF); 2697 PRINTINTR(ATW_INTR_BCNTC); 2698 PRINTINTR(ATW_INTR_ATIME); 2699 PRINTINTR(ATW_INTR_TBTT); 2700 PRINTINTR(ATW_INTR_TSCZ); 2701 PRINTINTR(ATW_INTR_TSFTF); 2702 printf(">\n"); 2703 } 2704 #undef PRINTINTR 2705 #endif /* ATW_DEBUG */ 2706 2707 if ((status & sc->sc_inten) == 0) 2708 break; 2709 2710 handled = 1; 2711 2712 rxstatus = status & sc->sc_rxint_mask; 2713 txstatus = status & sc->sc_txint_mask; 2714 linkstatus = status & sc->sc_linkint_mask; 2715 2716 if (linkstatus) { 2717 atw_linkintr(sc, linkstatus); 2718 } 2719 2720 if (rxstatus) { 2721 /* Grab any new packets. */ 2722 atw_rxintr(sc); 2723 2724 if (rxstatus & ATW_INTR_RDU) { 2725 printf("%s: receive ring overrun\n", 2726 sc->sc_dev.dv_xname); 2727 /* Get the receive process going again. */ 2728 ATW_WRITE(sc, ATW_RDR, 0x1); 2729 break; 2730 } 2731 } 2732 2733 if (txstatus) { 2734 /* Sweep up transmit descriptors. */ 2735 atw_txintr(sc); 2736 2737 if (txstatus & ATW_INTR_TLT) 2738 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2739 sc->sc_dev.dv_xname)); 2740 2741 if (txstatus & ATW_INTR_TRT) 2742 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2743 sc->sc_dev.dv_xname)); 2744 2745 /* If Tx under-run, increase our transmit threshold 2746 * if another is available. 2747 */ 2748 txthresh = sc->sc_txthresh + 1; 2749 if ((txstatus & ATW_INTR_TUF) && 2750 sc->sc_txth[txthresh].txth_name != NULL) { 2751 /* Idle the transmit process. */ 2752 atw_idle(sc, ATW_NAR_ST); 2753 2754 sc->sc_txthresh = txthresh; 2755 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2756 sc->sc_opmode |= 2757 sc->sc_txth[txthresh].txth_opmode; 2758 printf("%s: transmit underrun; new " 2759 "threshold: %s\n", sc->sc_dev.dv_xname, 2760 sc->sc_txth[txthresh].txth_name); 2761 2762 /* Set the new threshold and restart 2763 * the transmit process. 2764 */ 2765 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2766 /* XXX Log every Nth underrun from 2767 * XXX now on? 2768 */ 2769 } 2770 } 2771 2772 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2773 if (status & ATW_INTR_TPS) 2774 printf("%s: transmit process stopped\n", 2775 sc->sc_dev.dv_xname); 2776 if (status & ATW_INTR_RPS) 2777 printf("%s: receive process stopped\n", 2778 sc->sc_dev.dv_xname); 2779 (void)atw_init(ifp); 2780 break; 2781 } 2782 2783 if (status & ATW_INTR_FBE) { 2784 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2785 (void)atw_init(ifp); 2786 break; 2787 } 2788 2789 /* 2790 * Not handled: 2791 * 2792 * Transmit buffer unavailable -- normal 2793 * condition, nothing to do, really. 2794 * 2795 * Early receive interrupt -- not available on 2796 * all chips, we just use RI. We also only 2797 * use single-segment receive DMA, so this 2798 * is mostly useless. 2799 * 2800 * TBD others 2801 */ 2802 } 2803 2804 /* Try to get more packets going. */ 2805 atw_start(ifp); 2806 2807 return (handled); 2808 } 2809 2810 /* 2811 * atw_idle: 2812 * 2813 * Cause the transmit and/or receive processes to go idle. 2814 * 2815 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2816 * process in STSR if I clear SR or ST after the process has already 2817 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2818 * do not seem to be too reliable. Perhaps I have the sense of the 2819 * Rx bits switched with the Tx bits? 2820 */ 2821 void 2822 atw_idle(struct atw_softc *sc, u_int32_t bits) 2823 { 2824 u_int32_t ackmask = 0, opmode, stsr, test0; 2825 int i, s; 2826 2827 /* without this, somehow we run concurrently w/ interrupt handler */ 2828 s = splnet(); 2829 2830 opmode = sc->sc_opmode & ~bits; 2831 2832 if (bits & ATW_NAR_SR) 2833 ackmask |= ATW_INTR_RPS; 2834 2835 if (bits & ATW_NAR_ST) { 2836 ackmask |= ATW_INTR_TPS; 2837 /* set ATW_NAR_HF to flush TX FIFO. */ 2838 opmode |= ATW_NAR_HF; 2839 } 2840 2841 ATW_WRITE(sc, ATW_NAR, opmode); 2842 2843 for (i = 0; i < 1000; i++) { 2844 stsr = ATW_READ(sc, ATW_STSR); 2845 if ((stsr & ackmask) == ackmask) 2846 break; 2847 DELAY(10); 2848 } 2849 2850 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2851 2852 if ((stsr & ackmask) == ackmask) 2853 goto out; 2854 2855 test0 = ATW_READ(sc, ATW_TEST0); 2856 2857 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2858 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2859 printf("%s: transmit process not idle [%s]\n", 2860 sc->sc_dev.dv_xname, 2861 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2862 printf("%s: bits %08x test0 %08x stsr %08x\n", 2863 sc->sc_dev.dv_xname, bits, test0, stsr); 2864 } 2865 2866 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2867 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2868 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2869 sc->sc_dev.dv_xname, 2870 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2871 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2872 sc->sc_dev.dv_xname, bits, test0, stsr)); 2873 } 2874 out: 2875 splx(s); 2876 return; 2877 } 2878 2879 /* 2880 * atw_linkintr: 2881 * 2882 * Helper; handle link-status interrupts. 2883 */ 2884 void 2885 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2886 { 2887 struct ieee80211com *ic = &sc->sc_ic; 2888 2889 if (ic->ic_state != IEEE80211_S_RUN) 2890 return; 2891 2892 if (linkstatus & ATW_INTR_LINKON) { 2893 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2894 sc->sc_rescan_timer = 0; 2895 } else if (linkstatus & ATW_INTR_LINKOFF) { 2896 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2897 switch (ic->ic_opmode) { 2898 case IEEE80211_M_HOSTAP: 2899 return; 2900 case IEEE80211_M_IBSS: 2901 if (ic->ic_flags & IEEE80211_F_SIBSS) 2902 return; 2903 /*FALLTHROUGH*/ 2904 case IEEE80211_M_STA: 2905 sc->sc_rescan_timer = 3; 2906 ic->ic_if.if_timer = 1; 2907 break; 2908 default: 2909 break; 2910 } 2911 } 2912 } 2913 2914 /* 2915 * atw_rxintr: 2916 * 2917 * Helper; handle receive interrupts. 2918 */ 2919 void 2920 atw_rxintr(struct atw_softc *sc) 2921 { 2922 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2923 struct ieee80211com *ic = &sc->sc_ic; 2924 struct ieee80211_node *ni; 2925 struct ieee80211_frame *wh; 2926 struct ifnet *ifp = &ic->ic_if; 2927 struct atw_rxsoft *rxs; 2928 struct mbuf *m; 2929 u_int32_t rxstat; 2930 int i, len, rate, rate0; 2931 u_int32_t rssi; 2932 2933 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2934 rxs = &sc->sc_rxsoft[i]; 2935 2936 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2937 2938 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2939 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2940 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2941 2942 if (rxstat & ATW_RXSTAT_OWN) 2943 break; /* We have processed all receive buffers. */ 2944 2945 DPRINTF3(sc, 2946 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2947 sc->sc_dev.dv_xname, 2948 sc->sc_rxdescs[i].ar_stat, 2949 sc->sc_rxdescs[i].ar_rssi, 2950 sc->sc_rxdescs[i].ar_buf1, 2951 sc->sc_rxdescs[i].ar_buf2)); 2952 2953 /* 2954 * Make sure the packet fit in one buffer. This should 2955 * always be the case. 2956 */ 2957 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2958 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2959 printf("%s: incoming packet spilled, resetting\n", 2960 sc->sc_dev.dv_xname); 2961 (void)atw_init(ifp); 2962 return; 2963 } 2964 2965 /* 2966 * If an error occurred, update stats, clear the status 2967 * word, and leave the packet buffer in place. It will 2968 * simply be reused the next time the ring comes around. 2969 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2970 * error. 2971 */ 2972 2973 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2974 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2975 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2976 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2977 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2978 ATW_RXSTAT_ICVE)) != 0)) { 2979 #define PRINTERR(bit, str) \ 2980 if (rxstat & (bit)) \ 2981 printf("%s: receive error: %s\n", \ 2982 sc->sc_dev.dv_xname, str) 2983 ifp->if_ierrors++; 2984 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2985 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2986 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2987 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2988 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2989 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2990 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2991 #undef PRINTERR 2992 ATW_INIT_RXDESC(sc, i); 2993 continue; 2994 } 2995 2996 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2997 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2998 2999 /* 3000 * No errors; receive the packet. Note the ADM8211 3001 * includes the CRC in promiscuous mode. 3002 */ 3003 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3004 3005 /* 3006 * Allocate a new mbuf cluster. If that fails, we are 3007 * out of memory, and must drop the packet and recycle 3008 * the buffer that's already attached to this descriptor. 3009 */ 3010 m = rxs->rxs_mbuf; 3011 if (atw_add_rxbuf(sc, i) != 0) { 3012 ifp->if_ierrors++; 3013 ATW_INIT_RXDESC(sc, i); 3014 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3015 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3016 continue; 3017 } 3018 3019 ifp->if_ipackets++; 3020 if (sc->sc_opmode & ATW_NAR_PR) 3021 m->m_flags |= M_HASFCS; 3022 m->m_pkthdr.rcvif = ifp; 3023 m->m_pkthdr.len = m->m_len = len; 3024 3025 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3026 rate = 0; 3027 else 3028 rate = rate_tbl[rate0]; 3029 3030 #if NBPFILTER > 0 3031 /* Pass this up to any BPF listeners. */ 3032 if (sc->sc_radiobpf != NULL) { 3033 struct mbuf mb; 3034 3035 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3036 3037 tap->ar_rate = rate; 3038 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3039 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3040 3041 /* TBD verify units are dB */ 3042 tap->ar_antsignal = (int)rssi; 3043 /* TBD tap->ar_flags */ 3044 3045 M_COPY_PKTHDR(&mb, m); 3046 mb.m_data = (caddr_t)tap; 3047 mb.m_len = tap->ar_ihdr.it_len; 3048 mb.m_next = m; 3049 mb.m_pkthdr.len += mb.m_len; 3050 bpf_mtap(sc->sc_radiobpf, &mb); 3051 } 3052 #endif /* NPBFILTER > 0 */ 3053 3054 wh = mtod(m, struct ieee80211_frame *); 3055 ni = ieee80211_find_rxnode(ic, wh); 3056 if (m->m_pkthdr.len >= sizeof(struct ieee80211_frame_min) || 3057 ic->ic_opmode == IEEE80211_M_MONITOR) 3058 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3059 /* 3060 * The frame may have caused the node to be marked for 3061 * reclamation (e.g. in response to a DEAUTH message) 3062 * so use free_node here instead of unref_node. 3063 */ 3064 if (ni == ic->ic_bss) 3065 ieee80211_unref_node(&ni); 3066 else 3067 ieee80211_free_node(ic, ni); 3068 } 3069 3070 /* Update the receive pointer. */ 3071 sc->sc_rxptr = i; 3072 } 3073 3074 /* 3075 * atw_txintr: 3076 * 3077 * Helper; handle transmit interrupts. 3078 */ 3079 void 3080 atw_txintr(struct atw_softc *sc) 3081 { 3082 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3083 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3084 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3085 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3086 3087 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3088 struct ifnet *ifp = &sc->sc_ic.ic_if; 3089 struct atw_txsoft *txs; 3090 u_int32_t txstat; 3091 3092 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3093 sc->sc_dev.dv_xname, sc->sc_flags)); 3094 3095 ifp->if_flags &= ~IFF_OACTIVE; 3096 3097 /* 3098 * Go through our Tx list and free mbufs for those 3099 * frames that have been transmitted. 3100 */ 3101 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3102 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3103 txs->txs_ndescs, 3104 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3105 3106 #ifdef ATW_DEBUG 3107 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3108 int i; 3109 printf(" txsoft %p transmit chain:\n", txs); 3110 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3111 printf(" descriptor %d:\n", i); 3112 printf(" at_status: 0x%08x\n", 3113 le32toh(sc->sc_txdescs[i].at_stat)); 3114 printf(" at_flags: 0x%08x\n", 3115 le32toh(sc->sc_txdescs[i].at_flags)); 3116 printf(" at_buf1: 0x%08x\n", 3117 le32toh(sc->sc_txdescs[i].at_buf1)); 3118 printf(" at_buf2: 0x%08x\n", 3119 le32toh(sc->sc_txdescs[i].at_buf2)); 3120 if (i == txs->txs_lastdesc) 3121 break; 3122 } 3123 } 3124 #endif 3125 3126 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3127 if (txstat & ATW_TXSTAT_OWN) 3128 break; 3129 3130 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3131 3132 sc->sc_txfree += txs->txs_ndescs; 3133 3134 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3135 0, txs->txs_dmamap->dm_mapsize, 3136 BUS_DMASYNC_POSTWRITE); 3137 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3138 m_freem(txs->txs_mbuf); 3139 txs->txs_mbuf = NULL; 3140 3141 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3142 3143 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3144 (txstat & TXSTAT_ERRMASK) != 0) { 3145 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3146 txstat_buf, sizeof(txstat_buf)); 3147 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3148 txstat_buf, 3149 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3150 } 3151 3152 /* 3153 * Check for errors and collisions. 3154 */ 3155 if (txstat & ATW_TXSTAT_TUF) 3156 sc->sc_stats.ts_tx_tuf++; 3157 if (txstat & ATW_TXSTAT_TLT) 3158 sc->sc_stats.ts_tx_tlt++; 3159 if (txstat & ATW_TXSTAT_TRT) 3160 sc->sc_stats.ts_tx_trt++; 3161 if (txstat & ATW_TXSTAT_TRO) 3162 sc->sc_stats.ts_tx_tro++; 3163 if (txstat & ATW_TXSTAT_SOFBR) { 3164 sc->sc_stats.ts_tx_sofbr++; 3165 } 3166 3167 if ((txstat & ATW_TXSTAT_ES) == 0) 3168 ifp->if_collisions += 3169 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3170 else 3171 ifp->if_oerrors++; 3172 3173 ifp->if_opackets++; 3174 } 3175 3176 /* 3177 * If there are no more pending transmissions, cancel the watchdog 3178 * timer. 3179 */ 3180 if (txs == NULL) 3181 sc->sc_tx_timer = 0; 3182 #undef TXSTAT_ERRMASK 3183 #undef TXSTAT_FMT 3184 } 3185 3186 /* 3187 * atw_watchdog: [ifnet interface function] 3188 * 3189 * Watchdog timer handler. 3190 */ 3191 void 3192 atw_watchdog(struct ifnet *ifp) 3193 { 3194 struct atw_softc *sc = ifp->if_softc; 3195 struct ieee80211com *ic = &sc->sc_ic; 3196 3197 ifp->if_timer = 0; 3198 if (ATW_IS_ENABLED(sc) == 0) 3199 return; 3200 3201 if (sc->sc_rescan_timer) { 3202 if (--sc->sc_rescan_timer == 0) 3203 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3204 } 3205 if (sc->sc_tx_timer) { 3206 if (--sc->sc_tx_timer == 0 && 3207 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3208 printf("%s: transmit timeout\n", ifp->if_xname); 3209 ifp->if_oerrors++; 3210 (void)atw_init(ifp); 3211 atw_start(ifp); 3212 } 3213 } 3214 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3215 ifp->if_timer = 1; 3216 ieee80211_watchdog(ifp); 3217 } 3218 3219 /* Compute the 802.11 Duration field and the PLCP Length fields for 3220 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3221 * Write the fields to the ADM8211 Tx header, frm. 3222 * 3223 * TBD use the fragmentation threshold to find the right duration for 3224 * the first & last fragments. 3225 * 3226 * TBD make certain of the duration fields applied by the ADM8211 to each 3227 * fragment. I think that the ADM8211 knows how to subtract the CTS 3228 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3229 * I also think that the ADM8211 does *some* arithmetic for us, because 3230 * otherwise I think we would have to set a first duration for CTS/first 3231 * fragment, a second duration for fragments between the first and the 3232 * last, and a third duration for the last fragment. 3233 * 3234 * TBD make certain that duration fields reflect addition of FCS/WEP 3235 * and correct duration arithmetic as necessary. 3236 */ 3237 static void 3238 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3239 int len) 3240 { 3241 int remainder; 3242 3243 /* deal also with encrypted fragments */ 3244 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3245 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3246 sc->sc_dev.dv_xname)); 3247 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3248 IEEE80211_WEP_CRCLEN; 3249 } 3250 3251 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3252 * duration (XXX added by MAC?). 3253 */ 3254 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3255 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3256 3257 if (rate <= 4) 3258 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3259 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3260 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3261 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3262 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3263 else 3264 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3265 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3266 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3267 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3268 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3269 3270 /* lengthen duration if long preamble */ 3271 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3272 frm->atw_head_dur += 3273 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3274 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3275 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3276 IEEE80211_DUR_DS_FAST_PLCPHDR); 3277 3278 if (remainder != 0) 3279 frm->atw_head_dur++; 3280 3281 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3282 (rate == 2 || rate == 4)) { 3283 /* derived from Linux: how could this be right? */ 3284 frm->atw_head_plcplen = frm->atw_head_dur; 3285 } else { 3286 frm->atw_head_plcplen = (16 * len) / rate; 3287 remainder = (80 * len) % (rate * 5); 3288 3289 if (remainder != 0) { 3290 frm->atw_head_plcplen++; 3291 3292 /* XXX magic */ 3293 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3294 rate == 22 && remainder <= 30) 3295 frm->atw_head_plcplen |= 0x8000; 3296 } 3297 } 3298 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3299 htole16(frm->atw_head_plcplen); 3300 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3301 } 3302 3303 #ifdef ATW_DEBUG 3304 static void 3305 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3306 { 3307 struct atw_softc *sc = ifp->if_softc; 3308 struct mbuf *m; 3309 int i, noctets = 0; 3310 3311 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3312 m0->m_pkthdr.len); 3313 3314 for (m = m0; m; m = m->m_next) { 3315 if (m->m_len == 0) 3316 continue; 3317 for (i = 0; i < m->m_len; i++) { 3318 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3319 if (++noctets % 24 == 0) 3320 printf("\n"); 3321 } 3322 } 3323 printf("%s%s: %d bytes emitted\n", 3324 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3325 } 3326 #endif /* ATW_DEBUG */ 3327 3328 /* 3329 * atw_start: [ifnet interface function] 3330 * 3331 * Start packet transmission on the interface. 3332 */ 3333 void 3334 atw_start(struct ifnet *ifp) 3335 { 3336 struct atw_softc *sc = ifp->if_softc; 3337 struct ieee80211com *ic = &sc->sc_ic; 3338 struct ieee80211_node *ni; 3339 struct ieee80211_frame *wh; 3340 struct atw_frame *hh; 3341 struct mbuf *m0, *m; 3342 struct atw_txsoft *txs, *last_txs; 3343 struct atw_txdesc *txd; 3344 int do_encrypt, rate; 3345 bus_dmamap_t dmamap; 3346 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3347 3348 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3349 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3350 3351 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3352 return; 3353 3354 #if 0 /* TBD ??? */ 3355 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3356 return; 3357 #endif 3358 3359 /* 3360 * Remember the previous number of free descriptors and 3361 * the first descriptor we'll use. 3362 */ 3363 ofree = sc->sc_txfree; 3364 firsttx = sc->sc_txnext; 3365 3366 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3367 sc->sc_dev.dv_xname, ofree, firsttx)); 3368 3369 /* 3370 * Loop through the send queue, setting up transmit descriptors 3371 * until we drain the queue, or use up all available transmit 3372 * descriptors. 3373 */ 3374 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3375 sc->sc_txfree != 0) { 3376 3377 do_encrypt = 0; 3378 /* 3379 * Grab a packet off the management queue, if it 3380 * is not empty. Otherwise, from the data queue. 3381 */ 3382 IF_DEQUEUE(&ic->ic_mgtq, m0); 3383 if (m0 != NULL) { 3384 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3385 m0->m_pkthdr.rcvif = NULL; 3386 } else { 3387 IFQ_DEQUEUE(&ifp->if_snd, m0); 3388 if (m0 == NULL) 3389 break; 3390 #if NBPFILTER > 0 3391 if (ifp->if_bpf != NULL) 3392 bpf_mtap(ifp->if_bpf, m0); 3393 #endif /* NBPFILTER > 0 */ 3394 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3395 ifp->if_oerrors++; 3396 break; 3397 } 3398 } 3399 3400 rate = MAX(ieee80211_get_rate(ic), 2); 3401 3402 #if NBPFILTER > 0 3403 /* 3404 * Pass the packet to any BPF listeners. 3405 */ 3406 if (ic->ic_rawbpf != NULL) 3407 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3408 3409 if (sc->sc_radiobpf != NULL) { 3410 struct mbuf mb; 3411 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3412 3413 tap->at_rate = rate; 3414 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3415 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3416 3417 /* TBD tap->at_flags */ 3418 3419 M_COPY_PKTHDR(&mb, m0); 3420 mb.m_data = (caddr_t)tap; 3421 mb.m_len = tap->at_ihdr.it_len; 3422 mb.m_next = m0; 3423 mb.m_pkthdr.len += mb.m_len; 3424 bpf_mtap(sc->sc_radiobpf, &mb); 3425 } 3426 #endif /* NBPFILTER > 0 */ 3427 3428 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3429 3430 if (ni != NULL && ni != ic->ic_bss) 3431 ieee80211_free_node(ic, ni); 3432 3433 if (m0 == NULL) { 3434 ifp->if_oerrors++; 3435 break; 3436 } 3437 3438 /* just to make sure. */ 3439 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3440 3441 if (m0 == NULL) { 3442 ifp->if_oerrors++; 3443 break; 3444 } 3445 3446 hh = mtod(m0, struct atw_frame *); 3447 wh = &hh->atw_ihdr; 3448 3449 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3450 3451 /* Copy everything we need from the 802.11 header: 3452 * Frame Control; address 1, address 3, or addresses 3453 * 3 and 4. NIC fills in BSSID, SA. 3454 */ 3455 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3456 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3457 panic("%s: illegal WDS frame", 3458 sc->sc_dev.dv_xname); 3459 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3460 } else 3461 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3462 3463 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3464 3465 /* initialize remaining Tx parameters */ 3466 memset(&hh->u, 0, sizeof(hh->u)); 3467 3468 hh->atw_rate = rate * 5; 3469 /* XXX this could be incorrect if M_FCS. _encap should 3470 * probably strip FCS just in case it sticks around in 3471 * bridged packets. 3472 */ 3473 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3474 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3475 sizeof(struct atw_frame)); 3476 3477 #if 0 3478 /* this virtually guaranteed that WEP-encrypted frames 3479 * are fragmented. oops. 3480 */ 3481 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3482 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3483 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3484 #else 3485 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3486 #endif 3487 3488 hh->atw_rtylmt = 3; 3489 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3490 if (do_encrypt) { 3491 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3492 hh->atw_keyid = ic->ic_wep_txkey; 3493 } 3494 3495 /* TBD 4-addr frames */ 3496 atw_frame_setdurs(sc, hh, rate, 3497 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3498 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3499 3500 /* never fragment multicast frames */ 3501 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3502 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3503 } else if (sc->sc_flags & ATWF_RTSCTS) { 3504 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3505 } 3506 3507 #ifdef ATW_DEBUG 3508 /* experimental stuff */ 3509 if (atw_xrtylmt != ~0) 3510 hh->atw_rtylmt = atw_xrtylmt; 3511 if (atw_xhdrctl != 0) 3512 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3513 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3514 hh->atw_service = atw_xservice; 3515 if (atw_xpaylen != 0) 3516 hh->atw_paylen = htole16(atw_xpaylen); 3517 hh->atw_fragnum = 0; 3518 3519 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3520 printf("%s: dst = %s, rate = 0x%02x, " 3521 "service = 0x%02x, paylen = 0x%04x\n", 3522 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3523 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3524 3525 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3526 "dur1 = 0x%04x, dur2 = 0x%04x, " 3527 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3528 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3529 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3530 hh->atw_tail_dur, hh->atw_head_dur); 3531 3532 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3533 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3534 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3535 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3536 3537 printf("%s: keyid = %d\n", 3538 sc->sc_dev.dv_xname, hh->atw_keyid); 3539 3540 atw_dump_pkt(ifp, m0); 3541 } 3542 #endif /* ATW_DEBUG */ 3543 3544 dmamap = txs->txs_dmamap; 3545 3546 /* 3547 * Load the DMA map. Copy and try (once) again if the packet 3548 * didn't fit in the alloted number of segments. 3549 */ 3550 for (first = 1; 3551 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3552 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3553 first = 0) { 3554 MGETHDR(m, M_DONTWAIT, MT_DATA); 3555 if (m == NULL) { 3556 printf("%s: unable to allocate Tx mbuf\n", 3557 sc->sc_dev.dv_xname); 3558 break; 3559 } 3560 if (m0->m_pkthdr.len > MHLEN) { 3561 MCLGET(m, M_DONTWAIT); 3562 if ((m->m_flags & M_EXT) == 0) { 3563 printf("%s: unable to allocate Tx " 3564 "cluster\n", sc->sc_dev.dv_xname); 3565 m_freem(m); 3566 break; 3567 } 3568 } 3569 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3570 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3571 m_freem(m0); 3572 m0 = m; 3573 m = NULL; 3574 } 3575 if (error != 0) { 3576 printf("%s: unable to load Tx buffer, " 3577 "error = %d\n", sc->sc_dev.dv_xname, error); 3578 m_freem(m0); 3579 break; 3580 } 3581 3582 /* 3583 * Ensure we have enough descriptors free to describe 3584 * the packet. 3585 */ 3586 if (dmamap->dm_nsegs > sc->sc_txfree) { 3587 /* 3588 * Not enough free descriptors to transmit 3589 * this packet. Unload the DMA map and 3590 * drop the packet. Notify the upper layer 3591 * that there are no more slots left. 3592 * 3593 * XXX We could allocate an mbuf and copy, but 3594 * XXX it is worth it? 3595 */ 3596 ifp->if_flags |= IFF_OACTIVE; 3597 bus_dmamap_unload(sc->sc_dmat, dmamap); 3598 m_freem(m0); 3599 break; 3600 } 3601 3602 /* 3603 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3604 */ 3605 3606 /* Sync the DMA map. */ 3607 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3608 BUS_DMASYNC_PREWRITE); 3609 3610 /* XXX arbitrary retry limit; 8 because I have seen it in 3611 * use already and maybe 0 means "no tries" ! 3612 */ 3613 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3614 3615 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3616 sc->sc_dev.dv_xname, rate * 5)); 3617 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3618 3619 /* 3620 * Initialize the transmit descriptors. 3621 */ 3622 for (nexttx = sc->sc_txnext, seg = 0; 3623 seg < dmamap->dm_nsegs; 3624 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3625 /* 3626 * If this is the first descriptor we're 3627 * enqueueing, don't set the OWN bit just 3628 * yet. That could cause a race condition. 3629 * We'll do it below. 3630 */ 3631 txd = &sc->sc_txdescs[nexttx]; 3632 txd->at_ctl = ctl | 3633 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3634 3635 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3636 txd->at_flags = 3637 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3638 ATW_TXFLAG_TBS1_MASK)) | 3639 ((nexttx == (ATW_NTXDESC - 1)) 3640 ? htole32(ATW_TXFLAG_TER) : 0); 3641 lasttx = nexttx; 3642 } 3643 3644 IASSERT(lasttx != -1, ("bad lastx")); 3645 /* Set `first segment' and `last segment' appropriately. */ 3646 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3647 htole32(ATW_TXFLAG_FS); 3648 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3649 3650 #ifdef ATW_DEBUG 3651 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3652 printf(" txsoft %p transmit chain:\n", txs); 3653 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3654 printf(" descriptor %d:\n", seg); 3655 printf(" at_ctl: 0x%08x\n", 3656 le32toh(sc->sc_txdescs[seg].at_ctl)); 3657 printf(" at_flags: 0x%08x\n", 3658 le32toh(sc->sc_txdescs[seg].at_flags)); 3659 printf(" at_buf1: 0x%08x\n", 3660 le32toh(sc->sc_txdescs[seg].at_buf1)); 3661 printf(" at_buf2: 0x%08x\n", 3662 le32toh(sc->sc_txdescs[seg].at_buf2)); 3663 if (seg == lasttx) 3664 break; 3665 } 3666 } 3667 #endif 3668 3669 /* Sync the descriptors we're using. */ 3670 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3671 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3672 3673 /* 3674 * Store a pointer to the packet so we can free it later, 3675 * and remember what txdirty will be once the packet is 3676 * done. 3677 */ 3678 txs->txs_mbuf = m0; 3679 txs->txs_firstdesc = sc->sc_txnext; 3680 txs->txs_lastdesc = lasttx; 3681 txs->txs_ndescs = dmamap->dm_nsegs; 3682 3683 /* Advance the tx pointer. */ 3684 sc->sc_txfree -= dmamap->dm_nsegs; 3685 sc->sc_txnext = nexttx; 3686 3687 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3688 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3689 3690 last_txs = txs; 3691 } 3692 3693 if (txs == NULL || sc->sc_txfree == 0) { 3694 /* No more slots left; notify upper layer. */ 3695 ifp->if_flags |= IFF_OACTIVE; 3696 } 3697 3698 if (sc->sc_txfree != ofree) { 3699 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3700 sc->sc_dev.dv_xname, lasttx, firsttx)); 3701 /* 3702 * Cause a transmit interrupt to happen on the 3703 * last packet we enqueued. 3704 */ 3705 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3706 ATW_CDTXSYNC(sc, lasttx, 1, 3707 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3708 3709 /* 3710 * The entire packet chain is set up. Give the 3711 * first descriptor to the chip now. 3712 */ 3713 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3714 ATW_CDTXSYNC(sc, firsttx, 1, 3715 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3716 3717 /* Wake up the transmitter. */ 3718 /* XXX USE AUTOPOLLING? */ 3719 ATW_WRITE(sc, ATW_TDR, 0x1); 3720 3721 /* Set a watchdog timer in case the chip flakes out. */ 3722 sc->sc_tx_timer = 5; 3723 ifp->if_timer = 1; 3724 } 3725 } 3726 3727 /* 3728 * atw_power: 3729 * 3730 * Power management (suspend/resume) hook. 3731 */ 3732 void 3733 atw_power(int why, void *arg) 3734 { 3735 struct atw_softc *sc = arg; 3736 struct ifnet *ifp = &sc->sc_ic.ic_if; 3737 int s; 3738 3739 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3740 3741 s = splnet(); 3742 switch (why) { 3743 case PWR_STANDBY: 3744 /* XXX do nothing. */ 3745 break; 3746 case PWR_SUSPEND: 3747 atw_stop(ifp, 0); 3748 if (sc->sc_power != NULL) 3749 (*sc->sc_power)(sc, why); 3750 break; 3751 case PWR_RESUME: 3752 if (ifp->if_flags & IFF_UP) { 3753 if (sc->sc_power != NULL) 3754 (*sc->sc_power)(sc, why); 3755 atw_init(ifp); 3756 } 3757 break; 3758 case PWR_SOFTSUSPEND: 3759 case PWR_SOFTSTANDBY: 3760 case PWR_SOFTRESUME: 3761 break; 3762 } 3763 splx(s); 3764 } 3765 3766 /* 3767 * atw_ioctl: [ifnet interface function] 3768 * 3769 * Handle control requests from the operator. 3770 */ 3771 int 3772 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3773 { 3774 struct atw_softc *sc = ifp->if_softc; 3775 struct ifreq *ifr = (struct ifreq *)data; 3776 int s, error = 0; 3777 3778 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3779 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3780 return ENXIO; 3781 3782 s = splnet(); 3783 3784 switch (cmd) { 3785 case SIOCSIFFLAGS: 3786 if (ifp->if_flags & IFF_UP) { 3787 if (ATW_IS_ENABLED(sc)) { 3788 /* 3789 * To avoid rescanning another access point, 3790 * do not call atw_init() here. Instead, 3791 * only reflect media settings. 3792 */ 3793 atw_filter_setup(sc); 3794 } else 3795 error = atw_init(ifp); 3796 } else if (ATW_IS_ENABLED(sc)) 3797 atw_stop(ifp, 1); 3798 break; 3799 case SIOCADDMULTI: 3800 case SIOCDELMULTI: 3801 error = (cmd == SIOCADDMULTI) ? 3802 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3803 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3804 if (error == ENETRESET) { 3805 if (ATW_IS_ENABLED(sc)) 3806 atw_filter_setup(sc); /* do not rescan */ 3807 error = 0; 3808 } 3809 break; 3810 default: 3811 error = ieee80211_ioctl(ifp, cmd, data); 3812 if (error == ENETRESET) { 3813 if (ATW_IS_ENABLED(sc)) 3814 error = atw_init(ifp); 3815 else 3816 error = 0; 3817 } 3818 break; 3819 } 3820 3821 /* Try to get more packets going. */ 3822 if (ATW_IS_ENABLED(sc)) 3823 atw_start(ifp); 3824 3825 splx(s); 3826 return (error); 3827 } 3828 3829 static int 3830 atw_media_change(struct ifnet *ifp) 3831 { 3832 int error; 3833 3834 error = ieee80211_media_change(ifp); 3835 if (error == ENETRESET) { 3836 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3837 (IFF_RUNNING|IFF_UP)) 3838 atw_init(ifp); /* XXX lose error */ 3839 error = 0; 3840 } 3841 return error; 3842 } 3843 3844 static void 3845 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3846 { 3847 struct atw_softc *sc = ifp->if_softc; 3848 3849 if (ATW_IS_ENABLED(sc) == 0) { 3850 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3851 imr->ifm_status = 0; 3852 return; 3853 } 3854 ieee80211_media_status(ifp, imr); 3855 } 3856
Indexes created Mon Oct 20 20:10:13 GMT 2025