atw.c revision 1.33
1 /* $NetBSD: atw.c,v 1.33 2004/06/23 08:05:01 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.33 2004/06/23 08:05:01 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * IBSS join/create 131 * 132 * set ATW_NAR_EA (is set by ASIC?) 133 * 134 * BSS join: (re)association response 135 * 136 * set ATW_FRCTL_AID 137 * 138 * optimizations ??? 139 * 140 */ 141 142 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 143 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 144 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 145 146 int atw_rfio_enable_delay = 20 * 1000; 147 int atw_rfio_disable_delay = 2 * 1000; 148 int atw_writewep_delay = 5; 149 int atw_beacon_len_adjust = 4; 150 int atw_dwelltime = 200; 151 152 #ifdef ATW_DEBUG 153 int atw_xhdrctl = 0; 154 int atw_xrtylmt = ~0; 155 int atw_xservice = IEEE80211_PLCP_SERVICE; 156 int atw_xpaylen = 0; 157 158 int atw_debug = 0; 159 160 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 161 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 162 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 163 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 164 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 165 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 166 static void atw_print_regs(struct atw_softc *, const char *); 167 static void atw_rf3000_print(struct atw_softc *); 168 static void atw_si4126_print(struct atw_softc *); 169 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 170 #else 171 #define ATW_DPRINTF(x) 172 #define ATW_DPRINTF2(x) 173 #define ATW_DPRINTF3(x) 174 #define DPRINTF(sc, x) /* nothing */ 175 #define DPRINTF2(sc, x) /* nothing */ 176 #define DPRINTF3(sc, x) /* nothing */ 177 #endif 178 179 #ifdef ATW_STATS 180 void atw_print_stats(struct atw_softc *); 181 #endif 182 183 void atw_start(struct ifnet *); 184 void atw_watchdog(struct ifnet *); 185 int atw_ioctl(struct ifnet *, u_long, caddr_t); 186 int atw_init(struct ifnet *); 187 void atw_stop(struct ifnet *, int); 188 189 void atw_reset(struct atw_softc *); 190 int atw_read_srom(struct atw_softc *); 191 192 void atw_shutdown(void *); 193 194 void atw_rxdrain(struct atw_softc *); 195 int atw_add_rxbuf(struct atw_softc *, int); 196 void atw_idle(struct atw_softc *, u_int32_t); 197 198 int atw_enable(struct atw_softc *); 199 void atw_disable(struct atw_softc *); 200 void atw_power(int, void *); 201 202 void atw_rxintr(struct atw_softc *); 203 void atw_txintr(struct atw_softc *); 204 void atw_linkintr(struct atw_softc *, u_int32_t); 205 206 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 207 static void atw_tsf(struct atw_softc *); 208 static void atw_start_beacon(struct atw_softc *, int); 209 static void atw_write_wep(struct atw_softc *); 210 static void atw_write_bssid(struct atw_softc *); 211 static void atw_write_bcn_thresh(struct atw_softc *); 212 static void atw_write_ssid(struct atw_softc *); 213 static void atw_write_sup_rates(struct atw_softc *); 214 static void atw_clear_sram(struct atw_softc *); 215 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 216 static int atw_media_change(struct ifnet *); 217 static void atw_media_status(struct ifnet *, struct ifmediareq *); 218 static void atw_filter_setup(struct atw_softc *); 219 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 220 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 221 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 226 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 227 228 static int atw_tune(struct atw_softc *); 229 230 static void atw_rfio_enable(struct atw_softc *, int); 231 232 /* RFMD RF3000 Baseband Processor */ 233 static int atw_rf3000_init(struct atw_softc *); 234 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 235 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 236 #ifdef ATW_DEBUG 237 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 238 #endif /* ATW_DEBUG */ 239 240 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 241 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 242 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 243 #ifdef ATW_DEBUG 244 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 245 #endif /* ATW_DEBUG */ 246 247 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 248 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 249 250 const char *atw_tx_state[] = { 251 "STOPPED", 252 "RUNNING - read descriptor", 253 "RUNNING - transmitting", 254 "RUNNING - filling fifo", /* XXX */ 255 "SUSPENDED", 256 "RUNNING -- write descriptor", 257 "RUNNING -- write last descriptor", 258 "RUNNING - fifo full" 259 }; 260 261 const char *atw_rx_state[] = { 262 "STOPPED", 263 "RUNNING - read descriptor", 264 "RUNNING - check this packet, pre-fetch next", 265 "RUNNING - wait for reception", 266 "SUSPENDED", 267 "RUNNING - write descriptor", 268 "RUNNING - flush fifo", 269 "RUNNING - fifo drain" 270 }; 271 272 int 273 atw_activate(struct device *self, enum devact act) 274 { 275 struct atw_softc *sc = (struct atw_softc *)self; 276 int rv = 0, s; 277 278 s = splnet(); 279 switch (act) { 280 case DVACT_ACTIVATE: 281 rv = EOPNOTSUPP; 282 break; 283 284 case DVACT_DEACTIVATE: 285 if_deactivate(&sc->sc_ic.ic_if); 286 break; 287 } 288 splx(s); 289 return rv; 290 } 291 292 /* 293 * atw_enable: 294 * 295 * Enable the ADM8211 chip. 296 */ 297 int 298 atw_enable(struct atw_softc *sc) 299 { 300 301 if (ATW_IS_ENABLED(sc) == 0) { 302 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 303 printf("%s: device enable failed\n", 304 sc->sc_dev.dv_xname); 305 return (EIO); 306 } 307 sc->sc_flags |= ATWF_ENABLED; 308 } 309 return (0); 310 } 311 312 /* 313 * atw_disable: 314 * 315 * Disable the ADM8211 chip. 316 */ 317 void 318 atw_disable(struct atw_softc *sc) 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF(("\n\t")); 400 } 401 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 499 }; 500 struct ieee80211com *ic = &sc->sc_ic; 501 struct ifnet *ifp = &ic->ic_if; 502 int country_code, error, i, nrate; 503 u_int32_t reg; 504 static const char *type_strings[] = {"Intersil (not supported)", 505 "RFMD", "Marvel (not supported)"}; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 } 577 for (i = 0; i < ATW_NRXDESC; i++) { 578 sc->sc_rxsoft[i].rxs_mbuf = NULL; 579 } 580 581 /* Reset the chip to a known state. */ 582 atw_reset(sc); 583 584 if (atw_read_srom(sc) == -1) 585 return; 586 587 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_RFTYPE_MASK); 589 590 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 591 ATW_SR_BBPTYPE_MASK); 592 593 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 594 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 598 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 599 return; 600 } 601 602 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 603 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 604 605 /* XXX There exists a Linux driver which seems to use RFType = 0 for 606 * MARVEL. My bug, or theirs? 607 */ 608 609 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 610 611 switch (sc->sc_rftype) { 612 case ATW_RFTYPE_INTERSIL: 613 reg |= ATW_SYNCTL_CS1; 614 break; 615 case ATW_RFTYPE_RFMD: 616 reg |= ATW_SYNCTL_CS0; 617 break; 618 case ATW_RFTYPE_MARVEL: 619 break; 620 } 621 622 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 623 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 624 625 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 626 627 switch (sc->sc_bbptype) { 628 case ATW_BBPTYPE_INTERSIL: 629 reg |= ATW_BBPCTL_TWI; 630 break; 631 case ATW_BBPTYPE_RFMD: 632 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 633 ATW_BBPCTL_CCA_ACTLO; 634 break; 635 case ATW_BBPTYPE_MARVEL: 636 break; 637 } 638 639 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 640 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 641 642 /* 643 * From this point forward, the attachment cannot fail. A failure 644 * before this point releases all resources that may have been 645 * allocated. 646 */ 647 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 648 649 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 650 htole16(sc->sc_srom[ATW_SR_MAC00]), 651 htole16(sc->sc_srom[ATW_SR_MAC01]), 652 htole16(sc->sc_srom[ATW_SR_MAC10]))); 653 654 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 655 ATW_SR_CTRY_MASK); 656 657 #define ADD_CHANNEL(_ic, _chan) do { \ 658 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 659 _ic->ic_channels[_chan].ic_freq = \ 660 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 661 } while (0) 662 663 /* Find available channels */ 664 switch (country_code) { 665 case COUNTRY_MMK2: /* 1-14 */ 666 ADD_CHANNEL(ic, 14); 667 /*FALLTHROUGH*/ 668 case COUNTRY_ETSI: /* 1-13 */ 669 for (i = 1; i <= 13; i++) 670 ADD_CHANNEL(ic, i); 671 break; 672 case COUNTRY_FCC: /* 1-11 */ 673 case COUNTRY_IC: /* 1-11 */ 674 for (i = 1; i <= 11; i++) 675 ADD_CHANNEL(ic, i); 676 break; 677 case COUNTRY_MMK: /* 14 */ 678 ADD_CHANNEL(ic, 14); 679 break; 680 case COUNTRY_FRANCE: /* 10-13 */ 681 for (i = 10; i <= 13; i++) 682 ADD_CHANNEL(ic, i); 683 break; 684 default: /* assume channels 10-11 */ 685 case COUNTRY_SPAIN: /* 10-11 */ 686 for (i = 10; i <= 11; i++) 687 ADD_CHANNEL(ic, i); 688 break; 689 } 690 691 /* Read the MAC address. */ 692 reg = ATW_READ(sc, ATW_PAR0); 693 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 694 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 695 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 696 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 697 reg = ATW_READ(sc, ATW_PAR1); 698 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 699 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 700 701 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 702 printf(" could not get mac address, attach failed\n"); 703 return; 704 } 705 706 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 707 708 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 709 ifp->if_softc = sc; 710 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 711 IFF_NOTRAILERS; 712 ifp->if_ioctl = atw_ioctl; 713 ifp->if_start = atw_start; 714 ifp->if_watchdog = atw_watchdog; 715 ifp->if_init = atw_init; 716 ifp->if_stop = atw_stop; 717 IFQ_SET_READY(&ifp->if_snd); 718 719 ic->ic_phytype = IEEE80211_T_DS; 720 ic->ic_opmode = IEEE80211_M_STA; 721 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 722 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 723 724 nrate = 0; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 730 731 /* 732 * Call MI attach routines. 733 */ 734 735 if_attach(ifp); 736 ieee80211_ifattach(ifp); 737 738 sc->sc_newstate = ic->ic_newstate; 739 ic->ic_newstate = atw_newstate; 740 741 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 742 ic->ic_recv_mgmt = atw_recv_mgmt; 743 744 sc->sc_node_free = ic->ic_node_free; 745 ic->ic_node_free = atw_node_free; 746 747 sc->sc_node_alloc = ic->ic_node_alloc; 748 ic->ic_node_alloc = atw_node_alloc; 749 750 /* possibly we should fill in our own sc_send_prresp, since 751 * the ADM8211 is probably sending probe responses in ad hoc 752 * mode. 753 */ 754 755 /* complete initialization */ 756 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 757 callout_init(&sc->sc_scan_ch); 758 759 #if NBPFILTER > 0 760 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 761 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 762 #endif 763 764 /* 765 * Make sure the interface is shutdown during reboot. 766 */ 767 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 768 if (sc->sc_sdhook == NULL) 769 printf("%s: WARNING: unable to establish shutdown hook\n", 770 sc->sc_dev.dv_xname); 771 772 /* 773 * Add a suspend hook to make sure we come back up after a 774 * resume. 775 */ 776 sc->sc_powerhook = powerhook_establish(atw_power, sc); 777 if (sc->sc_powerhook == NULL) 778 printf("%s: WARNING: unable to establish power hook\n", 779 sc->sc_dev.dv_xname); 780 781 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 782 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 783 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 784 785 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 786 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 787 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 788 789 return; 790 791 /* 792 * Free any resources we've allocated during the failed attach 793 * attempt. Do this in reverse order and fall through. 794 */ 795 fail_5: 796 for (i = 0; i < ATW_NRXDESC; i++) { 797 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 798 continue; 799 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 800 } 801 fail_4: 802 for (i = 0; i < ATW_TXQUEUELEN; i++) { 803 if (sc->sc_txsoft[i].txs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 806 } 807 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 808 fail_3: 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 810 fail_2: 811 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 812 sizeof(struct atw_control_data)); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 815 fail_0: 816 return; 817 } 818 819 static struct ieee80211_node * 820 atw_node_alloc(struct ieee80211com *ic) 821 { 822 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 823 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 824 825 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 826 return ni; 827 } 828 829 static void 830 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 831 { 832 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 833 834 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 835 ether_sprintf(ni->ni_bssid))); 836 (*sc->sc_node_free)(ic, ni); 837 } 838 839 /* 840 * atw_reset: 841 * 842 * Perform a soft reset on the ADM8211. 843 */ 844 void 845 atw_reset(struct atw_softc *sc) 846 { 847 int i; 848 849 if (ATW_IS_ENABLED(sc) == 0) 850 return; 851 852 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 853 854 for (i = 0; i < 10000; i++) { 855 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 856 break; 857 DELAY(1); 858 } 859 860 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 861 862 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 863 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 864 865 /* Turn off maximum power saving. */ 866 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 867 868 /* Recall EEPROM. */ 869 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 870 871 DELAY(10 * 1000); 872 873 /* A reset seems to affect the SRAM contents, so put them into 874 * a known state. 875 */ 876 atw_clear_sram(sc); 877 878 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 879 880 sc->sc_lost_bcn_thresh = 0; 881 } 882 883 static void 884 atw_clear_sram(struct atw_softc *sc) 885 { 886 #if 0 887 for (addr = 0; addr < 448; addr++) { 888 ATW_WRITE(sc, ATW_WEPCTL, 889 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 890 DELAY(1000); 891 ATW_WRITE(sc, ATW_WESK, 0); 892 DELAY(1000); /* paranoia */ 893 } 894 return; 895 #endif 896 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 897 /* XXX not for revision 0x20. */ 898 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 899 } 900 901 /* TBD atw_init 902 * 903 * set MAC based on ic->ic_bss->myaddr 904 * write WEP keys 905 * set TX rate 906 */ 907 908 /* 909 * atw_init: [ ifnet interface function ] 910 * 911 * Initialize the interface. Must be called at splnet(). 912 */ 913 int 914 atw_init(struct ifnet *ifp) 915 { 916 struct atw_softc *sc = ifp->if_softc; 917 struct ieee80211com *ic = &sc->sc_ic; 918 struct atw_txsoft *txs; 919 struct atw_rxsoft *rxs; 920 u_int32_t reg; 921 int i, error = 0; 922 923 if ((error = atw_enable(sc)) != 0) 924 goto out; 925 926 /* 927 * Cancel any pending I/O. This also resets. 928 */ 929 atw_stop(ifp, 0); 930 931 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 932 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 933 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 934 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 935 936 /* Turn off APM??? (A binary-only driver does this.) 937 * 938 * Set Rx store-and-forward mode. 939 */ 940 reg = ATW_READ(sc, ATW_CMDR); 941 reg &= ~ATW_CMDR_APM; 942 reg &= ~ATW_CMDR_DRT_MASK; 943 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 944 945 ATW_WRITE(sc, ATW_CMDR, reg); 946 947 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 948 * 949 * XXX a binary-only driver sets a different service field than 950 * 0. why? 951 */ 952 reg = ATW_READ(sc, ATW_PLCPHD); 953 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 954 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 955 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 956 ATW_WRITE(sc, ATW_PLCPHD, reg); 957 958 /* XXX this magic can probably be figured out from the RFMD docs */ 959 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 960 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 961 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 962 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 963 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 964 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 965 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 966 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 967 ATW_WRITE(sc, ATW_TOFS2, reg); 968 969 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 970 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 971 972 /* XXX this resets an Intersil RF front-end? */ 973 /* TBD condition on Intersil RFType? */ 974 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 975 DELAY(10 * 1000); 976 ATW_WRITE(sc, ATW_SYNRF, 0); 977 DELAY(5 * 1000); 978 979 /* 16 TU max duration for contention-free period */ 980 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 981 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 982 983 /* XXX I guess that the Cardbus clock is 22MHz? 984 * I am assuming that the role of ATW_TOFS0_USCNT is 985 * to divide the bus clock to get a 1MHz clock---the datasheet is not 986 * very clear on this point. It says in the datasheet that it is 987 * possible for the ADM8211 to accomodate bus speeds between 22MHz 988 * and 33MHz; maybe this is the way? I see a binary-only driver write 989 * these values. These values are also the power-on default. 990 */ 991 ATW_WRITE(sc, ATW_TOFS0, 992 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 993 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 994 995 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 996 * driver. Go figure. 997 */ 998 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 999 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1000 ATW_IFST_SIFS_MASK) | 1001 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1002 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1003 1004 ATW_WRITE(sc, ATW_IFST, reg); 1005 1006 /* XXX More magic. Might relate to ACK timing. */ 1007 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1008 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1009 1010 /* Set up the MMI read/write addresses for the BBP. 1011 * 1012 * TBD find out the Marvel settings. 1013 */ 1014 switch (sc->sc_bbptype) { 1015 case ATW_BBPTYPE_INTERSIL: 1016 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1017 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1018 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1019 break; 1020 case ATW_BBPTYPE_MARVEL: 1021 break; 1022 case ATW_BBPTYPE_RFMD: 1023 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1024 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1025 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1026 default: 1027 break; 1028 } 1029 1030 sc->sc_wepctl = 0; 1031 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1032 1033 if ((error = atw_rf3000_init(sc)) != 0) 1034 goto out; 1035 1036 /* 1037 * Initialize the PCI Access Register. 1038 */ 1039 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1040 1041 /* 1042 * If we're allowed to do so, use Memory Read Line 1043 * and Memory Read Multiple. 1044 * 1045 * XXX Should we use Memory Write and Invalidate? 1046 */ 1047 if (sc->sc_flags & ATWF_MRL) 1048 sc->sc_busmode |= ATW_PAR_MRLE; 1049 if (sc->sc_flags & ATWF_MRM) 1050 sc->sc_busmode |= ATW_PAR_MRME; 1051 if (sc->sc_flags & ATWF_MWI) 1052 sc->sc_busmode |= ATW_PAR_MWIE; 1053 if (sc->sc_maxburst == 0) 1054 sc->sc_maxburst = 8; /* ADM8211 default */ 1055 1056 switch (sc->sc_cacheline) { 1057 default: 1058 /* Use burst length. */ 1059 break; 1060 case 8: 1061 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1062 break; 1063 case 16: 1064 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1065 break; 1066 case 32: 1067 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1068 break; 1069 } 1070 switch (sc->sc_maxburst) { 1071 case 1: 1072 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1073 break; 1074 case 2: 1075 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1076 break; 1077 case 4: 1078 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1079 break; 1080 case 8: 1081 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1082 break; 1083 case 16: 1084 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1085 break; 1086 case 32: 1087 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1088 break; 1089 default: 1090 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1091 break; 1092 } 1093 1094 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1095 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1096 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1097 1098 /* 1099 * Initialize the OPMODE register. We don't write it until 1100 * we're ready to begin the transmit and receive processes. 1101 */ 1102 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1103 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1104 1105 /* 1106 * Initialize the transmit descriptor ring. 1107 */ 1108 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1109 for (i = 0; i < ATW_NTXDESC; i++) { 1110 /* no transmit chaining */ 1111 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1112 sc->sc_txdescs[i].at_buf2 = 1113 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1114 } 1115 /* use ring mode */ 1116 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1117 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 sc->sc_txfree = ATW_NTXDESC; 1120 sc->sc_txnext = 0; 1121 1122 /* 1123 * Initialize the transmit job descriptors. 1124 */ 1125 SIMPLEQ_INIT(&sc->sc_txfreeq); 1126 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1127 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1128 txs = &sc->sc_txsoft[i]; 1129 txs->txs_mbuf = NULL; 1130 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1131 } 1132 1133 /* 1134 * Initialize the receive descriptor and receive job 1135 * descriptor rings. 1136 */ 1137 for (i = 0; i < ATW_NRXDESC; i++) { 1138 rxs = &sc->sc_rxsoft[i]; 1139 if (rxs->rxs_mbuf == NULL) { 1140 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1141 printf("%s: unable to allocate or map rx " 1142 "buffer %d, error = %d\n", 1143 sc->sc_dev.dv_xname, i, error); 1144 /* 1145 * XXX Should attempt to run with fewer receive 1146 * XXX buffers instead of just failing. 1147 */ 1148 atw_rxdrain(sc); 1149 goto out; 1150 } 1151 } else 1152 ATW_INIT_RXDESC(sc, i); 1153 } 1154 sc->sc_rxptr = 0; 1155 1156 /* disable all wake-up events */ 1157 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1158 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1159 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1160 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1161 1162 /* ack all wake-up events */ 1163 ATW_SET(sc, ATW_WCSR, 0); 1164 1165 /* 1166 * Initialize the interrupt mask and enable interrupts. 1167 */ 1168 /* normal interrupts */ 1169 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1170 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1171 1172 /* abnormal interrupts */ 1173 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1174 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1175 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1176 1177 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1178 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1179 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1180 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1181 ATW_INTR_TRT; 1182 1183 sc->sc_linkint_mask &= sc->sc_inten; 1184 sc->sc_rxint_mask &= sc->sc_inten; 1185 sc->sc_txint_mask &= sc->sc_inten; 1186 1187 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1188 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1189 if (sc->sc_intr_ack != NULL) 1190 (*sc->sc_intr_ack)(sc); 1191 1192 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1193 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1194 1195 /* 1196 * Give the transmit and receive rings to the ADM8211. 1197 */ 1198 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1199 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1200 1201 /* common 802.11 configuration */ 1202 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1203 switch (ic->ic_opmode) { 1204 case IEEE80211_M_STA: 1205 sc->sc_opmode &= ~ATW_NAR_EA; 1206 break; 1207 case IEEE80211_M_AHDEMO: /* XXX */ 1208 case IEEE80211_M_IBSS: 1209 ic->ic_flags |= IEEE80211_F_IBSSON; 1210 /*FALLTHROUGH*/ 1211 case IEEE80211_M_HOSTAP: /* XXX */ 1212 /* EA bit seems important for ad hoc reception. */ 1213 sc->sc_opmode |= ATW_NAR_EA; 1214 break; 1215 case IEEE80211_M_MONITOR: /* XXX */ 1216 break; 1217 } 1218 1219 atw_start_beacon(sc, 0); 1220 1221 switch (ic->ic_opmode) { 1222 case IEEE80211_M_AHDEMO: 1223 case IEEE80211_M_HOSTAP: 1224 ic->ic_bss->ni_intval = ic->ic_lintval; 1225 ic->ic_bss->ni_rssi = 0; 1226 ic->ic_bss->ni_rstamp = 0; 1227 break; 1228 default: /* XXX */ 1229 break; 1230 } 1231 1232 atw_write_ssid(sc); 1233 atw_write_sup_rates(sc); 1234 if (ic->ic_caps & IEEE80211_C_WEP) 1235 atw_write_wep(sc); 1236 1237 /* 1238 * Set the receive filter. This will start the transmit and 1239 * receive processes. 1240 */ 1241 atw_filter_setup(sc); 1242 1243 /* 1244 * Start the receive process. 1245 */ 1246 ATW_WRITE(sc, ATW_RDR, 0x1); 1247 1248 /* 1249 * Note that the interface is now running. 1250 */ 1251 ifp->if_flags |= IFF_RUNNING; 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 ic->ic_state = IEEE80211_S_INIT; 1254 1255 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1256 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1257 else 1258 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1259 out: 1260 if (error) { 1261 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1262 ifp->if_timer = 0; 1263 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1264 } 1265 #ifdef ATW_DEBUG 1266 atw_print_regs(sc, "end of init"); 1267 #endif /* ATW_DEBUG */ 1268 1269 return (error); 1270 } 1271 1272 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1273 * 0: MAC control of RF3000/Si4126. 1274 * 1275 * Applies power, or selects RF front-end? Sets reset condition. 1276 * 1277 * TBD support non-RFMD BBP, non-SiLabs synth. 1278 */ 1279 static void 1280 atw_rfio_enable(struct atw_softc *sc, int enable) 1281 { 1282 if (enable) { 1283 ATW_WRITE(sc, ATW_SYNRF, 1284 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1285 DELAY(atw_rfio_enable_delay); 1286 } else { 1287 ATW_WRITE(sc, ATW_SYNRF, 0); 1288 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1289 } 1290 } 1291 1292 static int 1293 atw_tune(struct atw_softc *sc) 1294 { 1295 int rc; 1296 u_int32_t reg; 1297 int chan; 1298 struct ieee80211com *ic = &sc->sc_ic; 1299 1300 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1301 if (chan == IEEE80211_CHAN_ANY) 1302 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1303 1304 if (chan == sc->sc_cur_chan) 1305 return 0; 1306 1307 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1308 sc->sc_cur_chan, chan)); 1309 1310 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1311 1312 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1313 (rc = atw_rf3000_tune(sc, chan)) != 0) 1314 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1315 chan); 1316 1317 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1318 ATW_WRITE(sc, ATW_CAP0, 1319 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1320 1321 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1322 1323 if (rc == 0) 1324 sc->sc_cur_chan = chan; 1325 1326 return rc; 1327 } 1328 1329 #ifdef ATW_DEBUG 1330 static void 1331 atw_si4126_print(struct atw_softc *sc) 1332 { 1333 struct ifnet *ifp = &sc->sc_ic.ic_if; 1334 u_int addr, val; 1335 1336 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1337 return; 1338 1339 for (addr = 0; addr <= 8; addr++) { 1340 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1341 if (atw_si4126_read(sc, addr, &val) == 0) { 1342 printf("<unknown> (quitting print-out)\n"); 1343 break; 1344 } 1345 printf("%05x\n", val); 1346 } 1347 } 1348 #endif /* ATW_DEBUG */ 1349 1350 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1351 * 1352 * The RF/IF synthesizer produces two reference frequencies for 1353 * the RF2948B transceiver. The first frequency the RF2948B requires 1354 * is two times the so-called "intermediate frequency" (IF). Since 1355 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1356 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1357 * frequency required by the transceiver is the radio frequency 1358 * (RF). This is a superheterodyne transceiver; for f(chan) the 1359 * center frequency of the channel we are tuning, RF = f(chan) - 1360 * IF. 1361 * 1362 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1363 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1364 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1365 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1366 */ 1367 static int 1368 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1369 { 1370 int rc = 0; 1371 u_int mhz; 1372 u_int R; 1373 u_int32_t reg; 1374 u_int16_t gain; 1375 1376 #ifdef ATW_DEBUG 1377 atw_si4126_print(sc); 1378 #endif /* ATW_DEBUG */ 1379 1380 if (chan == 14) 1381 mhz = 2484; 1382 else 1383 mhz = 2412 + 5 * (chan - 1); 1384 1385 /* Tune IF to 748MHz to suit the IF LO input of the 1386 * RF2494B, which is 2 x IF. No need to set an IF divider 1387 * because an IF in 526MHz - 952MHz is allowed. 1388 * 1389 * XIN is 44.000MHz, so divide it by two to get allowable 1390 * range of 2-25MHz. SiLabs tells me that this is not 1391 * strictly necessary. 1392 */ 1393 1394 R = 44; 1395 1396 atw_rfio_enable(sc, 1); 1397 1398 /* Power-up RF, IF synthesizers. */ 1399 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1400 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1401 goto out; 1402 1403 /* If RF2 N > 2047, then set KP2 to 1. */ 1404 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1405 1406 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1407 goto out; 1408 1409 /* set LPWR, too? */ 1410 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1411 SI4126_MAIN_XINDIV2)) != 0) 1412 goto out; 1413 1414 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1415 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1416 */ 1417 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1418 goto out; 1419 1420 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1421 goto out; 1422 1423 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1424 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1425 * which has no RF1! 1426 */ 1427 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1428 goto out; 1429 1430 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1431 goto out; 1432 1433 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1434 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1435 * Now let's multiply it to mhz. So mhz - IF = N. 1436 */ 1437 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1438 goto out; 1439 1440 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1441 goto out; 1442 1443 /* wait 100us from power-up for RF, IF to settle */ 1444 DELAY(100); 1445 1446 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1447 /* XXX there is a binary driver which sends 1448 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1449 * that this enables the Si4126 by raising its PWDN#, but I 1450 * think that it actually sets the Prism RF front-end 1451 * to a special mode for channel 14. 1452 */ 1453 reg = ATW_READ(sc, ATW_GPIO); 1454 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1455 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1456 ATW_WRITE(sc, ATW_GPIO, reg); 1457 } 1458 1459 #ifdef ATW_DEBUG 1460 atw_si4126_print(sc); 1461 #endif /* ATW_DEBUG */ 1462 1463 out: 1464 atw_rfio_enable(sc, 0); 1465 1466 return rc; 1467 } 1468 1469 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1470 * diversity. 1471 * 1472 * Call this w/ Tx/Rx suspended. 1473 */ 1474 static int 1475 atw_rf3000_init(struct atw_softc *sc) 1476 { 1477 int rc = 0; 1478 1479 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1480 1481 atw_rfio_enable(sc, 1); 1482 1483 /* enable diversity */ 1484 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1485 1486 if (rc != 0) 1487 goto out; 1488 1489 /* sensible setting from a binary-only driver */ 1490 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1491 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1492 1493 if (rc != 0) 1494 goto out; 1495 1496 /* magic from a binary-only driver */ 1497 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1498 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1499 1500 if (rc != 0) 1501 goto out; 1502 1503 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1504 1505 if (rc != 0) 1506 goto out; 1507 1508 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1509 1510 if (rc != 0) 1511 goto out; 1512 1513 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1514 1515 if (rc != 0) 1516 goto out; 1517 1518 /* CCA is acquisition sensitive */ 1519 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1520 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1521 1522 if (rc != 0) 1523 goto out; 1524 1525 out: 1526 atw_rfio_enable(sc, 0); 1527 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1528 return rc; 1529 } 1530 1531 #ifdef ATW_DEBUG 1532 static void 1533 atw_rf3000_print(struct atw_softc *sc) 1534 { 1535 struct ifnet *ifp = &sc->sc_ic.ic_if; 1536 u_int addr, val; 1537 1538 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1539 return; 1540 1541 for (addr = 0x01; addr <= 0x15; addr++) { 1542 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1543 if (atw_rf3000_read(sc, addr, &val) != 0) { 1544 printf("<unknown> (quitting print-out)\n"); 1545 break; 1546 } 1547 printf("%08x\n", val); 1548 } 1549 } 1550 #endif /* ATW_DEBUG */ 1551 1552 /* Set the power settings on the BBP for channel `chan'. */ 1553 static int 1554 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1555 { 1556 int rc = 0; 1557 u_int32_t reg; 1558 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1559 1560 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1561 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1562 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1563 1564 /* odd channels: LSB, even channels: MSB */ 1565 if (chan % 2 == 1) { 1566 txpower &= 0xFF; 1567 lpf_cutoff &= 0xFF; 1568 lna_gs_thresh &= 0xFF; 1569 } else { 1570 txpower >>= 8; 1571 lpf_cutoff >>= 8; 1572 lna_gs_thresh >>= 8; 1573 } 1574 1575 #ifdef ATW_DEBUG 1576 atw_rf3000_print(sc); 1577 #endif /* ATW_DEBUG */ 1578 1579 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1580 "lna_gs_thresh %02x\n", 1581 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1582 1583 atw_rfio_enable(sc, 1); 1584 1585 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1586 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1587 goto out; 1588 1589 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1590 goto out; 1591 1592 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1593 goto out; 1594 1595 /* from a binary-only driver. */ 1596 reg = ATW_READ(sc, ATW_PLCPHD); 1597 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1598 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1599 ATW_PLCPHD_SERVICE_MASK); 1600 ATW_WRITE(sc, ATW_PLCPHD, reg); 1601 1602 #ifdef ATW_DEBUG 1603 atw_rf3000_print(sc); 1604 #endif /* ATW_DEBUG */ 1605 1606 out: 1607 atw_rfio_enable(sc, 0); 1608 1609 return rc; 1610 } 1611 1612 /* Write a register on the RF3000 baseband processor using the 1613 * registers provided by the ADM8211 for this purpose. 1614 * 1615 * Return 0 on success. 1616 */ 1617 static int 1618 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1619 { 1620 u_int32_t reg; 1621 int i; 1622 1623 for (i = 1000; --i >= 0; ) { 1624 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1625 break; 1626 DELAY(100); 1627 } 1628 1629 if (i < 0) { 1630 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1631 return ETIMEDOUT; 1632 } 1633 1634 reg = sc->sc_bbpctl_wr | 1635 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1636 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1637 1638 ATW_WRITE(sc, ATW_BBPCTL, reg); 1639 1640 for (i = 1000; --i >= 0; ) { 1641 DELAY(100); 1642 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1643 break; 1644 } 1645 1646 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1647 1648 if (i < 0) { 1649 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1650 return ETIMEDOUT; 1651 } 1652 return 0; 1653 } 1654 1655 /* Read a register on the RF3000 baseband processor using the registers 1656 * the ADM8211 provides for this purpose. 1657 * 1658 * The 7-bit register address is addr. Record the 8-bit data in the register 1659 * in *val. 1660 * 1661 * Return 0 on success. 1662 * 1663 * XXX This does not seem to work. The ADM8211 must require more or 1664 * different magic to read the chip than to write it. Possibly some 1665 * of the magic I have derived from a binary-only driver concerns 1666 * the "chip address" (see the RF3000 manual). 1667 */ 1668 #ifdef ATW_DEBUG 1669 static int 1670 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1671 { 1672 u_int32_t reg; 1673 int i; 1674 1675 for (i = 1000; --i >= 0; ) { 1676 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1677 break; 1678 DELAY(100); 1679 } 1680 1681 if (i < 0) { 1682 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1683 sc->sc_dev.dv_xname); 1684 return ETIMEDOUT; 1685 } 1686 1687 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1688 1689 ATW_WRITE(sc, ATW_BBPCTL, reg); 1690 1691 for (i = 1000; --i >= 0; ) { 1692 DELAY(100); 1693 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1694 break; 1695 } 1696 1697 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1698 1699 if (i < 0) { 1700 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1701 sc->sc_dev.dv_xname, reg); 1702 return ETIMEDOUT; 1703 } 1704 if (val != NULL) 1705 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1706 return 0; 1707 } 1708 #endif /* ATW_DEBUG */ 1709 1710 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1711 * provided by the ADM8211 for that purpose. 1712 * 1713 * val is 18 bits of data, and val is the 4-bit address of the register. 1714 * 1715 * Return 0 on success. 1716 */ 1717 static int 1718 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1719 { 1720 u_int32_t bits, reg; 1721 int i; 1722 1723 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1724 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1725 1726 for (i = 1000; --i >= 0; ) { 1727 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1728 break; 1729 DELAY(100); 1730 } 1731 1732 if (i < 0) { 1733 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1734 sc->sc_dev.dv_xname); 1735 return ETIMEDOUT; 1736 } 1737 1738 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1739 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1740 1741 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1742 1743 ATW_WRITE(sc, ATW_SYNCTL, reg); 1744 1745 for (i = 1000; --i >= 0; ) { 1746 DELAY(100); 1747 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1748 break; 1749 } 1750 1751 /* restore to acceptable starting condition */ 1752 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1753 1754 if (i < 0) { 1755 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1756 sc->sc_dev.dv_xname, reg); 1757 return ETIMEDOUT; 1758 } 1759 return 0; 1760 } 1761 1762 /* Read 18-bit data from the 4-bit address addr in Si4126 1763 * RF synthesizer and write the data to *val. Return 0 on success. 1764 * 1765 * XXX This does not seem to work. The ADM8211 must require more or 1766 * different magic to read the chip than to write it. 1767 */ 1768 #ifdef ATW_DEBUG 1769 static int 1770 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1771 { 1772 u_int32_t reg; 1773 int i; 1774 1775 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1776 1777 for (i = 1000; --i >= 0; ) { 1778 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1779 break; 1780 DELAY(100); 1781 } 1782 1783 if (i < 0) { 1784 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1785 sc->sc_dev.dv_xname); 1786 return ETIMEDOUT; 1787 } 1788 1789 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1790 1791 ATW_WRITE(sc, ATW_SYNCTL, reg); 1792 1793 for (i = 1000; --i >= 0; ) { 1794 DELAY(100); 1795 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1796 break; 1797 } 1798 1799 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1800 1801 if (i < 0) { 1802 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1803 sc->sc_dev.dv_xname, reg); 1804 return ETIMEDOUT; 1805 } 1806 if (val != NULL) 1807 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1808 ATW_SYNCTL_DATA_MASK); 1809 return 0; 1810 } 1811 #endif /* ATW_DEBUG */ 1812 1813 /* XXX is the endianness correct? test. */ 1814 #define atw_calchash(addr) \ 1815 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1816 1817 /* 1818 * atw_filter_setup: 1819 * 1820 * Set the ADM8211's receive filter. 1821 */ 1822 static void 1823 atw_filter_setup(struct atw_softc *sc) 1824 { 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 struct ethercom *ec = &ic->ic_ec; 1827 struct ifnet *ifp = &sc->sc_ic.ic_if; 1828 int hash; 1829 u_int32_t hashes[2] = { 0, 0 }; 1830 struct ether_multi *enm; 1831 struct ether_multistep step; 1832 1833 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1834 sc->sc_dev.dv_xname, sc->sc_flags)); 1835 1836 /* 1837 * If we're running, idle the receive engine. If we're NOT running, 1838 * we're being called from atw_init(), and our writing ATW_NAR will 1839 * start the transmit and receive processes in motion. 1840 */ 1841 if (ifp->if_flags & IFF_RUNNING) 1842 atw_idle(sc, ATW_NAR_SR); 1843 1844 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1845 1846 ifp->if_flags &= ~IFF_ALLMULTI; 1847 1848 if (ifp->if_flags & IFF_PROMISC) { 1849 sc->sc_opmode |= ATW_NAR_PR; 1850 allmulti: 1851 ifp->if_flags |= IFF_ALLMULTI; 1852 goto setit; 1853 } 1854 1855 /* 1856 * Program the 64-bit multicast hash filter. 1857 */ 1858 ETHER_FIRST_MULTI(step, ec, enm); 1859 while (enm != NULL) { 1860 /* XXX */ 1861 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1862 ETHER_ADDR_LEN) != 0) 1863 goto allmulti; 1864 1865 hash = atw_calchash(enm->enm_addrlo); 1866 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1867 ETHER_NEXT_MULTI(step, enm); 1868 } 1869 1870 if (ifp->if_flags & IFF_BROADCAST) { 1871 hash = atw_calchash(etherbroadcastaddr); 1872 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1873 } 1874 1875 /* all bits set => hash is useless */ 1876 if (~(hashes[0] & hashes[1]) == 0) 1877 goto allmulti; 1878 1879 setit: 1880 if (ifp->if_flags & IFF_ALLMULTI) 1881 sc->sc_opmode |= ATW_NAR_MM; 1882 1883 /* XXX in scan mode, do not filter packets. maybe this is 1884 * unnecessary. 1885 */ 1886 if (ic->ic_state == IEEE80211_S_SCAN) 1887 sc->sc_opmode |= ATW_NAR_PR; 1888 1889 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1890 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1891 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1892 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1893 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1894 1895 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1896 } 1897 1898 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1899 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1900 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1901 * no beacon with the preferred BSSID and SSID in the number of 1902 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1903 */ 1904 static void 1905 atw_write_bssid(struct atw_softc *sc) 1906 { 1907 struct ieee80211com *ic = &sc->sc_ic; 1908 u_int8_t *bssid; 1909 1910 bssid = ic->ic_bss->ni_bssid; 1911 1912 ATW_WRITE(sc, ATW_ABDA1, 1913 (ATW_READ(sc, ATW_ABDA1) & 1914 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1915 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1916 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1917 1918 ATW_WRITE(sc, ATW_BSSID0, 1919 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1920 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1921 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1922 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1923 1924 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1925 ether_sprintf(sc->sc_bssid))); 1926 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1927 1928 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1929 } 1930 1931 /* Tell the ADM8211 how many beacon intervals must pass without 1932 * receiving a beacon with the preferred BSSID & SSID set by 1933 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1934 * raised. 1935 */ 1936 static void 1937 atw_write_bcn_thresh(struct atw_softc *sc) 1938 { 1939 struct ieee80211com *ic = &sc->sc_ic; 1940 int lost_bcn_thresh; 1941 1942 /* Lose link after one second or 7 beacons, whichever comes 1943 * first, but do not lose link before 2 beacons are lost. 1944 * 1945 * In host AP mode, set the lost-beacon threshold to 0. 1946 */ 1947 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1948 lost_bcn_thresh = 0; 1949 else { 1950 int beacons_per_second = 1951 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1952 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1953 } 1954 1955 /* XXX resets wake-up status bits */ 1956 ATW_WRITE(sc, ATW_WCSR, 1957 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1958 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1959 1960 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1961 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1962 1963 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1964 1965 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1966 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1967 } 1968 1969 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1970 * 16-bit word. 1971 */ 1972 static void 1973 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1974 { 1975 u_int i; 1976 u_int8_t *ptr; 1977 1978 memcpy(&sc->sc_sram[ofs], buf, buflen); 1979 1980 if (ofs % 2 != 0) { 1981 ofs--; 1982 buflen++; 1983 } 1984 1985 if (buflen % 2 != 0) 1986 buflen++; 1987 1988 assert(buflen + ofs <= ATW_SRAM_SIZE); 1989 1990 ptr = &sc->sc_sram[ofs]; 1991 1992 for (i = 0; i < buflen; i += 2) { 1993 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1994 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1995 DELAY(atw_writewep_delay); 1996 1997 ATW_WRITE(sc, ATW_WESK, 1998 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1999 DELAY(atw_writewep_delay); 2000 } 2001 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2002 2003 if (sc->sc_if.if_flags & IFF_DEBUG) { 2004 int n_octets = 0; 2005 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2006 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2007 for (i = 0; i < buflen; i++) { 2008 printf(" %02x", ptr[i]); 2009 if (++n_octets % 24 == 0) 2010 printf("\n"); 2011 } 2012 if (n_octets % 24 != 0) 2013 printf("\n"); 2014 } 2015 } 2016 2017 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2018 static void 2019 atw_write_wep(struct atw_softc *sc) 2020 { 2021 struct ieee80211com *ic = &sc->sc_ic; 2022 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2023 u_int8_t buf[IEEE80211_WEP_NKID] 2024 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2025 u_int32_t reg; 2026 int i; 2027 2028 sc->sc_wepctl = 0; 2029 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2030 2031 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2032 return; 2033 2034 memset(&buf[0][0], 0, sizeof(buf)); 2035 2036 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2037 if (ic->ic_nw_keys[i].wk_len > 5) { 2038 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2039 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2040 buf[i][1] = ATW_WEP_ENABLED; 2041 } else { 2042 buf[i][1] = 0; 2043 continue; 2044 } 2045 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2046 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2047 ic->ic_nw_keys[i].wk_len - 1); 2048 } 2049 2050 reg = ATW_READ(sc, ATW_MACTEST); 2051 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2052 reg &= ~ATW_MACTEST_KEYID_MASK; 2053 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2054 ATW_WRITE(sc, ATW_MACTEST, reg); 2055 2056 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2057 * throughout.) 2058 */ 2059 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2060 if (sc->sc_if.if_flags & IFF_LINK2) 2061 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2062 2063 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2064 sizeof(buf)); 2065 } 2066 2067 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2068 2069 static void 2070 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2071 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2072 { 2073 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2074 2075 switch (subtype) { 2076 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2077 /* do nothing: hardware answers probe request */ 2078 break; 2079 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2080 case IEEE80211_FC0_SUBTYPE_BEACON: 2081 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2082 break; 2083 default: 2084 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2085 break; 2086 } 2087 return; 2088 } 2089 2090 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2091 * of IBSSs with like SSID/channel but different BSSID. It joins the 2092 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2093 * convention. Possibly the ADMtek chip does this for us; I will have 2094 * to test to find out. 2095 * 2096 * XXX we should add the duration field of the received beacon to 2097 * the TSF time it contains before comparing it with the ADM8211's 2098 * TSF. 2099 */ 2100 static void 2101 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2102 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2103 { 2104 struct atw_softc *sc; 2105 struct ieee80211_frame *wh; 2106 u_int64_t tsft, bcn_tsft; 2107 u_int32_t tsftl, tsfth; 2108 int do_print = 0; 2109 2110 sc = (struct atw_softc*)ic->ic_if.if_softc; 2111 2112 if (ic->ic_if.if_flags & IFF_DEBUG) 2113 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2114 ? 1 : ratecheck(&sc->sc_last_beacon, 2115 &atw_beacon_mininterval); 2116 2117 wh = mtod(m0, struct ieee80211_frame *); 2118 2119 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2120 2121 if (ic->ic_state != IEEE80211_S_RUN) { 2122 if (do_print) 2123 printf("%s: atw_recv_beacon: not running\n", 2124 sc->sc_dev.dv_xname); 2125 return; 2126 } 2127 2128 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2129 ic->ic_bss->ni_chan)) == NULL) { 2130 if (do_print) 2131 printf("%s: atw_recv_beacon: no node %s\n", 2132 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2133 return; 2134 } 2135 2136 if (ieee80211_match_bss(ic, ni) != 0) { 2137 if (do_print) 2138 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2139 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2140 return; 2141 } 2142 2143 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2144 return; 2145 2146 if (do_print) 2147 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2148 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2149 2150 if (ic->ic_opmode != IEEE80211_M_IBSS) 2151 return; 2152 2153 /* If we read TSFTL right before rollover, we read a TSF timer 2154 * that is too high rather than too low. This prevents a spurious 2155 * synchronization down the line, however, our IBSS could suffer 2156 * from a creeping TSF.... 2157 */ 2158 tsftl = ATW_READ(sc, ATW_TSFTL); 2159 tsfth = ATW_READ(sc, ATW_TSFTH); 2160 2161 tsft = (u_int64_t)tsfth << 32 | tsftl; 2162 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2163 2164 if (do_print) 2165 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2166 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2167 2168 /* we are faster, let the other guy catch up */ 2169 if (bcn_tsft < tsft) 2170 return; 2171 2172 if (do_print) 2173 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2174 ether_sprintf(wh->i_addr2)); 2175 2176 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2177 2178 #if 0 2179 atw_tsf(sc); 2180 #endif 2181 2182 /* negotiate rates with new IBSS */ 2183 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2184 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2185 if (ni->ni_rates.rs_nrates == 0) { 2186 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2187 ether_sprintf(ni->ni_bssid)); 2188 return; 2189 } 2190 2191 if (do_print) { 2192 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2193 ether_sprintf(ic->ic_bss->ni_bssid)); 2194 printf("%s ", ether_sprintf(ni->ni_bssid)); 2195 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2196 } 2197 2198 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2199 2200 atw_write_bssid(sc); 2201 atw_write_bcn_thresh(sc); 2202 atw_start_beacon(sc, 1); 2203 } 2204 2205 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2206 * In ad hoc mode, the SSID is written to the beacons sent by the 2207 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2208 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2209 * indications. 2210 */ 2211 static void 2212 atw_write_ssid(struct atw_softc *sc) 2213 { 2214 struct ieee80211com *ic = &sc->sc_ic; 2215 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2216 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2217 2218 memset(buf, 0, sizeof(buf)); 2219 buf[0] = ic->ic_bss->ni_esslen; 2220 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2221 2222 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2223 } 2224 2225 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2226 * In ad hoc mode, the supported rates are written to beacons sent by the 2227 * ADM8211. 2228 */ 2229 static void 2230 atw_write_sup_rates(struct atw_softc *sc) 2231 { 2232 struct ieee80211com *ic = &sc->sc_ic; 2233 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2234 * supported rates 2235 */ 2236 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2237 2238 memset(buf, 0, sizeof(buf)); 2239 2240 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2241 2242 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2243 ic->ic_bss->ni_rates.rs_nrates); 2244 2245 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2246 } 2247 2248 /* Start/stop sending beacons. */ 2249 void 2250 atw_start_beacon(struct atw_softc *sc, int start) 2251 { 2252 struct ieee80211com *ic = &sc->sc_ic; 2253 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2254 2255 if (ATW_IS_ENABLED(sc) == 0) 2256 return; 2257 2258 len = capinfo = 0; 2259 2260 /* start beacons */ 2261 len = sizeof(struct ieee80211_frame) + 2262 8 /* timestamp */ + 2 /* beacon interval */ + 2263 2 /* capability info */ + 2264 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2265 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2266 3 /* DS parameters */ + 2267 IEEE80211_CRC_LEN; 2268 2269 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2270 2271 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2272 2273 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2274 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2275 2276 if (!start) 2277 return; 2278 2279 /* TBD use ni_capinfo */ 2280 2281 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2282 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2283 if (ic->ic_flags & IEEE80211_F_WEPON) 2284 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2285 2286 switch (ic->ic_opmode) { 2287 case IEEE80211_M_IBSS: 2288 len += 4; /* IBSS parameters */ 2289 capinfo |= IEEE80211_CAPINFO_IBSS; 2290 break; 2291 case IEEE80211_M_HOSTAP: 2292 /* XXX 6-byte minimum TIM */ 2293 len += atw_beacon_len_adjust; 2294 capinfo |= IEEE80211_CAPINFO_ESS; 2295 break; 2296 default: 2297 return; 2298 } 2299 2300 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2301 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2302 2303 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2304 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2305 2306 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2307 sc->sc_dev.dv_xname, reg_bcnt)); 2308 2309 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2310 sc->sc_dev.dv_xname, reg_cap1)); 2311 } 2312 2313 /* First beacon was sent at time 0 microseconds, current time is 2314 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2315 * microseconds. Return the expected time in microseconds for the 2316 * beacon after next. 2317 */ 2318 static __inline u_int64_t 2319 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2320 { 2321 return tsft + (tbtt - tsft % tbtt); 2322 } 2323 2324 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2325 * the ieee80211com. 2326 * 2327 * Predict the next target beacon transmission time (TBTT) and 2328 * write it to the ADM8211. 2329 */ 2330 static void 2331 atw_tsf(struct atw_softc *sc) 2332 { 2333 #define TBTTOFS 20 /* TU */ 2334 2335 struct ieee80211com *ic = &sc->sc_ic; 2336 u_int64_t tsft, tbtt; 2337 2338 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2339 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2340 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2341 tsft = ATW_READ(sc, ATW_TSFTH); 2342 tsft <<= 32; 2343 tsft |= ATW_READ(sc, ATW_TSFTL); 2344 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2345 } else 2346 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2347 2348 tbtt = atw_predict_beacon(tsft, 2349 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2350 2351 /* skip one more beacon so that the TBTT cannot pass before 2352 * we've programmed it, and also so that we can subtract a 2353 * few TU so that we wake a little before TBTT. 2354 */ 2355 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2356 2357 /* wake up a little early */ 2358 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2359 2360 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2361 sc->sc_dev.dv_xname, tsft, tbtt)); 2362 2363 ATW_WRITE(sc, ATW_TOFS1, 2364 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2365 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2366 LSHIFT( 2367 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2368 ATW_TOFS1_TBTTPRE_MASK)); 2369 #undef TBTTOFS 2370 } 2371 2372 static void 2373 atw_next_scan(void *arg) 2374 { 2375 struct atw_softc *sc = arg; 2376 struct ieee80211com *ic = &sc->sc_ic; 2377 struct ifnet *ifp = &ic->ic_if; 2378 int s; 2379 2380 /* don't call atw_start w/o network interrupts blocked */ 2381 s = splnet(); 2382 if (ic->ic_state == IEEE80211_S_SCAN) 2383 ieee80211_next_scan(ifp); 2384 splx(s); 2385 } 2386 2387 /* Synchronize the hardware state with the software state. */ 2388 static int 2389 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2390 { 2391 struct ifnet *ifp = &ic->ic_if; 2392 struct atw_softc *sc = ifp->if_softc; 2393 enum ieee80211_state ostate; 2394 int error; 2395 2396 ostate = ic->ic_state; 2397 2398 if (nstate == IEEE80211_S_INIT) { 2399 callout_stop(&sc->sc_scan_ch); 2400 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2401 atw_start_beacon(sc, 0); 2402 return (*sc->sc_newstate)(ic, nstate, arg); 2403 } 2404 2405 if ((error = atw_tune(sc)) != 0) 2406 return error; 2407 2408 switch (nstate) { 2409 case IEEE80211_S_ASSOC: 2410 break; 2411 case IEEE80211_S_INIT: 2412 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2413 break; 2414 case IEEE80211_S_SCAN: 2415 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2416 atw_write_bssid(sc); 2417 2418 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2419 atw_next_scan, sc); 2420 2421 break; 2422 case IEEE80211_S_RUN: 2423 if (ic->ic_opmode == IEEE80211_M_STA) 2424 break; 2425 /*FALLTHROUGH*/ 2426 case IEEE80211_S_AUTH: 2427 atw_write_bssid(sc); 2428 atw_write_bcn_thresh(sc); 2429 atw_write_ssid(sc); 2430 atw_write_sup_rates(sc); 2431 2432 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2433 ic->ic_opmode == IEEE80211_M_MONITOR) 2434 break; 2435 2436 /* set listen interval 2437 * XXX do software units agree w/ hardware? 2438 */ 2439 ATW_WRITE(sc, ATW_BPLI, 2440 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2441 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2442 ATW_BPLI_LI_MASK)); 2443 2444 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2445 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2446 2447 atw_tsf(sc); 2448 break; 2449 } 2450 2451 if (nstate != IEEE80211_S_SCAN) 2452 callout_stop(&sc->sc_scan_ch); 2453 2454 if (nstate == IEEE80211_S_RUN && 2455 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2456 ic->ic_opmode == IEEE80211_M_IBSS)) 2457 atw_start_beacon(sc, 1); 2458 else 2459 atw_start_beacon(sc, 0); 2460 2461 return (*sc->sc_newstate)(ic, nstate, arg); 2462 } 2463 2464 /* 2465 * atw_add_rxbuf: 2466 * 2467 * Add a receive buffer to the indicated descriptor. 2468 */ 2469 int 2470 atw_add_rxbuf(struct atw_softc *sc, int idx) 2471 { 2472 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2473 struct mbuf *m; 2474 int error; 2475 2476 MGETHDR(m, M_DONTWAIT, MT_DATA); 2477 if (m == NULL) 2478 return (ENOBUFS); 2479 2480 MCLGET(m, M_DONTWAIT); 2481 if ((m->m_flags & M_EXT) == 0) { 2482 m_freem(m); 2483 return (ENOBUFS); 2484 } 2485 2486 if (rxs->rxs_mbuf != NULL) 2487 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2488 2489 rxs->rxs_mbuf = m; 2490 2491 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2492 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2493 BUS_DMA_READ|BUS_DMA_NOWAIT); 2494 if (error) { 2495 printf("%s: can't load rx DMA map %d, error = %d\n", 2496 sc->sc_dev.dv_xname, idx, error); 2497 panic("atw_add_rxbuf"); /* XXX */ 2498 } 2499 2500 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2501 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2502 2503 ATW_INIT_RXDESC(sc, idx); 2504 2505 return (0); 2506 } 2507 2508 /* 2509 * atw_stop: [ ifnet interface function ] 2510 * 2511 * Stop transmission on the interface. 2512 */ 2513 void 2514 atw_stop(struct ifnet *ifp, int disable) 2515 { 2516 struct atw_softc *sc = ifp->if_softc; 2517 struct ieee80211com *ic = &sc->sc_ic; 2518 struct atw_txsoft *txs; 2519 2520 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2521 2522 /* Disable interrupts. */ 2523 ATW_WRITE(sc, ATW_IER, 0); 2524 2525 /* Stop the transmit and receive processes. */ 2526 sc->sc_opmode = 0; 2527 ATW_WRITE(sc, ATW_NAR, 0); 2528 ATW_WRITE(sc, ATW_TDBD, 0); 2529 ATW_WRITE(sc, ATW_TDBP, 0); 2530 ATW_WRITE(sc, ATW_RDB, 0); 2531 2532 /* 2533 * Release any queued transmit buffers. 2534 */ 2535 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2536 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2537 if (txs->txs_mbuf != NULL) { 2538 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2539 m_freem(txs->txs_mbuf); 2540 txs->txs_mbuf = NULL; 2541 } 2542 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2543 } 2544 2545 if (disable) { 2546 atw_rxdrain(sc); 2547 atw_disable(sc); 2548 } 2549 2550 /* 2551 * Mark the interface down and cancel the watchdog timer. 2552 */ 2553 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2554 ifp->if_timer = 0; 2555 2556 /* XXX */ 2557 atw_reset(sc); 2558 } 2559 2560 /* 2561 * atw_rxdrain: 2562 * 2563 * Drain the receive queue. 2564 */ 2565 void 2566 atw_rxdrain(struct atw_softc *sc) 2567 { 2568 struct atw_rxsoft *rxs; 2569 int i; 2570 2571 for (i = 0; i < ATW_NRXDESC; i++) { 2572 rxs = &sc->sc_rxsoft[i]; 2573 if (rxs->rxs_mbuf == NULL) 2574 continue; 2575 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2576 m_freem(rxs->rxs_mbuf); 2577 rxs->rxs_mbuf = NULL; 2578 } 2579 } 2580 2581 /* 2582 * atw_detach: 2583 * 2584 * Detach an ADM8211 interface. 2585 */ 2586 int 2587 atw_detach(struct atw_softc *sc) 2588 { 2589 struct ifnet *ifp = &sc->sc_ic.ic_if; 2590 struct atw_rxsoft *rxs; 2591 struct atw_txsoft *txs; 2592 int i; 2593 2594 /* 2595 * Succeed now if there isn't any work to do. 2596 */ 2597 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2598 return (0); 2599 2600 ieee80211_ifdetach(ifp); 2601 if_detach(ifp); 2602 2603 for (i = 0; i < ATW_NRXDESC; i++) { 2604 rxs = &sc->sc_rxsoft[i]; 2605 if (rxs->rxs_mbuf != NULL) { 2606 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2607 m_freem(rxs->rxs_mbuf); 2608 rxs->rxs_mbuf = NULL; 2609 } 2610 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2611 } 2612 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2613 txs = &sc->sc_txsoft[i]; 2614 if (txs->txs_mbuf != NULL) { 2615 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2616 m_freem(txs->txs_mbuf); 2617 txs->txs_mbuf = NULL; 2618 } 2619 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2620 } 2621 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2622 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2623 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2624 sizeof(struct atw_control_data)); 2625 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2626 2627 shutdownhook_disestablish(sc->sc_sdhook); 2628 powerhook_disestablish(sc->sc_powerhook); 2629 2630 if (sc->sc_srom) 2631 free(sc->sc_srom, M_DEVBUF); 2632 2633 return (0); 2634 } 2635 2636 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2637 void 2638 atw_shutdown(void *arg) 2639 { 2640 struct atw_softc *sc = arg; 2641 2642 atw_stop(&sc->sc_ic.ic_if, 1); 2643 } 2644 2645 int 2646 atw_intr(void *arg) 2647 { 2648 struct atw_softc *sc = arg; 2649 struct ifnet *ifp = &sc->sc_ic.ic_if; 2650 u_int32_t status, rxstatus, txstatus, linkstatus; 2651 int handled = 0, txthresh; 2652 2653 #ifdef DEBUG 2654 if (ATW_IS_ENABLED(sc) == 0) 2655 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2656 #endif 2657 2658 /* 2659 * If the interface isn't running, the interrupt couldn't 2660 * possibly have come from us. 2661 */ 2662 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2663 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2664 return (0); 2665 2666 for (;;) { 2667 status = ATW_READ(sc, ATW_STSR); 2668 2669 if (status) 2670 ATW_WRITE(sc, ATW_STSR, status); 2671 2672 if (sc->sc_intr_ack != NULL) 2673 (*sc->sc_intr_ack)(sc); 2674 2675 #ifdef ATW_DEBUG 2676 #define PRINTINTR(flag) do { \ 2677 if ((status & flag) != 0) { \ 2678 printf("%s" #flag, delim); \ 2679 delim = ","; \ 2680 } \ 2681 } while (0) 2682 2683 if (atw_debug > 1 && status) { 2684 const char *delim = "<"; 2685 2686 printf("%s: reg[STSR] = %x", 2687 sc->sc_dev.dv_xname, status); 2688 2689 PRINTINTR(ATW_INTR_FBE); 2690 PRINTINTR(ATW_INTR_LINKOFF); 2691 PRINTINTR(ATW_INTR_LINKON); 2692 PRINTINTR(ATW_INTR_RCI); 2693 PRINTINTR(ATW_INTR_RDU); 2694 PRINTINTR(ATW_INTR_REIS); 2695 PRINTINTR(ATW_INTR_RPS); 2696 PRINTINTR(ATW_INTR_TCI); 2697 PRINTINTR(ATW_INTR_TDU); 2698 PRINTINTR(ATW_INTR_TLT); 2699 PRINTINTR(ATW_INTR_TPS); 2700 PRINTINTR(ATW_INTR_TRT); 2701 PRINTINTR(ATW_INTR_TUF); 2702 PRINTINTR(ATW_INTR_BCNTC); 2703 PRINTINTR(ATW_INTR_ATIME); 2704 PRINTINTR(ATW_INTR_TBTT); 2705 PRINTINTR(ATW_INTR_TSCZ); 2706 PRINTINTR(ATW_INTR_TSFTF); 2707 printf(">\n"); 2708 } 2709 #undef PRINTINTR 2710 #endif /* ATW_DEBUG */ 2711 2712 if ((status & sc->sc_inten) == 0) 2713 break; 2714 2715 handled = 1; 2716 2717 rxstatus = status & sc->sc_rxint_mask; 2718 txstatus = status & sc->sc_txint_mask; 2719 linkstatus = status & sc->sc_linkint_mask; 2720 2721 if (linkstatus) { 2722 atw_linkintr(sc, linkstatus); 2723 } 2724 2725 if (rxstatus) { 2726 /* Grab any new packets. */ 2727 atw_rxintr(sc); 2728 2729 if (rxstatus & ATW_INTR_RDU) { 2730 printf("%s: receive ring overrun\n", 2731 sc->sc_dev.dv_xname); 2732 /* Get the receive process going again. */ 2733 ATW_WRITE(sc, ATW_RDR, 0x1); 2734 break; 2735 } 2736 } 2737 2738 if (txstatus) { 2739 /* Sweep up transmit descriptors. */ 2740 atw_txintr(sc); 2741 2742 if (txstatus & ATW_INTR_TLT) 2743 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2744 sc->sc_dev.dv_xname)); 2745 2746 if (txstatus & ATW_INTR_TRT) 2747 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2748 sc->sc_dev.dv_xname)); 2749 2750 /* If Tx under-run, increase our transmit threshold 2751 * if another is available. 2752 */ 2753 txthresh = sc->sc_txthresh + 1; 2754 if ((txstatus & ATW_INTR_TUF) && 2755 sc->sc_txth[txthresh].txth_name != NULL) { 2756 /* Idle the transmit process. */ 2757 atw_idle(sc, ATW_NAR_ST); 2758 2759 sc->sc_txthresh = txthresh; 2760 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2761 sc->sc_opmode |= 2762 sc->sc_txth[txthresh].txth_opmode; 2763 printf("%s: transmit underrun; new " 2764 "threshold: %s\n", sc->sc_dev.dv_xname, 2765 sc->sc_txth[txthresh].txth_name); 2766 2767 /* Set the new threshold and restart 2768 * the transmit process. 2769 */ 2770 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2771 /* XXX Log every Nth underrun from 2772 * XXX now on? 2773 */ 2774 } 2775 } 2776 2777 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2778 if (status & ATW_INTR_TPS) 2779 printf("%s: transmit process stopped\n", 2780 sc->sc_dev.dv_xname); 2781 if (status & ATW_INTR_RPS) 2782 printf("%s: receive process stopped\n", 2783 sc->sc_dev.dv_xname); 2784 (void)atw_init(ifp); 2785 break; 2786 } 2787 2788 if (status & ATW_INTR_FBE) { 2789 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2790 (void)atw_init(ifp); 2791 break; 2792 } 2793 2794 /* 2795 * Not handled: 2796 * 2797 * Transmit buffer unavailable -- normal 2798 * condition, nothing to do, really. 2799 * 2800 * Early receive interrupt -- not available on 2801 * all chips, we just use RI. We also only 2802 * use single-segment receive DMA, so this 2803 * is mostly useless. 2804 * 2805 * TBD others 2806 */ 2807 } 2808 2809 /* Try to get more packets going. */ 2810 atw_start(ifp); 2811 2812 return (handled); 2813 } 2814 2815 /* 2816 * atw_idle: 2817 * 2818 * Cause the transmit and/or receive processes to go idle. 2819 * 2820 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2821 * process in STSR if I clear SR or ST after the process has already 2822 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2823 * do not seem to be too reliable. Perhaps I have the sense of the 2824 * Rx bits switched with the Tx bits? 2825 */ 2826 void 2827 atw_idle(struct atw_softc *sc, u_int32_t bits) 2828 { 2829 u_int32_t ackmask = 0, opmode, stsr, test0; 2830 int i, s; 2831 2832 /* without this, somehow we run concurrently w/ interrupt handler */ 2833 s = splnet(); 2834 2835 opmode = sc->sc_opmode & ~bits; 2836 2837 if (bits & ATW_NAR_SR) 2838 ackmask |= ATW_INTR_RPS; 2839 2840 if (bits & ATW_NAR_ST) { 2841 ackmask |= ATW_INTR_TPS; 2842 /* set ATW_NAR_HF to flush TX FIFO. */ 2843 opmode |= ATW_NAR_HF; 2844 } 2845 2846 ATW_WRITE(sc, ATW_NAR, opmode); 2847 2848 for (i = 0; i < 1000; i++) { 2849 stsr = ATW_READ(sc, ATW_STSR); 2850 if ((stsr & ackmask) == ackmask) 2851 break; 2852 DELAY(10); 2853 } 2854 2855 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2856 2857 if ((stsr & ackmask) == ackmask) 2858 goto out; 2859 2860 test0 = ATW_READ(sc, ATW_TEST0); 2861 2862 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2863 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2864 printf("%s: transmit process not idle [%s]\n", 2865 sc->sc_dev.dv_xname, 2866 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2867 printf("%s: bits %08x test0 %08x stsr %08x\n", 2868 sc->sc_dev.dv_xname, bits, test0, stsr); 2869 } 2870 2871 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2872 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2873 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2874 sc->sc_dev.dv_xname, 2875 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2876 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2877 sc->sc_dev.dv_xname, bits, test0, stsr)); 2878 } 2879 out: 2880 splx(s); 2881 return; 2882 } 2883 2884 /* 2885 * atw_linkintr: 2886 * 2887 * Helper; handle link-status interrupts. 2888 */ 2889 void 2890 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2891 { 2892 struct ieee80211com *ic = &sc->sc_ic; 2893 2894 if (ic->ic_state != IEEE80211_S_RUN) 2895 return; 2896 2897 if (linkstatus & ATW_INTR_LINKON) { 2898 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2899 sc->sc_rescan_timer = 0; 2900 } else if (linkstatus & ATW_INTR_LINKOFF) { 2901 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2902 if (ic->ic_opmode != IEEE80211_M_STA) 2903 return; 2904 sc->sc_rescan_timer = 3; 2905 ic->ic_if.if_timer = 1; 2906 } 2907 } 2908 2909 /* 2910 * atw_rxintr: 2911 * 2912 * Helper; handle receive interrupts. 2913 */ 2914 void 2915 atw_rxintr(struct atw_softc *sc) 2916 { 2917 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2918 struct ieee80211com *ic = &sc->sc_ic; 2919 struct ieee80211_node *ni; 2920 struct ieee80211_frame *wh; 2921 struct ifnet *ifp = &ic->ic_if; 2922 struct atw_rxsoft *rxs; 2923 struct mbuf *m; 2924 u_int32_t rxstat; 2925 int i, len, rate, rate0; 2926 u_int32_t rssi; 2927 2928 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2929 rxs = &sc->sc_rxsoft[i]; 2930 2931 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2932 2933 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2934 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2935 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2936 2937 if (rxstat & ATW_RXSTAT_OWN) 2938 break; /* We have processed all receive buffers. */ 2939 2940 DPRINTF3(sc, 2941 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2942 sc->sc_dev.dv_xname, 2943 sc->sc_rxdescs[i].ar_stat, 2944 sc->sc_rxdescs[i].ar_rssi, 2945 sc->sc_rxdescs[i].ar_buf1, 2946 sc->sc_rxdescs[i].ar_buf2)); 2947 2948 /* 2949 * Make sure the packet fits in one buffer. This should 2950 * always be the case. 2951 */ 2952 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2953 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2954 printf("%s: incoming packet spilled, resetting\n", 2955 sc->sc_dev.dv_xname); 2956 (void)atw_init(ifp); 2957 return; 2958 } 2959 2960 /* 2961 * If an error occurred, update stats, clear the status 2962 * word, and leave the packet buffer in place. It will 2963 * simply be reused the next time the ring comes around. 2964 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2965 * error. 2966 */ 2967 2968 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2969 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2970 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2971 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2972 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2973 ATW_RXSTAT_ICVE)) != 0)) { 2974 #define PRINTERR(bit, str) \ 2975 if (rxstat & (bit)) \ 2976 printf("%s: receive error: %s\n", \ 2977 sc->sc_dev.dv_xname, str) 2978 ifp->if_ierrors++; 2979 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2980 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2981 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2982 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2983 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2984 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2985 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2986 #undef PRINTERR 2987 ATW_INIT_RXDESC(sc, i); 2988 continue; 2989 } 2990 2991 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2992 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2993 2994 /* 2995 * No errors; receive the packet. Note the ADM8211 2996 * includes the CRC in promiscuous mode. 2997 */ 2998 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2999 3000 /* 3001 * Allocate a new mbuf cluster. If that fails, we are 3002 * out of memory, and must drop the packet and recycle 3003 * the buffer that's already attached to this descriptor. 3004 */ 3005 m = rxs->rxs_mbuf; 3006 if (atw_add_rxbuf(sc, i) != 0) { 3007 ifp->if_ierrors++; 3008 ATW_INIT_RXDESC(sc, i); 3009 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3010 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3011 continue; 3012 } 3013 3014 ifp->if_ipackets++; 3015 if (sc->sc_opmode & ATW_NAR_PR) 3016 m->m_flags |= M_HASFCS; 3017 m->m_pkthdr.rcvif = ifp; 3018 m->m_pkthdr.len = m->m_len = len; 3019 3020 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3021 rate = 0; 3022 else 3023 rate = rate_tbl[rate0]; 3024 3025 #if NBPFILTER > 0 3026 /* Pass this up to any BPF listeners. */ 3027 if (sc->sc_radiobpf != NULL) { 3028 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3029 3030 tap->ar_rate = rate; 3031 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3032 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3033 3034 /* TBD verify units are dB */ 3035 tap->ar_antsignal = (int)rssi; 3036 /* TBD tap->ar_flags */ 3037 3038 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3039 tap->ar_ihdr.it_len, m); 3040 } 3041 #endif /* NPBFILTER > 0 */ 3042 3043 wh = mtod(m, struct ieee80211_frame *); 3044 ni = ieee80211_find_rxnode(ic, wh); 3045 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3046 /* 3047 * The frame may have caused the node to be marked for 3048 * reclamation (e.g. in response to a DEAUTH message) 3049 * so use free_node here instead of unref_node. 3050 */ 3051 if (ni == ic->ic_bss) 3052 ieee80211_unref_node(&ni); 3053 else 3054 ieee80211_free_node(ic, ni); 3055 } 3056 3057 /* Update the receive pointer. */ 3058 sc->sc_rxptr = i; 3059 } 3060 3061 /* 3062 * atw_txintr: 3063 * 3064 * Helper; handle transmit interrupts. 3065 */ 3066 void 3067 atw_txintr(struct atw_softc *sc) 3068 { 3069 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3070 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3071 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3072 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3073 3074 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3075 struct ifnet *ifp = &sc->sc_ic.ic_if; 3076 struct atw_txsoft *txs; 3077 u_int32_t txstat; 3078 3079 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3080 sc->sc_dev.dv_xname, sc->sc_flags)); 3081 3082 ifp->if_flags &= ~IFF_OACTIVE; 3083 3084 /* 3085 * Go through our Tx list and free mbufs for those 3086 * frames that have been transmitted. 3087 */ 3088 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3089 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3090 txs->txs_ndescs, 3091 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3092 3093 #ifdef ATW_DEBUG 3094 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3095 int i; 3096 printf(" txsoft %p transmit chain:\n", txs); 3097 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3098 printf(" descriptor %d:\n", i); 3099 printf(" at_status: 0x%08x\n", 3100 le32toh(sc->sc_txdescs[i].at_stat)); 3101 printf(" at_flags: 0x%08x\n", 3102 le32toh(sc->sc_txdescs[i].at_flags)); 3103 printf(" at_buf1: 0x%08x\n", 3104 le32toh(sc->sc_txdescs[i].at_buf1)); 3105 printf(" at_buf2: 0x%08x\n", 3106 le32toh(sc->sc_txdescs[i].at_buf2)); 3107 if (i == txs->txs_lastdesc) 3108 break; 3109 } 3110 } 3111 #endif 3112 3113 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3114 if (txstat & ATW_TXSTAT_OWN) 3115 break; 3116 3117 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3118 3119 sc->sc_txfree += txs->txs_ndescs; 3120 3121 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3122 0, txs->txs_dmamap->dm_mapsize, 3123 BUS_DMASYNC_POSTWRITE); 3124 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3125 m_freem(txs->txs_mbuf); 3126 txs->txs_mbuf = NULL; 3127 3128 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3129 3130 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3131 (txstat & TXSTAT_ERRMASK) != 0) { 3132 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3133 txstat_buf, sizeof(txstat_buf)); 3134 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3135 txstat_buf, 3136 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3137 } 3138 3139 /* 3140 * Check for errors and collisions. 3141 */ 3142 if (txstat & ATW_TXSTAT_TUF) 3143 sc->sc_stats.ts_tx_tuf++; 3144 if (txstat & ATW_TXSTAT_TLT) 3145 sc->sc_stats.ts_tx_tlt++; 3146 if (txstat & ATW_TXSTAT_TRT) 3147 sc->sc_stats.ts_tx_trt++; 3148 if (txstat & ATW_TXSTAT_TRO) 3149 sc->sc_stats.ts_tx_tro++; 3150 if (txstat & ATW_TXSTAT_SOFBR) { 3151 sc->sc_stats.ts_tx_sofbr++; 3152 } 3153 3154 if ((txstat & ATW_TXSTAT_ES) == 0) 3155 ifp->if_collisions += 3156 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3157 else 3158 ifp->if_oerrors++; 3159 3160 ifp->if_opackets++; 3161 } 3162 3163 /* 3164 * If there are no more pending transmissions, cancel the watchdog 3165 * timer. 3166 */ 3167 if (txs == NULL) 3168 sc->sc_tx_timer = 0; 3169 #undef TXSTAT_ERRMASK 3170 #undef TXSTAT_FMT 3171 } 3172 3173 /* 3174 * atw_watchdog: [ifnet interface function] 3175 * 3176 * Watchdog timer handler. 3177 */ 3178 void 3179 atw_watchdog(struct ifnet *ifp) 3180 { 3181 struct atw_softc *sc = ifp->if_softc; 3182 struct ieee80211com *ic = &sc->sc_ic; 3183 3184 ifp->if_timer = 0; 3185 if (ATW_IS_ENABLED(sc) == 0) 3186 return; 3187 3188 if (sc->sc_rescan_timer) { 3189 if (--sc->sc_rescan_timer == 0) 3190 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3191 } 3192 if (sc->sc_tx_timer) { 3193 if (--sc->sc_tx_timer == 0 && 3194 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3195 printf("%s: transmit timeout\n", ifp->if_xname); 3196 ifp->if_oerrors++; 3197 (void)atw_init(ifp); 3198 atw_start(ifp); 3199 } 3200 } 3201 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3202 ifp->if_timer = 1; 3203 ieee80211_watchdog(ifp); 3204 } 3205 3206 /* Compute the 802.11 Duration field and the PLCP Length fields for 3207 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3208 * Write the fields to the ADM8211 Tx header, frm. 3209 * 3210 * TBD use the fragmentation threshold to find the right duration for 3211 * the first & last fragments. 3212 * 3213 * TBD make certain of the duration fields applied by the ADM8211 to each 3214 * fragment. I think that the ADM8211 knows how to subtract the CTS 3215 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3216 * I also think that the ADM8211 does *some* arithmetic for us, because 3217 * otherwise I think we would have to set a first duration for CTS/first 3218 * fragment, a second duration for fragments between the first and the 3219 * last, and a third duration for the last fragment. 3220 * 3221 * TBD make certain that duration fields reflect addition of FCS/WEP 3222 * and correct duration arithmetic as necessary. 3223 */ 3224 static void 3225 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3226 int len) 3227 { 3228 int remainder; 3229 3230 /* deal also with encrypted fragments */ 3231 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3232 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3233 sc->sc_dev.dv_xname)); 3234 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3235 IEEE80211_WEP_CRCLEN; 3236 } 3237 3238 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3239 * duration (XXX added by MAC?). 3240 */ 3241 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3242 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3243 3244 if (rate <= 4) 3245 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3246 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3247 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3248 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3249 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3250 else 3251 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3252 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3253 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3254 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3255 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3256 3257 /* lengthen duration if long preamble */ 3258 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3259 frm->atw_head_dur += 3260 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3261 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3262 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3263 IEEE80211_DUR_DS_FAST_PLCPHDR); 3264 3265 if (remainder != 0) 3266 frm->atw_head_dur++; 3267 3268 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3269 (rate == 2 || rate == 4)) { 3270 /* derived from Linux: how could this be right? */ 3271 frm->atw_head_plcplen = frm->atw_head_dur; 3272 } else { 3273 frm->atw_head_plcplen = (16 * len) / rate; 3274 remainder = (80 * len) % (rate * 5); 3275 3276 if (remainder != 0) { 3277 frm->atw_head_plcplen++; 3278 3279 /* XXX magic */ 3280 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3281 rate == 22 && remainder <= 30) 3282 frm->atw_head_plcplen |= 0x8000; 3283 } 3284 } 3285 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3286 htole16(frm->atw_head_plcplen); 3287 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3288 } 3289 3290 #ifdef ATW_DEBUG 3291 static void 3292 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3293 { 3294 struct atw_softc *sc = ifp->if_softc; 3295 struct mbuf *m; 3296 int i, noctets = 0; 3297 3298 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3299 m0->m_pkthdr.len); 3300 3301 for (m = m0; m; m = m->m_next) { 3302 if (m->m_len == 0) 3303 continue; 3304 for (i = 0; i < m->m_len; i++) { 3305 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3306 if (++noctets % 24 == 0) 3307 printf("\n"); 3308 } 3309 } 3310 printf("%s%s: %d bytes emitted\n", 3311 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3312 } 3313 #endif /* ATW_DEBUG */ 3314 3315 /* 3316 * atw_start: [ifnet interface function] 3317 * 3318 * Start packet transmission on the interface. 3319 */ 3320 void 3321 atw_start(struct ifnet *ifp) 3322 { 3323 struct atw_softc *sc = ifp->if_softc; 3324 struct ieee80211com *ic = &sc->sc_ic; 3325 struct ieee80211_node *ni; 3326 struct ieee80211_frame *wh; 3327 struct atw_frame *hh; 3328 struct mbuf *m0, *m; 3329 struct atw_txsoft *txs, *last_txs; 3330 struct atw_txdesc *txd; 3331 int do_encrypt, rate; 3332 bus_dmamap_t dmamap; 3333 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3334 3335 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3336 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3337 3338 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3339 return; 3340 3341 #if 0 /* TBD ??? */ 3342 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3343 return; 3344 #endif 3345 3346 /* 3347 * Remember the previous number of free descriptors and 3348 * the first descriptor we'll use. 3349 */ 3350 ofree = sc->sc_txfree; 3351 firsttx = sc->sc_txnext; 3352 3353 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3354 sc->sc_dev.dv_xname, ofree, firsttx)); 3355 3356 /* 3357 * Loop through the send queue, setting up transmit descriptors 3358 * until we drain the queue, or use up all available transmit 3359 * descriptors. 3360 */ 3361 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3362 sc->sc_txfree != 0) { 3363 3364 /* 3365 * Grab a packet off the management queue, if it 3366 * is not empty. Otherwise, from the data queue. 3367 */ 3368 IF_DEQUEUE(&ic->ic_mgtq, m0); 3369 if (m0 != NULL) { 3370 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3371 m0->m_pkthdr.rcvif = NULL; 3372 } else { 3373 IFQ_DEQUEUE(&ifp->if_snd, m0); 3374 if (m0 == NULL) 3375 break; 3376 #if NBPFILTER > 0 3377 if (ifp->if_bpf != NULL) 3378 bpf_mtap(ifp->if_bpf, m0); 3379 #endif /* NBPFILTER > 0 */ 3380 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3381 ifp->if_oerrors++; 3382 break; 3383 } 3384 } 3385 3386 rate = MAX(ieee80211_get_rate(ic), 2); 3387 3388 #if NBPFILTER > 0 3389 /* 3390 * Pass the packet to any BPF listeners. 3391 */ 3392 if (ic->ic_rawbpf != NULL) 3393 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3394 3395 if (sc->sc_radiobpf != NULL) { 3396 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3397 3398 tap->at_rate = rate; 3399 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3400 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3401 3402 /* TBD tap->at_flags */ 3403 3404 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3405 tap->at_ihdr.it_len, m0); 3406 } 3407 #endif /* NBPFILTER > 0 */ 3408 3409 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3410 3411 if (ni != NULL && ni != ic->ic_bss) 3412 ieee80211_free_node(ic, ni); 3413 3414 if (m0 == NULL) { 3415 ifp->if_oerrors++; 3416 break; 3417 } 3418 3419 /* just to make sure. */ 3420 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3421 3422 if (m0 == NULL) { 3423 ifp->if_oerrors++; 3424 break; 3425 } 3426 3427 hh = mtod(m0, struct atw_frame *); 3428 wh = &hh->atw_ihdr; 3429 3430 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3431 3432 /* Copy everything we need from the 802.11 header: 3433 * Frame Control; address 1, address 3, or addresses 3434 * 3 and 4. NIC fills in BSSID, SA. 3435 */ 3436 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3437 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3438 panic("%s: illegal WDS frame", 3439 sc->sc_dev.dv_xname); 3440 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3441 } else 3442 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3443 3444 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3445 3446 /* initialize remaining Tx parameters */ 3447 memset(&hh->u, 0, sizeof(hh->u)); 3448 3449 hh->atw_rate = rate * 5; 3450 /* XXX this could be incorrect if M_FCS. _encap should 3451 * probably strip FCS just in case it sticks around in 3452 * bridged packets. 3453 */ 3454 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3455 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3456 sizeof(struct atw_frame)); 3457 3458 #if 0 3459 /* this virtually guaranteed that WEP-encrypted frames 3460 * are fragmented. oops. 3461 */ 3462 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3463 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3464 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3465 #else 3466 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3467 #endif 3468 3469 hh->atw_rtylmt = 3; 3470 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3471 if (do_encrypt) { 3472 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3473 hh->atw_keyid = ic->ic_wep_txkey; 3474 } 3475 3476 /* TBD 4-addr frames */ 3477 atw_frame_setdurs(sc, hh, rate, 3478 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3479 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3480 3481 /* never fragment multicast frames */ 3482 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3483 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3484 } else if (sc->sc_flags & ATWF_RTSCTS) { 3485 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3486 } 3487 3488 #ifdef ATW_DEBUG 3489 /* experimental stuff */ 3490 if (atw_xrtylmt != ~0) 3491 hh->atw_rtylmt = atw_xrtylmt; 3492 if (atw_xhdrctl != 0) 3493 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3494 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3495 hh->atw_service = atw_xservice; 3496 if (atw_xpaylen != 0) 3497 hh->atw_paylen = htole16(atw_xpaylen); 3498 hh->atw_fragnum = 0; 3499 3500 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3501 printf("%s: dst = %s, rate = 0x%02x, " 3502 "service = 0x%02x, paylen = 0x%04x\n", 3503 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3504 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3505 3506 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3507 "dur1 = 0x%04x, dur2 = 0x%04x, " 3508 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3509 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3510 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3511 hh->atw_tail_dur, hh->atw_head_dur); 3512 3513 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3514 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3515 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3516 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3517 3518 printf("%s: keyid = %d\n", 3519 sc->sc_dev.dv_xname, hh->atw_keyid); 3520 3521 atw_dump_pkt(ifp, m0); 3522 } 3523 #endif /* ATW_DEBUG */ 3524 3525 dmamap = txs->txs_dmamap; 3526 3527 /* 3528 * Load the DMA map. Copy and try (once) again if the packet 3529 * didn't fit in the alloted number of segments. 3530 */ 3531 for (first = 1; 3532 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3533 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3534 first = 0) { 3535 MGETHDR(m, M_DONTWAIT, MT_DATA); 3536 if (m == NULL) { 3537 printf("%s: unable to allocate Tx mbuf\n", 3538 sc->sc_dev.dv_xname); 3539 break; 3540 } 3541 if (m0->m_pkthdr.len > MHLEN) { 3542 MCLGET(m, M_DONTWAIT); 3543 if ((m->m_flags & M_EXT) == 0) { 3544 printf("%s: unable to allocate Tx " 3545 "cluster\n", sc->sc_dev.dv_xname); 3546 m_freem(m); 3547 break; 3548 } 3549 } 3550 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3551 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3552 m_freem(m0); 3553 m0 = m; 3554 m = NULL; 3555 } 3556 if (error != 0) { 3557 printf("%s: unable to load Tx buffer, " 3558 "error = %d\n", sc->sc_dev.dv_xname, error); 3559 m_freem(m0); 3560 break; 3561 } 3562 3563 /* 3564 * Ensure we have enough descriptors free to describe 3565 * the packet. 3566 */ 3567 if (dmamap->dm_nsegs > sc->sc_txfree) { 3568 /* 3569 * Not enough free descriptors to transmit 3570 * this packet. Unload the DMA map and 3571 * drop the packet. Notify the upper layer 3572 * that there are no more slots left. 3573 * 3574 * XXX We could allocate an mbuf and copy, but 3575 * XXX it is worth it? 3576 */ 3577 ifp->if_flags |= IFF_OACTIVE; 3578 bus_dmamap_unload(sc->sc_dmat, dmamap); 3579 m_freem(m0); 3580 break; 3581 } 3582 3583 /* 3584 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3585 */ 3586 3587 /* Sync the DMA map. */ 3588 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3589 BUS_DMASYNC_PREWRITE); 3590 3591 /* XXX arbitrary retry limit; 8 because I have seen it in 3592 * use already and maybe 0 means "no tries" ! 3593 */ 3594 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3595 3596 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3597 sc->sc_dev.dv_xname, rate * 5)); 3598 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3599 3600 /* 3601 * Initialize the transmit descriptors. 3602 */ 3603 for (nexttx = sc->sc_txnext, seg = 0; 3604 seg < dmamap->dm_nsegs; 3605 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3606 /* 3607 * If this is the first descriptor we're 3608 * enqueueing, don't set the OWN bit just 3609 * yet. That could cause a race condition. 3610 * We'll do it below. 3611 */ 3612 txd = &sc->sc_txdescs[nexttx]; 3613 txd->at_ctl = ctl | 3614 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3615 3616 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3617 txd->at_flags = 3618 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3619 ATW_TXFLAG_TBS1_MASK)) | 3620 ((nexttx == (ATW_NTXDESC - 1)) 3621 ? htole32(ATW_TXFLAG_TER) : 0); 3622 lasttx = nexttx; 3623 } 3624 3625 IASSERT(lasttx != -1, ("bad lastx")); 3626 /* Set `first segment' and `last segment' appropriately. */ 3627 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3628 htole32(ATW_TXFLAG_FS); 3629 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3630 3631 #ifdef ATW_DEBUG 3632 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3633 printf(" txsoft %p transmit chain:\n", txs); 3634 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3635 printf(" descriptor %d:\n", seg); 3636 printf(" at_ctl: 0x%08x\n", 3637 le32toh(sc->sc_txdescs[seg].at_ctl)); 3638 printf(" at_flags: 0x%08x\n", 3639 le32toh(sc->sc_txdescs[seg].at_flags)); 3640 printf(" at_buf1: 0x%08x\n", 3641 le32toh(sc->sc_txdescs[seg].at_buf1)); 3642 printf(" at_buf2: 0x%08x\n", 3643 le32toh(sc->sc_txdescs[seg].at_buf2)); 3644 if (seg == lasttx) 3645 break; 3646 } 3647 } 3648 #endif 3649 3650 /* Sync the descriptors we're using. */ 3651 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3652 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3653 3654 /* 3655 * Store a pointer to the packet so we can free it later, 3656 * and remember what txdirty will be once the packet is 3657 * done. 3658 */ 3659 txs->txs_mbuf = m0; 3660 txs->txs_firstdesc = sc->sc_txnext; 3661 txs->txs_lastdesc = lasttx; 3662 txs->txs_ndescs = dmamap->dm_nsegs; 3663 3664 /* Advance the tx pointer. */ 3665 sc->sc_txfree -= dmamap->dm_nsegs; 3666 sc->sc_txnext = nexttx; 3667 3668 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3669 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3670 3671 last_txs = txs; 3672 } 3673 3674 if (txs == NULL || sc->sc_txfree == 0) { 3675 /* No more slots left; notify upper layer. */ 3676 ifp->if_flags |= IFF_OACTIVE; 3677 } 3678 3679 if (sc->sc_txfree != ofree) { 3680 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3681 sc->sc_dev.dv_xname, lasttx, firsttx)); 3682 /* 3683 * Cause a transmit interrupt to happen on the 3684 * last packet we enqueued. 3685 */ 3686 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3687 ATW_CDTXSYNC(sc, lasttx, 1, 3688 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3689 3690 /* 3691 * The entire packet chain is set up. Give the 3692 * first descriptor to the chip now. 3693 */ 3694 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3695 ATW_CDTXSYNC(sc, firsttx, 1, 3696 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3697 3698 /* Wake up the transmitter. */ 3699 ATW_WRITE(sc, ATW_TDR, 0x1); 3700 3701 /* Set a watchdog timer in case the chip flakes out. */ 3702 sc->sc_tx_timer = 5; 3703 ifp->if_timer = 1; 3704 } 3705 } 3706 3707 /* 3708 * atw_power: 3709 * 3710 * Power management (suspend/resume) hook. 3711 */ 3712 void 3713 atw_power(int why, void *arg) 3714 { 3715 struct atw_softc *sc = arg; 3716 struct ifnet *ifp = &sc->sc_ic.ic_if; 3717 int s; 3718 3719 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3720 3721 s = splnet(); 3722 switch (why) { 3723 case PWR_STANDBY: 3724 /* XXX do nothing. */ 3725 break; 3726 case PWR_SUSPEND: 3727 atw_stop(ifp, 0); 3728 if (sc->sc_power != NULL) 3729 (*sc->sc_power)(sc, why); 3730 break; 3731 case PWR_RESUME: 3732 if (ifp->if_flags & IFF_UP) { 3733 if (sc->sc_power != NULL) 3734 (*sc->sc_power)(sc, why); 3735 atw_init(ifp); 3736 } 3737 break; 3738 case PWR_SOFTSUSPEND: 3739 case PWR_SOFTSTANDBY: 3740 case PWR_SOFTRESUME: 3741 break; 3742 } 3743 splx(s); 3744 } 3745 3746 /* 3747 * atw_ioctl: [ifnet interface function] 3748 * 3749 * Handle control requests from the operator. 3750 */ 3751 int 3752 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3753 { 3754 struct atw_softc *sc = ifp->if_softc; 3755 struct ifreq *ifr = (struct ifreq *)data; 3756 int s, error = 0; 3757 3758 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3759 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3760 return ENXIO; 3761 3762 s = splnet(); 3763 3764 switch (cmd) { 3765 case SIOCSIFFLAGS: 3766 if (ifp->if_flags & IFF_UP) { 3767 if (ATW_IS_ENABLED(sc)) { 3768 /* 3769 * To avoid rescanning another access point, 3770 * do not call atw_init() here. Instead, 3771 * only reflect media settings. 3772 */ 3773 atw_filter_setup(sc); 3774 } else 3775 error = atw_init(ifp); 3776 } else if (ATW_IS_ENABLED(sc)) 3777 atw_stop(ifp, 1); 3778 break; 3779 case SIOCADDMULTI: 3780 case SIOCDELMULTI: 3781 error = (cmd == SIOCADDMULTI) ? 3782 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3783 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3784 if (error == ENETRESET) { 3785 if (ATW_IS_ENABLED(sc)) 3786 atw_filter_setup(sc); /* do not rescan */ 3787 error = 0; 3788 } 3789 break; 3790 default: 3791 error = ieee80211_ioctl(ifp, cmd, data); 3792 if (error == ENETRESET) { 3793 if (ATW_IS_ENABLED(sc)) 3794 error = atw_init(ifp); 3795 else 3796 error = 0; 3797 } 3798 break; 3799 } 3800 3801 /* Try to get more packets going. */ 3802 if (ATW_IS_ENABLED(sc)) 3803 atw_start(ifp); 3804 3805 splx(s); 3806 return (error); 3807 } 3808 3809 static int 3810 atw_media_change(struct ifnet *ifp) 3811 { 3812 int error; 3813 3814 error = ieee80211_media_change(ifp); 3815 if (error == ENETRESET) { 3816 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3817 (IFF_RUNNING|IFF_UP)) 3818 atw_init(ifp); /* XXX lose error */ 3819 error = 0; 3820 } 3821 return error; 3822 } 3823 3824 static void 3825 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3826 { 3827 struct atw_softc *sc = ifp->if_softc; 3828 3829 if (ATW_IS_ENABLED(sc) == 0) { 3830 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3831 imr->ifm_status = 0; 3832 return; 3833 } 3834 ieee80211_media_status(ifp, imr); 3835 } 3836
Indexes created Fri Sep 26 20:09:58 GMT 2025