atw.c revision 1.35
1 /* $NetBSD: atw.c,v 1.35 2004/06/23 09:05:50 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.35 2004/06/23 09:05:50 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * IBSS join/create 131 * 132 * set ATW_NAR_EA (is set by ASIC?) 133 * 134 * BSS join: (re)association response 135 * 136 * set ATW_FRCTL_AID 137 * 138 * optimizations ??? 139 * 140 */ 141 142 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 143 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 144 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 145 146 int atw_rfio_enable_delay = 20 * 1000; 147 int atw_rfio_disable_delay = 2 * 1000; 148 int atw_writewep_delay = 5; 149 int atw_beacon_len_adjust = 4; 150 int atw_dwelltime = 200; 151 152 #ifdef ATW_DEBUG 153 int atw_xhdrctl = 0; 154 int atw_xrtylmt = ~0; 155 int atw_xservice = IEEE80211_PLCP_SERVICE; 156 int atw_xpaylen = 0; 157 158 int atw_debug = 0; 159 160 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 161 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 162 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 163 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 164 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 165 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 166 static void atw_print_regs(struct atw_softc *, const char *); 167 static void atw_rf3000_print(struct atw_softc *); 168 static void atw_si4126_print(struct atw_softc *); 169 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 170 #else 171 #define ATW_DPRINTF(x) 172 #define ATW_DPRINTF2(x) 173 #define ATW_DPRINTF3(x) 174 #define DPRINTF(sc, x) /* nothing */ 175 #define DPRINTF2(sc, x) /* nothing */ 176 #define DPRINTF3(sc, x) /* nothing */ 177 #endif 178 179 #ifdef ATW_STATS 180 void atw_print_stats(struct atw_softc *); 181 #endif 182 183 void atw_start(struct ifnet *); 184 void atw_watchdog(struct ifnet *); 185 int atw_ioctl(struct ifnet *, u_long, caddr_t); 186 int atw_init(struct ifnet *); 187 void atw_stop(struct ifnet *, int); 188 189 void atw_reset(struct atw_softc *); 190 int atw_read_srom(struct atw_softc *); 191 192 void atw_shutdown(void *); 193 194 void atw_rxdrain(struct atw_softc *); 195 int atw_add_rxbuf(struct atw_softc *, int); 196 void atw_idle(struct atw_softc *, u_int32_t); 197 198 int atw_enable(struct atw_softc *); 199 void atw_disable(struct atw_softc *); 200 void atw_power(int, void *); 201 202 void atw_rxintr(struct atw_softc *); 203 void atw_txintr(struct atw_softc *); 204 void atw_linkintr(struct atw_softc *, u_int32_t); 205 206 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 207 static void atw_tsf(struct atw_softc *); 208 static void atw_start_beacon(struct atw_softc *, int); 209 static void atw_write_wep(struct atw_softc *); 210 static void atw_write_bssid(struct atw_softc *); 211 static void atw_write_bcn_thresh(struct atw_softc *); 212 static void atw_write_ssid(struct atw_softc *); 213 static void atw_write_sup_rates(struct atw_softc *); 214 static void atw_clear_sram(struct atw_softc *); 215 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 216 static int atw_media_change(struct ifnet *); 217 static void atw_media_status(struct ifnet *, struct ifmediareq *); 218 static void atw_filter_setup(struct atw_softc *); 219 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 220 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 221 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 226 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 227 228 static int atw_tune(struct atw_softc *); 229 230 static void atw_rfio_enable(struct atw_softc *, int); 231 232 /* RFMD RF3000 Baseband Processor */ 233 static int atw_rf3000_init(struct atw_softc *); 234 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 235 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 236 #ifdef ATW_DEBUG 237 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 238 #endif /* ATW_DEBUG */ 239 240 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 241 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 242 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 243 #ifdef ATW_DEBUG 244 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 245 #endif /* ATW_DEBUG */ 246 247 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 248 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 249 250 const char *atw_tx_state[] = { 251 "STOPPED", 252 "RUNNING - read descriptor", 253 "RUNNING - transmitting", 254 "RUNNING - filling fifo", /* XXX */ 255 "SUSPENDED", 256 "RUNNING -- write descriptor", 257 "RUNNING -- write last descriptor", 258 "RUNNING - fifo full" 259 }; 260 261 const char *atw_rx_state[] = { 262 "STOPPED", 263 "RUNNING - read descriptor", 264 "RUNNING - check this packet, pre-fetch next", 265 "RUNNING - wait for reception", 266 "SUSPENDED", 267 "RUNNING - write descriptor", 268 "RUNNING - flush fifo", 269 "RUNNING - fifo drain" 270 }; 271 272 int 273 atw_activate(struct device *self, enum devact act) 274 { 275 struct atw_softc *sc = (struct atw_softc *)self; 276 int rv = 0, s; 277 278 s = splnet(); 279 switch (act) { 280 case DVACT_ACTIVATE: 281 rv = EOPNOTSUPP; 282 break; 283 284 case DVACT_DEACTIVATE: 285 if_deactivate(&sc->sc_ic.ic_if); 286 break; 287 } 288 splx(s); 289 return rv; 290 } 291 292 /* 293 * atw_enable: 294 * 295 * Enable the ADM8211 chip. 296 */ 297 int 298 atw_enable(struct atw_softc *sc) 299 { 300 301 if (ATW_IS_ENABLED(sc) == 0) { 302 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 303 printf("%s: device enable failed\n", 304 sc->sc_dev.dv_xname); 305 return (EIO); 306 } 307 sc->sc_flags |= ATWF_ENABLED; 308 } 309 return (0); 310 } 311 312 /* 313 * atw_disable: 314 * 315 * Disable the ADM8211 chip. 316 */ 317 void 318 atw_disable(struct atw_softc *sc) 319 { 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325 } 326 327 /* Returns -1 on failure. */ 328 int 329 atw_read_srom(struct atw_softc *sc) 330 { 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393 #ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF(("\n\t")); 400 } 401 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF(("\n")); 404 } 405 #endif /* ATW_DEBUG */ 406 return 0; 407 } 408 409 #ifdef ATW_DEBUG 410 static void 411 atw_print_regs(struct atw_softc *sc, const char *where) 412 { 413 #define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487 #undef PRINTREG 488 } 489 #endif /* ATW_DEBUG */ 490 491 /* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494 void 495 atw_attach(struct atw_softc *sc) 496 { 497 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 499 }; 500 struct ieee80211com *ic = &sc->sc_ic; 501 struct ifnet *ifp = &ic->ic_if; 502 int country_code, error, i, nrate; 503 u_int32_t reg; 504 static const char *type_strings[] = {"Intersil (not supported)", 505 "RFMD", "Marvel (not supported)"}; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512 #ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514 #endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 } 577 for (i = 0; i < ATW_NRXDESC; i++) { 578 sc->sc_rxsoft[i].rxs_mbuf = NULL; 579 } 580 581 /* Reset the chip to a known state. */ 582 atw_reset(sc); 583 584 if (atw_read_srom(sc) == -1) 585 return; 586 587 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_RFTYPE_MASK); 589 590 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 591 ATW_SR_BBPTYPE_MASK); 592 593 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 594 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 598 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 599 return; 600 } 601 602 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 603 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 604 605 /* XXX There exists a Linux driver which seems to use RFType = 0 for 606 * MARVEL. My bug, or theirs? 607 */ 608 609 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 610 611 switch (sc->sc_rftype) { 612 case ATW_RFTYPE_INTERSIL: 613 reg |= ATW_SYNCTL_CS1; 614 break; 615 case ATW_RFTYPE_RFMD: 616 reg |= ATW_SYNCTL_CS0; 617 break; 618 case ATW_RFTYPE_MARVEL: 619 break; 620 } 621 622 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 623 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 624 625 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 626 627 switch (sc->sc_bbptype) { 628 case ATW_BBPTYPE_INTERSIL: 629 reg |= ATW_BBPCTL_TWI; 630 break; 631 case ATW_BBPTYPE_RFMD: 632 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 633 ATW_BBPCTL_CCA_ACTLO; 634 break; 635 case ATW_BBPTYPE_MARVEL: 636 break; 637 case ATW_C_BBPTYPE_RFMD: 638 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 639 sc->sc_dev.dv_xname); 640 break; 641 } 642 643 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 644 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 645 646 /* 647 * From this point forward, the attachment cannot fail. A failure 648 * before this point releases all resources that may have been 649 * allocated. 650 */ 651 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 652 653 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 654 htole16(sc->sc_srom[ATW_SR_MAC00]), 655 htole16(sc->sc_srom[ATW_SR_MAC01]), 656 htole16(sc->sc_srom[ATW_SR_MAC10]))); 657 658 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 659 ATW_SR_CTRY_MASK); 660 661 #define ADD_CHANNEL(_ic, _chan) do { \ 662 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 663 _ic->ic_channels[_chan].ic_freq = \ 664 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 665 } while (0) 666 667 /* Find available channels */ 668 switch (country_code) { 669 case COUNTRY_MMK2: /* 1-14 */ 670 ADD_CHANNEL(ic, 14); 671 /*FALLTHROUGH*/ 672 case COUNTRY_ETSI: /* 1-13 */ 673 for (i = 1; i <= 13; i++) 674 ADD_CHANNEL(ic, i); 675 break; 676 case COUNTRY_FCC: /* 1-11 */ 677 case COUNTRY_IC: /* 1-11 */ 678 for (i = 1; i <= 11; i++) 679 ADD_CHANNEL(ic, i); 680 break; 681 case COUNTRY_MMK: /* 14 */ 682 ADD_CHANNEL(ic, 14); 683 break; 684 case COUNTRY_FRANCE: /* 10-13 */ 685 for (i = 10; i <= 13; i++) 686 ADD_CHANNEL(ic, i); 687 break; 688 default: /* assume channels 10-11 */ 689 case COUNTRY_SPAIN: /* 10-11 */ 690 for (i = 10; i <= 11; i++) 691 ADD_CHANNEL(ic, i); 692 break; 693 } 694 695 /* Read the MAC address. */ 696 reg = ATW_READ(sc, ATW_PAR0); 697 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 698 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 699 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 700 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 701 reg = ATW_READ(sc, ATW_PAR1); 702 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 703 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 704 705 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 706 printf(" could not get mac address, attach failed\n"); 707 return; 708 } 709 710 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 711 712 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 713 ifp->if_softc = sc; 714 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 715 IFF_NOTRAILERS; 716 ifp->if_ioctl = atw_ioctl; 717 ifp->if_start = atw_start; 718 ifp->if_watchdog = atw_watchdog; 719 ifp->if_init = atw_init; 720 ifp->if_stop = atw_stop; 721 IFQ_SET_READY(&ifp->if_snd); 722 723 ic->ic_phytype = IEEE80211_T_DS; 724 ic->ic_opmode = IEEE80211_M_STA; 725 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 726 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 727 728 nrate = 0; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 730 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 731 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 734 735 /* 736 * Call MI attach routines. 737 */ 738 739 if_attach(ifp); 740 ieee80211_ifattach(ifp); 741 742 sc->sc_newstate = ic->ic_newstate; 743 ic->ic_newstate = atw_newstate; 744 745 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 746 ic->ic_recv_mgmt = atw_recv_mgmt; 747 748 sc->sc_node_free = ic->ic_node_free; 749 ic->ic_node_free = atw_node_free; 750 751 sc->sc_node_alloc = ic->ic_node_alloc; 752 ic->ic_node_alloc = atw_node_alloc; 753 754 /* possibly we should fill in our own sc_send_prresp, since 755 * the ADM8211 is probably sending probe responses in ad hoc 756 * mode. 757 */ 758 759 /* complete initialization */ 760 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 761 callout_init(&sc->sc_scan_ch); 762 763 #if NBPFILTER > 0 764 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 765 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 766 #endif 767 768 /* 769 * Make sure the interface is shutdown during reboot. 770 */ 771 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 772 if (sc->sc_sdhook == NULL) 773 printf("%s: WARNING: unable to establish shutdown hook\n", 774 sc->sc_dev.dv_xname); 775 776 /* 777 * Add a suspend hook to make sure we come back up after a 778 * resume. 779 */ 780 sc->sc_powerhook = powerhook_establish(atw_power, sc); 781 if (sc->sc_powerhook == NULL) 782 printf("%s: WARNING: unable to establish power hook\n", 783 sc->sc_dev.dv_xname); 784 785 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 786 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 787 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 788 789 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 790 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 791 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 792 793 return; 794 795 /* 796 * Free any resources we've allocated during the failed attach 797 * attempt. Do this in reverse order and fall through. 798 */ 799 fail_5: 800 for (i = 0; i < ATW_NRXDESC; i++) { 801 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 802 continue; 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 804 } 805 fail_4: 806 for (i = 0; i < ATW_TXQUEUELEN; i++) { 807 if (sc->sc_txsoft[i].txs_dmamap == NULL) 808 continue; 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 810 } 811 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 812 fail_3: 813 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 814 fail_2: 815 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 816 sizeof(struct atw_control_data)); 817 fail_1: 818 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 819 fail_0: 820 return; 821 } 822 823 static struct ieee80211_node * 824 atw_node_alloc(struct ieee80211com *ic) 825 { 826 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 827 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 828 829 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 830 return ni; 831 } 832 833 static void 834 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 835 { 836 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 837 838 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 839 ether_sprintf(ni->ni_bssid))); 840 (*sc->sc_node_free)(ic, ni); 841 } 842 843 /* 844 * atw_reset: 845 * 846 * Perform a soft reset on the ADM8211. 847 */ 848 void 849 atw_reset(struct atw_softc *sc) 850 { 851 int i; 852 853 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 854 855 for (i = 0; i < 10000; i++) { 856 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 857 break; 858 DELAY(1); 859 } 860 861 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 862 863 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 864 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 865 866 /* Turn off maximum power saving. */ 867 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 868 869 /* Recall EEPROM. */ 870 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 871 872 DELAY(10 * 1000); 873 874 /* A reset seems to affect the SRAM contents, so put them into 875 * a known state. 876 */ 877 atw_clear_sram(sc); 878 879 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 880 881 sc->sc_lost_bcn_thresh = 0; 882 } 883 884 static void 885 atw_clear_sram(struct atw_softc *sc) 886 { 887 #if 0 888 for (addr = 0; addr < 448; addr++) { 889 ATW_WRITE(sc, ATW_WEPCTL, 890 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 891 DELAY(1000); 892 ATW_WRITE(sc, ATW_WESK, 0); 893 DELAY(1000); /* paranoia */ 894 } 895 return; 896 #endif 897 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 898 /* XXX not for revision 0x20. */ 899 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 900 } 901 902 /* TBD atw_init 903 * 904 * set MAC based on ic->ic_bss->myaddr 905 * write WEP keys 906 * set TX rate 907 */ 908 909 /* 910 * atw_init: [ ifnet interface function ] 911 * 912 * Initialize the interface. Must be called at splnet(). 913 */ 914 int 915 atw_init(struct ifnet *ifp) 916 { 917 struct atw_softc *sc = ifp->if_softc; 918 struct ieee80211com *ic = &sc->sc_ic; 919 struct atw_txsoft *txs; 920 struct atw_rxsoft *rxs; 921 u_int32_t reg; 922 int i, error = 0; 923 924 if ((error = atw_enable(sc)) != 0) 925 goto out; 926 927 /* 928 * Cancel any pending I/O. This also resets. 929 */ 930 atw_stop(ifp, 0); 931 932 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 933 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 934 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 935 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 936 937 /* Turn off APM??? (A binary-only driver does this.) 938 * 939 * Set Rx store-and-forward mode. 940 */ 941 reg = ATW_READ(sc, ATW_CMDR); 942 reg &= ~ATW_CMDR_APM; 943 reg &= ~ATW_CMDR_DRT_MASK; 944 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 945 946 ATW_WRITE(sc, ATW_CMDR, reg); 947 948 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 949 * 950 * XXX a binary-only driver sets a different service field than 951 * 0. why? 952 */ 953 reg = ATW_READ(sc, ATW_PLCPHD); 954 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 955 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 956 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 957 ATW_WRITE(sc, ATW_PLCPHD, reg); 958 959 /* XXX this magic can probably be figured out from the RFMD docs */ 960 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 961 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 962 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 963 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 964 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 965 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 966 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 967 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 968 ATW_WRITE(sc, ATW_TOFS2, reg); 969 970 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 971 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 972 973 /* XXX this resets an Intersil RF front-end? */ 974 /* TBD condition on Intersil RFType? */ 975 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 976 DELAY(10 * 1000); 977 ATW_WRITE(sc, ATW_SYNRF, 0); 978 DELAY(5 * 1000); 979 980 /* 16 TU max duration for contention-free period */ 981 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 982 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 983 984 /* XXX I guess that the Cardbus clock is 22MHz? 985 * I am assuming that the role of ATW_TOFS0_USCNT is 986 * to divide the bus clock to get a 1MHz clock---the datasheet is not 987 * very clear on this point. It says in the datasheet that it is 988 * possible for the ADM8211 to accomodate bus speeds between 22MHz 989 * and 33MHz; maybe this is the way? I see a binary-only driver write 990 * these values. These values are also the power-on default. 991 */ 992 ATW_WRITE(sc, ATW_TOFS0, 993 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 994 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 995 996 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 997 * driver. Go figure. 998 */ 999 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1000 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1001 ATW_IFST_SIFS_MASK) | 1002 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1003 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1004 1005 ATW_WRITE(sc, ATW_IFST, reg); 1006 1007 /* XXX More magic. Might relate to ACK timing. */ 1008 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1009 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1010 1011 /* Set up the MMI read/write addresses for the BBP. 1012 * 1013 * TBD find out the Marvel settings. 1014 */ 1015 switch (sc->sc_bbptype) { 1016 case ATW_BBPTYPE_INTERSIL: 1017 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1018 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1019 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1020 break; 1021 case ATW_BBPTYPE_MARVEL: 1022 break; 1023 case ATW_BBPTYPE_RFMD: 1024 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1025 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1026 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1027 default: 1028 break; 1029 } 1030 1031 sc->sc_wepctl = 0; 1032 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1033 1034 if ((error = atw_rf3000_init(sc)) != 0) 1035 goto out; 1036 1037 /* 1038 * Initialize the PCI Access Register. 1039 */ 1040 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1041 1042 /* 1043 * If we're allowed to do so, use Memory Read Line 1044 * and Memory Read Multiple. 1045 * 1046 * XXX Should we use Memory Write and Invalidate? 1047 */ 1048 if (sc->sc_flags & ATWF_MRL) 1049 sc->sc_busmode |= ATW_PAR_MRLE; 1050 if (sc->sc_flags & ATWF_MRM) 1051 sc->sc_busmode |= ATW_PAR_MRME; 1052 if (sc->sc_flags & ATWF_MWI) 1053 sc->sc_busmode |= ATW_PAR_MWIE; 1054 if (sc->sc_maxburst == 0) 1055 sc->sc_maxburst = 8; /* ADM8211 default */ 1056 1057 switch (sc->sc_cacheline) { 1058 default: 1059 /* Use burst length. */ 1060 break; 1061 case 8: 1062 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1063 break; 1064 case 16: 1065 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1066 break; 1067 case 32: 1068 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1069 break; 1070 } 1071 switch (sc->sc_maxburst) { 1072 case 1: 1073 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1074 break; 1075 case 2: 1076 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1077 break; 1078 case 4: 1079 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1080 break; 1081 case 8: 1082 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1083 break; 1084 case 16: 1085 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1086 break; 1087 case 32: 1088 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1089 break; 1090 default: 1091 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1092 break; 1093 } 1094 1095 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1096 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1097 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1098 1099 /* 1100 * Initialize the OPMODE register. We don't write it until 1101 * we're ready to begin the transmit and receive processes. 1102 */ 1103 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1104 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1105 1106 /* 1107 * Initialize the transmit descriptor ring. 1108 */ 1109 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1110 for (i = 0; i < ATW_NTXDESC; i++) { 1111 /* no transmit chaining */ 1112 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1113 sc->sc_txdescs[i].at_buf2 = 1114 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1115 } 1116 /* use ring mode */ 1117 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1118 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1119 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1120 sc->sc_txfree = ATW_NTXDESC; 1121 sc->sc_txnext = 0; 1122 1123 /* 1124 * Initialize the transmit job descriptors. 1125 */ 1126 SIMPLEQ_INIT(&sc->sc_txfreeq); 1127 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1128 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1129 txs = &sc->sc_txsoft[i]; 1130 txs->txs_mbuf = NULL; 1131 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1132 } 1133 1134 /* 1135 * Initialize the receive descriptor and receive job 1136 * descriptor rings. 1137 */ 1138 for (i = 0; i < ATW_NRXDESC; i++) { 1139 rxs = &sc->sc_rxsoft[i]; 1140 if (rxs->rxs_mbuf == NULL) { 1141 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1142 printf("%s: unable to allocate or map rx " 1143 "buffer %d, error = %d\n", 1144 sc->sc_dev.dv_xname, i, error); 1145 /* 1146 * XXX Should attempt to run with fewer receive 1147 * XXX buffers instead of just failing. 1148 */ 1149 atw_rxdrain(sc); 1150 goto out; 1151 } 1152 } else 1153 ATW_INIT_RXDESC(sc, i); 1154 } 1155 sc->sc_rxptr = 0; 1156 1157 /* disable all wake-up events */ 1158 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1159 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1160 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1161 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1162 1163 /* ack all wake-up events */ 1164 ATW_SET(sc, ATW_WCSR, 0); 1165 1166 /* 1167 * Initialize the interrupt mask and enable interrupts. 1168 */ 1169 /* normal interrupts */ 1170 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1171 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1172 1173 /* abnormal interrupts */ 1174 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1175 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1176 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1177 1178 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1179 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1180 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1181 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1182 ATW_INTR_TRT; 1183 1184 sc->sc_linkint_mask &= sc->sc_inten; 1185 sc->sc_rxint_mask &= sc->sc_inten; 1186 sc->sc_txint_mask &= sc->sc_inten; 1187 1188 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1189 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1190 if (sc->sc_intr_ack != NULL) 1191 (*sc->sc_intr_ack)(sc); 1192 1193 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1194 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1195 1196 /* 1197 * Give the transmit and receive rings to the ADM8211. 1198 */ 1199 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1200 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1201 1202 /* common 802.11 configuration */ 1203 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1204 switch (ic->ic_opmode) { 1205 case IEEE80211_M_STA: 1206 sc->sc_opmode &= ~ATW_NAR_EA; 1207 break; 1208 case IEEE80211_M_AHDEMO: /* XXX */ 1209 case IEEE80211_M_IBSS: 1210 ic->ic_flags |= IEEE80211_F_IBSSON; 1211 /*FALLTHROUGH*/ 1212 case IEEE80211_M_HOSTAP: /* XXX */ 1213 /* EA bit seems important for ad hoc reception. */ 1214 sc->sc_opmode |= ATW_NAR_EA; 1215 break; 1216 case IEEE80211_M_MONITOR: /* XXX */ 1217 break; 1218 } 1219 1220 atw_start_beacon(sc, 0); 1221 1222 switch (ic->ic_opmode) { 1223 case IEEE80211_M_AHDEMO: 1224 case IEEE80211_M_HOSTAP: 1225 ic->ic_bss->ni_intval = ic->ic_lintval; 1226 ic->ic_bss->ni_rssi = 0; 1227 ic->ic_bss->ni_rstamp = 0; 1228 break; 1229 default: /* XXX */ 1230 break; 1231 } 1232 1233 atw_write_ssid(sc); 1234 atw_write_sup_rates(sc); 1235 if (ic->ic_caps & IEEE80211_C_WEP) 1236 atw_write_wep(sc); 1237 1238 /* 1239 * Set the receive filter. This will start the transmit and 1240 * receive processes. 1241 */ 1242 atw_filter_setup(sc); 1243 1244 /* 1245 * Start the receive process. 1246 */ 1247 ATW_WRITE(sc, ATW_RDR, 0x1); 1248 1249 /* 1250 * Note that the interface is now running. 1251 */ 1252 ifp->if_flags |= IFF_RUNNING; 1253 ifp->if_flags &= ~IFF_OACTIVE; 1254 ic->ic_state = IEEE80211_S_INIT; 1255 1256 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1257 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1258 else 1259 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1260 out: 1261 if (error) { 1262 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1263 ifp->if_timer = 0; 1264 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1265 } 1266 #ifdef ATW_DEBUG 1267 atw_print_regs(sc, "end of init"); 1268 #endif /* ATW_DEBUG */ 1269 1270 return (error); 1271 } 1272 1273 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1274 * 0: MAC control of RF3000/Si4126. 1275 * 1276 * Applies power, or selects RF front-end? Sets reset condition. 1277 * 1278 * TBD support non-RFMD BBP, non-SiLabs synth. 1279 */ 1280 static void 1281 atw_rfio_enable(struct atw_softc *sc, int enable) 1282 { 1283 if (enable) { 1284 ATW_WRITE(sc, ATW_SYNRF, 1285 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1286 DELAY(atw_rfio_enable_delay); 1287 } else { 1288 ATW_WRITE(sc, ATW_SYNRF, 0); 1289 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1290 } 1291 } 1292 1293 static int 1294 atw_tune(struct atw_softc *sc) 1295 { 1296 int rc; 1297 u_int32_t reg; 1298 int chan; 1299 struct ieee80211com *ic = &sc->sc_ic; 1300 1301 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1302 if (chan == IEEE80211_CHAN_ANY) 1303 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1304 1305 if (chan == sc->sc_cur_chan) 1306 return 0; 1307 1308 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1309 sc->sc_cur_chan, chan)); 1310 1311 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1312 1313 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1314 (rc = atw_rf3000_tune(sc, chan)) != 0) 1315 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1316 chan); 1317 1318 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1319 ATW_WRITE(sc, ATW_CAP0, 1320 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1321 1322 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1323 1324 if (rc == 0) 1325 sc->sc_cur_chan = chan; 1326 1327 return rc; 1328 } 1329 1330 #ifdef ATW_DEBUG 1331 static void 1332 atw_si4126_print(struct atw_softc *sc) 1333 { 1334 struct ifnet *ifp = &sc->sc_ic.ic_if; 1335 u_int addr, val; 1336 1337 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1338 return; 1339 1340 for (addr = 0; addr <= 8; addr++) { 1341 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1342 if (atw_si4126_read(sc, addr, &val) == 0) { 1343 printf("<unknown> (quitting print-out)\n"); 1344 break; 1345 } 1346 printf("%05x\n", val); 1347 } 1348 } 1349 #endif /* ATW_DEBUG */ 1350 1351 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1352 * 1353 * The RF/IF synthesizer produces two reference frequencies for 1354 * the RF2948B transceiver. The first frequency the RF2948B requires 1355 * is two times the so-called "intermediate frequency" (IF). Since 1356 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1357 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1358 * frequency required by the transceiver is the radio frequency 1359 * (RF). This is a superheterodyne transceiver; for f(chan) the 1360 * center frequency of the channel we are tuning, RF = f(chan) - 1361 * IF. 1362 * 1363 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1364 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1365 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1366 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1367 */ 1368 static int 1369 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1370 { 1371 int rc = 0; 1372 u_int mhz; 1373 u_int R; 1374 u_int32_t reg; 1375 u_int16_t gain; 1376 1377 #ifdef ATW_DEBUG 1378 atw_si4126_print(sc); 1379 #endif /* ATW_DEBUG */ 1380 1381 if (chan == 14) 1382 mhz = 2484; 1383 else 1384 mhz = 2412 + 5 * (chan - 1); 1385 1386 /* Tune IF to 748MHz to suit the IF LO input of the 1387 * RF2494B, which is 2 x IF. No need to set an IF divider 1388 * because an IF in 526MHz - 952MHz is allowed. 1389 * 1390 * XIN is 44.000MHz, so divide it by two to get allowable 1391 * range of 2-25MHz. SiLabs tells me that this is not 1392 * strictly necessary. 1393 */ 1394 1395 R = 44; 1396 1397 atw_rfio_enable(sc, 1); 1398 1399 /* Power-up RF, IF synthesizers. */ 1400 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1401 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1402 goto out; 1403 1404 /* If RF2 N > 2047, then set KP2 to 1. */ 1405 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1406 1407 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1408 goto out; 1409 1410 /* set LPWR, too? */ 1411 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1412 SI4126_MAIN_XINDIV2)) != 0) 1413 goto out; 1414 1415 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1416 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1417 */ 1418 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1419 goto out; 1420 1421 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1422 goto out; 1423 1424 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1425 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1426 * which has no RF1! 1427 */ 1428 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1429 goto out; 1430 1431 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1432 goto out; 1433 1434 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1435 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1436 * Now let's multiply it to mhz. So mhz - IF = N. 1437 */ 1438 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1439 goto out; 1440 1441 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1442 goto out; 1443 1444 /* wait 100us from power-up for RF, IF to settle */ 1445 DELAY(100); 1446 1447 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1448 /* XXX there is a binary driver which sends 1449 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1450 * that this enables the Si4126 by raising its PWDN#, but I 1451 * think that it actually sets the Prism RF front-end 1452 * to a special mode for channel 14. 1453 */ 1454 reg = ATW_READ(sc, ATW_GPIO); 1455 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1456 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1457 ATW_WRITE(sc, ATW_GPIO, reg); 1458 } 1459 1460 #ifdef ATW_DEBUG 1461 atw_si4126_print(sc); 1462 #endif /* ATW_DEBUG */ 1463 1464 out: 1465 atw_rfio_enable(sc, 0); 1466 1467 return rc; 1468 } 1469 1470 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1471 * diversity. 1472 * 1473 * Call this w/ Tx/Rx suspended. 1474 */ 1475 static int 1476 atw_rf3000_init(struct atw_softc *sc) 1477 { 1478 int rc = 0; 1479 1480 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1481 1482 atw_rfio_enable(sc, 1); 1483 1484 /* enable diversity */ 1485 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1486 1487 if (rc != 0) 1488 goto out; 1489 1490 /* sensible setting from a binary-only driver */ 1491 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1492 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1493 1494 if (rc != 0) 1495 goto out; 1496 1497 /* magic from a binary-only driver */ 1498 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1499 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1500 1501 if (rc != 0) 1502 goto out; 1503 1504 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1505 1506 if (rc != 0) 1507 goto out; 1508 1509 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1510 1511 if (rc != 0) 1512 goto out; 1513 1514 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1515 1516 if (rc != 0) 1517 goto out; 1518 1519 /* CCA is acquisition sensitive */ 1520 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1521 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1522 1523 if (rc != 0) 1524 goto out; 1525 1526 out: 1527 atw_rfio_enable(sc, 0); 1528 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1529 return rc; 1530 } 1531 1532 #ifdef ATW_DEBUG 1533 static void 1534 atw_rf3000_print(struct atw_softc *sc) 1535 { 1536 struct ifnet *ifp = &sc->sc_ic.ic_if; 1537 u_int addr, val; 1538 1539 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1540 return; 1541 1542 for (addr = 0x01; addr <= 0x15; addr++) { 1543 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1544 if (atw_rf3000_read(sc, addr, &val) != 0) { 1545 printf("<unknown> (quitting print-out)\n"); 1546 break; 1547 } 1548 printf("%08x\n", val); 1549 } 1550 } 1551 #endif /* ATW_DEBUG */ 1552 1553 /* Set the power settings on the BBP for channel `chan'. */ 1554 static int 1555 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1556 { 1557 int rc = 0; 1558 u_int32_t reg; 1559 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1560 1561 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1562 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1563 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1564 1565 /* odd channels: LSB, even channels: MSB */ 1566 if (chan % 2 == 1) { 1567 txpower &= 0xFF; 1568 lpf_cutoff &= 0xFF; 1569 lna_gs_thresh &= 0xFF; 1570 } else { 1571 txpower >>= 8; 1572 lpf_cutoff >>= 8; 1573 lna_gs_thresh >>= 8; 1574 } 1575 1576 #ifdef ATW_DEBUG 1577 atw_rf3000_print(sc); 1578 #endif /* ATW_DEBUG */ 1579 1580 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1581 "lna_gs_thresh %02x\n", 1582 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1583 1584 atw_rfio_enable(sc, 1); 1585 1586 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1587 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1588 goto out; 1589 1590 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1591 goto out; 1592 1593 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1594 goto out; 1595 1596 /* from a binary-only driver. */ 1597 reg = ATW_READ(sc, ATW_PLCPHD); 1598 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1599 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1600 ATW_PLCPHD_SERVICE_MASK); 1601 ATW_WRITE(sc, ATW_PLCPHD, reg); 1602 1603 #ifdef ATW_DEBUG 1604 atw_rf3000_print(sc); 1605 #endif /* ATW_DEBUG */ 1606 1607 out: 1608 atw_rfio_enable(sc, 0); 1609 1610 return rc; 1611 } 1612 1613 /* Write a register on the RF3000 baseband processor using the 1614 * registers provided by the ADM8211 for this purpose. 1615 * 1616 * Return 0 on success. 1617 */ 1618 static int 1619 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1620 { 1621 u_int32_t reg; 1622 int i; 1623 1624 for (i = 1000; --i >= 0; ) { 1625 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1626 break; 1627 DELAY(100); 1628 } 1629 1630 if (i < 0) { 1631 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1632 return ETIMEDOUT; 1633 } 1634 1635 reg = sc->sc_bbpctl_wr | 1636 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1637 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1638 1639 ATW_WRITE(sc, ATW_BBPCTL, reg); 1640 1641 for (i = 1000; --i >= 0; ) { 1642 DELAY(100); 1643 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1644 break; 1645 } 1646 1647 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1648 1649 if (i < 0) { 1650 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1651 return ETIMEDOUT; 1652 } 1653 return 0; 1654 } 1655 1656 /* Read a register on the RF3000 baseband processor using the registers 1657 * the ADM8211 provides for this purpose. 1658 * 1659 * The 7-bit register address is addr. Record the 8-bit data in the register 1660 * in *val. 1661 * 1662 * Return 0 on success. 1663 * 1664 * XXX This does not seem to work. The ADM8211 must require more or 1665 * different magic to read the chip than to write it. Possibly some 1666 * of the magic I have derived from a binary-only driver concerns 1667 * the "chip address" (see the RF3000 manual). 1668 */ 1669 #ifdef ATW_DEBUG 1670 static int 1671 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1672 { 1673 u_int32_t reg; 1674 int i; 1675 1676 for (i = 1000; --i >= 0; ) { 1677 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1678 break; 1679 DELAY(100); 1680 } 1681 1682 if (i < 0) { 1683 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1684 sc->sc_dev.dv_xname); 1685 return ETIMEDOUT; 1686 } 1687 1688 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1689 1690 ATW_WRITE(sc, ATW_BBPCTL, reg); 1691 1692 for (i = 1000; --i >= 0; ) { 1693 DELAY(100); 1694 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1695 break; 1696 } 1697 1698 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1699 1700 if (i < 0) { 1701 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1702 sc->sc_dev.dv_xname, reg); 1703 return ETIMEDOUT; 1704 } 1705 if (val != NULL) 1706 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1707 return 0; 1708 } 1709 #endif /* ATW_DEBUG */ 1710 1711 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1712 * provided by the ADM8211 for that purpose. 1713 * 1714 * val is 18 bits of data, and val is the 4-bit address of the register. 1715 * 1716 * Return 0 on success. 1717 */ 1718 static int 1719 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1720 { 1721 u_int32_t bits, reg; 1722 int i; 1723 1724 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1725 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1726 1727 for (i = 1000; --i >= 0; ) { 1728 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1729 break; 1730 DELAY(100); 1731 } 1732 1733 if (i < 0) { 1734 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1735 sc->sc_dev.dv_xname); 1736 return ETIMEDOUT; 1737 } 1738 1739 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1740 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1741 1742 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1743 1744 ATW_WRITE(sc, ATW_SYNCTL, reg); 1745 1746 for (i = 1000; --i >= 0; ) { 1747 DELAY(100); 1748 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1749 break; 1750 } 1751 1752 /* restore to acceptable starting condition */ 1753 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1754 1755 if (i < 0) { 1756 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1757 sc->sc_dev.dv_xname, reg); 1758 return ETIMEDOUT; 1759 } 1760 return 0; 1761 } 1762 1763 /* Read 18-bit data from the 4-bit address addr in Si4126 1764 * RF synthesizer and write the data to *val. Return 0 on success. 1765 * 1766 * XXX This does not seem to work. The ADM8211 must require more or 1767 * different magic to read the chip than to write it. 1768 */ 1769 #ifdef ATW_DEBUG 1770 static int 1771 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1772 { 1773 u_int32_t reg; 1774 int i; 1775 1776 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1777 1778 for (i = 1000; --i >= 0; ) { 1779 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1780 break; 1781 DELAY(100); 1782 } 1783 1784 if (i < 0) { 1785 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1786 sc->sc_dev.dv_xname); 1787 return ETIMEDOUT; 1788 } 1789 1790 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1791 1792 ATW_WRITE(sc, ATW_SYNCTL, reg); 1793 1794 for (i = 1000; --i >= 0; ) { 1795 DELAY(100); 1796 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1797 break; 1798 } 1799 1800 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1801 1802 if (i < 0) { 1803 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1804 sc->sc_dev.dv_xname, reg); 1805 return ETIMEDOUT; 1806 } 1807 if (val != NULL) 1808 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1809 ATW_SYNCTL_DATA_MASK); 1810 return 0; 1811 } 1812 #endif /* ATW_DEBUG */ 1813 1814 /* XXX is the endianness correct? test. */ 1815 #define atw_calchash(addr) \ 1816 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1817 1818 /* 1819 * atw_filter_setup: 1820 * 1821 * Set the ADM8211's receive filter. 1822 */ 1823 static void 1824 atw_filter_setup(struct atw_softc *sc) 1825 { 1826 struct ieee80211com *ic = &sc->sc_ic; 1827 struct ethercom *ec = &ic->ic_ec; 1828 struct ifnet *ifp = &sc->sc_ic.ic_if; 1829 int hash; 1830 u_int32_t hashes[2] = { 0, 0 }; 1831 struct ether_multi *enm; 1832 struct ether_multistep step; 1833 1834 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1835 sc->sc_dev.dv_xname, sc->sc_flags)); 1836 1837 /* 1838 * If we're running, idle the receive engine. If we're NOT running, 1839 * we're being called from atw_init(), and our writing ATW_NAR will 1840 * start the transmit and receive processes in motion. 1841 */ 1842 if (ifp->if_flags & IFF_RUNNING) 1843 atw_idle(sc, ATW_NAR_SR); 1844 1845 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1846 1847 ifp->if_flags &= ~IFF_ALLMULTI; 1848 1849 if (ifp->if_flags & IFF_PROMISC) { 1850 sc->sc_opmode |= ATW_NAR_PR; 1851 allmulti: 1852 ifp->if_flags |= IFF_ALLMULTI; 1853 goto setit; 1854 } 1855 1856 /* 1857 * Program the 64-bit multicast hash filter. 1858 */ 1859 ETHER_FIRST_MULTI(step, ec, enm); 1860 while (enm != NULL) { 1861 /* XXX */ 1862 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1863 ETHER_ADDR_LEN) != 0) 1864 goto allmulti; 1865 1866 hash = atw_calchash(enm->enm_addrlo); 1867 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1868 ETHER_NEXT_MULTI(step, enm); 1869 } 1870 1871 if (ifp->if_flags & IFF_BROADCAST) { 1872 hash = atw_calchash(etherbroadcastaddr); 1873 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1874 } 1875 1876 /* all bits set => hash is useless */ 1877 if (~(hashes[0] & hashes[1]) == 0) 1878 goto allmulti; 1879 1880 setit: 1881 if (ifp->if_flags & IFF_ALLMULTI) 1882 sc->sc_opmode |= ATW_NAR_MM; 1883 1884 /* XXX in scan mode, do not filter packets. maybe this is 1885 * unnecessary. 1886 */ 1887 if (ic->ic_state == IEEE80211_S_SCAN) 1888 sc->sc_opmode |= ATW_NAR_PR; 1889 1890 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1891 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1892 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1893 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1894 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1895 1896 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1897 } 1898 1899 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1900 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1901 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1902 * no beacon with the preferred BSSID and SSID in the number of 1903 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1904 */ 1905 static void 1906 atw_write_bssid(struct atw_softc *sc) 1907 { 1908 struct ieee80211com *ic = &sc->sc_ic; 1909 u_int8_t *bssid; 1910 1911 bssid = ic->ic_bss->ni_bssid; 1912 1913 ATW_WRITE(sc, ATW_ABDA1, 1914 (ATW_READ(sc, ATW_ABDA1) & 1915 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1916 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1917 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1918 1919 ATW_WRITE(sc, ATW_BSSID0, 1920 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1921 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1922 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1923 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1924 1925 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1926 ether_sprintf(sc->sc_bssid))); 1927 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1928 1929 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1930 } 1931 1932 /* Tell the ADM8211 how many beacon intervals must pass without 1933 * receiving a beacon with the preferred BSSID & SSID set by 1934 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1935 * raised. 1936 */ 1937 static void 1938 atw_write_bcn_thresh(struct atw_softc *sc) 1939 { 1940 struct ieee80211com *ic = &sc->sc_ic; 1941 int lost_bcn_thresh; 1942 1943 /* Lose link after one second or 7 beacons, whichever comes 1944 * first, but do not lose link before 2 beacons are lost. 1945 * 1946 * In host AP mode, set the lost-beacon threshold to 0. 1947 */ 1948 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1949 lost_bcn_thresh = 0; 1950 else { 1951 int beacons_per_second = 1952 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1953 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1954 } 1955 1956 /* XXX resets wake-up status bits */ 1957 ATW_WRITE(sc, ATW_WCSR, 1958 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1959 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1960 1961 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1962 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1963 1964 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1965 1966 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1967 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1968 } 1969 1970 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1971 * 16-bit word. 1972 */ 1973 static void 1974 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1975 { 1976 u_int i; 1977 u_int8_t *ptr; 1978 1979 memcpy(&sc->sc_sram[ofs], buf, buflen); 1980 1981 if (ofs % 2 != 0) { 1982 ofs--; 1983 buflen++; 1984 } 1985 1986 if (buflen % 2 != 0) 1987 buflen++; 1988 1989 assert(buflen + ofs <= ATW_SRAM_SIZE); 1990 1991 ptr = &sc->sc_sram[ofs]; 1992 1993 for (i = 0; i < buflen; i += 2) { 1994 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1995 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1996 DELAY(atw_writewep_delay); 1997 1998 ATW_WRITE(sc, ATW_WESK, 1999 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2000 DELAY(atw_writewep_delay); 2001 } 2002 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2003 2004 if (sc->sc_if.if_flags & IFF_DEBUG) { 2005 int n_octets = 0; 2006 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2007 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2008 for (i = 0; i < buflen; i++) { 2009 printf(" %02x", ptr[i]); 2010 if (++n_octets % 24 == 0) 2011 printf("\n"); 2012 } 2013 if (n_octets % 24 != 0) 2014 printf("\n"); 2015 } 2016 } 2017 2018 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2019 static void 2020 atw_write_wep(struct atw_softc *sc) 2021 { 2022 struct ieee80211com *ic = &sc->sc_ic; 2023 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2024 u_int8_t buf[IEEE80211_WEP_NKID] 2025 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2026 u_int32_t reg; 2027 int i; 2028 2029 sc->sc_wepctl = 0; 2030 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2031 2032 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2033 return; 2034 2035 memset(&buf[0][0], 0, sizeof(buf)); 2036 2037 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2038 if (ic->ic_nw_keys[i].wk_len > 5) { 2039 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2040 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2041 buf[i][1] = ATW_WEP_ENABLED; 2042 } else { 2043 buf[i][1] = 0; 2044 continue; 2045 } 2046 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2047 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2048 ic->ic_nw_keys[i].wk_len - 1); 2049 } 2050 2051 reg = ATW_READ(sc, ATW_MACTEST); 2052 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2053 reg &= ~ATW_MACTEST_KEYID_MASK; 2054 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2055 ATW_WRITE(sc, ATW_MACTEST, reg); 2056 2057 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2058 * throughout.) 2059 */ 2060 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2061 if (sc->sc_if.if_flags & IFF_LINK2) 2062 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2063 2064 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2065 sizeof(buf)); 2066 } 2067 2068 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2069 2070 static void 2071 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2072 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2073 { 2074 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2075 2076 switch (subtype) { 2077 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2078 /* do nothing: hardware answers probe request */ 2079 break; 2080 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2081 case IEEE80211_FC0_SUBTYPE_BEACON: 2082 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2083 break; 2084 default: 2085 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2086 break; 2087 } 2088 return; 2089 } 2090 2091 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2092 * of IBSSs with like SSID/channel but different BSSID. It joins the 2093 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2094 * convention. Possibly the ADMtek chip does this for us; I will have 2095 * to test to find out. 2096 * 2097 * XXX we should add the duration field of the received beacon to 2098 * the TSF time it contains before comparing it with the ADM8211's 2099 * TSF. 2100 */ 2101 static void 2102 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2103 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2104 { 2105 struct atw_softc *sc; 2106 struct ieee80211_frame *wh; 2107 u_int64_t tsft, bcn_tsft; 2108 u_int32_t tsftl, tsfth; 2109 int do_print = 0; 2110 2111 sc = (struct atw_softc*)ic->ic_if.if_softc; 2112 2113 if (ic->ic_if.if_flags & IFF_DEBUG) 2114 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2115 ? 1 : ratecheck(&sc->sc_last_beacon, 2116 &atw_beacon_mininterval); 2117 2118 wh = mtod(m0, struct ieee80211_frame *); 2119 2120 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2121 2122 if (ic->ic_state != IEEE80211_S_RUN) { 2123 if (do_print) 2124 printf("%s: atw_recv_beacon: not running\n", 2125 sc->sc_dev.dv_xname); 2126 return; 2127 } 2128 2129 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2130 ic->ic_bss->ni_chan)) == NULL) { 2131 if (do_print) 2132 printf("%s: atw_recv_beacon: no node %s\n", 2133 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2134 return; 2135 } 2136 2137 if (ieee80211_match_bss(ic, ni) != 0) { 2138 if (do_print) 2139 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2140 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2141 return; 2142 } 2143 2144 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2145 return; 2146 2147 if (do_print) 2148 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2149 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2150 2151 if (ic->ic_opmode != IEEE80211_M_IBSS) 2152 return; 2153 2154 /* If we read TSFTL right before rollover, we read a TSF timer 2155 * that is too high rather than too low. This prevents a spurious 2156 * synchronization down the line, however, our IBSS could suffer 2157 * from a creeping TSF.... 2158 */ 2159 tsftl = ATW_READ(sc, ATW_TSFTL); 2160 tsfth = ATW_READ(sc, ATW_TSFTH); 2161 2162 tsft = (u_int64_t)tsfth << 32 | tsftl; 2163 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2164 2165 if (do_print) 2166 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2167 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2168 2169 /* we are faster, let the other guy catch up */ 2170 if (bcn_tsft < tsft) 2171 return; 2172 2173 if (do_print) 2174 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2175 ether_sprintf(wh->i_addr2)); 2176 2177 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2178 2179 #if 0 2180 atw_tsf(sc); 2181 #endif 2182 2183 /* negotiate rates with new IBSS */ 2184 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2185 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2186 if (ni->ni_rates.rs_nrates == 0) { 2187 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2188 ether_sprintf(ni->ni_bssid)); 2189 return; 2190 } 2191 2192 if (do_print) { 2193 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2194 ether_sprintf(ic->ic_bss->ni_bssid)); 2195 printf("%s ", ether_sprintf(ni->ni_bssid)); 2196 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2197 } 2198 2199 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2200 2201 atw_write_bssid(sc); 2202 atw_write_bcn_thresh(sc); 2203 atw_start_beacon(sc, 1); 2204 } 2205 2206 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2207 * In ad hoc mode, the SSID is written to the beacons sent by the 2208 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2209 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2210 * indications. 2211 */ 2212 static void 2213 atw_write_ssid(struct atw_softc *sc) 2214 { 2215 struct ieee80211com *ic = &sc->sc_ic; 2216 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2217 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2218 2219 memset(buf, 0, sizeof(buf)); 2220 buf[0] = ic->ic_bss->ni_esslen; 2221 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2222 2223 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2224 } 2225 2226 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2227 * In ad hoc mode, the supported rates are written to beacons sent by the 2228 * ADM8211. 2229 */ 2230 static void 2231 atw_write_sup_rates(struct atw_softc *sc) 2232 { 2233 struct ieee80211com *ic = &sc->sc_ic; 2234 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2235 * supported rates 2236 */ 2237 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2238 2239 memset(buf, 0, sizeof(buf)); 2240 2241 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2242 2243 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2244 ic->ic_bss->ni_rates.rs_nrates); 2245 2246 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2247 } 2248 2249 /* Start/stop sending beacons. */ 2250 void 2251 atw_start_beacon(struct atw_softc *sc, int start) 2252 { 2253 struct ieee80211com *ic = &sc->sc_ic; 2254 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2255 2256 if (ATW_IS_ENABLED(sc) == 0) 2257 return; 2258 2259 len = capinfo = 0; 2260 2261 /* start beacons */ 2262 len = sizeof(struct ieee80211_frame) + 2263 8 /* timestamp */ + 2 /* beacon interval */ + 2264 2 /* capability info */ + 2265 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2266 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2267 3 /* DS parameters */ + 2268 IEEE80211_CRC_LEN; 2269 2270 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2271 2272 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2273 2274 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2275 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2276 2277 if (!start) 2278 return; 2279 2280 /* TBD use ni_capinfo */ 2281 2282 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2283 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2284 if (ic->ic_flags & IEEE80211_F_WEPON) 2285 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2286 2287 switch (ic->ic_opmode) { 2288 case IEEE80211_M_IBSS: 2289 len += 4; /* IBSS parameters */ 2290 capinfo |= IEEE80211_CAPINFO_IBSS; 2291 break; 2292 case IEEE80211_M_HOSTAP: 2293 /* XXX 6-byte minimum TIM */ 2294 len += atw_beacon_len_adjust; 2295 capinfo |= IEEE80211_CAPINFO_ESS; 2296 break; 2297 default: 2298 return; 2299 } 2300 2301 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2302 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2303 2304 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2305 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2306 2307 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2308 sc->sc_dev.dv_xname, reg_bcnt)); 2309 2310 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2311 sc->sc_dev.dv_xname, reg_cap1)); 2312 } 2313 2314 /* First beacon was sent at time 0 microseconds, current time is 2315 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2316 * microseconds. Return the expected time in microseconds for the 2317 * beacon after next. 2318 */ 2319 static __inline u_int64_t 2320 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2321 { 2322 return tsft + (tbtt - tsft % tbtt); 2323 } 2324 2325 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2326 * the ieee80211com. 2327 * 2328 * Predict the next target beacon transmission time (TBTT) and 2329 * write it to the ADM8211. 2330 */ 2331 static void 2332 atw_tsf(struct atw_softc *sc) 2333 { 2334 #define TBTTOFS 20 /* TU */ 2335 2336 struct ieee80211com *ic = &sc->sc_ic; 2337 u_int64_t tsft, tbtt; 2338 2339 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2340 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2341 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2342 tsft = ATW_READ(sc, ATW_TSFTH); 2343 tsft <<= 32; 2344 tsft |= ATW_READ(sc, ATW_TSFTL); 2345 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2346 } else 2347 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2348 2349 tbtt = atw_predict_beacon(tsft, 2350 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2351 2352 /* skip one more beacon so that the TBTT cannot pass before 2353 * we've programmed it, and also so that we can subtract a 2354 * few TU so that we wake a little before TBTT. 2355 */ 2356 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2357 2358 /* wake up a little early */ 2359 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2360 2361 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2362 sc->sc_dev.dv_xname, tsft, tbtt)); 2363 2364 ATW_WRITE(sc, ATW_TOFS1, 2365 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2366 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2367 LSHIFT( 2368 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2369 ATW_TOFS1_TBTTPRE_MASK)); 2370 #undef TBTTOFS 2371 } 2372 2373 static void 2374 atw_next_scan(void *arg) 2375 { 2376 struct atw_softc *sc = arg; 2377 struct ieee80211com *ic = &sc->sc_ic; 2378 struct ifnet *ifp = &ic->ic_if; 2379 int s; 2380 2381 /* don't call atw_start w/o network interrupts blocked */ 2382 s = splnet(); 2383 if (ic->ic_state == IEEE80211_S_SCAN) 2384 ieee80211_next_scan(ifp); 2385 splx(s); 2386 } 2387 2388 /* Synchronize the hardware state with the software state. */ 2389 static int 2390 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2391 { 2392 struct ifnet *ifp = &ic->ic_if; 2393 struct atw_softc *sc = ifp->if_softc; 2394 enum ieee80211_state ostate; 2395 int error; 2396 2397 ostate = ic->ic_state; 2398 2399 if (nstate == IEEE80211_S_INIT) { 2400 callout_stop(&sc->sc_scan_ch); 2401 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2402 atw_start_beacon(sc, 0); 2403 return (*sc->sc_newstate)(ic, nstate, arg); 2404 } 2405 2406 if ((error = atw_tune(sc)) != 0) 2407 return error; 2408 2409 switch (nstate) { 2410 case IEEE80211_S_ASSOC: 2411 break; 2412 case IEEE80211_S_INIT: 2413 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2414 break; 2415 case IEEE80211_S_SCAN: 2416 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2417 atw_write_bssid(sc); 2418 2419 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2420 atw_next_scan, sc); 2421 2422 break; 2423 case IEEE80211_S_RUN: 2424 if (ic->ic_opmode == IEEE80211_M_STA) 2425 break; 2426 /*FALLTHROUGH*/ 2427 case IEEE80211_S_AUTH: 2428 atw_write_bssid(sc); 2429 atw_write_bcn_thresh(sc); 2430 atw_write_ssid(sc); 2431 atw_write_sup_rates(sc); 2432 2433 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2434 ic->ic_opmode == IEEE80211_M_MONITOR) 2435 break; 2436 2437 /* set listen interval 2438 * XXX do software units agree w/ hardware? 2439 */ 2440 ATW_WRITE(sc, ATW_BPLI, 2441 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2442 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2443 ATW_BPLI_LI_MASK)); 2444 2445 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2446 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2447 2448 atw_tsf(sc); 2449 break; 2450 } 2451 2452 if (nstate != IEEE80211_S_SCAN) 2453 callout_stop(&sc->sc_scan_ch); 2454 2455 if (nstate == IEEE80211_S_RUN && 2456 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2457 ic->ic_opmode == IEEE80211_M_IBSS)) 2458 atw_start_beacon(sc, 1); 2459 else 2460 atw_start_beacon(sc, 0); 2461 2462 return (*sc->sc_newstate)(ic, nstate, arg); 2463 } 2464 2465 /* 2466 * atw_add_rxbuf: 2467 * 2468 * Add a receive buffer to the indicated descriptor. 2469 */ 2470 int 2471 atw_add_rxbuf(struct atw_softc *sc, int idx) 2472 { 2473 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2474 struct mbuf *m; 2475 int error; 2476 2477 MGETHDR(m, M_DONTWAIT, MT_DATA); 2478 if (m == NULL) 2479 return (ENOBUFS); 2480 2481 MCLGET(m, M_DONTWAIT); 2482 if ((m->m_flags & M_EXT) == 0) { 2483 m_freem(m); 2484 return (ENOBUFS); 2485 } 2486 2487 if (rxs->rxs_mbuf != NULL) 2488 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2489 2490 rxs->rxs_mbuf = m; 2491 2492 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2493 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2494 BUS_DMA_READ|BUS_DMA_NOWAIT); 2495 if (error) { 2496 printf("%s: can't load rx DMA map %d, error = %d\n", 2497 sc->sc_dev.dv_xname, idx, error); 2498 panic("atw_add_rxbuf"); /* XXX */ 2499 } 2500 2501 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2502 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2503 2504 ATW_INIT_RXDESC(sc, idx); 2505 2506 return (0); 2507 } 2508 2509 /* 2510 * atw_stop: [ ifnet interface function ] 2511 * 2512 * Stop transmission on the interface. 2513 */ 2514 void 2515 atw_stop(struct ifnet *ifp, int disable) 2516 { 2517 struct atw_softc *sc = ifp->if_softc; 2518 struct ieee80211com *ic = &sc->sc_ic; 2519 struct atw_txsoft *txs; 2520 2521 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2522 2523 /* Disable interrupts. */ 2524 ATW_WRITE(sc, ATW_IER, 0); 2525 2526 /* Stop the transmit and receive processes. */ 2527 sc->sc_opmode = 0; 2528 ATW_WRITE(sc, ATW_NAR, 0); 2529 ATW_WRITE(sc, ATW_TDBD, 0); 2530 ATW_WRITE(sc, ATW_TDBP, 0); 2531 ATW_WRITE(sc, ATW_RDB, 0); 2532 2533 /* 2534 * Release any queued transmit buffers. 2535 */ 2536 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2537 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2538 if (txs->txs_mbuf != NULL) { 2539 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2540 m_freem(txs->txs_mbuf); 2541 txs->txs_mbuf = NULL; 2542 } 2543 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2544 } 2545 2546 if (disable) { 2547 atw_rxdrain(sc); 2548 atw_disable(sc); 2549 } 2550 2551 /* 2552 * Mark the interface down and cancel the watchdog timer. 2553 */ 2554 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2555 ifp->if_timer = 0; 2556 2557 /* XXX */ 2558 atw_reset(sc); 2559 } 2560 2561 /* 2562 * atw_rxdrain: 2563 * 2564 * Drain the receive queue. 2565 */ 2566 void 2567 atw_rxdrain(struct atw_softc *sc) 2568 { 2569 struct atw_rxsoft *rxs; 2570 int i; 2571 2572 for (i = 0; i < ATW_NRXDESC; i++) { 2573 rxs = &sc->sc_rxsoft[i]; 2574 if (rxs->rxs_mbuf == NULL) 2575 continue; 2576 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2577 m_freem(rxs->rxs_mbuf); 2578 rxs->rxs_mbuf = NULL; 2579 } 2580 } 2581 2582 /* 2583 * atw_detach: 2584 * 2585 * Detach an ADM8211 interface. 2586 */ 2587 int 2588 atw_detach(struct atw_softc *sc) 2589 { 2590 struct ifnet *ifp = &sc->sc_ic.ic_if; 2591 struct atw_rxsoft *rxs; 2592 struct atw_txsoft *txs; 2593 int i; 2594 2595 /* 2596 * Succeed now if there isn't any work to do. 2597 */ 2598 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2599 return (0); 2600 2601 ieee80211_ifdetach(ifp); 2602 if_detach(ifp); 2603 2604 for (i = 0; i < ATW_NRXDESC; i++) { 2605 rxs = &sc->sc_rxsoft[i]; 2606 if (rxs->rxs_mbuf != NULL) { 2607 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2608 m_freem(rxs->rxs_mbuf); 2609 rxs->rxs_mbuf = NULL; 2610 } 2611 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2612 } 2613 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2614 txs = &sc->sc_txsoft[i]; 2615 if (txs->txs_mbuf != NULL) { 2616 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2617 m_freem(txs->txs_mbuf); 2618 txs->txs_mbuf = NULL; 2619 } 2620 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2621 } 2622 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2623 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2624 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2625 sizeof(struct atw_control_data)); 2626 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2627 2628 shutdownhook_disestablish(sc->sc_sdhook); 2629 powerhook_disestablish(sc->sc_powerhook); 2630 2631 if (sc->sc_srom) 2632 free(sc->sc_srom, M_DEVBUF); 2633 2634 return (0); 2635 } 2636 2637 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2638 void 2639 atw_shutdown(void *arg) 2640 { 2641 struct atw_softc *sc = arg; 2642 2643 atw_stop(&sc->sc_ic.ic_if, 1); 2644 } 2645 2646 int 2647 atw_intr(void *arg) 2648 { 2649 struct atw_softc *sc = arg; 2650 struct ifnet *ifp = &sc->sc_ic.ic_if; 2651 u_int32_t status, rxstatus, txstatus, linkstatus; 2652 int handled = 0, txthresh; 2653 2654 #ifdef DEBUG 2655 if (ATW_IS_ENABLED(sc) == 0) 2656 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2657 #endif 2658 2659 /* 2660 * If the interface isn't running, the interrupt couldn't 2661 * possibly have come from us. 2662 */ 2663 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2664 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2665 return (0); 2666 2667 for (;;) { 2668 status = ATW_READ(sc, ATW_STSR); 2669 2670 if (status) 2671 ATW_WRITE(sc, ATW_STSR, status); 2672 2673 if (sc->sc_intr_ack != NULL) 2674 (*sc->sc_intr_ack)(sc); 2675 2676 #ifdef ATW_DEBUG 2677 #define PRINTINTR(flag) do { \ 2678 if ((status & flag) != 0) { \ 2679 printf("%s" #flag, delim); \ 2680 delim = ","; \ 2681 } \ 2682 } while (0) 2683 2684 if (atw_debug > 1 && status) { 2685 const char *delim = "<"; 2686 2687 printf("%s: reg[STSR] = %x", 2688 sc->sc_dev.dv_xname, status); 2689 2690 PRINTINTR(ATW_INTR_FBE); 2691 PRINTINTR(ATW_INTR_LINKOFF); 2692 PRINTINTR(ATW_INTR_LINKON); 2693 PRINTINTR(ATW_INTR_RCI); 2694 PRINTINTR(ATW_INTR_RDU); 2695 PRINTINTR(ATW_INTR_REIS); 2696 PRINTINTR(ATW_INTR_RPS); 2697 PRINTINTR(ATW_INTR_TCI); 2698 PRINTINTR(ATW_INTR_TDU); 2699 PRINTINTR(ATW_INTR_TLT); 2700 PRINTINTR(ATW_INTR_TPS); 2701 PRINTINTR(ATW_INTR_TRT); 2702 PRINTINTR(ATW_INTR_TUF); 2703 PRINTINTR(ATW_INTR_BCNTC); 2704 PRINTINTR(ATW_INTR_ATIME); 2705 PRINTINTR(ATW_INTR_TBTT); 2706 PRINTINTR(ATW_INTR_TSCZ); 2707 PRINTINTR(ATW_INTR_TSFTF); 2708 printf(">\n"); 2709 } 2710 #undef PRINTINTR 2711 #endif /* ATW_DEBUG */ 2712 2713 if ((status & sc->sc_inten) == 0) 2714 break; 2715 2716 handled = 1; 2717 2718 rxstatus = status & sc->sc_rxint_mask; 2719 txstatus = status & sc->sc_txint_mask; 2720 linkstatus = status & sc->sc_linkint_mask; 2721 2722 if (linkstatus) { 2723 atw_linkintr(sc, linkstatus); 2724 } 2725 2726 if (rxstatus) { 2727 /* Grab any new packets. */ 2728 atw_rxintr(sc); 2729 2730 if (rxstatus & ATW_INTR_RDU) { 2731 printf("%s: receive ring overrun\n", 2732 sc->sc_dev.dv_xname); 2733 /* Get the receive process going again. */ 2734 ATW_WRITE(sc, ATW_RDR, 0x1); 2735 break; 2736 } 2737 } 2738 2739 if (txstatus) { 2740 /* Sweep up transmit descriptors. */ 2741 atw_txintr(sc); 2742 2743 if (txstatus & ATW_INTR_TLT) 2744 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2745 sc->sc_dev.dv_xname)); 2746 2747 if (txstatus & ATW_INTR_TRT) 2748 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2749 sc->sc_dev.dv_xname)); 2750 2751 /* If Tx under-run, increase our transmit threshold 2752 * if another is available. 2753 */ 2754 txthresh = sc->sc_txthresh + 1; 2755 if ((txstatus & ATW_INTR_TUF) && 2756 sc->sc_txth[txthresh].txth_name != NULL) { 2757 /* Idle the transmit process. */ 2758 atw_idle(sc, ATW_NAR_ST); 2759 2760 sc->sc_txthresh = txthresh; 2761 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2762 sc->sc_opmode |= 2763 sc->sc_txth[txthresh].txth_opmode; 2764 printf("%s: transmit underrun; new " 2765 "threshold: %s\n", sc->sc_dev.dv_xname, 2766 sc->sc_txth[txthresh].txth_name); 2767 2768 /* Set the new threshold and restart 2769 * the transmit process. 2770 */ 2771 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2772 /* XXX Log every Nth underrun from 2773 * XXX now on? 2774 */ 2775 } 2776 } 2777 2778 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2779 if (status & ATW_INTR_TPS) 2780 printf("%s: transmit process stopped\n", 2781 sc->sc_dev.dv_xname); 2782 if (status & ATW_INTR_RPS) 2783 printf("%s: receive process stopped\n", 2784 sc->sc_dev.dv_xname); 2785 (void)atw_init(ifp); 2786 break; 2787 } 2788 2789 if (status & ATW_INTR_FBE) { 2790 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2791 (void)atw_init(ifp); 2792 break; 2793 } 2794 2795 /* 2796 * Not handled: 2797 * 2798 * Transmit buffer unavailable -- normal 2799 * condition, nothing to do, really. 2800 * 2801 * Early receive interrupt -- not available on 2802 * all chips, we just use RI. We also only 2803 * use single-segment receive DMA, so this 2804 * is mostly useless. 2805 * 2806 * TBD others 2807 */ 2808 } 2809 2810 /* Try to get more packets going. */ 2811 atw_start(ifp); 2812 2813 return (handled); 2814 } 2815 2816 /* 2817 * atw_idle: 2818 * 2819 * Cause the transmit and/or receive processes to go idle. 2820 * 2821 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2822 * process in STSR if I clear SR or ST after the process has already 2823 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2824 * do not seem to be too reliable. Perhaps I have the sense of the 2825 * Rx bits switched with the Tx bits? 2826 */ 2827 void 2828 atw_idle(struct atw_softc *sc, u_int32_t bits) 2829 { 2830 u_int32_t ackmask = 0, opmode, stsr, test0; 2831 int i, s; 2832 2833 /* without this, somehow we run concurrently w/ interrupt handler */ 2834 s = splnet(); 2835 2836 opmode = sc->sc_opmode & ~bits; 2837 2838 if (bits & ATW_NAR_SR) 2839 ackmask |= ATW_INTR_RPS; 2840 2841 if (bits & ATW_NAR_ST) { 2842 ackmask |= ATW_INTR_TPS; 2843 /* set ATW_NAR_HF to flush TX FIFO. */ 2844 opmode |= ATW_NAR_HF; 2845 } 2846 2847 ATW_WRITE(sc, ATW_NAR, opmode); 2848 2849 for (i = 0; i < 1000; i++) { 2850 stsr = ATW_READ(sc, ATW_STSR); 2851 if ((stsr & ackmask) == ackmask) 2852 break; 2853 DELAY(10); 2854 } 2855 2856 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2857 2858 if ((stsr & ackmask) == ackmask) 2859 goto out; 2860 2861 test0 = ATW_READ(sc, ATW_TEST0); 2862 2863 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2864 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2865 printf("%s: transmit process not idle [%s]\n", 2866 sc->sc_dev.dv_xname, 2867 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2868 printf("%s: bits %08x test0 %08x stsr %08x\n", 2869 sc->sc_dev.dv_xname, bits, test0, stsr); 2870 } 2871 2872 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2873 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2874 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2875 sc->sc_dev.dv_xname, 2876 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2877 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2878 sc->sc_dev.dv_xname, bits, test0, stsr)); 2879 } 2880 out: 2881 splx(s); 2882 return; 2883 } 2884 2885 /* 2886 * atw_linkintr: 2887 * 2888 * Helper; handle link-status interrupts. 2889 */ 2890 void 2891 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2892 { 2893 struct ieee80211com *ic = &sc->sc_ic; 2894 2895 if (ic->ic_state != IEEE80211_S_RUN) 2896 return; 2897 2898 if (linkstatus & ATW_INTR_LINKON) { 2899 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2900 sc->sc_rescan_timer = 0; 2901 } else if (linkstatus & ATW_INTR_LINKOFF) { 2902 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2903 if (ic->ic_opmode != IEEE80211_M_STA) 2904 return; 2905 sc->sc_rescan_timer = 3; 2906 ic->ic_if.if_timer = 1; 2907 } 2908 } 2909 2910 /* 2911 * atw_rxintr: 2912 * 2913 * Helper; handle receive interrupts. 2914 */ 2915 void 2916 atw_rxintr(struct atw_softc *sc) 2917 { 2918 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2919 struct ieee80211com *ic = &sc->sc_ic; 2920 struct ieee80211_node *ni; 2921 struct ieee80211_frame *wh; 2922 struct ifnet *ifp = &ic->ic_if; 2923 struct atw_rxsoft *rxs; 2924 struct mbuf *m; 2925 u_int32_t rxstat; 2926 int i, len, rate, rate0; 2927 u_int32_t rssi; 2928 2929 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2930 rxs = &sc->sc_rxsoft[i]; 2931 2932 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2933 2934 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2935 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2936 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2937 2938 if (rxstat & ATW_RXSTAT_OWN) 2939 break; /* We have processed all receive buffers. */ 2940 2941 DPRINTF3(sc, 2942 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2943 sc->sc_dev.dv_xname, 2944 sc->sc_rxdescs[i].ar_stat, 2945 sc->sc_rxdescs[i].ar_rssi, 2946 sc->sc_rxdescs[i].ar_buf1, 2947 sc->sc_rxdescs[i].ar_buf2)); 2948 2949 /* 2950 * Make sure the packet fits in one buffer. This should 2951 * always be the case. 2952 */ 2953 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2954 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2955 printf("%s: incoming packet spilled, resetting\n", 2956 sc->sc_dev.dv_xname); 2957 (void)atw_init(ifp); 2958 return; 2959 } 2960 2961 /* 2962 * If an error occurred, update stats, clear the status 2963 * word, and leave the packet buffer in place. It will 2964 * simply be reused the next time the ring comes around. 2965 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2966 * error. 2967 */ 2968 2969 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2970 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2971 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2972 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2973 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2974 ATW_RXSTAT_ICVE)) != 0)) { 2975 #define PRINTERR(bit, str) \ 2976 if (rxstat & (bit)) \ 2977 printf("%s: receive error: %s\n", \ 2978 sc->sc_dev.dv_xname, str) 2979 ifp->if_ierrors++; 2980 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2981 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2982 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2983 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2984 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2985 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2986 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2987 #undef PRINTERR 2988 ATW_INIT_RXDESC(sc, i); 2989 continue; 2990 } 2991 2992 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2993 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2994 2995 /* 2996 * No errors; receive the packet. Note the ADM8211 2997 * includes the CRC in promiscuous mode. 2998 */ 2999 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3000 3001 /* 3002 * Allocate a new mbuf cluster. If that fails, we are 3003 * out of memory, and must drop the packet and recycle 3004 * the buffer that's already attached to this descriptor. 3005 */ 3006 m = rxs->rxs_mbuf; 3007 if (atw_add_rxbuf(sc, i) != 0) { 3008 ifp->if_ierrors++; 3009 ATW_INIT_RXDESC(sc, i); 3010 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3011 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3012 continue; 3013 } 3014 3015 ifp->if_ipackets++; 3016 if (sc->sc_opmode & ATW_NAR_PR) 3017 m->m_flags |= M_HASFCS; 3018 m->m_pkthdr.rcvif = ifp; 3019 m->m_pkthdr.len = m->m_len = len; 3020 3021 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3022 rate = 0; 3023 else 3024 rate = rate_tbl[rate0]; 3025 3026 #if NBPFILTER > 0 3027 /* Pass this up to any BPF listeners. */ 3028 if (sc->sc_radiobpf != NULL) { 3029 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3030 3031 tap->ar_rate = rate; 3032 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3033 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3034 3035 /* TBD verify units are dB */ 3036 tap->ar_antsignal = (int)rssi; 3037 /* TBD tap->ar_flags */ 3038 3039 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3040 tap->ar_ihdr.it_len, m); 3041 } 3042 #endif /* NPBFILTER > 0 */ 3043 3044 wh = mtod(m, struct ieee80211_frame *); 3045 ni = ieee80211_find_rxnode(ic, wh); 3046 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3047 /* 3048 * The frame may have caused the node to be marked for 3049 * reclamation (e.g. in response to a DEAUTH message) 3050 * so use free_node here instead of unref_node. 3051 */ 3052 if (ni == ic->ic_bss) 3053 ieee80211_unref_node(&ni); 3054 else 3055 ieee80211_free_node(ic, ni); 3056 } 3057 3058 /* Update the receive pointer. */ 3059 sc->sc_rxptr = i; 3060 } 3061 3062 /* 3063 * atw_txintr: 3064 * 3065 * Helper; handle transmit interrupts. 3066 */ 3067 void 3068 atw_txintr(struct atw_softc *sc) 3069 { 3070 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3071 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3072 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3073 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3074 3075 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3076 struct ifnet *ifp = &sc->sc_ic.ic_if; 3077 struct atw_txsoft *txs; 3078 u_int32_t txstat; 3079 3080 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3081 sc->sc_dev.dv_xname, sc->sc_flags)); 3082 3083 ifp->if_flags &= ~IFF_OACTIVE; 3084 3085 /* 3086 * Go through our Tx list and free mbufs for those 3087 * frames that have been transmitted. 3088 */ 3089 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3090 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3091 txs->txs_ndescs, 3092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3093 3094 #ifdef ATW_DEBUG 3095 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3096 int i; 3097 printf(" txsoft %p transmit chain:\n", txs); 3098 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3099 printf(" descriptor %d:\n", i); 3100 printf(" at_status: 0x%08x\n", 3101 le32toh(sc->sc_txdescs[i].at_stat)); 3102 printf(" at_flags: 0x%08x\n", 3103 le32toh(sc->sc_txdescs[i].at_flags)); 3104 printf(" at_buf1: 0x%08x\n", 3105 le32toh(sc->sc_txdescs[i].at_buf1)); 3106 printf(" at_buf2: 0x%08x\n", 3107 le32toh(sc->sc_txdescs[i].at_buf2)); 3108 if (i == txs->txs_lastdesc) 3109 break; 3110 } 3111 } 3112 #endif 3113 3114 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3115 if (txstat & ATW_TXSTAT_OWN) 3116 break; 3117 3118 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3119 3120 sc->sc_txfree += txs->txs_ndescs; 3121 3122 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3123 0, txs->txs_dmamap->dm_mapsize, 3124 BUS_DMASYNC_POSTWRITE); 3125 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3126 m_freem(txs->txs_mbuf); 3127 txs->txs_mbuf = NULL; 3128 3129 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3130 3131 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3132 (txstat & TXSTAT_ERRMASK) != 0) { 3133 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3134 txstat_buf, sizeof(txstat_buf)); 3135 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3136 txstat_buf, 3137 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3138 } 3139 3140 /* 3141 * Check for errors and collisions. 3142 */ 3143 if (txstat & ATW_TXSTAT_TUF) 3144 sc->sc_stats.ts_tx_tuf++; 3145 if (txstat & ATW_TXSTAT_TLT) 3146 sc->sc_stats.ts_tx_tlt++; 3147 if (txstat & ATW_TXSTAT_TRT) 3148 sc->sc_stats.ts_tx_trt++; 3149 if (txstat & ATW_TXSTAT_TRO) 3150 sc->sc_stats.ts_tx_tro++; 3151 if (txstat & ATW_TXSTAT_SOFBR) { 3152 sc->sc_stats.ts_tx_sofbr++; 3153 } 3154 3155 if ((txstat & ATW_TXSTAT_ES) == 0) 3156 ifp->if_collisions += 3157 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3158 else 3159 ifp->if_oerrors++; 3160 3161 ifp->if_opackets++; 3162 } 3163 3164 /* 3165 * If there are no more pending transmissions, cancel the watchdog 3166 * timer. 3167 */ 3168 if (txs == NULL) 3169 sc->sc_tx_timer = 0; 3170 #undef TXSTAT_ERRMASK 3171 #undef TXSTAT_FMT 3172 } 3173 3174 /* 3175 * atw_watchdog: [ifnet interface function] 3176 * 3177 * Watchdog timer handler. 3178 */ 3179 void 3180 atw_watchdog(struct ifnet *ifp) 3181 { 3182 struct atw_softc *sc = ifp->if_softc; 3183 struct ieee80211com *ic = &sc->sc_ic; 3184 3185 ifp->if_timer = 0; 3186 if (ATW_IS_ENABLED(sc) == 0) 3187 return; 3188 3189 if (sc->sc_rescan_timer) { 3190 if (--sc->sc_rescan_timer == 0) 3191 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3192 } 3193 if (sc->sc_tx_timer) { 3194 if (--sc->sc_tx_timer == 0 && 3195 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3196 printf("%s: transmit timeout\n", ifp->if_xname); 3197 ifp->if_oerrors++; 3198 (void)atw_init(ifp); 3199 atw_start(ifp); 3200 } 3201 } 3202 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3203 ifp->if_timer = 1; 3204 ieee80211_watchdog(ifp); 3205 } 3206 3207 /* Compute the 802.11 Duration field and the PLCP Length fields for 3208 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3209 * Write the fields to the ADM8211 Tx header, frm. 3210 * 3211 * TBD use the fragmentation threshold to find the right duration for 3212 * the first & last fragments. 3213 * 3214 * TBD make certain of the duration fields applied by the ADM8211 to each 3215 * fragment. I think that the ADM8211 knows how to subtract the CTS 3216 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3217 * I also think that the ADM8211 does *some* arithmetic for us, because 3218 * otherwise I think we would have to set a first duration for CTS/first 3219 * fragment, a second duration for fragments between the first and the 3220 * last, and a third duration for the last fragment. 3221 * 3222 * TBD make certain that duration fields reflect addition of FCS/WEP 3223 * and correct duration arithmetic as necessary. 3224 */ 3225 static void 3226 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3227 int len) 3228 { 3229 int remainder; 3230 3231 /* deal also with encrypted fragments */ 3232 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3233 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3234 sc->sc_dev.dv_xname)); 3235 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3236 IEEE80211_WEP_CRCLEN; 3237 } 3238 3239 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3240 * duration (XXX added by MAC?). 3241 */ 3242 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3243 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3244 3245 if (rate <= 4) 3246 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3247 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3248 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3249 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3250 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3251 else 3252 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3253 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3254 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3255 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3256 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3257 3258 /* lengthen duration if long preamble */ 3259 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3260 frm->atw_head_dur += 3261 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3262 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3263 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3264 IEEE80211_DUR_DS_FAST_PLCPHDR); 3265 3266 if (remainder != 0) 3267 frm->atw_head_dur++; 3268 3269 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3270 (rate == 2 || rate == 4)) { 3271 /* derived from Linux: how could this be right? */ 3272 frm->atw_head_plcplen = frm->atw_head_dur; 3273 } else { 3274 frm->atw_head_plcplen = (16 * len) / rate; 3275 remainder = (80 * len) % (rate * 5); 3276 3277 if (remainder != 0) { 3278 frm->atw_head_plcplen++; 3279 3280 /* XXX magic */ 3281 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3282 rate == 22 && remainder <= 30) 3283 frm->atw_head_plcplen |= 0x8000; 3284 } 3285 } 3286 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3287 htole16(frm->atw_head_plcplen); 3288 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3289 } 3290 3291 #ifdef ATW_DEBUG 3292 static void 3293 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3294 { 3295 struct atw_softc *sc = ifp->if_softc; 3296 struct mbuf *m; 3297 int i, noctets = 0; 3298 3299 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3300 m0->m_pkthdr.len); 3301 3302 for (m = m0; m; m = m->m_next) { 3303 if (m->m_len == 0) 3304 continue; 3305 for (i = 0; i < m->m_len; i++) { 3306 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3307 if (++noctets % 24 == 0) 3308 printf("\n"); 3309 } 3310 } 3311 printf("%s%s: %d bytes emitted\n", 3312 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3313 } 3314 #endif /* ATW_DEBUG */ 3315 3316 /* 3317 * atw_start: [ifnet interface function] 3318 * 3319 * Start packet transmission on the interface. 3320 */ 3321 void 3322 atw_start(struct ifnet *ifp) 3323 { 3324 struct atw_softc *sc = ifp->if_softc; 3325 struct ieee80211com *ic = &sc->sc_ic; 3326 struct ieee80211_node *ni; 3327 struct ieee80211_frame *wh; 3328 struct atw_frame *hh; 3329 struct mbuf *m0, *m; 3330 struct atw_txsoft *txs, *last_txs; 3331 struct atw_txdesc *txd; 3332 int do_encrypt, rate; 3333 bus_dmamap_t dmamap; 3334 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3335 3336 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3337 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3338 3339 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3340 return; 3341 3342 #if 0 /* TBD ??? */ 3343 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3344 return; 3345 #endif 3346 3347 /* 3348 * Remember the previous number of free descriptors and 3349 * the first descriptor we'll use. 3350 */ 3351 ofree = sc->sc_txfree; 3352 firsttx = sc->sc_txnext; 3353 3354 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3355 sc->sc_dev.dv_xname, ofree, firsttx)); 3356 3357 /* 3358 * Loop through the send queue, setting up transmit descriptors 3359 * until we drain the queue, or use up all available transmit 3360 * descriptors. 3361 */ 3362 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3363 sc->sc_txfree != 0) { 3364 3365 /* 3366 * Grab a packet off the management queue, if it 3367 * is not empty. Otherwise, from the data queue. 3368 */ 3369 IF_DEQUEUE(&ic->ic_mgtq, m0); 3370 if (m0 != NULL) { 3371 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3372 m0->m_pkthdr.rcvif = NULL; 3373 } else { 3374 IFQ_DEQUEUE(&ifp->if_snd, m0); 3375 if (m0 == NULL) 3376 break; 3377 #if NBPFILTER > 0 3378 if (ifp->if_bpf != NULL) 3379 bpf_mtap(ifp->if_bpf, m0); 3380 #endif /* NBPFILTER > 0 */ 3381 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3382 ifp->if_oerrors++; 3383 break; 3384 } 3385 } 3386 3387 rate = MAX(ieee80211_get_rate(ic), 2); 3388 3389 #if NBPFILTER > 0 3390 /* 3391 * Pass the packet to any BPF listeners. 3392 */ 3393 if (ic->ic_rawbpf != NULL) 3394 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3395 3396 if (sc->sc_radiobpf != NULL) { 3397 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3398 3399 tap->at_rate = rate; 3400 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3401 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3402 3403 /* TBD tap->at_flags */ 3404 3405 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3406 tap->at_ihdr.it_len, m0); 3407 } 3408 #endif /* NBPFILTER > 0 */ 3409 3410 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3411 3412 if (ni != NULL && ni != ic->ic_bss) 3413 ieee80211_free_node(ic, ni); 3414 3415 if (m0 == NULL) { 3416 ifp->if_oerrors++; 3417 break; 3418 } 3419 3420 /* just to make sure. */ 3421 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3422 3423 if (m0 == NULL) { 3424 ifp->if_oerrors++; 3425 break; 3426 } 3427 3428 hh = mtod(m0, struct atw_frame *); 3429 wh = &hh->atw_ihdr; 3430 3431 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3432 3433 /* Copy everything we need from the 802.11 header: 3434 * Frame Control; address 1, address 3, or addresses 3435 * 3 and 4. NIC fills in BSSID, SA. 3436 */ 3437 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3438 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3439 panic("%s: illegal WDS frame", 3440 sc->sc_dev.dv_xname); 3441 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3442 } else 3443 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3444 3445 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3446 3447 /* initialize remaining Tx parameters */ 3448 memset(&hh->u, 0, sizeof(hh->u)); 3449 3450 hh->atw_rate = rate * 5; 3451 /* XXX this could be incorrect if M_FCS. _encap should 3452 * probably strip FCS just in case it sticks around in 3453 * bridged packets. 3454 */ 3455 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3456 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3457 sizeof(struct atw_frame)); 3458 3459 #if 0 3460 /* this virtually guaranteed that WEP-encrypted frames 3461 * are fragmented. oops. 3462 */ 3463 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3464 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3465 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3466 #else 3467 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3468 #endif 3469 3470 hh->atw_rtylmt = 3; 3471 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3472 if (do_encrypt) { 3473 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3474 hh->atw_keyid = ic->ic_wep_txkey; 3475 } 3476 3477 /* TBD 4-addr frames */ 3478 atw_frame_setdurs(sc, hh, rate, 3479 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3480 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3481 3482 /* never fragment multicast frames */ 3483 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3484 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3485 } else if (sc->sc_flags & ATWF_RTSCTS) { 3486 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3487 } 3488 3489 #ifdef ATW_DEBUG 3490 /* experimental stuff */ 3491 if (atw_xrtylmt != ~0) 3492 hh->atw_rtylmt = atw_xrtylmt; 3493 if (atw_xhdrctl != 0) 3494 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3495 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3496 hh->atw_service = atw_xservice; 3497 if (atw_xpaylen != 0) 3498 hh->atw_paylen = htole16(atw_xpaylen); 3499 hh->atw_fragnum = 0; 3500 3501 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3502 printf("%s: dst = %s, rate = 0x%02x, " 3503 "service = 0x%02x, paylen = 0x%04x\n", 3504 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3505 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3506 3507 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3508 "dur1 = 0x%04x, dur2 = 0x%04x, " 3509 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3510 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3511 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3512 hh->atw_tail_dur, hh->atw_head_dur); 3513 3514 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3515 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3516 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3517 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3518 3519 printf("%s: keyid = %d\n", 3520 sc->sc_dev.dv_xname, hh->atw_keyid); 3521 3522 atw_dump_pkt(ifp, m0); 3523 } 3524 #endif /* ATW_DEBUG */ 3525 3526 dmamap = txs->txs_dmamap; 3527 3528 /* 3529 * Load the DMA map. Copy and try (once) again if the packet 3530 * didn't fit in the alloted number of segments. 3531 */ 3532 for (first = 1; 3533 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3534 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3535 first = 0) { 3536 MGETHDR(m, M_DONTWAIT, MT_DATA); 3537 if (m == NULL) { 3538 printf("%s: unable to allocate Tx mbuf\n", 3539 sc->sc_dev.dv_xname); 3540 break; 3541 } 3542 if (m0->m_pkthdr.len > MHLEN) { 3543 MCLGET(m, M_DONTWAIT); 3544 if ((m->m_flags & M_EXT) == 0) { 3545 printf("%s: unable to allocate Tx " 3546 "cluster\n", sc->sc_dev.dv_xname); 3547 m_freem(m); 3548 break; 3549 } 3550 } 3551 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3552 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3553 m_freem(m0); 3554 m0 = m; 3555 m = NULL; 3556 } 3557 if (error != 0) { 3558 printf("%s: unable to load Tx buffer, " 3559 "error = %d\n", sc->sc_dev.dv_xname, error); 3560 m_freem(m0); 3561 break; 3562 } 3563 3564 /* 3565 * Ensure we have enough descriptors free to describe 3566 * the packet. 3567 */ 3568 if (dmamap->dm_nsegs > sc->sc_txfree) { 3569 /* 3570 * Not enough free descriptors to transmit 3571 * this packet. Unload the DMA map and 3572 * drop the packet. Notify the upper layer 3573 * that there are no more slots left. 3574 * 3575 * XXX We could allocate an mbuf and copy, but 3576 * XXX it is worth it? 3577 */ 3578 ifp->if_flags |= IFF_OACTIVE; 3579 bus_dmamap_unload(sc->sc_dmat, dmamap); 3580 m_freem(m0); 3581 break; 3582 } 3583 3584 /* 3585 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3586 */ 3587 3588 /* Sync the DMA map. */ 3589 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3590 BUS_DMASYNC_PREWRITE); 3591 3592 /* XXX arbitrary retry limit; 8 because I have seen it in 3593 * use already and maybe 0 means "no tries" ! 3594 */ 3595 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3596 3597 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3598 sc->sc_dev.dv_xname, rate * 5)); 3599 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3600 3601 /* 3602 * Initialize the transmit descriptors. 3603 */ 3604 for (nexttx = sc->sc_txnext, seg = 0; 3605 seg < dmamap->dm_nsegs; 3606 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3607 /* 3608 * If this is the first descriptor we're 3609 * enqueueing, don't set the OWN bit just 3610 * yet. That could cause a race condition. 3611 * We'll do it below. 3612 */ 3613 txd = &sc->sc_txdescs[nexttx]; 3614 txd->at_ctl = ctl | 3615 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3616 3617 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3618 txd->at_flags = 3619 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3620 ATW_TXFLAG_TBS1_MASK)) | 3621 ((nexttx == (ATW_NTXDESC - 1)) 3622 ? htole32(ATW_TXFLAG_TER) : 0); 3623 lasttx = nexttx; 3624 } 3625 3626 IASSERT(lasttx != -1, ("bad lastx")); 3627 /* Set `first segment' and `last segment' appropriately. */ 3628 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3629 htole32(ATW_TXFLAG_FS); 3630 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3631 3632 #ifdef ATW_DEBUG 3633 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3634 printf(" txsoft %p transmit chain:\n", txs); 3635 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3636 printf(" descriptor %d:\n", seg); 3637 printf(" at_ctl: 0x%08x\n", 3638 le32toh(sc->sc_txdescs[seg].at_ctl)); 3639 printf(" at_flags: 0x%08x\n", 3640 le32toh(sc->sc_txdescs[seg].at_flags)); 3641 printf(" at_buf1: 0x%08x\n", 3642 le32toh(sc->sc_txdescs[seg].at_buf1)); 3643 printf(" at_buf2: 0x%08x\n", 3644 le32toh(sc->sc_txdescs[seg].at_buf2)); 3645 if (seg == lasttx) 3646 break; 3647 } 3648 } 3649 #endif 3650 3651 /* Sync the descriptors we're using. */ 3652 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3653 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3654 3655 /* 3656 * Store a pointer to the packet so we can free it later, 3657 * and remember what txdirty will be once the packet is 3658 * done. 3659 */ 3660 txs->txs_mbuf = m0; 3661 txs->txs_firstdesc = sc->sc_txnext; 3662 txs->txs_lastdesc = lasttx; 3663 txs->txs_ndescs = dmamap->dm_nsegs; 3664 3665 /* Advance the tx pointer. */ 3666 sc->sc_txfree -= dmamap->dm_nsegs; 3667 sc->sc_txnext = nexttx; 3668 3669 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3670 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3671 3672 last_txs = txs; 3673 } 3674 3675 if (txs == NULL || sc->sc_txfree == 0) { 3676 /* No more slots left; notify upper layer. */ 3677 ifp->if_flags |= IFF_OACTIVE; 3678 } 3679 3680 if (sc->sc_txfree != ofree) { 3681 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3682 sc->sc_dev.dv_xname, lasttx, firsttx)); 3683 /* 3684 * Cause a transmit interrupt to happen on the 3685 * last packet we enqueued. 3686 */ 3687 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3688 ATW_CDTXSYNC(sc, lasttx, 1, 3689 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3690 3691 /* 3692 * The entire packet chain is set up. Give the 3693 * first descriptor to the chip now. 3694 */ 3695 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3696 ATW_CDTXSYNC(sc, firsttx, 1, 3697 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3698 3699 /* Wake up the transmitter. */ 3700 ATW_WRITE(sc, ATW_TDR, 0x1); 3701 3702 /* Set a watchdog timer in case the chip flakes out. */ 3703 sc->sc_tx_timer = 5; 3704 ifp->if_timer = 1; 3705 } 3706 } 3707 3708 /* 3709 * atw_power: 3710 * 3711 * Power management (suspend/resume) hook. 3712 */ 3713 void 3714 atw_power(int why, void *arg) 3715 { 3716 struct atw_softc *sc = arg; 3717 struct ifnet *ifp = &sc->sc_ic.ic_if; 3718 int s; 3719 3720 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3721 3722 s = splnet(); 3723 switch (why) { 3724 case PWR_STANDBY: 3725 /* XXX do nothing. */ 3726 break; 3727 case PWR_SUSPEND: 3728 atw_stop(ifp, 0); 3729 if (sc->sc_power != NULL) 3730 (*sc->sc_power)(sc, why); 3731 break; 3732 case PWR_RESUME: 3733 if (ifp->if_flags & IFF_UP) { 3734 if (sc->sc_power != NULL) 3735 (*sc->sc_power)(sc, why); 3736 atw_init(ifp); 3737 } 3738 break; 3739 case PWR_SOFTSUSPEND: 3740 case PWR_SOFTSTANDBY: 3741 case PWR_SOFTRESUME: 3742 break; 3743 } 3744 splx(s); 3745 } 3746 3747 /* 3748 * atw_ioctl: [ifnet interface function] 3749 * 3750 * Handle control requests from the operator. 3751 */ 3752 int 3753 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3754 { 3755 struct atw_softc *sc = ifp->if_softc; 3756 struct ifreq *ifr = (struct ifreq *)data; 3757 int s, error = 0; 3758 3759 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3760 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3761 return ENXIO; 3762 3763 s = splnet(); 3764 3765 switch (cmd) { 3766 case SIOCSIFFLAGS: 3767 if (ifp->if_flags & IFF_UP) { 3768 if (ATW_IS_ENABLED(sc)) { 3769 /* 3770 * To avoid rescanning another access point, 3771 * do not call atw_init() here. Instead, 3772 * only reflect media settings. 3773 */ 3774 atw_filter_setup(sc); 3775 } else 3776 error = atw_init(ifp); 3777 } else if (ATW_IS_ENABLED(sc)) 3778 atw_stop(ifp, 1); 3779 break; 3780 case SIOCADDMULTI: 3781 case SIOCDELMULTI: 3782 error = (cmd == SIOCADDMULTI) ? 3783 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3784 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3785 if (error == ENETRESET) { 3786 if (ATW_IS_ENABLED(sc)) 3787 atw_filter_setup(sc); /* do not rescan */ 3788 error = 0; 3789 } 3790 break; 3791 default: 3792 error = ieee80211_ioctl(ifp, cmd, data); 3793 if (error == ENETRESET) { 3794 if (ATW_IS_ENABLED(sc)) 3795 error = atw_init(ifp); 3796 else 3797 error = 0; 3798 } 3799 break; 3800 } 3801 3802 /* Try to get more packets going. */ 3803 if (ATW_IS_ENABLED(sc)) 3804 atw_start(ifp); 3805 3806 splx(s); 3807 return (error); 3808 } 3809 3810 static int 3811 atw_media_change(struct ifnet *ifp) 3812 { 3813 int error; 3814 3815 error = ieee80211_media_change(ifp); 3816 if (error == ENETRESET) { 3817 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3818 (IFF_RUNNING|IFF_UP)) 3819 atw_init(ifp); /* XXX lose error */ 3820 error = 0; 3821 } 3822 return error; 3823 } 3824 3825 static void 3826 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3827 { 3828 struct atw_softc *sc = ifp->if_softc; 3829 3830 if (ATW_IS_ENABLED(sc) == 0) { 3831 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3832 imr->ifm_status = 0; 3833 return; 3834 } 3835 ieee80211_media_status(ifp, imr); 3836 } 3837
Indexes created Wed Sep 24 15:09:51 GMT 2025