atw.c revision 1.37
1 /* $NetBSD: atw.c,v 1.37 2004/06/23 09:41:54 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.37 2004/06/23 09:41:54 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * IBSS join/create 131 * 132 * set ATW_NAR_EA (is set by ASIC?) 133 * 134 * BSS join: (re)association response 135 * 136 * set ATW_FRCTL_AID 137 * 138 * optimizations ??? 139 * 140 */ 141 142 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 143 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 144 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 145 146 int atw_rfio_enable_delay = 20 * 1000; 147 int atw_rfio_disable_delay = 2 * 1000; 148 int atw_writewep_delay = 5; 149 int atw_beacon_len_adjust = 4; 150 int atw_dwelltime = 200; 151 152 #ifdef ATW_DEBUG 153 int atw_xhdrctl = 0; 154 int atw_xrtylmt = ~0; 155 int atw_xservice = IEEE80211_PLCP_SERVICE; 156 int atw_xpaylen = 0; 157 158 int atw_debug = 0; 159 160 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 161 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 162 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 163 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 164 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 165 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 166 static void atw_print_regs(struct atw_softc *, const char *); 167 static void atw_rf3000_print(struct atw_softc *); 168 static void atw_si4126_print(struct atw_softc *); 169 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 170 #else 171 #define ATW_DPRINTF(x) 172 #define ATW_DPRINTF2(x) 173 #define ATW_DPRINTF3(x) 174 #define DPRINTF(sc, x) /* nothing */ 175 #define DPRINTF2(sc, x) /* nothing */ 176 #define DPRINTF3(sc, x) /* nothing */ 177 #endif 178 179 #ifdef ATW_STATS 180 void atw_print_stats(struct atw_softc *); 181 #endif 182 183 void atw_start(struct ifnet *); 184 void atw_watchdog(struct ifnet *); 185 int atw_ioctl(struct ifnet *, u_long, caddr_t); 186 int atw_init(struct ifnet *); 187 void atw_txdrain(struct atw_softc *); 188 void atw_stop(struct ifnet *, int); 189 190 void atw_reset(struct atw_softc *); 191 int atw_read_srom(struct atw_softc *); 192 193 void atw_shutdown(void *); 194 195 void atw_rxdrain(struct atw_softc *); 196 int atw_add_rxbuf(struct atw_softc *, int); 197 void atw_idle(struct atw_softc *, u_int32_t); 198 199 int atw_enable(struct atw_softc *); 200 void atw_disable(struct atw_softc *); 201 void atw_power(int, void *); 202 203 void atw_rxintr(struct atw_softc *); 204 void atw_txintr(struct atw_softc *); 205 void atw_linkintr(struct atw_softc *, u_int32_t); 206 207 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 208 static void atw_tsf(struct atw_softc *); 209 static void atw_start_beacon(struct atw_softc *, int); 210 static void atw_write_wep(struct atw_softc *); 211 static void atw_write_bssid(struct atw_softc *); 212 static void atw_write_bcn_thresh(struct atw_softc *); 213 static void atw_write_ssid(struct atw_softc *); 214 static void atw_write_sup_rates(struct atw_softc *); 215 static void atw_clear_sram(struct atw_softc *); 216 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 217 static int atw_media_change(struct ifnet *); 218 static void atw_media_status(struct ifnet *, struct ifmediareq *); 219 static void atw_filter_setup(struct atw_softc *); 220 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 221 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 222 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 223 struct ieee80211_node *, int, int, u_int32_t); 224 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 225 struct ieee80211_node *, int, int, u_int32_t); 226 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 227 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 228 229 static int atw_tune(struct atw_softc *); 230 231 static void atw_rfio_enable(struct atw_softc *, int); 232 233 /* RFMD RF3000 Baseband Processor */ 234 static int atw_rf3000_init(struct atw_softc *); 235 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 236 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 237 #ifdef ATW_DEBUG 238 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 239 #endif /* ATW_DEBUG */ 240 241 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 242 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 243 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 244 #ifdef ATW_DEBUG 245 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 246 #endif /* ATW_DEBUG */ 247 248 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 249 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 250 251 const char *atw_tx_state[] = { 252 "STOPPED", 253 "RUNNING - read descriptor", 254 "RUNNING - transmitting", 255 "RUNNING - filling fifo", /* XXX */ 256 "SUSPENDED", 257 "RUNNING -- write descriptor", 258 "RUNNING -- write last descriptor", 259 "RUNNING - fifo full" 260 }; 261 262 const char *atw_rx_state[] = { 263 "STOPPED", 264 "RUNNING - read descriptor", 265 "RUNNING - check this packet, pre-fetch next", 266 "RUNNING - wait for reception", 267 "SUSPENDED", 268 "RUNNING - write descriptor", 269 "RUNNING - flush fifo", 270 "RUNNING - fifo drain" 271 }; 272 273 int 274 atw_activate(struct device *self, enum devact act) 275 { 276 struct atw_softc *sc = (struct atw_softc *)self; 277 int rv = 0, s; 278 279 s = splnet(); 280 switch (act) { 281 case DVACT_ACTIVATE: 282 rv = EOPNOTSUPP; 283 break; 284 285 case DVACT_DEACTIVATE: 286 if_deactivate(&sc->sc_ic.ic_if); 287 break; 288 } 289 splx(s); 290 return rv; 291 } 292 293 /* 294 * atw_enable: 295 * 296 * Enable the ADM8211 chip. 297 */ 298 int 299 atw_enable(struct atw_softc *sc) 300 { 301 302 if (ATW_IS_ENABLED(sc) == 0) { 303 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 304 printf("%s: device enable failed\n", 305 sc->sc_dev.dv_xname); 306 return (EIO); 307 } 308 sc->sc_flags |= ATWF_ENABLED; 309 } 310 return (0); 311 } 312 313 /* 314 * atw_disable: 315 * 316 * Disable the ADM8211 chip. 317 */ 318 void 319 atw_disable(struct atw_softc *sc) 320 { 321 if (!ATW_IS_ENABLED(sc)) 322 return; 323 if (sc->sc_disable != NULL) 324 (*sc->sc_disable)(sc); 325 sc->sc_flags &= ~ATWF_ENABLED; 326 } 327 328 /* Returns -1 on failure. */ 329 int 330 atw_read_srom(struct atw_softc *sc) 331 { 332 struct seeprom_descriptor sd; 333 u_int32_t reg; 334 335 (void)memset(&sd, 0, sizeof(sd)); 336 337 reg = ATW_READ(sc, ATW_TEST0); 338 339 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 340 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 341 return -1; 342 } 343 344 switch (reg & ATW_TEST0_EPTYP_MASK) { 345 case ATW_TEST0_EPTYP_93c66: 346 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 347 sc->sc_sromsz = 512; 348 sd.sd_chip = C56_66; 349 break; 350 case ATW_TEST0_EPTYP_93c46: 351 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 352 sc->sc_sromsz = 128; 353 sd.sd_chip = C46; 354 break; 355 default: 356 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 357 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 358 return -1; 359 } 360 361 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 362 363 if (sc->sc_srom == NULL) { 364 printf("%s: unable to allocate SROM buffer\n", 365 sc->sc_dev.dv_xname); 366 return -1; 367 } 368 369 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 370 371 /* ADM8211 has a single 32-bit register for controlling the 372 * 93cx6 SROM. Bit SRS enables the serial port. There is no 373 * "ready" bit. The ADM8211 input/output sense is the reverse 374 * of read_seeprom's. 375 */ 376 sd.sd_tag = sc->sc_st; 377 sd.sd_bsh = sc->sc_sh; 378 sd.sd_regsize = 4; 379 sd.sd_control_offset = ATW_SPR; 380 sd.sd_status_offset = ATW_SPR; 381 sd.sd_dataout_offset = ATW_SPR; 382 sd.sd_CK = ATW_SPR_SCLK; 383 sd.sd_CS = ATW_SPR_SCS; 384 sd.sd_DI = ATW_SPR_SDO; 385 sd.sd_DO = ATW_SPR_SDI; 386 sd.sd_MS = ATW_SPR_SRS; 387 sd.sd_RDY = 0; 388 389 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 390 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 391 free(sc->sc_srom, M_DEVBUF); 392 return -1; 393 } 394 #ifdef ATW_DEBUG 395 { 396 int i; 397 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 398 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 399 if (((i % 8) == 0) && (i != 0)) { 400 ATW_DPRINTF(("\n\t")); 401 } 402 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 403 } 404 ATW_DPRINTF(("\n")); 405 } 406 #endif /* ATW_DEBUG */ 407 return 0; 408 } 409 410 #ifdef ATW_DEBUG 411 static void 412 atw_print_regs(struct atw_softc *sc, const char *where) 413 { 414 #define PRINTREG(sc, reg) \ 415 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 416 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 417 418 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 419 420 PRINTREG(sc, ATW_PAR); 421 PRINTREG(sc, ATW_FRCTL); 422 PRINTREG(sc, ATW_TDR); 423 PRINTREG(sc, ATW_WTDP); 424 PRINTREG(sc, ATW_RDR); 425 PRINTREG(sc, ATW_WRDP); 426 PRINTREG(sc, ATW_RDB); 427 PRINTREG(sc, ATW_CSR3A); 428 PRINTREG(sc, ATW_TDBD); 429 PRINTREG(sc, ATW_TDBP); 430 PRINTREG(sc, ATW_STSR); 431 PRINTREG(sc, ATW_CSR5A); 432 PRINTREG(sc, ATW_NAR); 433 PRINTREG(sc, ATW_CSR6A); 434 PRINTREG(sc, ATW_IER); 435 PRINTREG(sc, ATW_CSR7A); 436 PRINTREG(sc, ATW_LPC); 437 PRINTREG(sc, ATW_TEST1); 438 PRINTREG(sc, ATW_SPR); 439 PRINTREG(sc, ATW_TEST0); 440 PRINTREG(sc, ATW_WCSR); 441 PRINTREG(sc, ATW_WPDR); 442 PRINTREG(sc, ATW_GPTMR); 443 PRINTREG(sc, ATW_GPIO); 444 PRINTREG(sc, ATW_BBPCTL); 445 PRINTREG(sc, ATW_SYNCTL); 446 PRINTREG(sc, ATW_PLCPHD); 447 PRINTREG(sc, ATW_MMIWADDR); 448 PRINTREG(sc, ATW_MMIRADDR1); 449 PRINTREG(sc, ATW_MMIRADDR2); 450 PRINTREG(sc, ATW_TXBR); 451 PRINTREG(sc, ATW_CSR15A); 452 PRINTREG(sc, ATW_ALCSTAT); 453 PRINTREG(sc, ATW_TOFS2); 454 PRINTREG(sc, ATW_CMDR); 455 PRINTREG(sc, ATW_PCIC); 456 PRINTREG(sc, ATW_PMCSR); 457 PRINTREG(sc, ATW_PAR0); 458 PRINTREG(sc, ATW_PAR1); 459 PRINTREG(sc, ATW_MAR0); 460 PRINTREG(sc, ATW_MAR1); 461 PRINTREG(sc, ATW_ATIMDA0); 462 PRINTREG(sc, ATW_ABDA1); 463 PRINTREG(sc, ATW_BSSID0); 464 PRINTREG(sc, ATW_TXLMT); 465 PRINTREG(sc, ATW_MIBCNT); 466 PRINTREG(sc, ATW_BCNT); 467 PRINTREG(sc, ATW_TSFTH); 468 PRINTREG(sc, ATW_TSC); 469 PRINTREG(sc, ATW_SYNRF); 470 PRINTREG(sc, ATW_BPLI); 471 PRINTREG(sc, ATW_CAP0); 472 PRINTREG(sc, ATW_CAP1); 473 PRINTREG(sc, ATW_RMD); 474 PRINTREG(sc, ATW_CFPP); 475 PRINTREG(sc, ATW_TOFS0); 476 PRINTREG(sc, ATW_TOFS1); 477 PRINTREG(sc, ATW_IFST); 478 PRINTREG(sc, ATW_RSPT); 479 PRINTREG(sc, ATW_TSFTL); 480 PRINTREG(sc, ATW_WEPCTL); 481 PRINTREG(sc, ATW_WESK); 482 PRINTREG(sc, ATW_WEPCNT); 483 PRINTREG(sc, ATW_MACTEST); 484 PRINTREG(sc, ATW_FER); 485 PRINTREG(sc, ATW_FEMR); 486 PRINTREG(sc, ATW_FPSR); 487 PRINTREG(sc, ATW_FFER); 488 #undef PRINTREG 489 } 490 #endif /* ATW_DEBUG */ 491 492 /* 493 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 494 */ 495 void 496 atw_attach(struct atw_softc *sc) 497 { 498 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 499 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 500 }; 501 struct ieee80211com *ic = &sc->sc_ic; 502 struct ifnet *ifp = &ic->ic_if; 503 int country_code, error, i, nrate; 504 u_int32_t reg; 505 static const char *type_strings[] = {"Intersil (not supported)", 506 "RFMD", "Marvel (not supported)"}; 507 508 sc->sc_txth = atw_txthresh_tab_lo; 509 510 SIMPLEQ_INIT(&sc->sc_txfreeq); 511 SIMPLEQ_INIT(&sc->sc_txdirtyq); 512 513 #ifdef ATW_DEBUG 514 atw_print_regs(sc, "atw_attach"); 515 #endif /* ATW_DEBUG */ 516 517 /* 518 * Allocate the control data structures, and create and load the 519 * DMA map for it. 520 */ 521 if ((error = bus_dmamem_alloc(sc->sc_dmat, 522 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 523 1, &sc->sc_cdnseg, 0)) != 0) { 524 printf("%s: unable to allocate control data, error = %d\n", 525 sc->sc_dev.dv_xname, error); 526 goto fail_0; 527 } 528 529 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 530 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 531 BUS_DMA_COHERENT)) != 0) { 532 printf("%s: unable to map control data, error = %d\n", 533 sc->sc_dev.dv_xname, error); 534 goto fail_1; 535 } 536 537 if ((error = bus_dmamap_create(sc->sc_dmat, 538 sizeof(struct atw_control_data), 1, 539 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 540 printf("%s: unable to create control data DMA map, " 541 "error = %d\n", sc->sc_dev.dv_xname, error); 542 goto fail_2; 543 } 544 545 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 546 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 547 0)) != 0) { 548 printf("%s: unable to load control data DMA map, error = %d\n", 549 sc->sc_dev.dv_xname, error); 550 goto fail_3; 551 } 552 553 /* 554 * Create the transmit buffer DMA maps. 555 */ 556 sc->sc_ntxsegs = ATW_NTXSEGS; 557 for (i = 0; i < ATW_TXQUEUELEN; i++) { 558 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 559 sc->sc_ntxsegs, MCLBYTES, 0, 0, 560 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 561 printf("%s: unable to create tx DMA map %d, " 562 "error = %d\n", sc->sc_dev.dv_xname, i, error); 563 goto fail_4; 564 } 565 } 566 567 /* 568 * Create the receive buffer DMA maps. 569 */ 570 for (i = 0; i < ATW_NRXDESC; i++) { 571 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 572 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 573 printf("%s: unable to create rx DMA map %d, " 574 "error = %d\n", sc->sc_dev.dv_xname, i, error); 575 goto fail_5; 576 } 577 } 578 for (i = 0; i < ATW_NRXDESC; i++) { 579 sc->sc_rxsoft[i].rxs_mbuf = NULL; 580 } 581 582 /* Reset the chip to a known state. */ 583 atw_reset(sc); 584 585 if (atw_read_srom(sc) == -1) 586 return; 587 588 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 589 ATW_SR_RFTYPE_MASK); 590 591 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 592 ATW_SR_BBPTYPE_MASK); 593 594 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 595 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 596 return; 597 } 598 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 599 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 600 return; 601 } 602 603 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 604 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 605 606 /* XXX There exists a Linux driver which seems to use RFType = 0 for 607 * MARVEL. My bug, or theirs? 608 */ 609 610 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 611 612 switch (sc->sc_rftype) { 613 case ATW_RFTYPE_INTERSIL: 614 reg |= ATW_SYNCTL_CS1; 615 break; 616 case ATW_RFTYPE_RFMD: 617 reg |= ATW_SYNCTL_CS0; 618 break; 619 case ATW_RFTYPE_MARVEL: 620 break; 621 } 622 623 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 624 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 625 626 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 627 628 switch (sc->sc_bbptype) { 629 case ATW_BBPTYPE_INTERSIL: 630 reg |= ATW_BBPCTL_TWI; 631 break; 632 case ATW_BBPTYPE_RFMD: 633 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 634 ATW_BBPCTL_CCA_ACTLO; 635 break; 636 case ATW_BBPTYPE_MARVEL: 637 break; 638 case ATW_C_BBPTYPE_RFMD: 639 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 640 sc->sc_dev.dv_xname); 641 break; 642 } 643 644 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 645 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 646 647 /* 648 * From this point forward, the attachment cannot fail. A failure 649 * before this point releases all resources that may have been 650 * allocated. 651 */ 652 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 653 654 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 655 htole16(sc->sc_srom[ATW_SR_MAC00]), 656 htole16(sc->sc_srom[ATW_SR_MAC01]), 657 htole16(sc->sc_srom[ATW_SR_MAC10]))); 658 659 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 660 ATW_SR_CTRY_MASK); 661 662 #define ADD_CHANNEL(_ic, _chan) do { \ 663 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 664 _ic->ic_channels[_chan].ic_freq = \ 665 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 666 } while (0) 667 668 /* Find available channels */ 669 switch (country_code) { 670 case COUNTRY_MMK2: /* 1-14 */ 671 ADD_CHANNEL(ic, 14); 672 /*FALLTHROUGH*/ 673 case COUNTRY_ETSI: /* 1-13 */ 674 for (i = 1; i <= 13; i++) 675 ADD_CHANNEL(ic, i); 676 break; 677 case COUNTRY_FCC: /* 1-11 */ 678 case COUNTRY_IC: /* 1-11 */ 679 for (i = 1; i <= 11; i++) 680 ADD_CHANNEL(ic, i); 681 break; 682 case COUNTRY_MMK: /* 14 */ 683 ADD_CHANNEL(ic, 14); 684 break; 685 case COUNTRY_FRANCE: /* 10-13 */ 686 for (i = 10; i <= 13; i++) 687 ADD_CHANNEL(ic, i); 688 break; 689 default: /* assume channels 10-11 */ 690 case COUNTRY_SPAIN: /* 10-11 */ 691 for (i = 10; i <= 11; i++) 692 ADD_CHANNEL(ic, i); 693 break; 694 } 695 696 /* Read the MAC address. */ 697 reg = ATW_READ(sc, ATW_PAR0); 698 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 699 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 700 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 701 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 702 reg = ATW_READ(sc, ATW_PAR1); 703 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 704 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 705 706 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 707 printf(" could not get mac address, attach failed\n"); 708 return; 709 } 710 711 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 712 713 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 714 ifp->if_softc = sc; 715 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 716 IFF_NOTRAILERS; 717 ifp->if_ioctl = atw_ioctl; 718 ifp->if_start = atw_start; 719 ifp->if_watchdog = atw_watchdog; 720 ifp->if_init = atw_init; 721 ifp->if_stop = atw_stop; 722 IFQ_SET_READY(&ifp->if_snd); 723 724 ic->ic_phytype = IEEE80211_T_DS; 725 ic->ic_opmode = IEEE80211_M_STA; 726 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 727 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 728 729 nrate = 0; 730 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 731 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 735 736 /* 737 * Call MI attach routines. 738 */ 739 740 if_attach(ifp); 741 ieee80211_ifattach(ifp); 742 743 sc->sc_newstate = ic->ic_newstate; 744 ic->ic_newstate = atw_newstate; 745 746 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 747 ic->ic_recv_mgmt = atw_recv_mgmt; 748 749 sc->sc_node_free = ic->ic_node_free; 750 ic->ic_node_free = atw_node_free; 751 752 sc->sc_node_alloc = ic->ic_node_alloc; 753 ic->ic_node_alloc = atw_node_alloc; 754 755 /* possibly we should fill in our own sc_send_prresp, since 756 * the ADM8211 is probably sending probe responses in ad hoc 757 * mode. 758 */ 759 760 /* complete initialization */ 761 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 762 callout_init(&sc->sc_scan_ch); 763 764 #if NBPFILTER > 0 765 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 766 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 767 #endif 768 769 /* 770 * Make sure the interface is shutdown during reboot. 771 */ 772 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 773 if (sc->sc_sdhook == NULL) 774 printf("%s: WARNING: unable to establish shutdown hook\n", 775 sc->sc_dev.dv_xname); 776 777 /* 778 * Add a suspend hook to make sure we come back up after a 779 * resume. 780 */ 781 sc->sc_powerhook = powerhook_establish(atw_power, sc); 782 if (sc->sc_powerhook == NULL) 783 printf("%s: WARNING: unable to establish power hook\n", 784 sc->sc_dev.dv_xname); 785 786 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 787 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 788 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 789 790 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 791 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 792 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 793 794 return; 795 796 /* 797 * Free any resources we've allocated during the failed attach 798 * attempt. Do this in reverse order and fall through. 799 */ 800 fail_5: 801 for (i = 0; i < ATW_NRXDESC; i++) { 802 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 803 continue; 804 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 805 } 806 fail_4: 807 for (i = 0; i < ATW_TXQUEUELEN; i++) { 808 if (sc->sc_txsoft[i].txs_dmamap == NULL) 809 continue; 810 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 811 } 812 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 813 fail_3: 814 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 815 fail_2: 816 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 817 sizeof(struct atw_control_data)); 818 fail_1: 819 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 820 fail_0: 821 return; 822 } 823 824 static struct ieee80211_node * 825 atw_node_alloc(struct ieee80211com *ic) 826 { 827 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 828 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 829 830 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 831 return ni; 832 } 833 834 static void 835 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 836 { 837 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 838 839 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 840 ether_sprintf(ni->ni_bssid))); 841 (*sc->sc_node_free)(ic, ni); 842 } 843 844 /* 845 * atw_reset: 846 * 847 * Perform a soft reset on the ADM8211. 848 */ 849 void 850 atw_reset(struct atw_softc *sc) 851 { 852 int i; 853 854 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 855 856 for (i = 0; i < 10000; i++) { 857 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 858 break; 859 DELAY(1); 860 } 861 862 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 863 864 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 865 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 866 867 /* Turn off maximum power saving. */ 868 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 869 870 /* Recall EEPROM. */ 871 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 872 873 DELAY(10 * 1000); 874 875 /* A reset seems to affect the SRAM contents, so put them into 876 * a known state. 877 */ 878 atw_clear_sram(sc); 879 880 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 881 882 sc->sc_lost_bcn_thresh = 0; 883 } 884 885 static void 886 atw_clear_sram(struct atw_softc *sc) 887 { 888 #if 0 889 for (addr = 0; addr < 448; addr++) { 890 ATW_WRITE(sc, ATW_WEPCTL, 891 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 892 DELAY(1000); 893 ATW_WRITE(sc, ATW_WESK, 0); 894 DELAY(1000); /* paranoia */ 895 } 896 return; 897 #endif 898 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 899 /* XXX not for revision 0x20. */ 900 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 901 } 902 903 /* TBD atw_init 904 * 905 * set MAC based on ic->ic_bss->myaddr 906 * write WEP keys 907 * set TX rate 908 */ 909 910 /* 911 * atw_init: [ ifnet interface function ] 912 * 913 * Initialize the interface. Must be called at splnet(). 914 */ 915 int 916 atw_init(struct ifnet *ifp) 917 { 918 struct atw_softc *sc = ifp->if_softc; 919 struct ieee80211com *ic = &sc->sc_ic; 920 struct atw_txsoft *txs; 921 struct atw_rxsoft *rxs; 922 u_int32_t reg; 923 int i, error = 0; 924 925 if ((error = atw_enable(sc)) != 0) 926 goto out; 927 928 /* 929 * Cancel any pending I/O. This also resets. 930 */ 931 atw_stop(ifp, 0); 932 933 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 934 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 935 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 936 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 937 938 /* Turn off APM??? (A binary-only driver does this.) 939 * 940 * Set Rx store-and-forward mode. 941 */ 942 reg = ATW_READ(sc, ATW_CMDR); 943 reg &= ~ATW_CMDR_APM; 944 reg &= ~ATW_CMDR_DRT_MASK; 945 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 946 947 ATW_WRITE(sc, ATW_CMDR, reg); 948 949 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 950 * 951 * XXX a binary-only driver sets a different service field than 952 * 0. why? 953 */ 954 reg = ATW_READ(sc, ATW_PLCPHD); 955 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 956 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 957 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 958 ATW_WRITE(sc, ATW_PLCPHD, reg); 959 960 /* XXX this magic can probably be figured out from the RFMD docs */ 961 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 962 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 963 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 964 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 965 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 966 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 967 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 968 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 969 ATW_WRITE(sc, ATW_TOFS2, reg); 970 971 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 972 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 973 974 /* XXX this resets an Intersil RF front-end? */ 975 /* TBD condition on Intersil RFType? */ 976 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 977 DELAY(10 * 1000); 978 ATW_WRITE(sc, ATW_SYNRF, 0); 979 DELAY(5 * 1000); 980 981 /* 16 TU max duration for contention-free period */ 982 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 983 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 984 985 /* XXX I guess that the Cardbus clock is 22MHz? 986 * I am assuming that the role of ATW_TOFS0_USCNT is 987 * to divide the bus clock to get a 1MHz clock---the datasheet is not 988 * very clear on this point. It says in the datasheet that it is 989 * possible for the ADM8211 to accomodate bus speeds between 22MHz 990 * and 33MHz; maybe this is the way? I see a binary-only driver write 991 * these values. These values are also the power-on default. 992 */ 993 ATW_WRITE(sc, ATW_TOFS0, 994 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 995 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 996 997 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 998 * driver. Go figure. 999 */ 1000 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1001 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1002 ATW_IFST_SIFS_MASK) | 1003 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1004 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1005 1006 ATW_WRITE(sc, ATW_IFST, reg); 1007 1008 /* XXX More magic. Might relate to ACK timing. */ 1009 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1010 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1011 1012 /* Set up the MMI read/write addresses for the BBP. 1013 * 1014 * TBD find out the Marvel settings. 1015 */ 1016 switch (sc->sc_bbptype) { 1017 case ATW_BBPTYPE_INTERSIL: 1018 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1019 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1020 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1021 break; 1022 case ATW_BBPTYPE_MARVEL: 1023 break; 1024 case ATW_BBPTYPE_RFMD: 1025 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1026 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1027 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1028 default: 1029 break; 1030 } 1031 1032 sc->sc_wepctl = 0; 1033 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1034 1035 if ((error = atw_rf3000_init(sc)) != 0) 1036 goto out; 1037 1038 /* 1039 * Initialize the PCI Access Register. 1040 */ 1041 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1042 1043 /* 1044 * If we're allowed to do so, use Memory Read Line 1045 * and Memory Read Multiple. 1046 * 1047 * XXX Should we use Memory Write and Invalidate? 1048 */ 1049 if (sc->sc_flags & ATWF_MRL) 1050 sc->sc_busmode |= ATW_PAR_MRLE; 1051 if (sc->sc_flags & ATWF_MRM) 1052 sc->sc_busmode |= ATW_PAR_MRME; 1053 if (sc->sc_flags & ATWF_MWI) 1054 sc->sc_busmode |= ATW_PAR_MWIE; 1055 if (sc->sc_maxburst == 0) 1056 sc->sc_maxburst = 8; /* ADM8211 default */ 1057 1058 switch (sc->sc_cacheline) { 1059 default: 1060 /* Use burst length. */ 1061 break; 1062 case 8: 1063 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1064 break; 1065 case 16: 1066 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1067 break; 1068 case 32: 1069 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1070 break; 1071 } 1072 switch (sc->sc_maxburst) { 1073 case 1: 1074 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1075 break; 1076 case 2: 1077 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1078 break; 1079 case 4: 1080 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1081 break; 1082 case 8: 1083 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1084 break; 1085 case 16: 1086 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1087 break; 1088 case 32: 1089 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1090 break; 1091 default: 1092 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1093 break; 1094 } 1095 1096 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1097 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1098 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1099 1100 /* 1101 * Initialize the OPMODE register. We don't write it until 1102 * we're ready to begin the transmit and receive processes. 1103 */ 1104 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1105 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1106 1107 /* 1108 * Initialize the transmit descriptor ring. 1109 */ 1110 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1111 for (i = 0; i < ATW_NTXDESC; i++) { 1112 /* no transmit chaining */ 1113 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1114 sc->sc_txdescs[i].at_buf2 = 1115 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1116 } 1117 /* use ring mode */ 1118 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1119 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1121 sc->sc_txfree = ATW_NTXDESC; 1122 sc->sc_txnext = 0; 1123 1124 /* 1125 * Initialize the transmit job descriptors. 1126 */ 1127 SIMPLEQ_INIT(&sc->sc_txfreeq); 1128 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1129 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1130 txs = &sc->sc_txsoft[i]; 1131 txs->txs_mbuf = NULL; 1132 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1133 } 1134 1135 /* 1136 * Initialize the receive descriptor and receive job 1137 * descriptor rings. 1138 */ 1139 for (i = 0; i < ATW_NRXDESC; i++) { 1140 rxs = &sc->sc_rxsoft[i]; 1141 if (rxs->rxs_mbuf == NULL) { 1142 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1143 printf("%s: unable to allocate or map rx " 1144 "buffer %d, error = %d\n", 1145 sc->sc_dev.dv_xname, i, error); 1146 /* 1147 * XXX Should attempt to run with fewer receive 1148 * XXX buffers instead of just failing. 1149 */ 1150 atw_rxdrain(sc); 1151 goto out; 1152 } 1153 } else 1154 ATW_INIT_RXDESC(sc, i); 1155 } 1156 sc->sc_rxptr = 0; 1157 1158 /* disable all wake-up events */ 1159 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1160 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1161 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1162 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1163 1164 /* ack all wake-up events */ 1165 ATW_SET(sc, ATW_WCSR, 0); 1166 1167 /* 1168 * Initialize the interrupt mask and enable interrupts. 1169 */ 1170 /* normal interrupts */ 1171 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1172 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1173 1174 /* abnormal interrupts */ 1175 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1176 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1177 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1178 1179 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1180 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1181 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1182 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1183 ATW_INTR_TRT; 1184 1185 sc->sc_linkint_mask &= sc->sc_inten; 1186 sc->sc_rxint_mask &= sc->sc_inten; 1187 sc->sc_txint_mask &= sc->sc_inten; 1188 1189 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1190 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1191 if (sc->sc_intr_ack != NULL) 1192 (*sc->sc_intr_ack)(sc); 1193 1194 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1195 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1196 1197 /* 1198 * Give the transmit and receive rings to the ADM8211. 1199 */ 1200 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1201 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1202 1203 /* common 802.11 configuration */ 1204 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1205 switch (ic->ic_opmode) { 1206 case IEEE80211_M_STA: 1207 sc->sc_opmode &= ~ATW_NAR_EA; 1208 break; 1209 case IEEE80211_M_AHDEMO: /* XXX */ 1210 case IEEE80211_M_IBSS: 1211 ic->ic_flags |= IEEE80211_F_IBSSON; 1212 /*FALLTHROUGH*/ 1213 case IEEE80211_M_HOSTAP: /* XXX */ 1214 /* EA bit seems important for ad hoc reception. */ 1215 sc->sc_opmode |= ATW_NAR_EA; 1216 break; 1217 case IEEE80211_M_MONITOR: /* XXX */ 1218 break; 1219 } 1220 1221 atw_start_beacon(sc, 0); 1222 1223 switch (ic->ic_opmode) { 1224 case IEEE80211_M_AHDEMO: 1225 case IEEE80211_M_HOSTAP: 1226 ic->ic_bss->ni_intval = ic->ic_lintval; 1227 ic->ic_bss->ni_rssi = 0; 1228 ic->ic_bss->ni_rstamp = 0; 1229 break; 1230 default: /* XXX */ 1231 break; 1232 } 1233 1234 atw_write_ssid(sc); 1235 atw_write_sup_rates(sc); 1236 if (ic->ic_caps & IEEE80211_C_WEP) 1237 atw_write_wep(sc); 1238 1239 /* 1240 * Set the receive filter. This will start the transmit and 1241 * receive processes. 1242 */ 1243 atw_filter_setup(sc); 1244 1245 /* 1246 * Start the receive process. 1247 */ 1248 ATW_WRITE(sc, ATW_RDR, 0x1); 1249 1250 /* 1251 * Note that the interface is now running. 1252 */ 1253 ifp->if_flags |= IFF_RUNNING; 1254 ifp->if_flags &= ~IFF_OACTIVE; 1255 ic->ic_state = IEEE80211_S_INIT; 1256 1257 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1258 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1259 else 1260 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1261 out: 1262 if (error) { 1263 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1264 ifp->if_timer = 0; 1265 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1266 } 1267 #ifdef ATW_DEBUG 1268 atw_print_regs(sc, "end of init"); 1269 #endif /* ATW_DEBUG */ 1270 1271 return (error); 1272 } 1273 1274 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1275 * 0: MAC control of RF3000/Si4126. 1276 * 1277 * Applies power, or selects RF front-end? Sets reset condition. 1278 * 1279 * TBD support non-RFMD BBP, non-SiLabs synth. 1280 */ 1281 static void 1282 atw_rfio_enable(struct atw_softc *sc, int enable) 1283 { 1284 if (enable) { 1285 ATW_WRITE(sc, ATW_SYNRF, 1286 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1287 DELAY(atw_rfio_enable_delay); 1288 } else { 1289 ATW_WRITE(sc, ATW_SYNRF, 0); 1290 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1291 } 1292 } 1293 1294 static int 1295 atw_tune(struct atw_softc *sc) 1296 { 1297 int rc; 1298 u_int32_t reg; 1299 int chan; 1300 struct ieee80211com *ic = &sc->sc_ic; 1301 1302 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1303 if (chan == IEEE80211_CHAN_ANY) 1304 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1305 1306 if (chan == sc->sc_cur_chan) 1307 return 0; 1308 1309 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1310 sc->sc_cur_chan, chan)); 1311 1312 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1313 1314 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1315 (rc = atw_rf3000_tune(sc, chan)) != 0) 1316 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1317 chan); 1318 1319 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1320 ATW_WRITE(sc, ATW_CAP0, 1321 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1322 1323 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1324 1325 if (rc == 0) 1326 sc->sc_cur_chan = chan; 1327 1328 return rc; 1329 } 1330 1331 #ifdef ATW_DEBUG 1332 static void 1333 atw_si4126_print(struct atw_softc *sc) 1334 { 1335 struct ifnet *ifp = &sc->sc_ic.ic_if; 1336 u_int addr, val; 1337 1338 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1339 return; 1340 1341 for (addr = 0; addr <= 8; addr++) { 1342 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1343 if (atw_si4126_read(sc, addr, &val) == 0) { 1344 printf("<unknown> (quitting print-out)\n"); 1345 break; 1346 } 1347 printf("%05x\n", val); 1348 } 1349 } 1350 #endif /* ATW_DEBUG */ 1351 1352 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1353 * 1354 * The RF/IF synthesizer produces two reference frequencies for 1355 * the RF2948B transceiver. The first frequency the RF2948B requires 1356 * is two times the so-called "intermediate frequency" (IF). Since 1357 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1358 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1359 * frequency required by the transceiver is the radio frequency 1360 * (RF). This is a superheterodyne transceiver; for f(chan) the 1361 * center frequency of the channel we are tuning, RF = f(chan) - 1362 * IF. 1363 * 1364 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1365 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1366 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1367 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1368 */ 1369 static int 1370 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1371 { 1372 int rc = 0; 1373 u_int mhz; 1374 u_int R; 1375 u_int32_t reg; 1376 u_int16_t gain; 1377 1378 #ifdef ATW_DEBUG 1379 atw_si4126_print(sc); 1380 #endif /* ATW_DEBUG */ 1381 1382 if (chan == 14) 1383 mhz = 2484; 1384 else 1385 mhz = 2412 + 5 * (chan - 1); 1386 1387 /* Tune IF to 748MHz to suit the IF LO input of the 1388 * RF2494B, which is 2 x IF. No need to set an IF divider 1389 * because an IF in 526MHz - 952MHz is allowed. 1390 * 1391 * XIN is 44.000MHz, so divide it by two to get allowable 1392 * range of 2-25MHz. SiLabs tells me that this is not 1393 * strictly necessary. 1394 */ 1395 1396 R = 44; 1397 1398 atw_rfio_enable(sc, 1); 1399 1400 /* Power-up RF, IF synthesizers. */ 1401 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1402 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1403 goto out; 1404 1405 /* If RF2 N > 2047, then set KP2 to 1. */ 1406 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1407 1408 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1409 goto out; 1410 1411 /* set LPWR, too? */ 1412 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1413 SI4126_MAIN_XINDIV2)) != 0) 1414 goto out; 1415 1416 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1417 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1418 */ 1419 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1420 goto out; 1421 1422 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1423 goto out; 1424 1425 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1426 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1427 * which has no RF1! 1428 */ 1429 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1430 goto out; 1431 1432 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1433 goto out; 1434 1435 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1436 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1437 * Now let's multiply it to mhz. So mhz - IF = N. 1438 */ 1439 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1440 goto out; 1441 1442 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1443 goto out; 1444 1445 /* wait 100us from power-up for RF, IF to settle */ 1446 DELAY(100); 1447 1448 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1449 /* XXX there is a binary driver which sends 1450 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1451 * that this enables the Si4126 by raising its PWDN#, but I 1452 * think that it actually sets the Prism RF front-end 1453 * to a special mode for channel 14. 1454 */ 1455 reg = ATW_READ(sc, ATW_GPIO); 1456 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1457 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1458 ATW_WRITE(sc, ATW_GPIO, reg); 1459 } 1460 1461 #ifdef ATW_DEBUG 1462 atw_si4126_print(sc); 1463 #endif /* ATW_DEBUG */ 1464 1465 out: 1466 atw_rfio_enable(sc, 0); 1467 1468 return rc; 1469 } 1470 1471 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1472 * diversity. 1473 * 1474 * Call this w/ Tx/Rx suspended. 1475 */ 1476 static int 1477 atw_rf3000_init(struct atw_softc *sc) 1478 { 1479 int rc = 0; 1480 1481 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1482 1483 atw_rfio_enable(sc, 1); 1484 1485 /* enable diversity */ 1486 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1487 1488 if (rc != 0) 1489 goto out; 1490 1491 /* sensible setting from a binary-only driver */ 1492 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1493 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1494 1495 if (rc != 0) 1496 goto out; 1497 1498 /* magic from a binary-only driver */ 1499 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1500 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1501 1502 if (rc != 0) 1503 goto out; 1504 1505 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1506 1507 if (rc != 0) 1508 goto out; 1509 1510 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1511 1512 if (rc != 0) 1513 goto out; 1514 1515 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1516 1517 if (rc != 0) 1518 goto out; 1519 1520 /* CCA is acquisition sensitive */ 1521 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1522 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1523 1524 if (rc != 0) 1525 goto out; 1526 1527 out: 1528 atw_rfio_enable(sc, 0); 1529 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1530 return rc; 1531 } 1532 1533 #ifdef ATW_DEBUG 1534 static void 1535 atw_rf3000_print(struct atw_softc *sc) 1536 { 1537 struct ifnet *ifp = &sc->sc_ic.ic_if; 1538 u_int addr, val; 1539 1540 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1541 return; 1542 1543 for (addr = 0x01; addr <= 0x15; addr++) { 1544 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1545 if (atw_rf3000_read(sc, addr, &val) != 0) { 1546 printf("<unknown> (quitting print-out)\n"); 1547 break; 1548 } 1549 printf("%08x\n", val); 1550 } 1551 } 1552 #endif /* ATW_DEBUG */ 1553 1554 /* Set the power settings on the BBP for channel `chan'. */ 1555 static int 1556 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1557 { 1558 int rc = 0; 1559 u_int32_t reg; 1560 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1561 1562 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1563 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1564 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1565 1566 /* odd channels: LSB, even channels: MSB */ 1567 if (chan % 2 == 1) { 1568 txpower &= 0xFF; 1569 lpf_cutoff &= 0xFF; 1570 lna_gs_thresh &= 0xFF; 1571 } else { 1572 txpower >>= 8; 1573 lpf_cutoff >>= 8; 1574 lna_gs_thresh >>= 8; 1575 } 1576 1577 #ifdef ATW_DEBUG 1578 atw_rf3000_print(sc); 1579 #endif /* ATW_DEBUG */ 1580 1581 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1582 "lna_gs_thresh %02x\n", 1583 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1584 1585 atw_rfio_enable(sc, 1); 1586 1587 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1588 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1589 goto out; 1590 1591 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1592 goto out; 1593 1594 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1595 goto out; 1596 1597 /* from a binary-only driver. */ 1598 reg = ATW_READ(sc, ATW_PLCPHD); 1599 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1600 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1601 ATW_PLCPHD_SERVICE_MASK); 1602 ATW_WRITE(sc, ATW_PLCPHD, reg); 1603 1604 #ifdef ATW_DEBUG 1605 atw_rf3000_print(sc); 1606 #endif /* ATW_DEBUG */ 1607 1608 out: 1609 atw_rfio_enable(sc, 0); 1610 1611 return rc; 1612 } 1613 1614 /* Write a register on the RF3000 baseband processor using the 1615 * registers provided by the ADM8211 for this purpose. 1616 * 1617 * Return 0 on success. 1618 */ 1619 static int 1620 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1621 { 1622 u_int32_t reg; 1623 int i; 1624 1625 for (i = 1000; --i >= 0; ) { 1626 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1627 break; 1628 DELAY(100); 1629 } 1630 1631 if (i < 0) { 1632 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1633 return ETIMEDOUT; 1634 } 1635 1636 reg = sc->sc_bbpctl_wr | 1637 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1638 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1639 1640 ATW_WRITE(sc, ATW_BBPCTL, reg); 1641 1642 for (i = 1000; --i >= 0; ) { 1643 DELAY(100); 1644 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1645 break; 1646 } 1647 1648 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1649 1650 if (i < 0) { 1651 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1652 return ETIMEDOUT; 1653 } 1654 return 0; 1655 } 1656 1657 /* Read a register on the RF3000 baseband processor using the registers 1658 * the ADM8211 provides for this purpose. 1659 * 1660 * The 7-bit register address is addr. Record the 8-bit data in the register 1661 * in *val. 1662 * 1663 * Return 0 on success. 1664 * 1665 * XXX This does not seem to work. The ADM8211 must require more or 1666 * different magic to read the chip than to write it. Possibly some 1667 * of the magic I have derived from a binary-only driver concerns 1668 * the "chip address" (see the RF3000 manual). 1669 */ 1670 #ifdef ATW_DEBUG 1671 static int 1672 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1673 { 1674 u_int32_t reg; 1675 int i; 1676 1677 for (i = 1000; --i >= 0; ) { 1678 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1679 break; 1680 DELAY(100); 1681 } 1682 1683 if (i < 0) { 1684 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1685 sc->sc_dev.dv_xname); 1686 return ETIMEDOUT; 1687 } 1688 1689 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1690 1691 ATW_WRITE(sc, ATW_BBPCTL, reg); 1692 1693 for (i = 1000; --i >= 0; ) { 1694 DELAY(100); 1695 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1696 break; 1697 } 1698 1699 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1700 1701 if (i < 0) { 1702 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1703 sc->sc_dev.dv_xname, reg); 1704 return ETIMEDOUT; 1705 } 1706 if (val != NULL) 1707 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1708 return 0; 1709 } 1710 #endif /* ATW_DEBUG */ 1711 1712 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1713 * provided by the ADM8211 for that purpose. 1714 * 1715 * val is 18 bits of data, and val is the 4-bit address of the register. 1716 * 1717 * Return 0 on success. 1718 */ 1719 static int 1720 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1721 { 1722 u_int32_t bits, reg; 1723 int i; 1724 1725 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1726 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1727 1728 for (i = 1000; --i >= 0; ) { 1729 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1730 break; 1731 DELAY(100); 1732 } 1733 1734 if (i < 0) { 1735 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1736 sc->sc_dev.dv_xname); 1737 return ETIMEDOUT; 1738 } 1739 1740 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1741 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1742 1743 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1744 1745 ATW_WRITE(sc, ATW_SYNCTL, reg); 1746 1747 for (i = 1000; --i >= 0; ) { 1748 DELAY(100); 1749 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1750 break; 1751 } 1752 1753 /* restore to acceptable starting condition */ 1754 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1755 1756 if (i < 0) { 1757 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1758 sc->sc_dev.dv_xname, reg); 1759 return ETIMEDOUT; 1760 } 1761 return 0; 1762 } 1763 1764 /* Read 18-bit data from the 4-bit address addr in Si4126 1765 * RF synthesizer and write the data to *val. Return 0 on success. 1766 * 1767 * XXX This does not seem to work. The ADM8211 must require more or 1768 * different magic to read the chip than to write it. 1769 */ 1770 #ifdef ATW_DEBUG 1771 static int 1772 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1773 { 1774 u_int32_t reg; 1775 int i; 1776 1777 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1778 1779 for (i = 1000; --i >= 0; ) { 1780 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1781 break; 1782 DELAY(100); 1783 } 1784 1785 if (i < 0) { 1786 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1787 sc->sc_dev.dv_xname); 1788 return ETIMEDOUT; 1789 } 1790 1791 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1792 1793 ATW_WRITE(sc, ATW_SYNCTL, reg); 1794 1795 for (i = 1000; --i >= 0; ) { 1796 DELAY(100); 1797 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1798 break; 1799 } 1800 1801 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1802 1803 if (i < 0) { 1804 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1805 sc->sc_dev.dv_xname, reg); 1806 return ETIMEDOUT; 1807 } 1808 if (val != NULL) 1809 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1810 ATW_SYNCTL_DATA_MASK); 1811 return 0; 1812 } 1813 #endif /* ATW_DEBUG */ 1814 1815 /* XXX is the endianness correct? test. */ 1816 #define atw_calchash(addr) \ 1817 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1818 1819 /* 1820 * atw_filter_setup: 1821 * 1822 * Set the ADM8211's receive filter. 1823 */ 1824 static void 1825 atw_filter_setup(struct atw_softc *sc) 1826 { 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ethercom *ec = &ic->ic_ec; 1829 struct ifnet *ifp = &sc->sc_ic.ic_if; 1830 int hash; 1831 u_int32_t hashes[2] = { 0, 0 }; 1832 struct ether_multi *enm; 1833 struct ether_multistep step; 1834 1835 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1836 sc->sc_dev.dv_xname, sc->sc_flags)); 1837 1838 /* 1839 * If we're running, idle the receive engine. If we're NOT running, 1840 * we're being called from atw_init(), and our writing ATW_NAR will 1841 * start the transmit and receive processes in motion. 1842 */ 1843 if (ifp->if_flags & IFF_RUNNING) 1844 atw_idle(sc, ATW_NAR_SR); 1845 1846 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1847 1848 ifp->if_flags &= ~IFF_ALLMULTI; 1849 1850 if (ifp->if_flags & IFF_PROMISC) { 1851 sc->sc_opmode |= ATW_NAR_PR; 1852 allmulti: 1853 ifp->if_flags |= IFF_ALLMULTI; 1854 goto setit; 1855 } 1856 1857 /* 1858 * Program the 64-bit multicast hash filter. 1859 */ 1860 ETHER_FIRST_MULTI(step, ec, enm); 1861 while (enm != NULL) { 1862 /* XXX */ 1863 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1864 ETHER_ADDR_LEN) != 0) 1865 goto allmulti; 1866 1867 hash = atw_calchash(enm->enm_addrlo); 1868 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1869 ETHER_NEXT_MULTI(step, enm); 1870 } 1871 1872 if (ifp->if_flags & IFF_BROADCAST) { 1873 hash = atw_calchash(etherbroadcastaddr); 1874 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1875 } 1876 1877 /* all bits set => hash is useless */ 1878 if (~(hashes[0] & hashes[1]) == 0) 1879 goto allmulti; 1880 1881 setit: 1882 if (ifp->if_flags & IFF_ALLMULTI) 1883 sc->sc_opmode |= ATW_NAR_MM; 1884 1885 /* XXX in scan mode, do not filter packets. maybe this is 1886 * unnecessary. 1887 */ 1888 if (ic->ic_state == IEEE80211_S_SCAN) 1889 sc->sc_opmode |= ATW_NAR_PR; 1890 1891 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1892 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1893 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1894 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1895 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1896 1897 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1898 } 1899 1900 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1901 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1902 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1903 * no beacon with the preferred BSSID and SSID in the number of 1904 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1905 */ 1906 static void 1907 atw_write_bssid(struct atw_softc *sc) 1908 { 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 u_int8_t *bssid; 1911 1912 bssid = ic->ic_bss->ni_bssid; 1913 1914 ATW_WRITE(sc, ATW_ABDA1, 1915 (ATW_READ(sc, ATW_ABDA1) & 1916 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1917 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1918 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1919 1920 ATW_WRITE(sc, ATW_BSSID0, 1921 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1922 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1923 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1924 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1925 1926 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1927 ether_sprintf(sc->sc_bssid))); 1928 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1929 1930 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1931 } 1932 1933 /* Tell the ADM8211 how many beacon intervals must pass without 1934 * receiving a beacon with the preferred BSSID & SSID set by 1935 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1936 * raised. 1937 */ 1938 static void 1939 atw_write_bcn_thresh(struct atw_softc *sc) 1940 { 1941 struct ieee80211com *ic = &sc->sc_ic; 1942 int lost_bcn_thresh; 1943 1944 /* Lose link after one second or 7 beacons, whichever comes 1945 * first, but do not lose link before 2 beacons are lost. 1946 * 1947 * In host AP mode, set the lost-beacon threshold to 0. 1948 */ 1949 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1950 lost_bcn_thresh = 0; 1951 else { 1952 int beacons_per_second = 1953 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1954 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1955 } 1956 1957 /* XXX resets wake-up status bits */ 1958 ATW_WRITE(sc, ATW_WCSR, 1959 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1960 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1961 1962 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1963 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1964 1965 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1966 1967 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1968 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1969 } 1970 1971 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1972 * 16-bit word. 1973 */ 1974 static void 1975 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1976 { 1977 u_int i; 1978 u_int8_t *ptr; 1979 1980 memcpy(&sc->sc_sram[ofs], buf, buflen); 1981 1982 if (ofs % 2 != 0) { 1983 ofs--; 1984 buflen++; 1985 } 1986 1987 if (buflen % 2 != 0) 1988 buflen++; 1989 1990 assert(buflen + ofs <= ATW_SRAM_SIZE); 1991 1992 ptr = &sc->sc_sram[ofs]; 1993 1994 for (i = 0; i < buflen; i += 2) { 1995 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1996 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1997 DELAY(atw_writewep_delay); 1998 1999 ATW_WRITE(sc, ATW_WESK, 2000 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2001 DELAY(atw_writewep_delay); 2002 } 2003 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2004 2005 if (sc->sc_if.if_flags & IFF_DEBUG) { 2006 int n_octets = 0; 2007 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2008 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2009 for (i = 0; i < buflen; i++) { 2010 printf(" %02x", ptr[i]); 2011 if (++n_octets % 24 == 0) 2012 printf("\n"); 2013 } 2014 if (n_octets % 24 != 0) 2015 printf("\n"); 2016 } 2017 } 2018 2019 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2020 static void 2021 atw_write_wep(struct atw_softc *sc) 2022 { 2023 struct ieee80211com *ic = &sc->sc_ic; 2024 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2025 u_int8_t buf[IEEE80211_WEP_NKID] 2026 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2027 u_int32_t reg; 2028 int i; 2029 2030 sc->sc_wepctl = 0; 2031 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2032 2033 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2034 return; 2035 2036 memset(&buf[0][0], 0, sizeof(buf)); 2037 2038 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2039 if (ic->ic_nw_keys[i].wk_len > 5) { 2040 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2041 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2042 buf[i][1] = ATW_WEP_ENABLED; 2043 } else { 2044 buf[i][1] = 0; 2045 continue; 2046 } 2047 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2048 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2049 ic->ic_nw_keys[i].wk_len - 1); 2050 } 2051 2052 reg = ATW_READ(sc, ATW_MACTEST); 2053 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2054 reg &= ~ATW_MACTEST_KEYID_MASK; 2055 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2056 ATW_WRITE(sc, ATW_MACTEST, reg); 2057 2058 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2059 * throughout.) 2060 */ 2061 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2062 if (sc->sc_if.if_flags & IFF_LINK2) 2063 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2064 2065 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2066 sizeof(buf)); 2067 } 2068 2069 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2070 2071 static void 2072 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2073 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2074 { 2075 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2076 2077 switch (subtype) { 2078 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2079 /* do nothing: hardware answers probe request */ 2080 break; 2081 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2082 case IEEE80211_FC0_SUBTYPE_BEACON: 2083 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2084 break; 2085 default: 2086 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2087 break; 2088 } 2089 return; 2090 } 2091 2092 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2093 * of IBSSs with like SSID/channel but different BSSID. It joins the 2094 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2095 * convention. Possibly the ADMtek chip does this for us; I will have 2096 * to test to find out. 2097 * 2098 * XXX we should add the duration field of the received beacon to 2099 * the TSF time it contains before comparing it with the ADM8211's 2100 * TSF. 2101 */ 2102 static void 2103 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2104 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2105 { 2106 struct atw_softc *sc; 2107 struct ieee80211_frame *wh; 2108 u_int64_t tsft, bcn_tsft; 2109 u_int32_t tsftl, tsfth; 2110 int do_print = 0; 2111 2112 sc = (struct atw_softc*)ic->ic_if.if_softc; 2113 2114 if (ic->ic_if.if_flags & IFF_DEBUG) 2115 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2116 ? 1 : ratecheck(&sc->sc_last_beacon, 2117 &atw_beacon_mininterval); 2118 2119 wh = mtod(m0, struct ieee80211_frame *); 2120 2121 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2122 2123 if (ic->ic_state != IEEE80211_S_RUN) { 2124 if (do_print) 2125 printf("%s: atw_recv_beacon: not running\n", 2126 sc->sc_dev.dv_xname); 2127 return; 2128 } 2129 2130 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2131 ic->ic_bss->ni_chan)) == NULL) { 2132 if (do_print) 2133 printf("%s: atw_recv_beacon: no node %s\n", 2134 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2135 return; 2136 } 2137 2138 if (ieee80211_match_bss(ic, ni) != 0) { 2139 if (do_print) 2140 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2141 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2142 return; 2143 } 2144 2145 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2146 return; 2147 2148 if (do_print) 2149 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2150 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2151 2152 if (ic->ic_opmode != IEEE80211_M_IBSS) 2153 return; 2154 2155 /* If we read TSFTL right before rollover, we read a TSF timer 2156 * that is too high rather than too low. This prevents a spurious 2157 * synchronization down the line, however, our IBSS could suffer 2158 * from a creeping TSF.... 2159 */ 2160 tsftl = ATW_READ(sc, ATW_TSFTL); 2161 tsfth = ATW_READ(sc, ATW_TSFTH); 2162 2163 tsft = (u_int64_t)tsfth << 32 | tsftl; 2164 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2165 2166 if (do_print) 2167 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2168 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2169 2170 /* we are faster, let the other guy catch up */ 2171 if (bcn_tsft < tsft) 2172 return; 2173 2174 if (do_print) 2175 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2176 ether_sprintf(wh->i_addr2)); 2177 2178 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2179 2180 #if 0 2181 atw_tsf(sc); 2182 #endif 2183 2184 /* negotiate rates with new IBSS */ 2185 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2186 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2187 if (ni->ni_rates.rs_nrates == 0) { 2188 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2189 ether_sprintf(ni->ni_bssid)); 2190 return; 2191 } 2192 2193 if (do_print) { 2194 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2195 ether_sprintf(ic->ic_bss->ni_bssid)); 2196 printf("%s ", ether_sprintf(ni->ni_bssid)); 2197 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2198 } 2199 2200 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2201 2202 atw_write_bssid(sc); 2203 atw_write_bcn_thresh(sc); 2204 atw_start_beacon(sc, 1); 2205 } 2206 2207 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2208 * In ad hoc mode, the SSID is written to the beacons sent by the 2209 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2210 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2211 * indications. 2212 */ 2213 static void 2214 atw_write_ssid(struct atw_softc *sc) 2215 { 2216 struct ieee80211com *ic = &sc->sc_ic; 2217 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2218 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2219 2220 memset(buf, 0, sizeof(buf)); 2221 buf[0] = ic->ic_bss->ni_esslen; 2222 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2223 2224 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2225 } 2226 2227 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2228 * In ad hoc mode, the supported rates are written to beacons sent by the 2229 * ADM8211. 2230 */ 2231 static void 2232 atw_write_sup_rates(struct atw_softc *sc) 2233 { 2234 struct ieee80211com *ic = &sc->sc_ic; 2235 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2236 * supported rates 2237 */ 2238 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2239 2240 memset(buf, 0, sizeof(buf)); 2241 2242 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2243 2244 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2245 ic->ic_bss->ni_rates.rs_nrates); 2246 2247 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2248 } 2249 2250 /* Start/stop sending beacons. */ 2251 void 2252 atw_start_beacon(struct atw_softc *sc, int start) 2253 { 2254 struct ieee80211com *ic = &sc->sc_ic; 2255 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2256 2257 if (ATW_IS_ENABLED(sc) == 0) 2258 return; 2259 2260 len = capinfo = 0; 2261 2262 /* start beacons */ 2263 len = sizeof(struct ieee80211_frame) + 2264 8 /* timestamp */ + 2 /* beacon interval */ + 2265 2 /* capability info */ + 2266 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2267 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2268 3 /* DS parameters */ + 2269 IEEE80211_CRC_LEN; 2270 2271 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2272 2273 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2274 2275 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2276 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2277 2278 if (!start) 2279 return; 2280 2281 /* TBD use ni_capinfo */ 2282 2283 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2284 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2285 if (ic->ic_flags & IEEE80211_F_WEPON) 2286 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2287 2288 switch (ic->ic_opmode) { 2289 case IEEE80211_M_IBSS: 2290 len += 4; /* IBSS parameters */ 2291 capinfo |= IEEE80211_CAPINFO_IBSS; 2292 break; 2293 case IEEE80211_M_HOSTAP: 2294 /* XXX 6-byte minimum TIM */ 2295 len += atw_beacon_len_adjust; 2296 capinfo |= IEEE80211_CAPINFO_ESS; 2297 break; 2298 default: 2299 return; 2300 } 2301 2302 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2303 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2304 2305 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2306 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2307 2308 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2309 sc->sc_dev.dv_xname, reg_bcnt)); 2310 2311 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2312 sc->sc_dev.dv_xname, reg_cap1)); 2313 } 2314 2315 /* First beacon was sent at time 0 microseconds, current time is 2316 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2317 * microseconds. Return the expected time in microseconds for the 2318 * beacon after next. 2319 */ 2320 static __inline u_int64_t 2321 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2322 { 2323 return tsft + (tbtt - tsft % tbtt); 2324 } 2325 2326 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2327 * the ieee80211com. 2328 * 2329 * Predict the next target beacon transmission time (TBTT) and 2330 * write it to the ADM8211. 2331 */ 2332 static void 2333 atw_tsf(struct atw_softc *sc) 2334 { 2335 #define TBTTOFS 20 /* TU */ 2336 2337 struct ieee80211com *ic = &sc->sc_ic; 2338 u_int64_t tsft, tbtt; 2339 2340 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2341 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2342 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2343 tsft = ATW_READ(sc, ATW_TSFTH); 2344 tsft <<= 32; 2345 tsft |= ATW_READ(sc, ATW_TSFTL); 2346 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2347 } else 2348 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2349 2350 tbtt = atw_predict_beacon(tsft, 2351 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2352 2353 /* skip one more beacon so that the TBTT cannot pass before 2354 * we've programmed it, and also so that we can subtract a 2355 * few TU so that we wake a little before TBTT. 2356 */ 2357 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2358 2359 /* wake up a little early */ 2360 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2361 2362 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2363 sc->sc_dev.dv_xname, tsft, tbtt)); 2364 2365 ATW_WRITE(sc, ATW_TOFS1, 2366 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2367 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2368 LSHIFT( 2369 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2370 ATW_TOFS1_TBTTPRE_MASK)); 2371 #undef TBTTOFS 2372 } 2373 2374 static void 2375 atw_next_scan(void *arg) 2376 { 2377 struct atw_softc *sc = arg; 2378 struct ieee80211com *ic = &sc->sc_ic; 2379 struct ifnet *ifp = &ic->ic_if; 2380 int s; 2381 2382 /* don't call atw_start w/o network interrupts blocked */ 2383 s = splnet(); 2384 if (ic->ic_state == IEEE80211_S_SCAN) 2385 ieee80211_next_scan(ifp); 2386 splx(s); 2387 } 2388 2389 /* Synchronize the hardware state with the software state. */ 2390 static int 2391 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2392 { 2393 struct ifnet *ifp = &ic->ic_if; 2394 struct atw_softc *sc = ifp->if_softc; 2395 enum ieee80211_state ostate; 2396 int error; 2397 2398 ostate = ic->ic_state; 2399 2400 if (nstate == IEEE80211_S_INIT) { 2401 callout_stop(&sc->sc_scan_ch); 2402 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2403 atw_start_beacon(sc, 0); 2404 return (*sc->sc_newstate)(ic, nstate, arg); 2405 } 2406 2407 if ((error = atw_tune(sc)) != 0) 2408 return error; 2409 2410 switch (nstate) { 2411 case IEEE80211_S_ASSOC: 2412 break; 2413 case IEEE80211_S_INIT: 2414 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2415 break; 2416 case IEEE80211_S_SCAN: 2417 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2418 atw_write_bssid(sc); 2419 2420 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2421 atw_next_scan, sc); 2422 2423 break; 2424 case IEEE80211_S_RUN: 2425 if (ic->ic_opmode == IEEE80211_M_STA) 2426 break; 2427 /*FALLTHROUGH*/ 2428 case IEEE80211_S_AUTH: 2429 atw_write_bssid(sc); 2430 atw_write_bcn_thresh(sc); 2431 atw_write_ssid(sc); 2432 atw_write_sup_rates(sc); 2433 2434 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2435 ic->ic_opmode == IEEE80211_M_MONITOR) 2436 break; 2437 2438 /* set listen interval 2439 * XXX do software units agree w/ hardware? 2440 */ 2441 ATW_WRITE(sc, ATW_BPLI, 2442 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2443 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2444 ATW_BPLI_LI_MASK)); 2445 2446 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2447 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2448 2449 atw_tsf(sc); 2450 break; 2451 } 2452 2453 if (nstate != IEEE80211_S_SCAN) 2454 callout_stop(&sc->sc_scan_ch); 2455 2456 if (nstate == IEEE80211_S_RUN && 2457 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2458 ic->ic_opmode == IEEE80211_M_IBSS)) 2459 atw_start_beacon(sc, 1); 2460 else 2461 atw_start_beacon(sc, 0); 2462 2463 return (*sc->sc_newstate)(ic, nstate, arg); 2464 } 2465 2466 /* 2467 * atw_add_rxbuf: 2468 * 2469 * Add a receive buffer to the indicated descriptor. 2470 */ 2471 int 2472 atw_add_rxbuf(struct atw_softc *sc, int idx) 2473 { 2474 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2475 struct mbuf *m; 2476 int error; 2477 2478 MGETHDR(m, M_DONTWAIT, MT_DATA); 2479 if (m == NULL) 2480 return (ENOBUFS); 2481 2482 MCLGET(m, M_DONTWAIT); 2483 if ((m->m_flags & M_EXT) == 0) { 2484 m_freem(m); 2485 return (ENOBUFS); 2486 } 2487 2488 if (rxs->rxs_mbuf != NULL) 2489 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2490 2491 rxs->rxs_mbuf = m; 2492 2493 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2494 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2495 BUS_DMA_READ|BUS_DMA_NOWAIT); 2496 if (error) { 2497 printf("%s: can't load rx DMA map %d, error = %d\n", 2498 sc->sc_dev.dv_xname, idx, error); 2499 panic("atw_add_rxbuf"); /* XXX */ 2500 } 2501 2502 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2503 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2504 2505 ATW_INIT_RXDESC(sc, idx); 2506 2507 return (0); 2508 } 2509 2510 /* 2511 * Release any queued transmit buffers. 2512 */ 2513 void 2514 atw_txdrain(struct atw_softc *sc) 2515 { 2516 struct atw_txsoft *txs; 2517 2518 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2519 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2520 if (txs->txs_mbuf != NULL) { 2521 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2522 m_freem(txs->txs_mbuf); 2523 txs->txs_mbuf = NULL; 2524 } 2525 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2526 } 2527 sc->sc_tx_timer = 0; 2528 } 2529 2530 /* 2531 * atw_stop: [ ifnet interface function ] 2532 * 2533 * Stop transmission on the interface. 2534 */ 2535 void 2536 atw_stop(struct ifnet *ifp, int disable) 2537 { 2538 struct atw_softc *sc = ifp->if_softc; 2539 struct ieee80211com *ic = &sc->sc_ic; 2540 2541 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2542 2543 /* Disable interrupts. */ 2544 ATW_WRITE(sc, ATW_IER, 0); 2545 2546 /* Stop the transmit and receive processes. */ 2547 sc->sc_opmode = 0; 2548 ATW_WRITE(sc, ATW_NAR, 0); 2549 ATW_WRITE(sc, ATW_TDBD, 0); 2550 ATW_WRITE(sc, ATW_TDBP, 0); 2551 ATW_WRITE(sc, ATW_RDB, 0); 2552 2553 atw_txdrain(sc); 2554 2555 if (disable) { 2556 atw_rxdrain(sc); 2557 atw_disable(sc); 2558 } 2559 2560 /* 2561 * Mark the interface down and cancel the watchdog timer. 2562 */ 2563 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2564 ifp->if_timer = 0; 2565 2566 if (!disable) 2567 atw_reset(sc); 2568 } 2569 2570 /* 2571 * atw_rxdrain: 2572 * 2573 * Drain the receive queue. 2574 */ 2575 void 2576 atw_rxdrain(struct atw_softc *sc) 2577 { 2578 struct atw_rxsoft *rxs; 2579 int i; 2580 2581 for (i = 0; i < ATW_NRXDESC; i++) { 2582 rxs = &sc->sc_rxsoft[i]; 2583 if (rxs->rxs_mbuf == NULL) 2584 continue; 2585 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2586 m_freem(rxs->rxs_mbuf); 2587 rxs->rxs_mbuf = NULL; 2588 } 2589 } 2590 2591 /* 2592 * atw_detach: 2593 * 2594 * Detach an ADM8211 interface. 2595 */ 2596 int 2597 atw_detach(struct atw_softc *sc) 2598 { 2599 struct ifnet *ifp = &sc->sc_ic.ic_if; 2600 struct atw_rxsoft *rxs; 2601 struct atw_txsoft *txs; 2602 int i; 2603 2604 /* 2605 * Succeed now if there isn't any work to do. 2606 */ 2607 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2608 return (0); 2609 2610 ieee80211_ifdetach(ifp); 2611 if_detach(ifp); 2612 2613 for (i = 0; i < ATW_NRXDESC; i++) { 2614 rxs = &sc->sc_rxsoft[i]; 2615 if (rxs->rxs_mbuf != NULL) { 2616 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2617 m_freem(rxs->rxs_mbuf); 2618 rxs->rxs_mbuf = NULL; 2619 } 2620 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2621 } 2622 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2623 txs = &sc->sc_txsoft[i]; 2624 if (txs->txs_mbuf != NULL) { 2625 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2626 m_freem(txs->txs_mbuf); 2627 txs->txs_mbuf = NULL; 2628 } 2629 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2630 } 2631 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2632 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2633 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2634 sizeof(struct atw_control_data)); 2635 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2636 2637 shutdownhook_disestablish(sc->sc_sdhook); 2638 powerhook_disestablish(sc->sc_powerhook); 2639 2640 if (sc->sc_srom) 2641 free(sc->sc_srom, M_DEVBUF); 2642 2643 return (0); 2644 } 2645 2646 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2647 void 2648 atw_shutdown(void *arg) 2649 { 2650 struct atw_softc *sc = arg; 2651 2652 atw_stop(&sc->sc_ic.ic_if, 1); 2653 } 2654 2655 int 2656 atw_intr(void *arg) 2657 { 2658 struct atw_softc *sc = arg; 2659 struct ifnet *ifp = &sc->sc_ic.ic_if; 2660 u_int32_t status, rxstatus, txstatus, linkstatus; 2661 int handled = 0, txthresh; 2662 2663 #ifdef DEBUG 2664 if (ATW_IS_ENABLED(sc) == 0) 2665 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2666 #endif 2667 2668 /* 2669 * If the interface isn't running, the interrupt couldn't 2670 * possibly have come from us. 2671 */ 2672 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2673 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2674 return (0); 2675 2676 for (;;) { 2677 status = ATW_READ(sc, ATW_STSR); 2678 2679 if (status) 2680 ATW_WRITE(sc, ATW_STSR, status); 2681 2682 if (sc->sc_intr_ack != NULL) 2683 (*sc->sc_intr_ack)(sc); 2684 2685 #ifdef ATW_DEBUG 2686 #define PRINTINTR(flag) do { \ 2687 if ((status & flag) != 0) { \ 2688 printf("%s" #flag, delim); \ 2689 delim = ","; \ 2690 } \ 2691 } while (0) 2692 2693 if (atw_debug > 1 && status) { 2694 const char *delim = "<"; 2695 2696 printf("%s: reg[STSR] = %x", 2697 sc->sc_dev.dv_xname, status); 2698 2699 PRINTINTR(ATW_INTR_FBE); 2700 PRINTINTR(ATW_INTR_LINKOFF); 2701 PRINTINTR(ATW_INTR_LINKON); 2702 PRINTINTR(ATW_INTR_RCI); 2703 PRINTINTR(ATW_INTR_RDU); 2704 PRINTINTR(ATW_INTR_REIS); 2705 PRINTINTR(ATW_INTR_RPS); 2706 PRINTINTR(ATW_INTR_TCI); 2707 PRINTINTR(ATW_INTR_TDU); 2708 PRINTINTR(ATW_INTR_TLT); 2709 PRINTINTR(ATW_INTR_TPS); 2710 PRINTINTR(ATW_INTR_TRT); 2711 PRINTINTR(ATW_INTR_TUF); 2712 PRINTINTR(ATW_INTR_BCNTC); 2713 PRINTINTR(ATW_INTR_ATIME); 2714 PRINTINTR(ATW_INTR_TBTT); 2715 PRINTINTR(ATW_INTR_TSCZ); 2716 PRINTINTR(ATW_INTR_TSFTF); 2717 printf(">\n"); 2718 } 2719 #undef PRINTINTR 2720 #endif /* ATW_DEBUG */ 2721 2722 if ((status & sc->sc_inten) == 0) 2723 break; 2724 2725 handled = 1; 2726 2727 rxstatus = status & sc->sc_rxint_mask; 2728 txstatus = status & sc->sc_txint_mask; 2729 linkstatus = status & sc->sc_linkint_mask; 2730 2731 if (linkstatus) { 2732 atw_linkintr(sc, linkstatus); 2733 } 2734 2735 if (rxstatus) { 2736 /* Grab any new packets. */ 2737 atw_rxintr(sc); 2738 2739 if (rxstatus & ATW_INTR_RDU) { 2740 printf("%s: receive ring overrun\n", 2741 sc->sc_dev.dv_xname); 2742 /* Get the receive process going again. */ 2743 ATW_WRITE(sc, ATW_RDR, 0x1); 2744 break; 2745 } 2746 } 2747 2748 if (txstatus) { 2749 /* Sweep up transmit descriptors. */ 2750 atw_txintr(sc); 2751 2752 if (txstatus & ATW_INTR_TLT) 2753 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2754 sc->sc_dev.dv_xname)); 2755 2756 if (txstatus & ATW_INTR_TRT) 2757 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2758 sc->sc_dev.dv_xname)); 2759 2760 /* If Tx under-run, increase our transmit threshold 2761 * if another is available. 2762 */ 2763 txthresh = sc->sc_txthresh + 1; 2764 if ((txstatus & ATW_INTR_TUF) && 2765 sc->sc_txth[txthresh].txth_name != NULL) { 2766 /* Idle the transmit process. */ 2767 atw_idle(sc, ATW_NAR_ST); 2768 2769 sc->sc_txthresh = txthresh; 2770 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2771 sc->sc_opmode |= 2772 sc->sc_txth[txthresh].txth_opmode; 2773 printf("%s: transmit underrun; new " 2774 "threshold: %s\n", sc->sc_dev.dv_xname, 2775 sc->sc_txth[txthresh].txth_name); 2776 2777 /* Set the new threshold and restart 2778 * the transmit process. 2779 */ 2780 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2781 /* XXX Log every Nth underrun from 2782 * XXX now on? 2783 */ 2784 } 2785 } 2786 2787 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2788 if (status & ATW_INTR_TPS) 2789 printf("%s: transmit process stopped\n", 2790 sc->sc_dev.dv_xname); 2791 if (status & ATW_INTR_RPS) 2792 printf("%s: receive process stopped\n", 2793 sc->sc_dev.dv_xname); 2794 (void)atw_init(ifp); 2795 break; 2796 } 2797 2798 if (status & ATW_INTR_FBE) { 2799 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2800 (void)atw_init(ifp); 2801 break; 2802 } 2803 2804 /* 2805 * Not handled: 2806 * 2807 * Transmit buffer unavailable -- normal 2808 * condition, nothing to do, really. 2809 * 2810 * Early receive interrupt -- not available on 2811 * all chips, we just use RI. We also only 2812 * use single-segment receive DMA, so this 2813 * is mostly useless. 2814 * 2815 * TBD others 2816 */ 2817 } 2818 2819 /* Try to get more packets going. */ 2820 atw_start(ifp); 2821 2822 return (handled); 2823 } 2824 2825 /* 2826 * atw_idle: 2827 * 2828 * Cause the transmit and/or receive processes to go idle. 2829 * 2830 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2831 * process in STSR if I clear SR or ST after the process has already 2832 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2833 * do not seem to be too reliable. Perhaps I have the sense of the 2834 * Rx bits switched with the Tx bits? 2835 */ 2836 void 2837 atw_idle(struct atw_softc *sc, u_int32_t bits) 2838 { 2839 u_int32_t ackmask = 0, opmode, stsr, test0; 2840 int i, s; 2841 2842 /* without this, somehow we run concurrently w/ interrupt handler */ 2843 s = splnet(); 2844 2845 opmode = sc->sc_opmode & ~bits; 2846 2847 if (bits & ATW_NAR_SR) 2848 ackmask |= ATW_INTR_RPS; 2849 2850 if (bits & ATW_NAR_ST) { 2851 ackmask |= ATW_INTR_TPS; 2852 /* set ATW_NAR_HF to flush TX FIFO. */ 2853 opmode |= ATW_NAR_HF; 2854 } 2855 2856 ATW_WRITE(sc, ATW_NAR, opmode); 2857 2858 for (i = 0; i < 1000; i++) { 2859 stsr = ATW_READ(sc, ATW_STSR); 2860 if ((stsr & ackmask) == ackmask) 2861 break; 2862 DELAY(10); 2863 } 2864 2865 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2866 2867 if ((stsr & ackmask) == ackmask) 2868 goto out; 2869 2870 test0 = ATW_READ(sc, ATW_TEST0); 2871 2872 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2873 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2874 printf("%s: transmit process not idle [%s]\n", 2875 sc->sc_dev.dv_xname, 2876 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2877 printf("%s: bits %08x test0 %08x stsr %08x\n", 2878 sc->sc_dev.dv_xname, bits, test0, stsr); 2879 } 2880 2881 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2882 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2883 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2884 sc->sc_dev.dv_xname, 2885 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2886 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2887 sc->sc_dev.dv_xname, bits, test0, stsr)); 2888 } 2889 out: 2890 if ((bits & ATW_NAR_ST) != 0) 2891 atw_txdrain(sc); 2892 splx(s); 2893 return; 2894 } 2895 2896 /* 2897 * atw_linkintr: 2898 * 2899 * Helper; handle link-status interrupts. 2900 */ 2901 void 2902 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2903 { 2904 struct ieee80211com *ic = &sc->sc_ic; 2905 2906 if (ic->ic_state != IEEE80211_S_RUN) 2907 return; 2908 2909 if (linkstatus & ATW_INTR_LINKON) { 2910 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2911 sc->sc_rescan_timer = 0; 2912 } else if (linkstatus & ATW_INTR_LINKOFF) { 2913 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2914 if (ic->ic_opmode != IEEE80211_M_STA) 2915 return; 2916 sc->sc_rescan_timer = 3; 2917 ic->ic_if.if_timer = 1; 2918 } 2919 } 2920 2921 /* 2922 * atw_rxintr: 2923 * 2924 * Helper; handle receive interrupts. 2925 */ 2926 void 2927 atw_rxintr(struct atw_softc *sc) 2928 { 2929 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2930 struct ieee80211com *ic = &sc->sc_ic; 2931 struct ieee80211_node *ni; 2932 struct ieee80211_frame *wh; 2933 struct ifnet *ifp = &ic->ic_if; 2934 struct atw_rxsoft *rxs; 2935 struct mbuf *m; 2936 u_int32_t rxstat; 2937 int i, len, rate, rate0; 2938 u_int32_t rssi; 2939 2940 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2941 rxs = &sc->sc_rxsoft[i]; 2942 2943 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2944 2945 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2946 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2947 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2948 2949 if (rxstat & ATW_RXSTAT_OWN) 2950 break; /* We have processed all receive buffers. */ 2951 2952 DPRINTF3(sc, 2953 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2954 sc->sc_dev.dv_xname, 2955 sc->sc_rxdescs[i].ar_stat, 2956 sc->sc_rxdescs[i].ar_rssi, 2957 sc->sc_rxdescs[i].ar_buf1, 2958 sc->sc_rxdescs[i].ar_buf2)); 2959 2960 /* 2961 * Make sure the packet fits in one buffer. This should 2962 * always be the case. 2963 */ 2964 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2965 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2966 printf("%s: incoming packet spilled, resetting\n", 2967 sc->sc_dev.dv_xname); 2968 (void)atw_init(ifp); 2969 return; 2970 } 2971 2972 /* 2973 * If an error occurred, update stats, clear the status 2974 * word, and leave the packet buffer in place. It will 2975 * simply be reused the next time the ring comes around. 2976 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2977 * error. 2978 */ 2979 2980 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2981 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2982 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2983 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2984 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2985 ATW_RXSTAT_ICVE)) != 0)) { 2986 #define PRINTERR(bit, str) \ 2987 if (rxstat & (bit)) \ 2988 printf("%s: receive error: %s\n", \ 2989 sc->sc_dev.dv_xname, str) 2990 ifp->if_ierrors++; 2991 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2992 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2993 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2994 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2995 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2996 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2997 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2998 #undef PRINTERR 2999 ATW_INIT_RXDESC(sc, i); 3000 continue; 3001 } 3002 3003 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3004 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3005 3006 /* 3007 * No errors; receive the packet. Note the ADM8211 3008 * includes the CRC in promiscuous mode. 3009 */ 3010 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3011 3012 /* 3013 * Allocate a new mbuf cluster. If that fails, we are 3014 * out of memory, and must drop the packet and recycle 3015 * the buffer that's already attached to this descriptor. 3016 */ 3017 m = rxs->rxs_mbuf; 3018 if (atw_add_rxbuf(sc, i) != 0) { 3019 ifp->if_ierrors++; 3020 ATW_INIT_RXDESC(sc, i); 3021 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3022 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3023 continue; 3024 } 3025 3026 ifp->if_ipackets++; 3027 if (sc->sc_opmode & ATW_NAR_PR) 3028 m->m_flags |= M_HASFCS; 3029 m->m_pkthdr.rcvif = ifp; 3030 m->m_pkthdr.len = m->m_len = len; 3031 3032 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3033 rate = 0; 3034 else 3035 rate = rate_tbl[rate0]; 3036 3037 #if NBPFILTER > 0 3038 /* Pass this up to any BPF listeners. */ 3039 if (sc->sc_radiobpf != NULL) { 3040 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3041 3042 tap->ar_rate = rate; 3043 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3044 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3045 3046 /* TBD verify units are dB */ 3047 tap->ar_antsignal = (int)rssi; 3048 /* TBD tap->ar_flags */ 3049 3050 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3051 tap->ar_ihdr.it_len, m); 3052 } 3053 #endif /* NPBFILTER > 0 */ 3054 3055 wh = mtod(m, struct ieee80211_frame *); 3056 ni = ieee80211_find_rxnode(ic, wh); 3057 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3058 /* 3059 * The frame may have caused the node to be marked for 3060 * reclamation (e.g. in response to a DEAUTH message) 3061 * so use free_node here instead of unref_node. 3062 */ 3063 if (ni == ic->ic_bss) 3064 ieee80211_unref_node(&ni); 3065 else 3066 ieee80211_free_node(ic, ni); 3067 } 3068 3069 /* Update the receive pointer. */ 3070 sc->sc_rxptr = i; 3071 } 3072 3073 /* 3074 * atw_txintr: 3075 * 3076 * Helper; handle transmit interrupts. 3077 */ 3078 void 3079 atw_txintr(struct atw_softc *sc) 3080 { 3081 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3082 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3083 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3084 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3085 3086 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3087 struct ifnet *ifp = &sc->sc_ic.ic_if; 3088 struct atw_txsoft *txs; 3089 u_int32_t txstat; 3090 3091 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3092 sc->sc_dev.dv_xname, sc->sc_flags)); 3093 3094 ifp->if_flags &= ~IFF_OACTIVE; 3095 3096 /* 3097 * Go through our Tx list and free mbufs for those 3098 * frames that have been transmitted. 3099 */ 3100 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3101 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3102 txs->txs_ndescs, 3103 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3104 3105 #ifdef ATW_DEBUG 3106 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3107 int i; 3108 printf(" txsoft %p transmit chain:\n", txs); 3109 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3110 printf(" descriptor %d:\n", i); 3111 printf(" at_status: 0x%08x\n", 3112 le32toh(sc->sc_txdescs[i].at_stat)); 3113 printf(" at_flags: 0x%08x\n", 3114 le32toh(sc->sc_txdescs[i].at_flags)); 3115 printf(" at_buf1: 0x%08x\n", 3116 le32toh(sc->sc_txdescs[i].at_buf1)); 3117 printf(" at_buf2: 0x%08x\n", 3118 le32toh(sc->sc_txdescs[i].at_buf2)); 3119 if (i == txs->txs_lastdesc) 3120 break; 3121 } 3122 } 3123 #endif 3124 3125 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3126 if (txstat & ATW_TXSTAT_OWN) 3127 break; 3128 3129 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3130 3131 sc->sc_txfree += txs->txs_ndescs; 3132 3133 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3134 0, txs->txs_dmamap->dm_mapsize, 3135 BUS_DMASYNC_POSTWRITE); 3136 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3137 m_freem(txs->txs_mbuf); 3138 txs->txs_mbuf = NULL; 3139 3140 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3141 3142 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3143 (txstat & TXSTAT_ERRMASK) != 0) { 3144 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3145 txstat_buf, sizeof(txstat_buf)); 3146 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3147 txstat_buf, 3148 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3149 } 3150 3151 /* 3152 * Check for errors and collisions. 3153 */ 3154 if (txstat & ATW_TXSTAT_TUF) 3155 sc->sc_stats.ts_tx_tuf++; 3156 if (txstat & ATW_TXSTAT_TLT) 3157 sc->sc_stats.ts_tx_tlt++; 3158 if (txstat & ATW_TXSTAT_TRT) 3159 sc->sc_stats.ts_tx_trt++; 3160 if (txstat & ATW_TXSTAT_TRO) 3161 sc->sc_stats.ts_tx_tro++; 3162 if (txstat & ATW_TXSTAT_SOFBR) { 3163 sc->sc_stats.ts_tx_sofbr++; 3164 } 3165 3166 if ((txstat & ATW_TXSTAT_ES) == 0) 3167 ifp->if_collisions += 3168 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3169 else 3170 ifp->if_oerrors++; 3171 3172 ifp->if_opackets++; 3173 } 3174 3175 /* 3176 * If there are no more pending transmissions, cancel the watchdog 3177 * timer. 3178 */ 3179 if (txs == NULL) 3180 sc->sc_tx_timer = 0; 3181 #undef TXSTAT_ERRMASK 3182 #undef TXSTAT_FMT 3183 } 3184 3185 /* 3186 * atw_watchdog: [ifnet interface function] 3187 * 3188 * Watchdog timer handler. 3189 */ 3190 void 3191 atw_watchdog(struct ifnet *ifp) 3192 { 3193 struct atw_softc *sc = ifp->if_softc; 3194 struct ieee80211com *ic = &sc->sc_ic; 3195 3196 ifp->if_timer = 0; 3197 if (ATW_IS_ENABLED(sc) == 0) 3198 return; 3199 3200 if (sc->sc_rescan_timer) { 3201 if (--sc->sc_rescan_timer == 0) 3202 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3203 } 3204 if (sc->sc_tx_timer) { 3205 if (--sc->sc_tx_timer == 0 && 3206 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3207 printf("%s: transmit timeout\n", ifp->if_xname); 3208 ifp->if_oerrors++; 3209 (void)atw_init(ifp); 3210 atw_start(ifp); 3211 } 3212 } 3213 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3214 ifp->if_timer = 1; 3215 ieee80211_watchdog(ifp); 3216 } 3217 3218 /* Compute the 802.11 Duration field and the PLCP Length fields for 3219 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3220 * Write the fields to the ADM8211 Tx header, frm. 3221 * 3222 * TBD use the fragmentation threshold to find the right duration for 3223 * the first & last fragments. 3224 * 3225 * TBD make certain of the duration fields applied by the ADM8211 to each 3226 * fragment. I think that the ADM8211 knows how to subtract the CTS 3227 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3228 * I also think that the ADM8211 does *some* arithmetic for us, because 3229 * otherwise I think we would have to set a first duration for CTS/first 3230 * fragment, a second duration for fragments between the first and the 3231 * last, and a third duration for the last fragment. 3232 * 3233 * TBD make certain that duration fields reflect addition of FCS/WEP 3234 * and correct duration arithmetic as necessary. 3235 */ 3236 static void 3237 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3238 int len) 3239 { 3240 int remainder; 3241 3242 /* deal also with encrypted fragments */ 3243 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3244 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3245 sc->sc_dev.dv_xname)); 3246 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3247 IEEE80211_WEP_CRCLEN; 3248 } 3249 3250 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3251 * duration (XXX added by MAC?). 3252 */ 3253 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3254 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3255 3256 if (rate <= 4) 3257 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3258 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3259 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3260 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3261 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3262 else 3263 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3264 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3265 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3266 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3267 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3268 3269 /* lengthen duration if long preamble */ 3270 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3271 frm->atw_head_dur += 3272 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3273 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3274 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3275 IEEE80211_DUR_DS_FAST_PLCPHDR); 3276 3277 if (remainder != 0) 3278 frm->atw_head_dur++; 3279 3280 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3281 (rate == 2 || rate == 4)) { 3282 /* derived from Linux: how could this be right? */ 3283 frm->atw_head_plcplen = frm->atw_head_dur; 3284 } else { 3285 frm->atw_head_plcplen = (16 * len) / rate; 3286 remainder = (80 * len) % (rate * 5); 3287 3288 if (remainder != 0) { 3289 frm->atw_head_plcplen++; 3290 3291 /* XXX magic */ 3292 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3293 rate == 22 && remainder <= 30) 3294 frm->atw_head_plcplen |= 0x8000; 3295 } 3296 } 3297 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3298 htole16(frm->atw_head_plcplen); 3299 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3300 } 3301 3302 #ifdef ATW_DEBUG 3303 static void 3304 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3305 { 3306 struct atw_softc *sc = ifp->if_softc; 3307 struct mbuf *m; 3308 int i, noctets = 0; 3309 3310 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3311 m0->m_pkthdr.len); 3312 3313 for (m = m0; m; m = m->m_next) { 3314 if (m->m_len == 0) 3315 continue; 3316 for (i = 0; i < m->m_len; i++) { 3317 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3318 if (++noctets % 24 == 0) 3319 printf("\n"); 3320 } 3321 } 3322 printf("%s%s: %d bytes emitted\n", 3323 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3324 } 3325 #endif /* ATW_DEBUG */ 3326 3327 /* 3328 * atw_start: [ifnet interface function] 3329 * 3330 * Start packet transmission on the interface. 3331 */ 3332 void 3333 atw_start(struct ifnet *ifp) 3334 { 3335 struct atw_softc *sc = ifp->if_softc; 3336 struct ieee80211com *ic = &sc->sc_ic; 3337 struct ieee80211_node *ni; 3338 struct ieee80211_frame *wh; 3339 struct atw_frame *hh; 3340 struct mbuf *m0, *m; 3341 struct atw_txsoft *txs, *last_txs; 3342 struct atw_txdesc *txd; 3343 int do_encrypt, rate; 3344 bus_dmamap_t dmamap; 3345 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3346 3347 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3348 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3349 3350 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3351 return; 3352 3353 #if 0 /* TBD ??? */ 3354 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3355 return; 3356 #endif 3357 3358 /* 3359 * Remember the previous number of free descriptors and 3360 * the first descriptor we'll use. 3361 */ 3362 ofree = sc->sc_txfree; 3363 firsttx = sc->sc_txnext; 3364 3365 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3366 sc->sc_dev.dv_xname, ofree, firsttx)); 3367 3368 /* 3369 * Loop through the send queue, setting up transmit descriptors 3370 * until we drain the queue, or use up all available transmit 3371 * descriptors. 3372 */ 3373 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3374 sc->sc_txfree != 0) { 3375 3376 /* 3377 * Grab a packet off the management queue, if it 3378 * is not empty. Otherwise, from the data queue. 3379 */ 3380 IF_DEQUEUE(&ic->ic_mgtq, m0); 3381 if (m0 != NULL) { 3382 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3383 m0->m_pkthdr.rcvif = NULL; 3384 } else { 3385 IFQ_DEQUEUE(&ifp->if_snd, m0); 3386 if (m0 == NULL) 3387 break; 3388 #if NBPFILTER > 0 3389 if (ifp->if_bpf != NULL) 3390 bpf_mtap(ifp->if_bpf, m0); 3391 #endif /* NBPFILTER > 0 */ 3392 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3393 ifp->if_oerrors++; 3394 break; 3395 } 3396 } 3397 3398 rate = MAX(ieee80211_get_rate(ic), 2); 3399 3400 #if NBPFILTER > 0 3401 /* 3402 * Pass the packet to any BPF listeners. 3403 */ 3404 if (ic->ic_rawbpf != NULL) 3405 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3406 3407 if (sc->sc_radiobpf != NULL) { 3408 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3409 3410 tap->at_rate = rate; 3411 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3412 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3413 3414 /* TBD tap->at_flags */ 3415 3416 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3417 tap->at_ihdr.it_len, m0); 3418 } 3419 #endif /* NBPFILTER > 0 */ 3420 3421 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3422 3423 if (ni != NULL && ni != ic->ic_bss) 3424 ieee80211_free_node(ic, ni); 3425 3426 if (m0 == NULL) { 3427 ifp->if_oerrors++; 3428 break; 3429 } 3430 3431 /* just to make sure. */ 3432 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3433 3434 if (m0 == NULL) { 3435 ifp->if_oerrors++; 3436 break; 3437 } 3438 3439 hh = mtod(m0, struct atw_frame *); 3440 wh = &hh->atw_ihdr; 3441 3442 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3443 3444 /* Copy everything we need from the 802.11 header: 3445 * Frame Control; address 1, address 3, or addresses 3446 * 3 and 4. NIC fills in BSSID, SA. 3447 */ 3448 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3449 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3450 panic("%s: illegal WDS frame", 3451 sc->sc_dev.dv_xname); 3452 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3453 } else 3454 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3455 3456 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3457 3458 /* initialize remaining Tx parameters */ 3459 memset(&hh->u, 0, sizeof(hh->u)); 3460 3461 hh->atw_rate = rate * 5; 3462 /* XXX this could be incorrect if M_FCS. _encap should 3463 * probably strip FCS just in case it sticks around in 3464 * bridged packets. 3465 */ 3466 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3467 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3468 sizeof(struct atw_frame)); 3469 3470 #if 0 3471 /* this virtually guaranteed that WEP-encrypted frames 3472 * are fragmented. oops. 3473 */ 3474 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3475 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3476 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3477 #else 3478 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3479 #endif 3480 3481 hh->atw_rtylmt = 3; 3482 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3483 if (do_encrypt) { 3484 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3485 hh->atw_keyid = ic->ic_wep_txkey; 3486 } 3487 3488 /* TBD 4-addr frames */ 3489 atw_frame_setdurs(sc, hh, rate, 3490 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3491 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3492 3493 /* never fragment multicast frames */ 3494 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3495 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3496 } else if (sc->sc_flags & ATWF_RTSCTS) { 3497 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3498 } 3499 3500 #ifdef ATW_DEBUG 3501 /* experimental stuff */ 3502 if (atw_xrtylmt != ~0) 3503 hh->atw_rtylmt = atw_xrtylmt; 3504 if (atw_xhdrctl != 0) 3505 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3506 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3507 hh->atw_service = atw_xservice; 3508 if (atw_xpaylen != 0) 3509 hh->atw_paylen = htole16(atw_xpaylen); 3510 hh->atw_fragnum = 0; 3511 3512 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3513 printf("%s: dst = %s, rate = 0x%02x, " 3514 "service = 0x%02x, paylen = 0x%04x\n", 3515 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3516 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3517 3518 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3519 "dur1 = 0x%04x, dur2 = 0x%04x, " 3520 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3521 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3522 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3523 hh->atw_tail_dur, hh->atw_head_dur); 3524 3525 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3526 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3527 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3528 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3529 3530 printf("%s: keyid = %d\n", 3531 sc->sc_dev.dv_xname, hh->atw_keyid); 3532 3533 atw_dump_pkt(ifp, m0); 3534 } 3535 #endif /* ATW_DEBUG */ 3536 3537 dmamap = txs->txs_dmamap; 3538 3539 /* 3540 * Load the DMA map. Copy and try (once) again if the packet 3541 * didn't fit in the alloted number of segments. 3542 */ 3543 for (first = 1; 3544 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3545 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3546 first = 0) { 3547 MGETHDR(m, M_DONTWAIT, MT_DATA); 3548 if (m == NULL) { 3549 printf("%s: unable to allocate Tx mbuf\n", 3550 sc->sc_dev.dv_xname); 3551 break; 3552 } 3553 if (m0->m_pkthdr.len > MHLEN) { 3554 MCLGET(m, M_DONTWAIT); 3555 if ((m->m_flags & M_EXT) == 0) { 3556 printf("%s: unable to allocate Tx " 3557 "cluster\n", sc->sc_dev.dv_xname); 3558 m_freem(m); 3559 break; 3560 } 3561 } 3562 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3563 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3564 m_freem(m0); 3565 m0 = m; 3566 m = NULL; 3567 } 3568 if (error != 0) { 3569 printf("%s: unable to load Tx buffer, " 3570 "error = %d\n", sc->sc_dev.dv_xname, error); 3571 m_freem(m0); 3572 break; 3573 } 3574 3575 /* 3576 * Ensure we have enough descriptors free to describe 3577 * the packet. 3578 */ 3579 if (dmamap->dm_nsegs > sc->sc_txfree) { 3580 /* 3581 * Not enough free descriptors to transmit 3582 * this packet. Unload the DMA map and 3583 * drop the packet. Notify the upper layer 3584 * that there are no more slots left. 3585 * 3586 * XXX We could allocate an mbuf and copy, but 3587 * XXX it is worth it? 3588 */ 3589 ifp->if_flags |= IFF_OACTIVE; 3590 bus_dmamap_unload(sc->sc_dmat, dmamap); 3591 m_freem(m0); 3592 break; 3593 } 3594 3595 /* 3596 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3597 */ 3598 3599 /* Sync the DMA map. */ 3600 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3601 BUS_DMASYNC_PREWRITE); 3602 3603 /* XXX arbitrary retry limit; 8 because I have seen it in 3604 * use already and maybe 0 means "no tries" ! 3605 */ 3606 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3607 3608 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3609 sc->sc_dev.dv_xname, rate * 5)); 3610 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3611 3612 /* 3613 * Initialize the transmit descriptors. 3614 */ 3615 for (nexttx = sc->sc_txnext, seg = 0; 3616 seg < dmamap->dm_nsegs; 3617 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3618 /* 3619 * If this is the first descriptor we're 3620 * enqueueing, don't set the OWN bit just 3621 * yet. That could cause a race condition. 3622 * We'll do it below. 3623 */ 3624 txd = &sc->sc_txdescs[nexttx]; 3625 txd->at_ctl = ctl | 3626 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3627 3628 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3629 txd->at_flags = 3630 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3631 ATW_TXFLAG_TBS1_MASK)) | 3632 ((nexttx == (ATW_NTXDESC - 1)) 3633 ? htole32(ATW_TXFLAG_TER) : 0); 3634 lasttx = nexttx; 3635 } 3636 3637 IASSERT(lasttx != -1, ("bad lastx")); 3638 /* Set `first segment' and `last segment' appropriately. */ 3639 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3640 htole32(ATW_TXFLAG_FS); 3641 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3642 3643 #ifdef ATW_DEBUG 3644 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3645 printf(" txsoft %p transmit chain:\n", txs); 3646 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3647 printf(" descriptor %d:\n", seg); 3648 printf(" at_ctl: 0x%08x\n", 3649 le32toh(sc->sc_txdescs[seg].at_ctl)); 3650 printf(" at_flags: 0x%08x\n", 3651 le32toh(sc->sc_txdescs[seg].at_flags)); 3652 printf(" at_buf1: 0x%08x\n", 3653 le32toh(sc->sc_txdescs[seg].at_buf1)); 3654 printf(" at_buf2: 0x%08x\n", 3655 le32toh(sc->sc_txdescs[seg].at_buf2)); 3656 if (seg == lasttx) 3657 break; 3658 } 3659 } 3660 #endif 3661 3662 /* Sync the descriptors we're using. */ 3663 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3664 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3665 3666 /* 3667 * Store a pointer to the packet so we can free it later, 3668 * and remember what txdirty will be once the packet is 3669 * done. 3670 */ 3671 txs->txs_mbuf = m0; 3672 txs->txs_firstdesc = sc->sc_txnext; 3673 txs->txs_lastdesc = lasttx; 3674 txs->txs_ndescs = dmamap->dm_nsegs; 3675 3676 /* Advance the tx pointer. */ 3677 sc->sc_txfree -= dmamap->dm_nsegs; 3678 sc->sc_txnext = nexttx; 3679 3680 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3681 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3682 3683 last_txs = txs; 3684 } 3685 3686 if (txs == NULL || sc->sc_txfree == 0) { 3687 /* No more slots left; notify upper layer. */ 3688 ifp->if_flags |= IFF_OACTIVE; 3689 } 3690 3691 if (sc->sc_txfree != ofree) { 3692 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3693 sc->sc_dev.dv_xname, lasttx, firsttx)); 3694 /* 3695 * Cause a transmit interrupt to happen on the 3696 * last packet we enqueued. 3697 */ 3698 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3699 ATW_CDTXSYNC(sc, lasttx, 1, 3700 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3701 3702 /* 3703 * The entire packet chain is set up. Give the 3704 * first descriptor to the chip now. 3705 */ 3706 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3707 ATW_CDTXSYNC(sc, firsttx, 1, 3708 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3709 3710 /* Wake up the transmitter. */ 3711 ATW_WRITE(sc, ATW_TDR, 0x1); 3712 3713 /* Set a watchdog timer in case the chip flakes out. */ 3714 sc->sc_tx_timer = 5; 3715 ifp->if_timer = 1; 3716 } 3717 } 3718 3719 /* 3720 * atw_power: 3721 * 3722 * Power management (suspend/resume) hook. 3723 */ 3724 void 3725 atw_power(int why, void *arg) 3726 { 3727 struct atw_softc *sc = arg; 3728 struct ifnet *ifp = &sc->sc_ic.ic_if; 3729 int s; 3730 3731 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3732 3733 s = splnet(); 3734 switch (why) { 3735 case PWR_STANDBY: 3736 /* XXX do nothing. */ 3737 break; 3738 case PWR_SUSPEND: 3739 atw_stop(ifp, 0); 3740 if (sc->sc_power != NULL) 3741 (*sc->sc_power)(sc, why); 3742 break; 3743 case PWR_RESUME: 3744 if (ifp->if_flags & IFF_UP) { 3745 if (sc->sc_power != NULL) 3746 (*sc->sc_power)(sc, why); 3747 atw_init(ifp); 3748 } 3749 break; 3750 case PWR_SOFTSUSPEND: 3751 case PWR_SOFTSTANDBY: 3752 case PWR_SOFTRESUME: 3753 break; 3754 } 3755 splx(s); 3756 } 3757 3758 /* 3759 * atw_ioctl: [ifnet interface function] 3760 * 3761 * Handle control requests from the operator. 3762 */ 3763 int 3764 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3765 { 3766 struct atw_softc *sc = ifp->if_softc; 3767 struct ifreq *ifr = (struct ifreq *)data; 3768 int s, error = 0; 3769 3770 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3771 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3772 return ENXIO; 3773 3774 s = splnet(); 3775 3776 switch (cmd) { 3777 case SIOCSIFFLAGS: 3778 if (ifp->if_flags & IFF_UP) { 3779 if (ATW_IS_ENABLED(sc)) { 3780 /* 3781 * To avoid rescanning another access point, 3782 * do not call atw_init() here. Instead, 3783 * only reflect media settings. 3784 */ 3785 atw_filter_setup(sc); 3786 } else 3787 error = atw_init(ifp); 3788 } else if (ATW_IS_ENABLED(sc)) 3789 atw_stop(ifp, 1); 3790 break; 3791 case SIOCADDMULTI: 3792 case SIOCDELMULTI: 3793 error = (cmd == SIOCADDMULTI) ? 3794 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3795 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3796 if (error == ENETRESET) { 3797 if (ATW_IS_ENABLED(sc)) 3798 atw_filter_setup(sc); /* do not rescan */ 3799 error = 0; 3800 } 3801 break; 3802 default: 3803 error = ieee80211_ioctl(ifp, cmd, data); 3804 if (error == ENETRESET) { 3805 if (ATW_IS_ENABLED(sc)) 3806 error = atw_init(ifp); 3807 else 3808 error = 0; 3809 } 3810 break; 3811 } 3812 3813 /* Try to get more packets going. */ 3814 if (ATW_IS_ENABLED(sc)) 3815 atw_start(ifp); 3816 3817 splx(s); 3818 return (error); 3819 } 3820 3821 static int 3822 atw_media_change(struct ifnet *ifp) 3823 { 3824 int error; 3825 3826 error = ieee80211_media_change(ifp); 3827 if (error == ENETRESET) { 3828 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3829 (IFF_RUNNING|IFF_UP)) 3830 atw_init(ifp); /* XXX lose error */ 3831 error = 0; 3832 } 3833 return error; 3834 } 3835 3836 static void 3837 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3838 { 3839 struct atw_softc *sc = ifp->if_softc; 3840 3841 if (ATW_IS_ENABLED(sc) == 0) { 3842 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3843 imr->ifm_status = 0; 3844 return; 3845 } 3846 ieee80211_media_status(ifp, imr); 3847 } 3848
Indexes created Tue Sep 23 14:10:03 GMT 2025