atw.c revision 1.38
1 /* $NetBSD: atw.c,v 1.38 2004/07/15 05:43:50 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.38 2004/07/15 05:43:50 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 139 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 140 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 141 142 int atw_rfio_enable_delay = 20 * 1000; 143 int atw_rfio_disable_delay = 2 * 1000; 144 int atw_writewep_delay = 5; 145 int atw_beacon_len_adjust = 4; 146 int atw_dwelltime = 200; 147 148 #ifdef ATW_DEBUG 149 int atw_xhdrctl = 0; 150 int atw_xrtylmt = ~0; 151 int atw_xservice = IEEE80211_PLCP_SERVICE; 152 int atw_xpaylen = 0; 153 154 int atw_debug = 0; 155 156 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 157 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 158 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 159 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 160 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 161 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 162 static void atw_print_regs(struct atw_softc *, const char *); 163 static void atw_rf3000_print(struct atw_softc *); 164 static void atw_si4126_print(struct atw_softc *); 165 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 166 #else 167 #define ATW_DPRINTF(x) 168 #define ATW_DPRINTF2(x) 169 #define ATW_DPRINTF3(x) 170 #define DPRINTF(sc, x) /* nothing */ 171 #define DPRINTF2(sc, x) /* nothing */ 172 #define DPRINTF3(sc, x) /* nothing */ 173 #endif 174 175 #ifdef ATW_STATS 176 void atw_print_stats(struct atw_softc *); 177 #endif 178 179 void atw_start(struct ifnet *); 180 void atw_watchdog(struct ifnet *); 181 int atw_ioctl(struct ifnet *, u_long, caddr_t); 182 int atw_init(struct ifnet *); 183 void atw_txdrain(struct atw_softc *); 184 void atw_stop(struct ifnet *, int); 185 186 void atw_reset(struct atw_softc *); 187 int atw_read_srom(struct atw_softc *); 188 189 void atw_shutdown(void *); 190 191 void atw_rxdrain(struct atw_softc *); 192 int atw_add_rxbuf(struct atw_softc *, int); 193 void atw_idle(struct atw_softc *, u_int32_t); 194 195 int atw_enable(struct atw_softc *); 196 void atw_disable(struct atw_softc *); 197 void atw_power(int, void *); 198 199 void atw_rxintr(struct atw_softc *); 200 void atw_txintr(struct atw_softc *); 201 void atw_linkintr(struct atw_softc *, u_int32_t); 202 203 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 204 static void atw_tsf(struct atw_softc *); 205 static void atw_start_beacon(struct atw_softc *, int); 206 static void atw_write_wep(struct atw_softc *); 207 static void atw_write_bssid(struct atw_softc *); 208 static void atw_write_bcn_thresh(struct atw_softc *); 209 static void atw_write_ssid(struct atw_softc *); 210 static void atw_write_sup_rates(struct atw_softc *); 211 static void atw_clear_sram(struct atw_softc *); 212 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 213 static int atw_media_change(struct ifnet *); 214 static void atw_media_status(struct ifnet *, struct ifmediareq *); 215 static void atw_filter_setup(struct atw_softc *); 216 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 217 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 218 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 219 struct ieee80211_node *, int, int, u_int32_t); 220 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 221 struct ieee80211_node *, int, int, u_int32_t); 222 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 223 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 224 225 static int atw_tune(struct atw_softc *); 226 227 static void atw_rfio_enable(struct atw_softc *, int); 228 229 /* RFMD RF3000 Baseband Processor */ 230 static int atw_rf3000_init(struct atw_softc *); 231 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 232 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 233 #ifdef ATW_DEBUG 234 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 235 #endif /* ATW_DEBUG */ 236 237 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 238 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 239 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 240 #ifdef ATW_DEBUG 241 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 242 #endif /* ATW_DEBUG */ 243 244 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 245 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 246 247 const char *atw_tx_state[] = { 248 "STOPPED", 249 "RUNNING - read descriptor", 250 "RUNNING - transmitting", 251 "RUNNING - filling fifo", /* XXX */ 252 "SUSPENDED", 253 "RUNNING -- write descriptor", 254 "RUNNING -- write last descriptor", 255 "RUNNING - fifo full" 256 }; 257 258 const char *atw_rx_state[] = { 259 "STOPPED", 260 "RUNNING - read descriptor", 261 "RUNNING - check this packet, pre-fetch next", 262 "RUNNING - wait for reception", 263 "SUSPENDED", 264 "RUNNING - write descriptor", 265 "RUNNING - flush fifo", 266 "RUNNING - fifo drain" 267 }; 268 269 int 270 atw_activate(struct device *self, enum devact act) 271 { 272 struct atw_softc *sc = (struct atw_softc *)self; 273 int rv = 0, s; 274 275 s = splnet(); 276 switch (act) { 277 case DVACT_ACTIVATE: 278 rv = EOPNOTSUPP; 279 break; 280 281 case DVACT_DEACTIVATE: 282 if_deactivate(&sc->sc_ic.ic_if); 283 break; 284 } 285 splx(s); 286 return rv; 287 } 288 289 /* 290 * atw_enable: 291 * 292 * Enable the ADM8211 chip. 293 */ 294 int 295 atw_enable(struct atw_softc *sc) 296 { 297 298 if (ATW_IS_ENABLED(sc) == 0) { 299 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 300 printf("%s: device enable failed\n", 301 sc->sc_dev.dv_xname); 302 return (EIO); 303 } 304 sc->sc_flags |= ATWF_ENABLED; 305 } 306 return (0); 307 } 308 309 /* 310 * atw_disable: 311 * 312 * Disable the ADM8211 chip. 313 */ 314 void 315 atw_disable(struct atw_softc *sc) 316 { 317 if (!ATW_IS_ENABLED(sc)) 318 return; 319 if (sc->sc_disable != NULL) 320 (*sc->sc_disable)(sc); 321 sc->sc_flags &= ~ATWF_ENABLED; 322 } 323 324 /* Returns -1 on failure. */ 325 int 326 atw_read_srom(struct atw_softc *sc) 327 { 328 struct seeprom_descriptor sd; 329 u_int32_t reg; 330 331 (void)memset(&sd, 0, sizeof(sd)); 332 333 reg = ATW_READ(sc, ATW_TEST0); 334 335 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 336 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 337 return -1; 338 } 339 340 switch (reg & ATW_TEST0_EPTYP_MASK) { 341 case ATW_TEST0_EPTYP_93c66: 342 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 343 sc->sc_sromsz = 512; 344 sd.sd_chip = C56_66; 345 break; 346 case ATW_TEST0_EPTYP_93c46: 347 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 348 sc->sc_sromsz = 128; 349 sd.sd_chip = C46; 350 break; 351 default: 352 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 353 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 354 return -1; 355 } 356 357 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 358 359 if (sc->sc_srom == NULL) { 360 printf("%s: unable to allocate SROM buffer\n", 361 sc->sc_dev.dv_xname); 362 return -1; 363 } 364 365 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 366 367 /* ADM8211 has a single 32-bit register for controlling the 368 * 93cx6 SROM. Bit SRS enables the serial port. There is no 369 * "ready" bit. The ADM8211 input/output sense is the reverse 370 * of read_seeprom's. 371 */ 372 sd.sd_tag = sc->sc_st; 373 sd.sd_bsh = sc->sc_sh; 374 sd.sd_regsize = 4; 375 sd.sd_control_offset = ATW_SPR; 376 sd.sd_status_offset = ATW_SPR; 377 sd.sd_dataout_offset = ATW_SPR; 378 sd.sd_CK = ATW_SPR_SCLK; 379 sd.sd_CS = ATW_SPR_SCS; 380 sd.sd_DI = ATW_SPR_SDO; 381 sd.sd_DO = ATW_SPR_SDI; 382 sd.sd_MS = ATW_SPR_SRS; 383 sd.sd_RDY = 0; 384 385 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 386 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 387 free(sc->sc_srom, M_DEVBUF); 388 return -1; 389 } 390 #ifdef ATW_DEBUG 391 { 392 int i; 393 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 394 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 395 if (((i % 8) == 0) && (i != 0)) { 396 ATW_DPRINTF(("\n\t")); 397 } 398 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 399 } 400 ATW_DPRINTF(("\n")); 401 } 402 #endif /* ATW_DEBUG */ 403 return 0; 404 } 405 406 #ifdef ATW_DEBUG 407 static void 408 atw_print_regs(struct atw_softc *sc, const char *where) 409 { 410 #define PRINTREG(sc, reg) \ 411 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 412 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 413 414 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 415 416 PRINTREG(sc, ATW_PAR); 417 PRINTREG(sc, ATW_FRCTL); 418 PRINTREG(sc, ATW_TDR); 419 PRINTREG(sc, ATW_WTDP); 420 PRINTREG(sc, ATW_RDR); 421 PRINTREG(sc, ATW_WRDP); 422 PRINTREG(sc, ATW_RDB); 423 PRINTREG(sc, ATW_CSR3A); 424 PRINTREG(sc, ATW_TDBD); 425 PRINTREG(sc, ATW_TDBP); 426 PRINTREG(sc, ATW_STSR); 427 PRINTREG(sc, ATW_CSR5A); 428 PRINTREG(sc, ATW_NAR); 429 PRINTREG(sc, ATW_CSR6A); 430 PRINTREG(sc, ATW_IER); 431 PRINTREG(sc, ATW_CSR7A); 432 PRINTREG(sc, ATW_LPC); 433 PRINTREG(sc, ATW_TEST1); 434 PRINTREG(sc, ATW_SPR); 435 PRINTREG(sc, ATW_TEST0); 436 PRINTREG(sc, ATW_WCSR); 437 PRINTREG(sc, ATW_WPDR); 438 PRINTREG(sc, ATW_GPTMR); 439 PRINTREG(sc, ATW_GPIO); 440 PRINTREG(sc, ATW_BBPCTL); 441 PRINTREG(sc, ATW_SYNCTL); 442 PRINTREG(sc, ATW_PLCPHD); 443 PRINTREG(sc, ATW_MMIWADDR); 444 PRINTREG(sc, ATW_MMIRADDR1); 445 PRINTREG(sc, ATW_MMIRADDR2); 446 PRINTREG(sc, ATW_TXBR); 447 PRINTREG(sc, ATW_CSR15A); 448 PRINTREG(sc, ATW_ALCSTAT); 449 PRINTREG(sc, ATW_TOFS2); 450 PRINTREG(sc, ATW_CMDR); 451 PRINTREG(sc, ATW_PCIC); 452 PRINTREG(sc, ATW_PMCSR); 453 PRINTREG(sc, ATW_PAR0); 454 PRINTREG(sc, ATW_PAR1); 455 PRINTREG(sc, ATW_MAR0); 456 PRINTREG(sc, ATW_MAR1); 457 PRINTREG(sc, ATW_ATIMDA0); 458 PRINTREG(sc, ATW_ABDA1); 459 PRINTREG(sc, ATW_BSSID0); 460 PRINTREG(sc, ATW_TXLMT); 461 PRINTREG(sc, ATW_MIBCNT); 462 PRINTREG(sc, ATW_BCNT); 463 PRINTREG(sc, ATW_TSFTH); 464 PRINTREG(sc, ATW_TSC); 465 PRINTREG(sc, ATW_SYNRF); 466 PRINTREG(sc, ATW_BPLI); 467 PRINTREG(sc, ATW_CAP0); 468 PRINTREG(sc, ATW_CAP1); 469 PRINTREG(sc, ATW_RMD); 470 PRINTREG(sc, ATW_CFPP); 471 PRINTREG(sc, ATW_TOFS0); 472 PRINTREG(sc, ATW_TOFS1); 473 PRINTREG(sc, ATW_IFST); 474 PRINTREG(sc, ATW_RSPT); 475 PRINTREG(sc, ATW_TSFTL); 476 PRINTREG(sc, ATW_WEPCTL); 477 PRINTREG(sc, ATW_WESK); 478 PRINTREG(sc, ATW_WEPCNT); 479 PRINTREG(sc, ATW_MACTEST); 480 PRINTREG(sc, ATW_FER); 481 PRINTREG(sc, ATW_FEMR); 482 PRINTREG(sc, ATW_FPSR); 483 PRINTREG(sc, ATW_FFER); 484 #undef PRINTREG 485 } 486 #endif /* ATW_DEBUG */ 487 488 /* 489 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 490 */ 491 void 492 atw_attach(struct atw_softc *sc) 493 { 494 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 496 }; 497 struct ieee80211com *ic = &sc->sc_ic; 498 struct ifnet *ifp = &ic->ic_if; 499 int country_code, error, i, nrate; 500 u_int32_t reg; 501 static const char *type_strings[] = {"Intersil (not supported)", 502 "RFMD", "Marvel (not supported)"}; 503 504 sc->sc_txth = atw_txthresh_tab_lo; 505 506 SIMPLEQ_INIT(&sc->sc_txfreeq); 507 SIMPLEQ_INIT(&sc->sc_txdirtyq); 508 509 #ifdef ATW_DEBUG 510 atw_print_regs(sc, "atw_attach"); 511 #endif /* ATW_DEBUG */ 512 513 /* 514 * Allocate the control data structures, and create and load the 515 * DMA map for it. 516 */ 517 if ((error = bus_dmamem_alloc(sc->sc_dmat, 518 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 519 1, &sc->sc_cdnseg, 0)) != 0) { 520 printf("%s: unable to allocate control data, error = %d\n", 521 sc->sc_dev.dv_xname, error); 522 goto fail_0; 523 } 524 525 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 526 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 527 BUS_DMA_COHERENT)) != 0) { 528 printf("%s: unable to map control data, error = %d\n", 529 sc->sc_dev.dv_xname, error); 530 goto fail_1; 531 } 532 533 if ((error = bus_dmamap_create(sc->sc_dmat, 534 sizeof(struct atw_control_data), 1, 535 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 536 printf("%s: unable to create control data DMA map, " 537 "error = %d\n", sc->sc_dev.dv_xname, error); 538 goto fail_2; 539 } 540 541 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 542 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 543 0)) != 0) { 544 printf("%s: unable to load control data DMA map, error = %d\n", 545 sc->sc_dev.dv_xname, error); 546 goto fail_3; 547 } 548 549 /* 550 * Create the transmit buffer DMA maps. 551 */ 552 sc->sc_ntxsegs = ATW_NTXSEGS; 553 for (i = 0; i < ATW_TXQUEUELEN; i++) { 554 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 555 sc->sc_ntxsegs, MCLBYTES, 0, 0, 556 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 557 printf("%s: unable to create tx DMA map %d, " 558 "error = %d\n", sc->sc_dev.dv_xname, i, error); 559 goto fail_4; 560 } 561 } 562 563 /* 564 * Create the receive buffer DMA maps. 565 */ 566 for (i = 0; i < ATW_NRXDESC; i++) { 567 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 568 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 569 printf("%s: unable to create rx DMA map %d, " 570 "error = %d\n", sc->sc_dev.dv_xname, i, error); 571 goto fail_5; 572 } 573 } 574 for (i = 0; i < ATW_NRXDESC; i++) { 575 sc->sc_rxsoft[i].rxs_mbuf = NULL; 576 } 577 578 /* Reset the chip to a known state. */ 579 atw_reset(sc); 580 581 if (atw_read_srom(sc) == -1) 582 return; 583 584 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 585 ATW_SR_RFTYPE_MASK); 586 587 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_BBPTYPE_MASK); 589 590 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 591 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 592 return; 593 } 594 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 595 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 596 return; 597 } 598 599 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 600 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 601 602 /* XXX There exists a Linux driver which seems to use RFType = 0 for 603 * MARVEL. My bug, or theirs? 604 */ 605 606 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 607 608 switch (sc->sc_rftype) { 609 case ATW_RFTYPE_INTERSIL: 610 reg |= ATW_SYNCTL_CS1; 611 break; 612 case ATW_RFTYPE_RFMD: 613 reg |= ATW_SYNCTL_CS0; 614 break; 615 case ATW_RFTYPE_MARVEL: 616 break; 617 } 618 619 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 620 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 621 622 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 623 624 switch (sc->sc_bbptype) { 625 case ATW_BBPTYPE_INTERSIL: 626 reg |= ATW_BBPCTL_TWI; 627 break; 628 case ATW_BBPTYPE_RFMD: 629 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 630 ATW_BBPCTL_CCA_ACTLO; 631 break; 632 case ATW_BBPTYPE_MARVEL: 633 break; 634 case ATW_C_BBPTYPE_RFMD: 635 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 636 sc->sc_dev.dv_xname); 637 break; 638 } 639 640 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 641 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 642 643 /* 644 * From this point forward, the attachment cannot fail. A failure 645 * before this point releases all resources that may have been 646 * allocated. 647 */ 648 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 649 650 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 651 htole16(sc->sc_srom[ATW_SR_MAC00]), 652 htole16(sc->sc_srom[ATW_SR_MAC01]), 653 htole16(sc->sc_srom[ATW_SR_MAC10]))); 654 655 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 656 ATW_SR_CTRY_MASK); 657 658 #define ADD_CHANNEL(_ic, _chan) do { \ 659 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 660 _ic->ic_channels[_chan].ic_freq = \ 661 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 662 } while (0) 663 664 /* Find available channels */ 665 switch (country_code) { 666 case COUNTRY_MMK2: /* 1-14 */ 667 ADD_CHANNEL(ic, 14); 668 /*FALLTHROUGH*/ 669 case COUNTRY_ETSI: /* 1-13 */ 670 for (i = 1; i <= 13; i++) 671 ADD_CHANNEL(ic, i); 672 break; 673 case COUNTRY_FCC: /* 1-11 */ 674 case COUNTRY_IC: /* 1-11 */ 675 for (i = 1; i <= 11; i++) 676 ADD_CHANNEL(ic, i); 677 break; 678 case COUNTRY_MMK: /* 14 */ 679 ADD_CHANNEL(ic, 14); 680 break; 681 case COUNTRY_FRANCE: /* 10-13 */ 682 for (i = 10; i <= 13; i++) 683 ADD_CHANNEL(ic, i); 684 break; 685 default: /* assume channels 10-11 */ 686 case COUNTRY_SPAIN: /* 10-11 */ 687 for (i = 10; i <= 11; i++) 688 ADD_CHANNEL(ic, i); 689 break; 690 } 691 692 /* Read the MAC address. */ 693 reg = ATW_READ(sc, ATW_PAR0); 694 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 695 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 696 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 697 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 698 reg = ATW_READ(sc, ATW_PAR1); 699 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 700 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 701 702 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 703 printf(" could not get mac address, attach failed\n"); 704 return; 705 } 706 707 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 708 709 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 710 ifp->if_softc = sc; 711 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 712 IFF_NOTRAILERS; 713 ifp->if_ioctl = atw_ioctl; 714 ifp->if_start = atw_start; 715 ifp->if_watchdog = atw_watchdog; 716 ifp->if_init = atw_init; 717 ifp->if_stop = atw_stop; 718 IFQ_SET_READY(&ifp->if_snd); 719 720 ic->ic_phytype = IEEE80211_T_DS; 721 ic->ic_opmode = IEEE80211_M_STA; 722 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 723 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 724 725 nrate = 0; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 730 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 731 732 /* 733 * Call MI attach routines. 734 */ 735 736 if_attach(ifp); 737 ieee80211_ifattach(ifp); 738 739 sc->sc_newstate = ic->ic_newstate; 740 ic->ic_newstate = atw_newstate; 741 742 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 743 ic->ic_recv_mgmt = atw_recv_mgmt; 744 745 sc->sc_node_free = ic->ic_node_free; 746 ic->ic_node_free = atw_node_free; 747 748 sc->sc_node_alloc = ic->ic_node_alloc; 749 ic->ic_node_alloc = atw_node_alloc; 750 751 /* possibly we should fill in our own sc_send_prresp, since 752 * the ADM8211 is probably sending probe responses in ad hoc 753 * mode. 754 */ 755 756 /* complete initialization */ 757 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 758 callout_init(&sc->sc_scan_ch); 759 760 #if NBPFILTER > 0 761 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 762 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 763 #endif 764 765 /* 766 * Make sure the interface is shutdown during reboot. 767 */ 768 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 769 if (sc->sc_sdhook == NULL) 770 printf("%s: WARNING: unable to establish shutdown hook\n", 771 sc->sc_dev.dv_xname); 772 773 /* 774 * Add a suspend hook to make sure we come back up after a 775 * resume. 776 */ 777 sc->sc_powerhook = powerhook_establish(atw_power, sc); 778 if (sc->sc_powerhook == NULL) 779 printf("%s: WARNING: unable to establish power hook\n", 780 sc->sc_dev.dv_xname); 781 782 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 783 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 784 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 785 786 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 787 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 788 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 789 790 return; 791 792 /* 793 * Free any resources we've allocated during the failed attach 794 * attempt. Do this in reverse order and fall through. 795 */ 796 fail_5: 797 for (i = 0; i < ATW_NRXDESC; i++) { 798 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 799 continue; 800 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 801 } 802 fail_4: 803 for (i = 0; i < ATW_TXQUEUELEN; i++) { 804 if (sc->sc_txsoft[i].txs_dmamap == NULL) 805 continue; 806 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 807 } 808 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 809 fail_3: 810 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 811 fail_2: 812 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 813 sizeof(struct atw_control_data)); 814 fail_1: 815 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 816 fail_0: 817 return; 818 } 819 820 static struct ieee80211_node * 821 atw_node_alloc(struct ieee80211com *ic) 822 { 823 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 824 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 825 826 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 827 return ni; 828 } 829 830 static void 831 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 832 { 833 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 834 835 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 836 ether_sprintf(ni->ni_bssid))); 837 (*sc->sc_node_free)(ic, ni); 838 } 839 840 /* 841 * atw_reset: 842 * 843 * Perform a soft reset on the ADM8211. 844 */ 845 void 846 atw_reset(struct atw_softc *sc) 847 { 848 int i; 849 850 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 851 852 for (i = 0; i < 10000; i++) { 853 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 854 break; 855 DELAY(1); 856 } 857 858 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 859 860 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 861 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 862 863 /* Turn off maximum power saving. */ 864 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 865 866 /* Recall EEPROM. */ 867 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 868 869 DELAY(10 * 1000); 870 871 /* A reset seems to affect the SRAM contents, so put them into 872 * a known state. 873 */ 874 atw_clear_sram(sc); 875 876 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 877 878 sc->sc_lost_bcn_thresh = 0; 879 } 880 881 static void 882 atw_clear_sram(struct atw_softc *sc) 883 { 884 #if 0 885 for (addr = 0; addr < 448; addr++) { 886 ATW_WRITE(sc, ATW_WEPCTL, 887 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 888 DELAY(1000); 889 ATW_WRITE(sc, ATW_WESK, 0); 890 DELAY(1000); /* paranoia */ 891 } 892 return; 893 #endif 894 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 895 /* XXX not for revision 0x20. */ 896 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 897 } 898 899 /* TBD atw_init 900 * 901 * set MAC based on ic->ic_bss->myaddr 902 * write WEP keys 903 * set TX rate 904 */ 905 906 /* 907 * atw_init: [ ifnet interface function ] 908 * 909 * Initialize the interface. Must be called at splnet(). 910 */ 911 int 912 atw_init(struct ifnet *ifp) 913 { 914 struct atw_softc *sc = ifp->if_softc; 915 struct ieee80211com *ic = &sc->sc_ic; 916 struct atw_txsoft *txs; 917 struct atw_rxsoft *rxs; 918 u_int32_t reg; 919 int i, error = 0; 920 921 if ((error = atw_enable(sc)) != 0) 922 goto out; 923 924 /* 925 * Cancel any pending I/O. This also resets. 926 */ 927 atw_stop(ifp, 0); 928 929 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 930 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 931 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 932 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 933 934 /* Turn off APM??? (A binary-only driver does this.) 935 * 936 * Set Rx store-and-forward mode. 937 */ 938 reg = ATW_READ(sc, ATW_CMDR); 939 reg &= ~ATW_CMDR_APM; 940 reg &= ~ATW_CMDR_DRT_MASK; 941 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 942 943 ATW_WRITE(sc, ATW_CMDR, reg); 944 945 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 946 * 947 * XXX a binary-only driver sets a different service field than 948 * 0. why? 949 */ 950 reg = ATW_READ(sc, ATW_PLCPHD); 951 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 952 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 953 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 954 ATW_WRITE(sc, ATW_PLCPHD, reg); 955 956 /* XXX this magic can probably be figured out from the RFMD docs */ 957 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 958 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 959 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 960 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 961 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 962 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 963 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 964 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 965 ATW_WRITE(sc, ATW_TOFS2, reg); 966 967 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 968 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 969 970 /* XXX this resets an Intersil RF front-end? */ 971 /* TBD condition on Intersil RFType? */ 972 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 973 DELAY(10 * 1000); 974 ATW_WRITE(sc, ATW_SYNRF, 0); 975 DELAY(5 * 1000); 976 977 /* 16 TU max duration for contention-free period */ 978 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 979 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 980 981 /* XXX I guess that the Cardbus clock is 22MHz? 982 * I am assuming that the role of ATW_TOFS0_USCNT is 983 * to divide the bus clock to get a 1MHz clock---the datasheet is not 984 * very clear on this point. It says in the datasheet that it is 985 * possible for the ADM8211 to accomodate bus speeds between 22MHz 986 * and 33MHz; maybe this is the way? I see a binary-only driver write 987 * these values. These values are also the power-on default. 988 */ 989 ATW_WRITE(sc, ATW_TOFS0, 990 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 991 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 992 993 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 994 * driver. Go figure. 995 */ 996 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 997 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 998 ATW_IFST_SIFS_MASK) | 999 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1000 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1001 1002 ATW_WRITE(sc, ATW_IFST, reg); 1003 1004 /* XXX More magic. Might relate to ACK timing. */ 1005 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1006 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1007 1008 /* Set up the MMI read/write addresses for the BBP. 1009 * 1010 * TBD find out the Marvel settings. 1011 */ 1012 switch (sc->sc_bbptype) { 1013 case ATW_BBPTYPE_INTERSIL: 1014 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1015 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1016 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1017 break; 1018 case ATW_BBPTYPE_MARVEL: 1019 break; 1020 case ATW_BBPTYPE_RFMD: 1021 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1022 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1023 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1024 default: 1025 break; 1026 } 1027 1028 sc->sc_wepctl = 0; 1029 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1030 1031 if ((error = atw_rf3000_init(sc)) != 0) 1032 goto out; 1033 1034 /* 1035 * Initialize the PCI Access Register. 1036 */ 1037 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1038 1039 /* 1040 * If we're allowed to do so, use Memory Read Line 1041 * and Memory Read Multiple. 1042 * 1043 * XXX Should we use Memory Write and Invalidate? 1044 */ 1045 if (sc->sc_flags & ATWF_MRL) 1046 sc->sc_busmode |= ATW_PAR_MRLE; 1047 if (sc->sc_flags & ATWF_MRM) 1048 sc->sc_busmode |= ATW_PAR_MRME; 1049 if (sc->sc_flags & ATWF_MWI) 1050 sc->sc_busmode |= ATW_PAR_MWIE; 1051 if (sc->sc_maxburst == 0) 1052 sc->sc_maxburst = 8; /* ADM8211 default */ 1053 1054 switch (sc->sc_cacheline) { 1055 default: 1056 /* Use burst length. */ 1057 break; 1058 case 8: 1059 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1060 break; 1061 case 16: 1062 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1063 break; 1064 case 32: 1065 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1066 break; 1067 } 1068 switch (sc->sc_maxburst) { 1069 case 1: 1070 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1071 break; 1072 case 2: 1073 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1074 break; 1075 case 4: 1076 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1077 break; 1078 case 8: 1079 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1080 break; 1081 case 16: 1082 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1083 break; 1084 case 32: 1085 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1086 break; 1087 default: 1088 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1089 break; 1090 } 1091 1092 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1093 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1094 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1095 1096 /* 1097 * Initialize the OPMODE register. We don't write it until 1098 * we're ready to begin the transmit and receive processes. 1099 */ 1100 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1101 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1102 1103 /* 1104 * Initialize the transmit descriptor ring. 1105 */ 1106 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1107 for (i = 0; i < ATW_NTXDESC; i++) { 1108 /* no transmit chaining */ 1109 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1110 sc->sc_txdescs[i].at_buf2 = 1111 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1112 } 1113 /* use ring mode */ 1114 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1115 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1116 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1117 sc->sc_txfree = ATW_NTXDESC; 1118 sc->sc_txnext = 0; 1119 1120 /* 1121 * Initialize the transmit job descriptors. 1122 */ 1123 SIMPLEQ_INIT(&sc->sc_txfreeq); 1124 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1125 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1126 txs = &sc->sc_txsoft[i]; 1127 txs->txs_mbuf = NULL; 1128 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1129 } 1130 1131 /* 1132 * Initialize the receive descriptor and receive job 1133 * descriptor rings. 1134 */ 1135 for (i = 0; i < ATW_NRXDESC; i++) { 1136 rxs = &sc->sc_rxsoft[i]; 1137 if (rxs->rxs_mbuf == NULL) { 1138 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1139 printf("%s: unable to allocate or map rx " 1140 "buffer %d, error = %d\n", 1141 sc->sc_dev.dv_xname, i, error); 1142 /* 1143 * XXX Should attempt to run with fewer receive 1144 * XXX buffers instead of just failing. 1145 */ 1146 atw_rxdrain(sc); 1147 goto out; 1148 } 1149 } else 1150 ATW_INIT_RXDESC(sc, i); 1151 } 1152 sc->sc_rxptr = 0; 1153 1154 /* disable all wake-up events */ 1155 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1156 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1157 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1158 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1159 1160 /* ack all wake-up events */ 1161 ATW_SET(sc, ATW_WCSR, 0); 1162 1163 /* 1164 * Initialize the interrupt mask and enable interrupts. 1165 */ 1166 /* normal interrupts */ 1167 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1168 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1169 1170 /* abnormal interrupts */ 1171 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1172 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1173 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1174 1175 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1176 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1177 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1178 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1179 ATW_INTR_TRT; 1180 1181 sc->sc_linkint_mask &= sc->sc_inten; 1182 sc->sc_rxint_mask &= sc->sc_inten; 1183 sc->sc_txint_mask &= sc->sc_inten; 1184 1185 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1186 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1187 if (sc->sc_intr_ack != NULL) 1188 (*sc->sc_intr_ack)(sc); 1189 1190 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1191 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1192 1193 /* 1194 * Give the transmit and receive rings to the ADM8211. 1195 */ 1196 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1197 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1198 1199 /* common 802.11 configuration */ 1200 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1201 switch (ic->ic_opmode) { 1202 case IEEE80211_M_STA: 1203 break; 1204 case IEEE80211_M_AHDEMO: /* XXX */ 1205 case IEEE80211_M_IBSS: 1206 ic->ic_flags |= IEEE80211_F_IBSSON; 1207 /*FALLTHROUGH*/ 1208 case IEEE80211_M_HOSTAP: /* XXX */ 1209 break; 1210 case IEEE80211_M_MONITOR: /* XXX */ 1211 break; 1212 } 1213 1214 atw_start_beacon(sc, 0); 1215 1216 switch (ic->ic_opmode) { 1217 case IEEE80211_M_AHDEMO: 1218 case IEEE80211_M_HOSTAP: 1219 ic->ic_bss->ni_intval = ic->ic_lintval; 1220 ic->ic_bss->ni_rssi = 0; 1221 ic->ic_bss->ni_rstamp = 0; 1222 break; 1223 default: /* XXX */ 1224 break; 1225 } 1226 1227 atw_write_ssid(sc); 1228 atw_write_sup_rates(sc); 1229 if (ic->ic_caps & IEEE80211_C_WEP) 1230 atw_write_wep(sc); 1231 1232 /* 1233 * Set the receive filter. This will start the transmit and 1234 * receive processes. 1235 */ 1236 atw_filter_setup(sc); 1237 1238 /* 1239 * Start the receive process. 1240 */ 1241 ATW_WRITE(sc, ATW_RDR, 0x1); 1242 1243 /* 1244 * Note that the interface is now running. 1245 */ 1246 ifp->if_flags |= IFF_RUNNING; 1247 ifp->if_flags &= ~IFF_OACTIVE; 1248 ic->ic_state = IEEE80211_S_INIT; 1249 1250 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1251 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1252 else 1253 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1254 out: 1255 if (error) { 1256 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1257 ifp->if_timer = 0; 1258 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1259 } 1260 #ifdef ATW_DEBUG 1261 atw_print_regs(sc, "end of init"); 1262 #endif /* ATW_DEBUG */ 1263 1264 return (error); 1265 } 1266 1267 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1268 * 0: MAC control of RF3000/Si4126. 1269 * 1270 * Applies power, or selects RF front-end? Sets reset condition. 1271 * 1272 * TBD support non-RFMD BBP, non-SiLabs synth. 1273 */ 1274 static void 1275 atw_rfio_enable(struct atw_softc *sc, int enable) 1276 { 1277 if (enable) { 1278 ATW_WRITE(sc, ATW_SYNRF, 1279 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1280 DELAY(atw_rfio_enable_delay); 1281 } else { 1282 ATW_WRITE(sc, ATW_SYNRF, 0); 1283 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1284 } 1285 } 1286 1287 static int 1288 atw_tune(struct atw_softc *sc) 1289 { 1290 int rc; 1291 u_int32_t reg; 1292 int chan; 1293 struct ieee80211com *ic = &sc->sc_ic; 1294 1295 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1296 if (chan == IEEE80211_CHAN_ANY) 1297 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1298 1299 if (chan == sc->sc_cur_chan) 1300 return 0; 1301 1302 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1303 sc->sc_cur_chan, chan)); 1304 1305 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1306 1307 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1308 (rc = atw_rf3000_tune(sc, chan)) != 0) 1309 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1310 chan); 1311 1312 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1313 ATW_WRITE(sc, ATW_CAP0, 1314 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1315 1316 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1317 1318 if (rc == 0) 1319 sc->sc_cur_chan = chan; 1320 1321 return rc; 1322 } 1323 1324 #ifdef ATW_DEBUG 1325 static void 1326 atw_si4126_print(struct atw_softc *sc) 1327 { 1328 struct ifnet *ifp = &sc->sc_ic.ic_if; 1329 u_int addr, val; 1330 1331 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1332 return; 1333 1334 for (addr = 0; addr <= 8; addr++) { 1335 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1336 if (atw_si4126_read(sc, addr, &val) == 0) { 1337 printf("<unknown> (quitting print-out)\n"); 1338 break; 1339 } 1340 printf("%05x\n", val); 1341 } 1342 } 1343 #endif /* ATW_DEBUG */ 1344 1345 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1346 * 1347 * The RF/IF synthesizer produces two reference frequencies for 1348 * the RF2948B transceiver. The first frequency the RF2948B requires 1349 * is two times the so-called "intermediate frequency" (IF). Since 1350 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1351 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1352 * frequency required by the transceiver is the radio frequency 1353 * (RF). This is a superheterodyne transceiver; for f(chan) the 1354 * center frequency of the channel we are tuning, RF = f(chan) - 1355 * IF. 1356 * 1357 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1358 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1359 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1360 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1361 */ 1362 static int 1363 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1364 { 1365 int rc = 0; 1366 u_int mhz; 1367 u_int R; 1368 u_int32_t reg; 1369 u_int16_t gain; 1370 1371 #ifdef ATW_DEBUG 1372 atw_si4126_print(sc); 1373 #endif /* ATW_DEBUG */ 1374 1375 if (chan == 14) 1376 mhz = 2484; 1377 else 1378 mhz = 2412 + 5 * (chan - 1); 1379 1380 /* Tune IF to 748MHz to suit the IF LO input of the 1381 * RF2494B, which is 2 x IF. No need to set an IF divider 1382 * because an IF in 526MHz - 952MHz is allowed. 1383 * 1384 * XIN is 44.000MHz, so divide it by two to get allowable 1385 * range of 2-25MHz. SiLabs tells me that this is not 1386 * strictly necessary. 1387 */ 1388 1389 R = 44; 1390 1391 atw_rfio_enable(sc, 1); 1392 1393 /* Power-up RF, IF synthesizers. */ 1394 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1395 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1396 goto out; 1397 1398 /* If RF2 N > 2047, then set KP2 to 1. */ 1399 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1400 1401 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1402 goto out; 1403 1404 /* set LPWR, too? */ 1405 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1406 SI4126_MAIN_XINDIV2)) != 0) 1407 goto out; 1408 1409 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1410 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1411 */ 1412 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1413 goto out; 1414 1415 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1416 goto out; 1417 1418 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1419 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1420 * which has no RF1! 1421 */ 1422 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1423 goto out; 1424 1425 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1426 goto out; 1427 1428 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1429 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1430 * Now let's multiply it to mhz. So mhz - IF = N. 1431 */ 1432 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1433 goto out; 1434 1435 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1436 goto out; 1437 1438 /* wait 100us from power-up for RF, IF to settle */ 1439 DELAY(100); 1440 1441 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1442 /* XXX there is a binary driver which sends 1443 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1444 * that this enables the Si4126 by raising its PWDN#, but I 1445 * think that it actually sets the Prism RF front-end 1446 * to a special mode for channel 14. 1447 */ 1448 reg = ATW_READ(sc, ATW_GPIO); 1449 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1450 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1451 ATW_WRITE(sc, ATW_GPIO, reg); 1452 } 1453 1454 #ifdef ATW_DEBUG 1455 atw_si4126_print(sc); 1456 #endif /* ATW_DEBUG */ 1457 1458 out: 1459 atw_rfio_enable(sc, 0); 1460 1461 return rc; 1462 } 1463 1464 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1465 * diversity. 1466 * 1467 * Call this w/ Tx/Rx suspended. 1468 */ 1469 static int 1470 atw_rf3000_init(struct atw_softc *sc) 1471 { 1472 int rc = 0; 1473 1474 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1475 1476 atw_rfio_enable(sc, 1); 1477 1478 /* enable diversity */ 1479 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1480 1481 if (rc != 0) 1482 goto out; 1483 1484 /* sensible setting from a binary-only driver */ 1485 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1486 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1487 1488 if (rc != 0) 1489 goto out; 1490 1491 /* magic from a binary-only driver */ 1492 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1493 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1494 1495 if (rc != 0) 1496 goto out; 1497 1498 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1499 1500 if (rc != 0) 1501 goto out; 1502 1503 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1504 1505 if (rc != 0) 1506 goto out; 1507 1508 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1509 1510 if (rc != 0) 1511 goto out; 1512 1513 /* CCA is acquisition sensitive */ 1514 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1515 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1516 1517 if (rc != 0) 1518 goto out; 1519 1520 out: 1521 atw_rfio_enable(sc, 0); 1522 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1523 return rc; 1524 } 1525 1526 #ifdef ATW_DEBUG 1527 static void 1528 atw_rf3000_print(struct atw_softc *sc) 1529 { 1530 struct ifnet *ifp = &sc->sc_ic.ic_if; 1531 u_int addr, val; 1532 1533 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1534 return; 1535 1536 for (addr = 0x01; addr <= 0x15; addr++) { 1537 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1538 if (atw_rf3000_read(sc, addr, &val) != 0) { 1539 printf("<unknown> (quitting print-out)\n"); 1540 break; 1541 } 1542 printf("%08x\n", val); 1543 } 1544 } 1545 #endif /* ATW_DEBUG */ 1546 1547 /* Set the power settings on the BBP for channel `chan'. */ 1548 static int 1549 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1550 { 1551 int rc = 0; 1552 u_int32_t reg; 1553 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1554 1555 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1556 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1557 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1558 1559 /* odd channels: LSB, even channels: MSB */ 1560 if (chan % 2 == 1) { 1561 txpower &= 0xFF; 1562 lpf_cutoff &= 0xFF; 1563 lna_gs_thresh &= 0xFF; 1564 } else { 1565 txpower >>= 8; 1566 lpf_cutoff >>= 8; 1567 lna_gs_thresh >>= 8; 1568 } 1569 1570 #ifdef ATW_DEBUG 1571 atw_rf3000_print(sc); 1572 #endif /* ATW_DEBUG */ 1573 1574 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1575 "lna_gs_thresh %02x\n", 1576 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1577 1578 atw_rfio_enable(sc, 1); 1579 1580 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1581 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1582 goto out; 1583 1584 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1585 goto out; 1586 1587 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1588 goto out; 1589 1590 /* from a binary-only driver. */ 1591 reg = ATW_READ(sc, ATW_PLCPHD); 1592 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1593 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1594 ATW_PLCPHD_SERVICE_MASK); 1595 ATW_WRITE(sc, ATW_PLCPHD, reg); 1596 1597 #ifdef ATW_DEBUG 1598 atw_rf3000_print(sc); 1599 #endif /* ATW_DEBUG */ 1600 1601 out: 1602 atw_rfio_enable(sc, 0); 1603 1604 return rc; 1605 } 1606 1607 /* Write a register on the RF3000 baseband processor using the 1608 * registers provided by the ADM8211 for this purpose. 1609 * 1610 * Return 0 on success. 1611 */ 1612 static int 1613 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1614 { 1615 u_int32_t reg; 1616 int i; 1617 1618 for (i = 1000; --i >= 0; ) { 1619 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1620 break; 1621 DELAY(100); 1622 } 1623 1624 if (i < 0) { 1625 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1626 return ETIMEDOUT; 1627 } 1628 1629 reg = sc->sc_bbpctl_wr | 1630 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1631 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1632 1633 ATW_WRITE(sc, ATW_BBPCTL, reg); 1634 1635 for (i = 1000; --i >= 0; ) { 1636 DELAY(100); 1637 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1638 break; 1639 } 1640 1641 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1642 1643 if (i < 0) { 1644 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1645 return ETIMEDOUT; 1646 } 1647 return 0; 1648 } 1649 1650 /* Read a register on the RF3000 baseband processor using the registers 1651 * the ADM8211 provides for this purpose. 1652 * 1653 * The 7-bit register address is addr. Record the 8-bit data in the register 1654 * in *val. 1655 * 1656 * Return 0 on success. 1657 * 1658 * XXX This does not seem to work. The ADM8211 must require more or 1659 * different magic to read the chip than to write it. Possibly some 1660 * of the magic I have derived from a binary-only driver concerns 1661 * the "chip address" (see the RF3000 manual). 1662 */ 1663 #ifdef ATW_DEBUG 1664 static int 1665 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1666 { 1667 u_int32_t reg; 1668 int i; 1669 1670 for (i = 1000; --i >= 0; ) { 1671 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1672 break; 1673 DELAY(100); 1674 } 1675 1676 if (i < 0) { 1677 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1678 sc->sc_dev.dv_xname); 1679 return ETIMEDOUT; 1680 } 1681 1682 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1683 1684 ATW_WRITE(sc, ATW_BBPCTL, reg); 1685 1686 for (i = 1000; --i >= 0; ) { 1687 DELAY(100); 1688 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1689 break; 1690 } 1691 1692 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1693 1694 if (i < 0) { 1695 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1696 sc->sc_dev.dv_xname, reg); 1697 return ETIMEDOUT; 1698 } 1699 if (val != NULL) 1700 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1701 return 0; 1702 } 1703 #endif /* ATW_DEBUG */ 1704 1705 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1706 * provided by the ADM8211 for that purpose. 1707 * 1708 * val is 18 bits of data, and val is the 4-bit address of the register. 1709 * 1710 * Return 0 on success. 1711 */ 1712 static int 1713 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1714 { 1715 u_int32_t bits, reg; 1716 int i; 1717 1718 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1719 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1720 1721 for (i = 1000; --i >= 0; ) { 1722 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1723 break; 1724 DELAY(100); 1725 } 1726 1727 if (i < 0) { 1728 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1729 sc->sc_dev.dv_xname); 1730 return ETIMEDOUT; 1731 } 1732 1733 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1734 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1735 1736 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1737 1738 ATW_WRITE(sc, ATW_SYNCTL, reg); 1739 1740 for (i = 1000; --i >= 0; ) { 1741 DELAY(100); 1742 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1743 break; 1744 } 1745 1746 /* restore to acceptable starting condition */ 1747 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1748 1749 if (i < 0) { 1750 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1751 sc->sc_dev.dv_xname, reg); 1752 return ETIMEDOUT; 1753 } 1754 return 0; 1755 } 1756 1757 /* Read 18-bit data from the 4-bit address addr in Si4126 1758 * RF synthesizer and write the data to *val. Return 0 on success. 1759 * 1760 * XXX This does not seem to work. The ADM8211 must require more or 1761 * different magic to read the chip than to write it. 1762 */ 1763 #ifdef ATW_DEBUG 1764 static int 1765 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1766 { 1767 u_int32_t reg; 1768 int i; 1769 1770 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1771 1772 for (i = 1000; --i >= 0; ) { 1773 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1774 break; 1775 DELAY(100); 1776 } 1777 1778 if (i < 0) { 1779 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1780 sc->sc_dev.dv_xname); 1781 return ETIMEDOUT; 1782 } 1783 1784 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1785 1786 ATW_WRITE(sc, ATW_SYNCTL, reg); 1787 1788 for (i = 1000; --i >= 0; ) { 1789 DELAY(100); 1790 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1791 break; 1792 } 1793 1794 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1795 1796 if (i < 0) { 1797 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1798 sc->sc_dev.dv_xname, reg); 1799 return ETIMEDOUT; 1800 } 1801 if (val != NULL) 1802 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1803 ATW_SYNCTL_DATA_MASK); 1804 return 0; 1805 } 1806 #endif /* ATW_DEBUG */ 1807 1808 /* XXX is the endianness correct? test. */ 1809 #define atw_calchash(addr) \ 1810 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1811 1812 /* 1813 * atw_filter_setup: 1814 * 1815 * Set the ADM8211's receive filter. 1816 */ 1817 static void 1818 atw_filter_setup(struct atw_softc *sc) 1819 { 1820 struct ieee80211com *ic = &sc->sc_ic; 1821 struct ethercom *ec = &ic->ic_ec; 1822 struct ifnet *ifp = &sc->sc_ic.ic_if; 1823 int hash; 1824 u_int32_t hashes[2] = { 0, 0 }; 1825 struct ether_multi *enm; 1826 struct ether_multistep step; 1827 1828 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1829 sc->sc_dev.dv_xname, sc->sc_flags)); 1830 1831 /* 1832 * If we're running, idle the receive engine. If we're NOT running, 1833 * we're being called from atw_init(), and our writing ATW_NAR will 1834 * start the transmit and receive processes in motion. 1835 */ 1836 if (ifp->if_flags & IFF_RUNNING) 1837 atw_idle(sc, ATW_NAR_SR); 1838 1839 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1840 1841 ifp->if_flags &= ~IFF_ALLMULTI; 1842 1843 if (ifp->if_flags & IFF_PROMISC) { 1844 sc->sc_opmode |= ATW_NAR_PR; 1845 allmulti: 1846 ifp->if_flags |= IFF_ALLMULTI; 1847 goto setit; 1848 } 1849 1850 /* 1851 * Program the 64-bit multicast hash filter. 1852 */ 1853 ETHER_FIRST_MULTI(step, ec, enm); 1854 while (enm != NULL) { 1855 /* XXX */ 1856 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1857 ETHER_ADDR_LEN) != 0) 1858 goto allmulti; 1859 1860 hash = atw_calchash(enm->enm_addrlo); 1861 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1862 ETHER_NEXT_MULTI(step, enm); 1863 } 1864 1865 if (ifp->if_flags & IFF_BROADCAST) { 1866 hash = atw_calchash(etherbroadcastaddr); 1867 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1868 } 1869 1870 /* all bits set => hash is useless */ 1871 if (~(hashes[0] & hashes[1]) == 0) 1872 goto allmulti; 1873 1874 setit: 1875 if (ifp->if_flags & IFF_ALLMULTI) 1876 sc->sc_opmode |= ATW_NAR_MM; 1877 1878 /* XXX in scan mode, do not filter packets. maybe this is 1879 * unnecessary. 1880 */ 1881 if (ic->ic_state == IEEE80211_S_SCAN) 1882 sc->sc_opmode |= ATW_NAR_PR; 1883 1884 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1885 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1886 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1887 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1888 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1889 1890 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1891 } 1892 1893 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1894 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1895 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1896 * no beacon with the preferred BSSID and SSID in the number of 1897 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1898 */ 1899 static void 1900 atw_write_bssid(struct atw_softc *sc) 1901 { 1902 struct ieee80211com *ic = &sc->sc_ic; 1903 u_int8_t *bssid; 1904 1905 bssid = ic->ic_bss->ni_bssid; 1906 1907 ATW_WRITE(sc, ATW_ABDA1, 1908 (ATW_READ(sc, ATW_ABDA1) & 1909 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1910 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1911 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1912 1913 ATW_WRITE(sc, ATW_BSSID0, 1914 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1915 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1916 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1917 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1918 1919 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1920 ether_sprintf(sc->sc_bssid))); 1921 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1922 1923 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1924 } 1925 1926 /* Tell the ADM8211 how many beacon intervals must pass without 1927 * receiving a beacon with the preferred BSSID & SSID set by 1928 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1929 * raised. 1930 */ 1931 static void 1932 atw_write_bcn_thresh(struct atw_softc *sc) 1933 { 1934 struct ieee80211com *ic = &sc->sc_ic; 1935 int lost_bcn_thresh; 1936 1937 /* Lose link after one second or 7 beacons, whichever comes 1938 * first, but do not lose link before 2 beacons are lost. 1939 * 1940 * In host AP mode, set the lost-beacon threshold to 0. 1941 */ 1942 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1943 lost_bcn_thresh = 0; 1944 else { 1945 int beacons_per_second = 1946 1000000 / (IEEE80211_DUR_TU * MAX(1,ic->ic_bss->ni_intval)); 1947 lost_bcn_thresh = MAX(2, MIN(7, beacons_per_second)); 1948 } 1949 1950 /* XXX resets wake-up status bits */ 1951 ATW_WRITE(sc, ATW_WCSR, 1952 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1953 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1954 1955 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1956 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1957 1958 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1959 1960 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1961 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1962 } 1963 1964 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1965 * 16-bit word. 1966 */ 1967 static void 1968 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1969 { 1970 u_int i; 1971 u_int8_t *ptr; 1972 1973 memcpy(&sc->sc_sram[ofs], buf, buflen); 1974 1975 if (ofs % 2 != 0) { 1976 ofs--; 1977 buflen++; 1978 } 1979 1980 if (buflen % 2 != 0) 1981 buflen++; 1982 1983 assert(buflen + ofs <= ATW_SRAM_SIZE); 1984 1985 ptr = &sc->sc_sram[ofs]; 1986 1987 for (i = 0; i < buflen; i += 2) { 1988 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1989 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1990 DELAY(atw_writewep_delay); 1991 1992 ATW_WRITE(sc, ATW_WESK, 1993 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1994 DELAY(atw_writewep_delay); 1995 } 1996 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1997 1998 if (sc->sc_if.if_flags & IFF_DEBUG) { 1999 int n_octets = 0; 2000 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2001 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2002 for (i = 0; i < buflen; i++) { 2003 printf(" %02x", ptr[i]); 2004 if (++n_octets % 24 == 0) 2005 printf("\n"); 2006 } 2007 if (n_octets % 24 != 0) 2008 printf("\n"); 2009 } 2010 } 2011 2012 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2013 static void 2014 atw_write_wep(struct atw_softc *sc) 2015 { 2016 struct ieee80211com *ic = &sc->sc_ic; 2017 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2018 u_int8_t buf[IEEE80211_WEP_NKID] 2019 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2020 u_int32_t reg; 2021 int i; 2022 2023 sc->sc_wepctl = 0; 2024 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2025 2026 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2027 return; 2028 2029 memset(&buf[0][0], 0, sizeof(buf)); 2030 2031 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2032 if (ic->ic_nw_keys[i].wk_len > 5) { 2033 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2034 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2035 buf[i][1] = ATW_WEP_ENABLED; 2036 } else { 2037 buf[i][1] = 0; 2038 continue; 2039 } 2040 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2041 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2042 ic->ic_nw_keys[i].wk_len - 1); 2043 } 2044 2045 reg = ATW_READ(sc, ATW_MACTEST); 2046 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2047 reg &= ~ATW_MACTEST_KEYID_MASK; 2048 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2049 ATW_WRITE(sc, ATW_MACTEST, reg); 2050 2051 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2052 * throughout.) 2053 */ 2054 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2055 if (sc->sc_if.if_flags & IFF_LINK2) 2056 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2057 2058 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2059 sizeof(buf)); 2060 } 2061 2062 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2063 2064 static void 2065 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2066 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2067 { 2068 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2069 2070 switch (subtype) { 2071 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2072 /* do nothing: hardware answers probe request */ 2073 break; 2074 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2075 case IEEE80211_FC0_SUBTYPE_BEACON: 2076 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2077 break; 2078 default: 2079 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2080 break; 2081 } 2082 return; 2083 } 2084 2085 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2086 * of IBSSs with like SSID/channel but different BSSID. It joins the 2087 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2088 * convention. Possibly the ADMtek chip does this for us; I will have 2089 * to test to find out. 2090 * 2091 * XXX we should add the duration field of the received beacon to 2092 * the TSF time it contains before comparing it with the ADM8211's 2093 * TSF. 2094 */ 2095 static void 2096 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2097 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2098 { 2099 struct atw_softc *sc; 2100 struct ieee80211_frame *wh; 2101 u_int64_t tsft, bcn_tsft; 2102 u_int32_t tsftl, tsfth; 2103 int do_print = 0; 2104 2105 sc = (struct atw_softc*)ic->ic_if.if_softc; 2106 2107 if (ic->ic_if.if_flags & IFF_DEBUG) 2108 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2109 ? 1 : ratecheck(&sc->sc_last_beacon, 2110 &atw_beacon_mininterval); 2111 2112 wh = mtod(m0, struct ieee80211_frame *); 2113 2114 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2115 2116 if (ic->ic_state != IEEE80211_S_RUN) { 2117 if (do_print) 2118 printf("%s: atw_recv_beacon: not running\n", 2119 sc->sc_dev.dv_xname); 2120 return; 2121 } 2122 2123 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2124 ic->ic_bss->ni_chan)) == NULL) { 2125 if (do_print) 2126 printf("%s: atw_recv_beacon: no node %s\n", 2127 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2128 return; 2129 } 2130 2131 if (ieee80211_match_bss(ic, ni) != 0) { 2132 if (do_print) 2133 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2134 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2135 return; 2136 } 2137 2138 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2139 return; 2140 2141 if (do_print) 2142 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2143 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2144 2145 if (ic->ic_opmode != IEEE80211_M_IBSS) 2146 return; 2147 2148 /* If we read TSFTL right before rollover, we read a TSF timer 2149 * that is too high rather than too low. This prevents a spurious 2150 * synchronization down the line, however, our IBSS could suffer 2151 * from a creeping TSF.... 2152 */ 2153 tsftl = ATW_READ(sc, ATW_TSFTL); 2154 tsfth = ATW_READ(sc, ATW_TSFTH); 2155 2156 tsft = (u_int64_t)tsfth << 32 | tsftl; 2157 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2158 2159 if (do_print) 2160 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2161 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2162 2163 /* we are faster, let the other guy catch up */ 2164 if (bcn_tsft < tsft) 2165 return; 2166 2167 if (do_print) 2168 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2169 ether_sprintf(wh->i_addr2)); 2170 2171 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2172 2173 #if 0 2174 atw_tsf(sc); 2175 #endif 2176 2177 /* negotiate rates with new IBSS */ 2178 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2179 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2180 if (ni->ni_rates.rs_nrates == 0) { 2181 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2182 ether_sprintf(ni->ni_bssid)); 2183 return; 2184 } 2185 2186 if (do_print) { 2187 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2188 ether_sprintf(ic->ic_bss->ni_bssid)); 2189 printf("%s ", ether_sprintf(ni->ni_bssid)); 2190 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2191 } 2192 2193 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2194 2195 atw_write_bssid(sc); 2196 atw_write_bcn_thresh(sc); 2197 atw_start_beacon(sc, 1); 2198 } 2199 2200 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2201 * In ad hoc mode, the SSID is written to the beacons sent by the 2202 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2203 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2204 * indications. 2205 */ 2206 static void 2207 atw_write_ssid(struct atw_softc *sc) 2208 { 2209 struct ieee80211com *ic = &sc->sc_ic; 2210 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2211 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2212 2213 memset(buf, 0, sizeof(buf)); 2214 buf[0] = ic->ic_bss->ni_esslen; 2215 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2216 2217 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2218 } 2219 2220 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2221 * In ad hoc mode, the supported rates are written to beacons sent by the 2222 * ADM8211. 2223 */ 2224 static void 2225 atw_write_sup_rates(struct atw_softc *sc) 2226 { 2227 struct ieee80211com *ic = &sc->sc_ic; 2228 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2229 * supported rates 2230 */ 2231 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2232 2233 memset(buf, 0, sizeof(buf)); 2234 2235 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2236 2237 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2238 ic->ic_bss->ni_rates.rs_nrates); 2239 2240 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2241 } 2242 2243 /* Start/stop sending beacons. */ 2244 void 2245 atw_start_beacon(struct atw_softc *sc, int start) 2246 { 2247 struct ieee80211com *ic = &sc->sc_ic; 2248 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2249 2250 if (ATW_IS_ENABLED(sc) == 0) 2251 return; 2252 2253 len = capinfo = 0; 2254 2255 /* start beacons */ 2256 len = sizeof(struct ieee80211_frame) + 2257 8 /* timestamp */ + 2 /* beacon interval */ + 2258 2 /* capability info */ + 2259 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2260 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2261 3 /* DS parameters */ + 2262 IEEE80211_CRC_LEN; 2263 2264 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2265 2266 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2267 2268 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2269 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2270 2271 if (!start) 2272 return; 2273 2274 /* TBD use ni_capinfo */ 2275 2276 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2277 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2278 if (ic->ic_flags & IEEE80211_F_WEPON) 2279 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2280 2281 switch (ic->ic_opmode) { 2282 case IEEE80211_M_IBSS: 2283 len += 4; /* IBSS parameters */ 2284 capinfo |= IEEE80211_CAPINFO_IBSS; 2285 break; 2286 case IEEE80211_M_HOSTAP: 2287 /* XXX 6-byte minimum TIM */ 2288 len += atw_beacon_len_adjust; 2289 capinfo |= IEEE80211_CAPINFO_ESS; 2290 break; 2291 default: 2292 return; 2293 } 2294 2295 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2296 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2297 2298 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2299 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2300 2301 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2302 sc->sc_dev.dv_xname, reg_bcnt)); 2303 2304 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2305 sc->sc_dev.dv_xname, reg_cap1)); 2306 } 2307 2308 /* First beacon was sent at time 0 microseconds, current time is 2309 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2310 * microseconds. Return the expected time in microseconds for the 2311 * beacon after next. 2312 */ 2313 static __inline u_int64_t 2314 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2315 { 2316 return tsft + (tbtt - tsft % tbtt); 2317 } 2318 2319 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2320 * the ieee80211com. 2321 * 2322 * Predict the next target beacon transmission time (TBTT) and 2323 * write it to the ADM8211. 2324 */ 2325 static void 2326 atw_tsf(struct atw_softc *sc) 2327 { 2328 #define TBTTOFS 20 /* TU */ 2329 2330 struct ieee80211com *ic = &sc->sc_ic; 2331 u_int64_t tsft, tbtt; 2332 2333 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2334 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2335 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2336 tsft = ATW_READ(sc, ATW_TSFTH); 2337 tsft <<= 32; 2338 tsft |= ATW_READ(sc, ATW_TSFTL); 2339 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2340 } else 2341 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2342 2343 tbtt = atw_predict_beacon(tsft, 2344 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2345 2346 /* skip one more beacon so that the TBTT cannot pass before 2347 * we've programmed it, and also so that we can subtract a 2348 * few TU so that we wake a little before TBTT. 2349 */ 2350 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2351 2352 /* wake up a little early */ 2353 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2354 2355 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2356 sc->sc_dev.dv_xname, tsft, tbtt)); 2357 2358 ATW_WRITE(sc, ATW_TOFS1, 2359 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2360 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2361 LSHIFT( 2362 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2363 ATW_TOFS1_TBTTPRE_MASK)); 2364 #undef TBTTOFS 2365 } 2366 2367 static void 2368 atw_next_scan(void *arg) 2369 { 2370 struct atw_softc *sc = arg; 2371 struct ieee80211com *ic = &sc->sc_ic; 2372 struct ifnet *ifp = &ic->ic_if; 2373 int s; 2374 2375 /* don't call atw_start w/o network interrupts blocked */ 2376 s = splnet(); 2377 if (ic->ic_state == IEEE80211_S_SCAN) 2378 ieee80211_next_scan(ifp); 2379 splx(s); 2380 } 2381 2382 /* Synchronize the hardware state with the software state. */ 2383 static int 2384 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2385 { 2386 struct ifnet *ifp = &ic->ic_if; 2387 struct atw_softc *sc = ifp->if_softc; 2388 enum ieee80211_state ostate; 2389 int error; 2390 2391 ostate = ic->ic_state; 2392 2393 if (nstate == IEEE80211_S_INIT) { 2394 callout_stop(&sc->sc_scan_ch); 2395 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2396 atw_start_beacon(sc, 0); 2397 return (*sc->sc_newstate)(ic, nstate, arg); 2398 } 2399 2400 if ((error = atw_tune(sc)) != 0) 2401 return error; 2402 2403 switch (nstate) { 2404 case IEEE80211_S_ASSOC: 2405 break; 2406 case IEEE80211_S_INIT: 2407 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2408 break; 2409 case IEEE80211_S_SCAN: 2410 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2411 atw_write_bssid(sc); 2412 2413 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2414 atw_next_scan, sc); 2415 2416 break; 2417 case IEEE80211_S_RUN: 2418 if (ic->ic_opmode == IEEE80211_M_STA) 2419 break; 2420 /*FALLTHROUGH*/ 2421 case IEEE80211_S_AUTH: 2422 atw_write_bssid(sc); 2423 atw_write_bcn_thresh(sc); 2424 atw_write_ssid(sc); 2425 atw_write_sup_rates(sc); 2426 2427 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2428 ic->ic_opmode == IEEE80211_M_MONITOR) 2429 break; 2430 2431 /* set listen interval 2432 * XXX do software units agree w/ hardware? 2433 */ 2434 ATW_WRITE(sc, ATW_BPLI, 2435 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2436 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2437 ATW_BPLI_LI_MASK)); 2438 2439 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2440 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2441 2442 atw_tsf(sc); 2443 break; 2444 } 2445 2446 if (nstate != IEEE80211_S_SCAN) 2447 callout_stop(&sc->sc_scan_ch); 2448 2449 if (nstate == IEEE80211_S_RUN && 2450 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2451 ic->ic_opmode == IEEE80211_M_IBSS)) 2452 atw_start_beacon(sc, 1); 2453 else 2454 atw_start_beacon(sc, 0); 2455 2456 return (*sc->sc_newstate)(ic, nstate, arg); 2457 } 2458 2459 /* 2460 * atw_add_rxbuf: 2461 * 2462 * Add a receive buffer to the indicated descriptor. 2463 */ 2464 int 2465 atw_add_rxbuf(struct atw_softc *sc, int idx) 2466 { 2467 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2468 struct mbuf *m; 2469 int error; 2470 2471 MGETHDR(m, M_DONTWAIT, MT_DATA); 2472 if (m == NULL) 2473 return (ENOBUFS); 2474 2475 MCLGET(m, M_DONTWAIT); 2476 if ((m->m_flags & M_EXT) == 0) { 2477 m_freem(m); 2478 return (ENOBUFS); 2479 } 2480 2481 if (rxs->rxs_mbuf != NULL) 2482 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2483 2484 rxs->rxs_mbuf = m; 2485 2486 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2487 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2488 BUS_DMA_READ|BUS_DMA_NOWAIT); 2489 if (error) { 2490 printf("%s: can't load rx DMA map %d, error = %d\n", 2491 sc->sc_dev.dv_xname, idx, error); 2492 panic("atw_add_rxbuf"); /* XXX */ 2493 } 2494 2495 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2496 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2497 2498 ATW_INIT_RXDESC(sc, idx); 2499 2500 return (0); 2501 } 2502 2503 /* 2504 * Release any queued transmit buffers. 2505 */ 2506 void 2507 atw_txdrain(struct atw_softc *sc) 2508 { 2509 struct atw_txsoft *txs; 2510 2511 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2512 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2513 if (txs->txs_mbuf != NULL) { 2514 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2515 m_freem(txs->txs_mbuf); 2516 txs->txs_mbuf = NULL; 2517 } 2518 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2519 } 2520 sc->sc_tx_timer = 0; 2521 } 2522 2523 /* 2524 * atw_stop: [ ifnet interface function ] 2525 * 2526 * Stop transmission on the interface. 2527 */ 2528 void 2529 atw_stop(struct ifnet *ifp, int disable) 2530 { 2531 struct atw_softc *sc = ifp->if_softc; 2532 struct ieee80211com *ic = &sc->sc_ic; 2533 2534 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2535 2536 /* Disable interrupts. */ 2537 ATW_WRITE(sc, ATW_IER, 0); 2538 2539 /* Stop the transmit and receive processes. */ 2540 sc->sc_opmode = 0; 2541 ATW_WRITE(sc, ATW_NAR, 0); 2542 ATW_WRITE(sc, ATW_TDBD, 0); 2543 ATW_WRITE(sc, ATW_TDBP, 0); 2544 ATW_WRITE(sc, ATW_RDB, 0); 2545 2546 atw_txdrain(sc); 2547 2548 if (disable) { 2549 atw_rxdrain(sc); 2550 atw_disable(sc); 2551 } 2552 2553 /* 2554 * Mark the interface down and cancel the watchdog timer. 2555 */ 2556 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2557 ifp->if_timer = 0; 2558 2559 if (!disable) 2560 atw_reset(sc); 2561 } 2562 2563 /* 2564 * atw_rxdrain: 2565 * 2566 * Drain the receive queue. 2567 */ 2568 void 2569 atw_rxdrain(struct atw_softc *sc) 2570 { 2571 struct atw_rxsoft *rxs; 2572 int i; 2573 2574 for (i = 0; i < ATW_NRXDESC; i++) { 2575 rxs = &sc->sc_rxsoft[i]; 2576 if (rxs->rxs_mbuf == NULL) 2577 continue; 2578 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2579 m_freem(rxs->rxs_mbuf); 2580 rxs->rxs_mbuf = NULL; 2581 } 2582 } 2583 2584 /* 2585 * atw_detach: 2586 * 2587 * Detach an ADM8211 interface. 2588 */ 2589 int 2590 atw_detach(struct atw_softc *sc) 2591 { 2592 struct ifnet *ifp = &sc->sc_ic.ic_if; 2593 struct atw_rxsoft *rxs; 2594 struct atw_txsoft *txs; 2595 int i; 2596 2597 /* 2598 * Succeed now if there isn't any work to do. 2599 */ 2600 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2601 return (0); 2602 2603 ieee80211_ifdetach(ifp); 2604 if_detach(ifp); 2605 2606 for (i = 0; i < ATW_NRXDESC; i++) { 2607 rxs = &sc->sc_rxsoft[i]; 2608 if (rxs->rxs_mbuf != NULL) { 2609 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2610 m_freem(rxs->rxs_mbuf); 2611 rxs->rxs_mbuf = NULL; 2612 } 2613 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2614 } 2615 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2616 txs = &sc->sc_txsoft[i]; 2617 if (txs->txs_mbuf != NULL) { 2618 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2619 m_freem(txs->txs_mbuf); 2620 txs->txs_mbuf = NULL; 2621 } 2622 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2623 } 2624 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2625 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2626 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2627 sizeof(struct atw_control_data)); 2628 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2629 2630 shutdownhook_disestablish(sc->sc_sdhook); 2631 powerhook_disestablish(sc->sc_powerhook); 2632 2633 if (sc->sc_srom) 2634 free(sc->sc_srom, M_DEVBUF); 2635 2636 return (0); 2637 } 2638 2639 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2640 void 2641 atw_shutdown(void *arg) 2642 { 2643 struct atw_softc *sc = arg; 2644 2645 atw_stop(&sc->sc_ic.ic_if, 1); 2646 } 2647 2648 int 2649 atw_intr(void *arg) 2650 { 2651 struct atw_softc *sc = arg; 2652 struct ifnet *ifp = &sc->sc_ic.ic_if; 2653 u_int32_t status, rxstatus, txstatus, linkstatus; 2654 int handled = 0, txthresh; 2655 2656 #ifdef DEBUG 2657 if (ATW_IS_ENABLED(sc) == 0) 2658 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2659 #endif 2660 2661 /* 2662 * If the interface isn't running, the interrupt couldn't 2663 * possibly have come from us. 2664 */ 2665 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2666 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2667 return (0); 2668 2669 for (;;) { 2670 status = ATW_READ(sc, ATW_STSR); 2671 2672 if (status) 2673 ATW_WRITE(sc, ATW_STSR, status); 2674 2675 if (sc->sc_intr_ack != NULL) 2676 (*sc->sc_intr_ack)(sc); 2677 2678 #ifdef ATW_DEBUG 2679 #define PRINTINTR(flag) do { \ 2680 if ((status & flag) != 0) { \ 2681 printf("%s" #flag, delim); \ 2682 delim = ","; \ 2683 } \ 2684 } while (0) 2685 2686 if (atw_debug > 1 && status) { 2687 const char *delim = "<"; 2688 2689 printf("%s: reg[STSR] = %x", 2690 sc->sc_dev.dv_xname, status); 2691 2692 PRINTINTR(ATW_INTR_FBE); 2693 PRINTINTR(ATW_INTR_LINKOFF); 2694 PRINTINTR(ATW_INTR_LINKON); 2695 PRINTINTR(ATW_INTR_RCI); 2696 PRINTINTR(ATW_INTR_RDU); 2697 PRINTINTR(ATW_INTR_REIS); 2698 PRINTINTR(ATW_INTR_RPS); 2699 PRINTINTR(ATW_INTR_TCI); 2700 PRINTINTR(ATW_INTR_TDU); 2701 PRINTINTR(ATW_INTR_TLT); 2702 PRINTINTR(ATW_INTR_TPS); 2703 PRINTINTR(ATW_INTR_TRT); 2704 PRINTINTR(ATW_INTR_TUF); 2705 PRINTINTR(ATW_INTR_BCNTC); 2706 PRINTINTR(ATW_INTR_ATIME); 2707 PRINTINTR(ATW_INTR_TBTT); 2708 PRINTINTR(ATW_INTR_TSCZ); 2709 PRINTINTR(ATW_INTR_TSFTF); 2710 printf(">\n"); 2711 } 2712 #undef PRINTINTR 2713 #endif /* ATW_DEBUG */ 2714 2715 if ((status & sc->sc_inten) == 0) 2716 break; 2717 2718 handled = 1; 2719 2720 rxstatus = status & sc->sc_rxint_mask; 2721 txstatus = status & sc->sc_txint_mask; 2722 linkstatus = status & sc->sc_linkint_mask; 2723 2724 if (linkstatus) { 2725 atw_linkintr(sc, linkstatus); 2726 } 2727 2728 if (rxstatus) { 2729 /* Grab any new packets. */ 2730 atw_rxintr(sc); 2731 2732 if (rxstatus & ATW_INTR_RDU) { 2733 printf("%s: receive ring overrun\n", 2734 sc->sc_dev.dv_xname); 2735 /* Get the receive process going again. */ 2736 ATW_WRITE(sc, ATW_RDR, 0x1); 2737 break; 2738 } 2739 } 2740 2741 if (txstatus) { 2742 /* Sweep up transmit descriptors. */ 2743 atw_txintr(sc); 2744 2745 if (txstatus & ATW_INTR_TLT) 2746 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2747 sc->sc_dev.dv_xname)); 2748 2749 if (txstatus & ATW_INTR_TRT) 2750 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2751 sc->sc_dev.dv_xname)); 2752 2753 /* If Tx under-run, increase our transmit threshold 2754 * if another is available. 2755 */ 2756 txthresh = sc->sc_txthresh + 1; 2757 if ((txstatus & ATW_INTR_TUF) && 2758 sc->sc_txth[txthresh].txth_name != NULL) { 2759 /* Idle the transmit process. */ 2760 atw_idle(sc, ATW_NAR_ST); 2761 2762 sc->sc_txthresh = txthresh; 2763 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2764 sc->sc_opmode |= 2765 sc->sc_txth[txthresh].txth_opmode; 2766 printf("%s: transmit underrun; new " 2767 "threshold: %s\n", sc->sc_dev.dv_xname, 2768 sc->sc_txth[txthresh].txth_name); 2769 2770 /* Set the new threshold and restart 2771 * the transmit process. 2772 */ 2773 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2774 /* XXX Log every Nth underrun from 2775 * XXX now on? 2776 */ 2777 } 2778 } 2779 2780 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2781 if (status & ATW_INTR_TPS) 2782 printf("%s: transmit process stopped\n", 2783 sc->sc_dev.dv_xname); 2784 if (status & ATW_INTR_RPS) 2785 printf("%s: receive process stopped\n", 2786 sc->sc_dev.dv_xname); 2787 (void)atw_init(ifp); 2788 break; 2789 } 2790 2791 if (status & ATW_INTR_FBE) { 2792 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2793 (void)atw_init(ifp); 2794 break; 2795 } 2796 2797 /* 2798 * Not handled: 2799 * 2800 * Transmit buffer unavailable -- normal 2801 * condition, nothing to do, really. 2802 * 2803 * Early receive interrupt -- not available on 2804 * all chips, we just use RI. We also only 2805 * use single-segment receive DMA, so this 2806 * is mostly useless. 2807 * 2808 * TBD others 2809 */ 2810 } 2811 2812 /* Try to get more packets going. */ 2813 atw_start(ifp); 2814 2815 return (handled); 2816 } 2817 2818 /* 2819 * atw_idle: 2820 * 2821 * Cause the transmit and/or receive processes to go idle. 2822 * 2823 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2824 * process in STSR if I clear SR or ST after the process has already 2825 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2826 * do not seem to be too reliable. Perhaps I have the sense of the 2827 * Rx bits switched with the Tx bits? 2828 */ 2829 void 2830 atw_idle(struct atw_softc *sc, u_int32_t bits) 2831 { 2832 u_int32_t ackmask = 0, opmode, stsr, test0; 2833 int i, s; 2834 2835 /* without this, somehow we run concurrently w/ interrupt handler */ 2836 s = splnet(); 2837 2838 opmode = sc->sc_opmode & ~bits; 2839 2840 if (bits & ATW_NAR_SR) 2841 ackmask |= ATW_INTR_RPS; 2842 2843 if (bits & ATW_NAR_ST) { 2844 ackmask |= ATW_INTR_TPS; 2845 /* set ATW_NAR_HF to flush TX FIFO. */ 2846 opmode |= ATW_NAR_HF; 2847 } 2848 2849 ATW_WRITE(sc, ATW_NAR, opmode); 2850 2851 for (i = 0; i < 1000; i++) { 2852 stsr = ATW_READ(sc, ATW_STSR); 2853 if ((stsr & ackmask) == ackmask) 2854 break; 2855 DELAY(10); 2856 } 2857 2858 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2859 2860 if ((stsr & ackmask) == ackmask) 2861 goto out; 2862 2863 test0 = ATW_READ(sc, ATW_TEST0); 2864 2865 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2866 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2867 printf("%s: transmit process not idle [%s]\n", 2868 sc->sc_dev.dv_xname, 2869 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2870 printf("%s: bits %08x test0 %08x stsr %08x\n", 2871 sc->sc_dev.dv_xname, bits, test0, stsr); 2872 } 2873 2874 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2875 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2876 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2877 sc->sc_dev.dv_xname, 2878 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2879 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2880 sc->sc_dev.dv_xname, bits, test0, stsr)); 2881 } 2882 out: 2883 if ((bits & ATW_NAR_ST) != 0) 2884 atw_txdrain(sc); 2885 splx(s); 2886 return; 2887 } 2888 2889 /* 2890 * atw_linkintr: 2891 * 2892 * Helper; handle link-status interrupts. 2893 */ 2894 void 2895 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2896 { 2897 struct ieee80211com *ic = &sc->sc_ic; 2898 2899 if (ic->ic_state != IEEE80211_S_RUN) 2900 return; 2901 2902 if (linkstatus & ATW_INTR_LINKON) { 2903 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2904 sc->sc_rescan_timer = 0; 2905 } else if (linkstatus & ATW_INTR_LINKOFF) { 2906 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2907 if (ic->ic_opmode != IEEE80211_M_STA) 2908 return; 2909 sc->sc_rescan_timer = 3; 2910 ic->ic_if.if_timer = 1; 2911 } 2912 } 2913 2914 /* 2915 * atw_rxintr: 2916 * 2917 * Helper; handle receive interrupts. 2918 */ 2919 void 2920 atw_rxintr(struct atw_softc *sc) 2921 { 2922 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2923 struct ieee80211com *ic = &sc->sc_ic; 2924 struct ieee80211_node *ni; 2925 struct ieee80211_frame *wh; 2926 struct ifnet *ifp = &ic->ic_if; 2927 struct atw_rxsoft *rxs; 2928 struct mbuf *m; 2929 u_int32_t rxstat; 2930 int i, len, rate, rate0; 2931 u_int32_t rssi; 2932 2933 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2934 rxs = &sc->sc_rxsoft[i]; 2935 2936 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2937 2938 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2939 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2940 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2941 2942 if (rxstat & ATW_RXSTAT_OWN) 2943 break; /* We have processed all receive buffers. */ 2944 2945 DPRINTF3(sc, 2946 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2947 sc->sc_dev.dv_xname, 2948 sc->sc_rxdescs[i].ar_stat, 2949 sc->sc_rxdescs[i].ar_rssi, 2950 sc->sc_rxdescs[i].ar_buf1, 2951 sc->sc_rxdescs[i].ar_buf2)); 2952 2953 /* 2954 * Make sure the packet fits in one buffer. This should 2955 * always be the case. 2956 */ 2957 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2958 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2959 printf("%s: incoming packet spilled, resetting\n", 2960 sc->sc_dev.dv_xname); 2961 (void)atw_init(ifp); 2962 return; 2963 } 2964 2965 /* 2966 * If an error occurred, update stats, clear the status 2967 * word, and leave the packet buffer in place. It will 2968 * simply be reused the next time the ring comes around. 2969 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2970 * error. 2971 */ 2972 2973 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2974 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2975 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2976 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2977 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2978 ATW_RXSTAT_ICVE)) != 0)) { 2979 #define PRINTERR(bit, str) \ 2980 if (rxstat & (bit)) \ 2981 printf("%s: receive error: %s\n", \ 2982 sc->sc_dev.dv_xname, str) 2983 ifp->if_ierrors++; 2984 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2985 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2986 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2987 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2988 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2989 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2990 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2991 #undef PRINTERR 2992 ATW_INIT_RXDESC(sc, i); 2993 continue; 2994 } 2995 2996 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2997 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2998 2999 /* 3000 * No errors; receive the packet. Note the ADM8211 3001 * includes the CRC in promiscuous mode. 3002 */ 3003 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3004 3005 /* 3006 * Allocate a new mbuf cluster. If that fails, we are 3007 * out of memory, and must drop the packet and recycle 3008 * the buffer that's already attached to this descriptor. 3009 */ 3010 m = rxs->rxs_mbuf; 3011 if (atw_add_rxbuf(sc, i) != 0) { 3012 ifp->if_ierrors++; 3013 ATW_INIT_RXDESC(sc, i); 3014 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3015 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3016 continue; 3017 } 3018 3019 ifp->if_ipackets++; 3020 if (sc->sc_opmode & ATW_NAR_PR) 3021 m->m_flags |= M_HASFCS; 3022 m->m_pkthdr.rcvif = ifp; 3023 m->m_pkthdr.len = m->m_len = len; 3024 3025 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3026 rate = 0; 3027 else 3028 rate = rate_tbl[rate0]; 3029 3030 #if NBPFILTER > 0 3031 /* Pass this up to any BPF listeners. */ 3032 if (sc->sc_radiobpf != NULL) { 3033 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3034 3035 tap->ar_rate = rate; 3036 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3037 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3038 3039 /* TBD verify units are dB */ 3040 tap->ar_antsignal = (int)rssi; 3041 /* TBD tap->ar_flags */ 3042 3043 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3044 tap->ar_ihdr.it_len, m); 3045 } 3046 #endif /* NPBFILTER > 0 */ 3047 3048 wh = mtod(m, struct ieee80211_frame *); 3049 ni = ieee80211_find_rxnode(ic, wh); 3050 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3051 /* 3052 * The frame may have caused the node to be marked for 3053 * reclamation (e.g. in response to a DEAUTH message) 3054 * so use free_node here instead of unref_node. 3055 */ 3056 if (ni == ic->ic_bss) 3057 ieee80211_unref_node(&ni); 3058 else 3059 ieee80211_free_node(ic, ni); 3060 } 3061 3062 /* Update the receive pointer. */ 3063 sc->sc_rxptr = i; 3064 } 3065 3066 /* 3067 * atw_txintr: 3068 * 3069 * Helper; handle transmit interrupts. 3070 */ 3071 void 3072 atw_txintr(struct atw_softc *sc) 3073 { 3074 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3075 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3076 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3077 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3078 3079 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3080 struct ifnet *ifp = &sc->sc_ic.ic_if; 3081 struct atw_txsoft *txs; 3082 u_int32_t txstat; 3083 3084 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3085 sc->sc_dev.dv_xname, sc->sc_flags)); 3086 3087 ifp->if_flags &= ~IFF_OACTIVE; 3088 3089 /* 3090 * Go through our Tx list and free mbufs for those 3091 * frames that have been transmitted. 3092 */ 3093 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3094 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3095 txs->txs_ndescs, 3096 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3097 3098 #ifdef ATW_DEBUG 3099 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3100 int i; 3101 printf(" txsoft %p transmit chain:\n", txs); 3102 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3103 printf(" descriptor %d:\n", i); 3104 printf(" at_status: 0x%08x\n", 3105 le32toh(sc->sc_txdescs[i].at_stat)); 3106 printf(" at_flags: 0x%08x\n", 3107 le32toh(sc->sc_txdescs[i].at_flags)); 3108 printf(" at_buf1: 0x%08x\n", 3109 le32toh(sc->sc_txdescs[i].at_buf1)); 3110 printf(" at_buf2: 0x%08x\n", 3111 le32toh(sc->sc_txdescs[i].at_buf2)); 3112 if (i == txs->txs_lastdesc) 3113 break; 3114 } 3115 } 3116 #endif 3117 3118 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3119 if (txstat & ATW_TXSTAT_OWN) 3120 break; 3121 3122 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3123 3124 sc->sc_txfree += txs->txs_ndescs; 3125 3126 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3127 0, txs->txs_dmamap->dm_mapsize, 3128 BUS_DMASYNC_POSTWRITE); 3129 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3130 m_freem(txs->txs_mbuf); 3131 txs->txs_mbuf = NULL; 3132 3133 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3134 3135 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3136 (txstat & TXSTAT_ERRMASK) != 0) { 3137 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3138 txstat_buf, sizeof(txstat_buf)); 3139 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3140 txstat_buf, 3141 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3142 } 3143 3144 /* 3145 * Check for errors and collisions. 3146 */ 3147 if (txstat & ATW_TXSTAT_TUF) 3148 sc->sc_stats.ts_tx_tuf++; 3149 if (txstat & ATW_TXSTAT_TLT) 3150 sc->sc_stats.ts_tx_tlt++; 3151 if (txstat & ATW_TXSTAT_TRT) 3152 sc->sc_stats.ts_tx_trt++; 3153 if (txstat & ATW_TXSTAT_TRO) 3154 sc->sc_stats.ts_tx_tro++; 3155 if (txstat & ATW_TXSTAT_SOFBR) { 3156 sc->sc_stats.ts_tx_sofbr++; 3157 } 3158 3159 if ((txstat & ATW_TXSTAT_ES) == 0) 3160 ifp->if_collisions += 3161 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3162 else 3163 ifp->if_oerrors++; 3164 3165 ifp->if_opackets++; 3166 } 3167 3168 /* 3169 * If there are no more pending transmissions, cancel the watchdog 3170 * timer. 3171 */ 3172 if (txs == NULL) 3173 sc->sc_tx_timer = 0; 3174 #undef TXSTAT_ERRMASK 3175 #undef TXSTAT_FMT 3176 } 3177 3178 /* 3179 * atw_watchdog: [ifnet interface function] 3180 * 3181 * Watchdog timer handler. 3182 */ 3183 void 3184 atw_watchdog(struct ifnet *ifp) 3185 { 3186 struct atw_softc *sc = ifp->if_softc; 3187 struct ieee80211com *ic = &sc->sc_ic; 3188 3189 ifp->if_timer = 0; 3190 if (ATW_IS_ENABLED(sc) == 0) 3191 return; 3192 3193 if (sc->sc_rescan_timer) { 3194 if (--sc->sc_rescan_timer == 0) 3195 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3196 } 3197 if (sc->sc_tx_timer) { 3198 if (--sc->sc_tx_timer == 0 && 3199 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3200 printf("%s: transmit timeout\n", ifp->if_xname); 3201 ifp->if_oerrors++; 3202 (void)atw_init(ifp); 3203 atw_start(ifp); 3204 } 3205 } 3206 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3207 ifp->if_timer = 1; 3208 ieee80211_watchdog(ifp); 3209 } 3210 3211 /* Compute the 802.11 Duration field and the PLCP Length fields for 3212 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3213 * Write the fields to the ADM8211 Tx header, frm. 3214 * 3215 * TBD use the fragmentation threshold to find the right duration for 3216 * the first & last fragments. 3217 * 3218 * TBD make certain of the duration fields applied by the ADM8211 to each 3219 * fragment. I think that the ADM8211 knows how to subtract the CTS 3220 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3221 * I also think that the ADM8211 does *some* arithmetic for us, because 3222 * otherwise I think we would have to set a first duration for CTS/first 3223 * fragment, a second duration for fragments between the first and the 3224 * last, and a third duration for the last fragment. 3225 * 3226 * TBD make certain that duration fields reflect addition of FCS/WEP 3227 * and correct duration arithmetic as necessary. 3228 */ 3229 static void 3230 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3231 int len) 3232 { 3233 int remainder; 3234 3235 /* deal also with encrypted fragments */ 3236 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3237 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3238 sc->sc_dev.dv_xname)); 3239 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3240 IEEE80211_WEP_CRCLEN; 3241 } 3242 3243 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3244 * duration (XXX added by MAC?). 3245 */ 3246 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3247 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3248 3249 if (rate <= 4) 3250 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3251 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3252 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3253 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3254 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3255 else 3256 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3257 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3258 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3259 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3260 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3261 3262 /* lengthen duration if long preamble */ 3263 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3264 frm->atw_head_dur += 3265 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3266 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3267 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3268 IEEE80211_DUR_DS_FAST_PLCPHDR); 3269 3270 if (remainder != 0) 3271 frm->atw_head_dur++; 3272 3273 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3274 (rate == 2 || rate == 4)) { 3275 /* derived from Linux: how could this be right? */ 3276 frm->atw_head_plcplen = frm->atw_head_dur; 3277 } else { 3278 frm->atw_head_plcplen = (16 * len) / rate; 3279 remainder = (80 * len) % (rate * 5); 3280 3281 if (remainder != 0) { 3282 frm->atw_head_plcplen++; 3283 3284 /* XXX magic */ 3285 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3286 rate == 22 && remainder <= 30) 3287 frm->atw_head_plcplen |= 0x8000; 3288 } 3289 } 3290 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3291 htole16(frm->atw_head_plcplen); 3292 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3293 } 3294 3295 #ifdef ATW_DEBUG 3296 static void 3297 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3298 { 3299 struct atw_softc *sc = ifp->if_softc; 3300 struct mbuf *m; 3301 int i, noctets = 0; 3302 3303 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3304 m0->m_pkthdr.len); 3305 3306 for (m = m0; m; m = m->m_next) { 3307 if (m->m_len == 0) 3308 continue; 3309 for (i = 0; i < m->m_len; i++) { 3310 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3311 if (++noctets % 24 == 0) 3312 printf("\n"); 3313 } 3314 } 3315 printf("%s%s: %d bytes emitted\n", 3316 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3317 } 3318 #endif /* ATW_DEBUG */ 3319 3320 /* 3321 * atw_start: [ifnet interface function] 3322 * 3323 * Start packet transmission on the interface. 3324 */ 3325 void 3326 atw_start(struct ifnet *ifp) 3327 { 3328 struct atw_softc *sc = ifp->if_softc; 3329 struct ieee80211com *ic = &sc->sc_ic; 3330 struct ieee80211_node *ni; 3331 struct ieee80211_frame *wh; 3332 struct atw_frame *hh; 3333 struct mbuf *m0, *m; 3334 struct atw_txsoft *txs, *last_txs; 3335 struct atw_txdesc *txd; 3336 int do_encrypt, rate; 3337 bus_dmamap_t dmamap; 3338 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3339 3340 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3341 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3342 3343 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3344 return; 3345 3346 #if 0 /* TBD ??? */ 3347 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3348 return; 3349 #endif 3350 3351 /* 3352 * Remember the previous number of free descriptors and 3353 * the first descriptor we'll use. 3354 */ 3355 ofree = sc->sc_txfree; 3356 firsttx = sc->sc_txnext; 3357 3358 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3359 sc->sc_dev.dv_xname, ofree, firsttx)); 3360 3361 /* 3362 * Loop through the send queue, setting up transmit descriptors 3363 * until we drain the queue, or use up all available transmit 3364 * descriptors. 3365 */ 3366 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3367 sc->sc_txfree != 0) { 3368 3369 /* 3370 * Grab a packet off the management queue, if it 3371 * is not empty. Otherwise, from the data queue. 3372 */ 3373 IF_DEQUEUE(&ic->ic_mgtq, m0); 3374 if (m0 != NULL) { 3375 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3376 m0->m_pkthdr.rcvif = NULL; 3377 } else { 3378 IFQ_DEQUEUE(&ifp->if_snd, m0); 3379 if (m0 == NULL) 3380 break; 3381 #if NBPFILTER > 0 3382 if (ifp->if_bpf != NULL) 3383 bpf_mtap(ifp->if_bpf, m0); 3384 #endif /* NBPFILTER > 0 */ 3385 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3386 ifp->if_oerrors++; 3387 break; 3388 } 3389 } 3390 3391 rate = MAX(ieee80211_get_rate(ic), 2); 3392 3393 #if NBPFILTER > 0 3394 /* 3395 * Pass the packet to any BPF listeners. 3396 */ 3397 if (ic->ic_rawbpf != NULL) 3398 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3399 3400 if (sc->sc_radiobpf != NULL) { 3401 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3402 3403 tap->at_rate = rate; 3404 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3405 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3406 3407 /* TBD tap->at_flags */ 3408 3409 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3410 tap->at_ihdr.it_len, m0); 3411 } 3412 #endif /* NBPFILTER > 0 */ 3413 3414 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3415 3416 if (ni != NULL && ni != ic->ic_bss) 3417 ieee80211_free_node(ic, ni); 3418 3419 if (m0 == NULL) { 3420 ifp->if_oerrors++; 3421 break; 3422 } 3423 3424 /* just to make sure. */ 3425 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3426 3427 if (m0 == NULL) { 3428 ifp->if_oerrors++; 3429 break; 3430 } 3431 3432 hh = mtod(m0, struct atw_frame *); 3433 wh = &hh->atw_ihdr; 3434 3435 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3436 3437 /* Copy everything we need from the 802.11 header: 3438 * Frame Control; address 1, address 3, or addresses 3439 * 3 and 4. NIC fills in BSSID, SA. 3440 */ 3441 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3442 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3443 panic("%s: illegal WDS frame", 3444 sc->sc_dev.dv_xname); 3445 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3446 } else 3447 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3448 3449 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3450 3451 /* initialize remaining Tx parameters */ 3452 memset(&hh->u, 0, sizeof(hh->u)); 3453 3454 hh->atw_rate = rate * 5; 3455 /* XXX this could be incorrect if M_FCS. _encap should 3456 * probably strip FCS just in case it sticks around in 3457 * bridged packets. 3458 */ 3459 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3460 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3461 sizeof(struct atw_frame)); 3462 3463 #if 0 3464 /* this virtually guaranteed that WEP-encrypted frames 3465 * are fragmented. oops. 3466 */ 3467 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3468 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3469 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3470 #else 3471 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3472 #endif 3473 3474 hh->atw_rtylmt = 3; 3475 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3476 if (do_encrypt) { 3477 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3478 hh->atw_keyid = ic->ic_wep_txkey; 3479 } 3480 3481 /* TBD 4-addr frames */ 3482 atw_frame_setdurs(sc, hh, rate, 3483 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3484 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3485 3486 /* never fragment multicast frames */ 3487 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3488 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3489 } else if (sc->sc_flags & ATWF_RTSCTS) { 3490 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3491 } 3492 3493 #ifdef ATW_DEBUG 3494 /* experimental stuff */ 3495 if (atw_xrtylmt != ~0) 3496 hh->atw_rtylmt = atw_xrtylmt; 3497 if (atw_xhdrctl != 0) 3498 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3499 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3500 hh->atw_service = atw_xservice; 3501 if (atw_xpaylen != 0) 3502 hh->atw_paylen = htole16(atw_xpaylen); 3503 hh->atw_fragnum = 0; 3504 3505 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3506 printf("%s: dst = %s, rate = 0x%02x, " 3507 "service = 0x%02x, paylen = 0x%04x\n", 3508 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3509 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3510 3511 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3512 "dur1 = 0x%04x, dur2 = 0x%04x, " 3513 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3514 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3515 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3516 hh->atw_tail_dur, hh->atw_head_dur); 3517 3518 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3519 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3520 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3521 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3522 3523 printf("%s: keyid = %d\n", 3524 sc->sc_dev.dv_xname, hh->atw_keyid); 3525 3526 atw_dump_pkt(ifp, m0); 3527 } 3528 #endif /* ATW_DEBUG */ 3529 3530 dmamap = txs->txs_dmamap; 3531 3532 /* 3533 * Load the DMA map. Copy and try (once) again if the packet 3534 * didn't fit in the alloted number of segments. 3535 */ 3536 for (first = 1; 3537 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3538 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3539 first = 0) { 3540 MGETHDR(m, M_DONTWAIT, MT_DATA); 3541 if (m == NULL) { 3542 printf("%s: unable to allocate Tx mbuf\n", 3543 sc->sc_dev.dv_xname); 3544 break; 3545 } 3546 if (m0->m_pkthdr.len > MHLEN) { 3547 MCLGET(m, M_DONTWAIT); 3548 if ((m->m_flags & M_EXT) == 0) { 3549 printf("%s: unable to allocate Tx " 3550 "cluster\n", sc->sc_dev.dv_xname); 3551 m_freem(m); 3552 break; 3553 } 3554 } 3555 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3556 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3557 m_freem(m0); 3558 m0 = m; 3559 m = NULL; 3560 } 3561 if (error != 0) { 3562 printf("%s: unable to load Tx buffer, " 3563 "error = %d\n", sc->sc_dev.dv_xname, error); 3564 m_freem(m0); 3565 break; 3566 } 3567 3568 /* 3569 * Ensure we have enough descriptors free to describe 3570 * the packet. 3571 */ 3572 if (dmamap->dm_nsegs > sc->sc_txfree) { 3573 /* 3574 * Not enough free descriptors to transmit 3575 * this packet. Unload the DMA map and 3576 * drop the packet. Notify the upper layer 3577 * that there are no more slots left. 3578 * 3579 * XXX We could allocate an mbuf and copy, but 3580 * XXX it is worth it? 3581 */ 3582 ifp->if_flags |= IFF_OACTIVE; 3583 bus_dmamap_unload(sc->sc_dmat, dmamap); 3584 m_freem(m0); 3585 break; 3586 } 3587 3588 /* 3589 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3590 */ 3591 3592 /* Sync the DMA map. */ 3593 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3594 BUS_DMASYNC_PREWRITE); 3595 3596 /* XXX arbitrary retry limit; 8 because I have seen it in 3597 * use already and maybe 0 means "no tries" ! 3598 */ 3599 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3600 3601 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3602 sc->sc_dev.dv_xname, rate * 5)); 3603 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3604 3605 /* 3606 * Initialize the transmit descriptors. 3607 */ 3608 for (nexttx = sc->sc_txnext, seg = 0; 3609 seg < dmamap->dm_nsegs; 3610 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3611 /* 3612 * If this is the first descriptor we're 3613 * enqueueing, don't set the OWN bit just 3614 * yet. That could cause a race condition. 3615 * We'll do it below. 3616 */ 3617 txd = &sc->sc_txdescs[nexttx]; 3618 txd->at_ctl = ctl | 3619 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3620 3621 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3622 txd->at_flags = 3623 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3624 ATW_TXFLAG_TBS1_MASK)) | 3625 ((nexttx == (ATW_NTXDESC - 1)) 3626 ? htole32(ATW_TXFLAG_TER) : 0); 3627 lasttx = nexttx; 3628 } 3629 3630 IASSERT(lasttx != -1, ("bad lastx")); 3631 /* Set `first segment' and `last segment' appropriately. */ 3632 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3633 htole32(ATW_TXFLAG_FS); 3634 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3635 3636 #ifdef ATW_DEBUG 3637 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3638 printf(" txsoft %p transmit chain:\n", txs); 3639 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3640 printf(" descriptor %d:\n", seg); 3641 printf(" at_ctl: 0x%08x\n", 3642 le32toh(sc->sc_txdescs[seg].at_ctl)); 3643 printf(" at_flags: 0x%08x\n", 3644 le32toh(sc->sc_txdescs[seg].at_flags)); 3645 printf(" at_buf1: 0x%08x\n", 3646 le32toh(sc->sc_txdescs[seg].at_buf1)); 3647 printf(" at_buf2: 0x%08x\n", 3648 le32toh(sc->sc_txdescs[seg].at_buf2)); 3649 if (seg == lasttx) 3650 break; 3651 } 3652 } 3653 #endif 3654 3655 /* Sync the descriptors we're using. */ 3656 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3657 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3658 3659 /* 3660 * Store a pointer to the packet so we can free it later, 3661 * and remember what txdirty will be once the packet is 3662 * done. 3663 */ 3664 txs->txs_mbuf = m0; 3665 txs->txs_firstdesc = sc->sc_txnext; 3666 txs->txs_lastdesc = lasttx; 3667 txs->txs_ndescs = dmamap->dm_nsegs; 3668 3669 /* Advance the tx pointer. */ 3670 sc->sc_txfree -= dmamap->dm_nsegs; 3671 sc->sc_txnext = nexttx; 3672 3673 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3674 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3675 3676 last_txs = txs; 3677 } 3678 3679 if (txs == NULL || sc->sc_txfree == 0) { 3680 /* No more slots left; notify upper layer. */ 3681 ifp->if_flags |= IFF_OACTIVE; 3682 } 3683 3684 if (sc->sc_txfree != ofree) { 3685 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3686 sc->sc_dev.dv_xname, lasttx, firsttx)); 3687 /* 3688 * Cause a transmit interrupt to happen on the 3689 * last packet we enqueued. 3690 */ 3691 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3692 ATW_CDTXSYNC(sc, lasttx, 1, 3693 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3694 3695 /* 3696 * The entire packet chain is set up. Give the 3697 * first descriptor to the chip now. 3698 */ 3699 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3700 ATW_CDTXSYNC(sc, firsttx, 1, 3701 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3702 3703 /* Wake up the transmitter. */ 3704 ATW_WRITE(sc, ATW_TDR, 0x1); 3705 3706 /* Set a watchdog timer in case the chip flakes out. */ 3707 sc->sc_tx_timer = 5; 3708 ifp->if_timer = 1; 3709 } 3710 } 3711 3712 /* 3713 * atw_power: 3714 * 3715 * Power management (suspend/resume) hook. 3716 */ 3717 void 3718 atw_power(int why, void *arg) 3719 { 3720 struct atw_softc *sc = arg; 3721 struct ifnet *ifp = &sc->sc_ic.ic_if; 3722 int s; 3723 3724 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3725 3726 s = splnet(); 3727 switch (why) { 3728 case PWR_STANDBY: 3729 /* XXX do nothing. */ 3730 break; 3731 case PWR_SUSPEND: 3732 atw_stop(ifp, 0); 3733 if (sc->sc_power != NULL) 3734 (*sc->sc_power)(sc, why); 3735 break; 3736 case PWR_RESUME: 3737 if (ifp->if_flags & IFF_UP) { 3738 if (sc->sc_power != NULL) 3739 (*sc->sc_power)(sc, why); 3740 atw_init(ifp); 3741 } 3742 break; 3743 case PWR_SOFTSUSPEND: 3744 case PWR_SOFTSTANDBY: 3745 case PWR_SOFTRESUME: 3746 break; 3747 } 3748 splx(s); 3749 } 3750 3751 /* 3752 * atw_ioctl: [ifnet interface function] 3753 * 3754 * Handle control requests from the operator. 3755 */ 3756 int 3757 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3758 { 3759 struct atw_softc *sc = ifp->if_softc; 3760 struct ifreq *ifr = (struct ifreq *)data; 3761 int s, error = 0; 3762 3763 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3764 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3765 return ENXIO; 3766 3767 s = splnet(); 3768 3769 switch (cmd) { 3770 case SIOCSIFFLAGS: 3771 if (ifp->if_flags & IFF_UP) { 3772 if (ATW_IS_ENABLED(sc)) { 3773 /* 3774 * To avoid rescanning another access point, 3775 * do not call atw_init() here. Instead, 3776 * only reflect media settings. 3777 */ 3778 atw_filter_setup(sc); 3779 } else 3780 error = atw_init(ifp); 3781 } else if (ATW_IS_ENABLED(sc)) 3782 atw_stop(ifp, 1); 3783 break; 3784 case SIOCADDMULTI: 3785 case SIOCDELMULTI: 3786 error = (cmd == SIOCADDMULTI) ? 3787 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3788 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3789 if (error == ENETRESET) { 3790 if (ATW_IS_ENABLED(sc)) 3791 atw_filter_setup(sc); /* do not rescan */ 3792 error = 0; 3793 } 3794 break; 3795 default: 3796 error = ieee80211_ioctl(ifp, cmd, data); 3797 if (error == ENETRESET) { 3798 if (ATW_IS_ENABLED(sc)) 3799 error = atw_init(ifp); 3800 else 3801 error = 0; 3802 } 3803 break; 3804 } 3805 3806 /* Try to get more packets going. */ 3807 if (ATW_IS_ENABLED(sc)) 3808 atw_start(ifp); 3809 3810 splx(s); 3811 return (error); 3812 } 3813 3814 static int 3815 atw_media_change(struct ifnet *ifp) 3816 { 3817 int error; 3818 3819 error = ieee80211_media_change(ifp); 3820 if (error == ENETRESET) { 3821 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3822 (IFF_RUNNING|IFF_UP)) 3823 atw_init(ifp); /* XXX lose error */ 3824 error = 0; 3825 } 3826 return error; 3827 } 3828 3829 static void 3830 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3831 { 3832 struct atw_softc *sc = ifp->if_softc; 3833 3834 if (ATW_IS_ENABLED(sc) == 0) { 3835 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3836 imr->ifm_status = 0; 3837 return; 3838 } 3839 ieee80211_media_status(ifp, imr); 3840 } 3841
Indexes created Fri Oct 17 09:09:57 GMT 2025