atw.c revision 1.41
1 /* $NetBSD: atw.c,v 1.41 2004/07/15 06:20:58 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.41 2004/07/15 06:20:58 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 139 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 140 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 141 142 int atw_rfio_enable_delay = 20 * 1000; 143 int atw_rfio_disable_delay = 2 * 1000; 144 int atw_writewep_delay = 5; 145 int atw_beacon_len_adjust = 4; 146 int atw_dwelltime = 200; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_print_regs(struct atw_softc *, const char *); 159 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 164 static void atw_rf3000_print(struct atw_softc *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 169 static void atw_si4126_print(struct atw_softc *); 170 # endif /* ATW_SYNDEBUG */ 171 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #endif 180 181 #ifdef ATW_STATS 182 void atw_print_stats(struct atw_softc *); 183 #endif 184 185 void atw_start(struct ifnet *); 186 void atw_watchdog(struct ifnet *); 187 int atw_ioctl(struct ifnet *, u_long, caddr_t); 188 int atw_init(struct ifnet *); 189 void atw_txdrain(struct atw_softc *); 190 void atw_stop(struct ifnet *, int); 191 192 void atw_reset(struct atw_softc *); 193 int atw_read_srom(struct atw_softc *); 194 195 void atw_shutdown(void *); 196 197 void atw_rxdrain(struct atw_softc *); 198 int atw_add_rxbuf(struct atw_softc *, int); 199 void atw_idle(struct atw_softc *, u_int32_t); 200 201 int atw_enable(struct atw_softc *); 202 void atw_disable(struct atw_softc *); 203 void atw_power(int, void *); 204 205 void atw_rxintr(struct atw_softc *); 206 void atw_txintr(struct atw_softc *); 207 void atw_linkintr(struct atw_softc *, u_int32_t); 208 209 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 210 static void atw_tsf(struct atw_softc *); 211 static void atw_start_beacon(struct atw_softc *, int); 212 static void atw_write_wep(struct atw_softc *); 213 static void atw_write_bssid(struct atw_softc *); 214 static void atw_write_ssid(struct atw_softc *); 215 static void atw_write_sup_rates(struct atw_softc *); 216 static void atw_clear_sram(struct atw_softc *); 217 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 218 static int atw_media_change(struct ifnet *); 219 static void atw_media_status(struct ifnet *, struct ifmediareq *); 220 static void atw_filter_setup(struct atw_softc *); 221 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 222 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 223 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 228 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 229 230 static int atw_tune(struct atw_softc *); 231 232 static void atw_rfio_enable(struct atw_softc *, int); 233 234 /* RFMD RF3000 Baseband Processor */ 235 static int atw_rf3000_init(struct atw_softc *); 236 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 237 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 238 #ifdef ATW_DEBUG 239 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 240 #endif /* ATW_DEBUG */ 241 242 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 243 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 244 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 245 #ifdef ATW_DEBUG 246 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 247 #endif /* ATW_DEBUG */ 248 249 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 250 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 251 252 const char *atw_tx_state[] = { 253 "STOPPED", 254 "RUNNING - read descriptor", 255 "RUNNING - transmitting", 256 "RUNNING - filling fifo", /* XXX */ 257 "SUSPENDED", 258 "RUNNING -- write descriptor", 259 "RUNNING -- write last descriptor", 260 "RUNNING - fifo full" 261 }; 262 263 const char *atw_rx_state[] = { 264 "STOPPED", 265 "RUNNING - read descriptor", 266 "RUNNING - check this packet, pre-fetch next", 267 "RUNNING - wait for reception", 268 "SUSPENDED", 269 "RUNNING - write descriptor", 270 "RUNNING - flush fifo", 271 "RUNNING - fifo drain" 272 }; 273 274 int 275 atw_activate(struct device *self, enum devact act) 276 { 277 struct atw_softc *sc = (struct atw_softc *)self; 278 int rv = 0, s; 279 280 s = splnet(); 281 switch (act) { 282 case DVACT_ACTIVATE: 283 rv = EOPNOTSUPP; 284 break; 285 286 case DVACT_DEACTIVATE: 287 if_deactivate(&sc->sc_ic.ic_if); 288 break; 289 } 290 splx(s); 291 return rv; 292 } 293 294 /* 295 * atw_enable: 296 * 297 * Enable the ADM8211 chip. 298 */ 299 int 300 atw_enable(struct atw_softc *sc) 301 { 302 303 if (ATW_IS_ENABLED(sc) == 0) { 304 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 305 printf("%s: device enable failed\n", 306 sc->sc_dev.dv_xname); 307 return (EIO); 308 } 309 sc->sc_flags |= ATWF_ENABLED; 310 } 311 return (0); 312 } 313 314 /* 315 * atw_disable: 316 * 317 * Disable the ADM8211 chip. 318 */ 319 void 320 atw_disable(struct atw_softc *sc) 321 { 322 if (!ATW_IS_ENABLED(sc)) 323 return; 324 if (sc->sc_disable != NULL) 325 (*sc->sc_disable)(sc); 326 sc->sc_flags &= ~ATWF_ENABLED; 327 } 328 329 /* Returns -1 on failure. */ 330 int 331 atw_read_srom(struct atw_softc *sc) 332 { 333 struct seeprom_descriptor sd; 334 u_int32_t reg; 335 336 (void)memset(&sd, 0, sizeof(sd)); 337 338 reg = ATW_READ(sc, ATW_TEST0); 339 340 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 341 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 342 return -1; 343 } 344 345 switch (reg & ATW_TEST0_EPTYP_MASK) { 346 case ATW_TEST0_EPTYP_93c66: 347 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 348 sc->sc_sromsz = 512; 349 sd.sd_chip = C56_66; 350 break; 351 case ATW_TEST0_EPTYP_93c46: 352 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 353 sc->sc_sromsz = 128; 354 sd.sd_chip = C46; 355 break; 356 default: 357 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 358 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 359 return -1; 360 } 361 362 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 363 364 if (sc->sc_srom == NULL) { 365 printf("%s: unable to allocate SROM buffer\n", 366 sc->sc_dev.dv_xname); 367 return -1; 368 } 369 370 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 371 372 /* ADM8211 has a single 32-bit register for controlling the 373 * 93cx6 SROM. Bit SRS enables the serial port. There is no 374 * "ready" bit. The ADM8211 input/output sense is the reverse 375 * of read_seeprom's. 376 */ 377 sd.sd_tag = sc->sc_st; 378 sd.sd_bsh = sc->sc_sh; 379 sd.sd_regsize = 4; 380 sd.sd_control_offset = ATW_SPR; 381 sd.sd_status_offset = ATW_SPR; 382 sd.sd_dataout_offset = ATW_SPR; 383 sd.sd_CK = ATW_SPR_SCLK; 384 sd.sd_CS = ATW_SPR_SCS; 385 sd.sd_DI = ATW_SPR_SDO; 386 sd.sd_DO = ATW_SPR_SDI; 387 sd.sd_MS = ATW_SPR_SRS; 388 sd.sd_RDY = 0; 389 390 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 391 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 392 free(sc->sc_srom, M_DEVBUF); 393 return -1; 394 } 395 #ifdef ATW_DEBUG 396 { 397 int i; 398 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 399 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 400 if (((i % 8) == 0) && (i != 0)) { 401 ATW_DPRINTF(("\n\t")); 402 } 403 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 404 } 405 ATW_DPRINTF(("\n")); 406 } 407 #endif /* ATW_DEBUG */ 408 return 0; 409 } 410 411 #ifdef ATW_DEBUG 412 static void 413 atw_print_regs(struct atw_softc *sc, const char *where) 414 { 415 #define PRINTREG(sc, reg) \ 416 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 417 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 418 419 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 420 421 PRINTREG(sc, ATW_PAR); 422 PRINTREG(sc, ATW_FRCTL); 423 PRINTREG(sc, ATW_TDR); 424 PRINTREG(sc, ATW_WTDP); 425 PRINTREG(sc, ATW_RDR); 426 PRINTREG(sc, ATW_WRDP); 427 PRINTREG(sc, ATW_RDB); 428 PRINTREG(sc, ATW_CSR3A); 429 PRINTREG(sc, ATW_TDBD); 430 PRINTREG(sc, ATW_TDBP); 431 PRINTREG(sc, ATW_STSR); 432 PRINTREG(sc, ATW_CSR5A); 433 PRINTREG(sc, ATW_NAR); 434 PRINTREG(sc, ATW_CSR6A); 435 PRINTREG(sc, ATW_IER); 436 PRINTREG(sc, ATW_CSR7A); 437 PRINTREG(sc, ATW_LPC); 438 PRINTREG(sc, ATW_TEST1); 439 PRINTREG(sc, ATW_SPR); 440 PRINTREG(sc, ATW_TEST0); 441 PRINTREG(sc, ATW_WCSR); 442 PRINTREG(sc, ATW_WPDR); 443 PRINTREG(sc, ATW_GPTMR); 444 PRINTREG(sc, ATW_GPIO); 445 PRINTREG(sc, ATW_BBPCTL); 446 PRINTREG(sc, ATW_SYNCTL); 447 PRINTREG(sc, ATW_PLCPHD); 448 PRINTREG(sc, ATW_MMIWADDR); 449 PRINTREG(sc, ATW_MMIRADDR1); 450 PRINTREG(sc, ATW_MMIRADDR2); 451 PRINTREG(sc, ATW_TXBR); 452 PRINTREG(sc, ATW_CSR15A); 453 PRINTREG(sc, ATW_ALCSTAT); 454 PRINTREG(sc, ATW_TOFS2); 455 PRINTREG(sc, ATW_CMDR); 456 PRINTREG(sc, ATW_PCIC); 457 PRINTREG(sc, ATW_PMCSR); 458 PRINTREG(sc, ATW_PAR0); 459 PRINTREG(sc, ATW_PAR1); 460 PRINTREG(sc, ATW_MAR0); 461 PRINTREG(sc, ATW_MAR1); 462 PRINTREG(sc, ATW_ATIMDA0); 463 PRINTREG(sc, ATW_ABDA1); 464 PRINTREG(sc, ATW_BSSID0); 465 PRINTREG(sc, ATW_TXLMT); 466 PRINTREG(sc, ATW_MIBCNT); 467 PRINTREG(sc, ATW_BCNT); 468 PRINTREG(sc, ATW_TSFTH); 469 PRINTREG(sc, ATW_TSC); 470 PRINTREG(sc, ATW_SYNRF); 471 PRINTREG(sc, ATW_BPLI); 472 PRINTREG(sc, ATW_CAP0); 473 PRINTREG(sc, ATW_CAP1); 474 PRINTREG(sc, ATW_RMD); 475 PRINTREG(sc, ATW_CFPP); 476 PRINTREG(sc, ATW_TOFS0); 477 PRINTREG(sc, ATW_TOFS1); 478 PRINTREG(sc, ATW_IFST); 479 PRINTREG(sc, ATW_RSPT); 480 PRINTREG(sc, ATW_TSFTL); 481 PRINTREG(sc, ATW_WEPCTL); 482 PRINTREG(sc, ATW_WESK); 483 PRINTREG(sc, ATW_WEPCNT); 484 PRINTREG(sc, ATW_MACTEST); 485 PRINTREG(sc, ATW_FER); 486 PRINTREG(sc, ATW_FEMR); 487 PRINTREG(sc, ATW_FPSR); 488 PRINTREG(sc, ATW_FFER); 489 #undef PRINTREG 490 } 491 #endif /* ATW_DEBUG */ 492 493 /* 494 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 495 */ 496 void 497 atw_attach(struct atw_softc *sc) 498 { 499 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 500 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 501 }; 502 struct ieee80211com *ic = &sc->sc_ic; 503 struct ifnet *ifp = &ic->ic_if; 504 int country_code, error, i, nrate; 505 u_int32_t reg; 506 static const char *type_strings[] = {"Intersil (not supported)", 507 "RFMD", "Marvel (not supported)"}; 508 509 sc->sc_txth = atw_txthresh_tab_lo; 510 511 SIMPLEQ_INIT(&sc->sc_txfreeq); 512 SIMPLEQ_INIT(&sc->sc_txdirtyq); 513 514 #ifdef ATW_DEBUG 515 atw_print_regs(sc, "atw_attach"); 516 #endif /* ATW_DEBUG */ 517 518 /* 519 * Allocate the control data structures, and create and load the 520 * DMA map for it. 521 */ 522 if ((error = bus_dmamem_alloc(sc->sc_dmat, 523 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 524 1, &sc->sc_cdnseg, 0)) != 0) { 525 printf("%s: unable to allocate control data, error = %d\n", 526 sc->sc_dev.dv_xname, error); 527 goto fail_0; 528 } 529 530 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 531 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 532 BUS_DMA_COHERENT)) != 0) { 533 printf("%s: unable to map control data, error = %d\n", 534 sc->sc_dev.dv_xname, error); 535 goto fail_1; 536 } 537 538 if ((error = bus_dmamap_create(sc->sc_dmat, 539 sizeof(struct atw_control_data), 1, 540 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 541 printf("%s: unable to create control data DMA map, " 542 "error = %d\n", sc->sc_dev.dv_xname, error); 543 goto fail_2; 544 } 545 546 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 547 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 548 0)) != 0) { 549 printf("%s: unable to load control data DMA map, error = %d\n", 550 sc->sc_dev.dv_xname, error); 551 goto fail_3; 552 } 553 554 /* 555 * Create the transmit buffer DMA maps. 556 */ 557 sc->sc_ntxsegs = ATW_NTXSEGS; 558 for (i = 0; i < ATW_TXQUEUELEN; i++) { 559 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 560 sc->sc_ntxsegs, MCLBYTES, 0, 0, 561 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 562 printf("%s: unable to create tx DMA map %d, " 563 "error = %d\n", sc->sc_dev.dv_xname, i, error); 564 goto fail_4; 565 } 566 } 567 568 /* 569 * Create the receive buffer DMA maps. 570 */ 571 for (i = 0; i < ATW_NRXDESC; i++) { 572 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 573 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 574 printf("%s: unable to create rx DMA map %d, " 575 "error = %d\n", sc->sc_dev.dv_xname, i, error); 576 goto fail_5; 577 } 578 } 579 for (i = 0; i < ATW_NRXDESC; i++) { 580 sc->sc_rxsoft[i].rxs_mbuf = NULL; 581 } 582 583 /* Reset the chip to a known state. */ 584 atw_reset(sc); 585 586 if (atw_read_srom(sc) == -1) 587 return; 588 589 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 590 ATW_SR_RFTYPE_MASK); 591 592 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 593 ATW_SR_BBPTYPE_MASK); 594 595 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 600 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 601 return; 602 } 603 604 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 605 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 606 607 /* XXX There exists a Linux driver which seems to use RFType = 0 for 608 * MARVEL. My bug, or theirs? 609 */ 610 611 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 612 613 switch (sc->sc_rftype) { 614 case ATW_RFTYPE_INTERSIL: 615 reg |= ATW_SYNCTL_CS1; 616 break; 617 case ATW_RFTYPE_RFMD: 618 reg |= ATW_SYNCTL_CS0; 619 break; 620 case ATW_RFTYPE_MARVEL: 621 break; 622 } 623 624 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 625 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 626 627 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 628 629 switch (sc->sc_bbptype) { 630 case ATW_BBPTYPE_INTERSIL: 631 reg |= ATW_BBPCTL_TWI; 632 break; 633 case ATW_BBPTYPE_RFMD: 634 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 635 ATW_BBPCTL_CCA_ACTLO; 636 break; 637 case ATW_BBPTYPE_MARVEL: 638 break; 639 case ATW_C_BBPTYPE_RFMD: 640 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 641 sc->sc_dev.dv_xname); 642 break; 643 } 644 645 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 646 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 647 648 /* 649 * From this point forward, the attachment cannot fail. A failure 650 * before this point releases all resources that may have been 651 * allocated. 652 */ 653 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 654 655 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 656 htole16(sc->sc_srom[ATW_SR_MAC00]), 657 htole16(sc->sc_srom[ATW_SR_MAC01]), 658 htole16(sc->sc_srom[ATW_SR_MAC10]))); 659 660 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 661 ATW_SR_CTRY_MASK); 662 663 #define ADD_CHANNEL(_ic, _chan) do { \ 664 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 665 _ic->ic_channels[_chan].ic_freq = \ 666 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 667 } while (0) 668 669 /* Find available channels */ 670 switch (country_code) { 671 case COUNTRY_MMK2: /* 1-14 */ 672 ADD_CHANNEL(ic, 14); 673 /*FALLTHROUGH*/ 674 case COUNTRY_ETSI: /* 1-13 */ 675 for (i = 1; i <= 13; i++) 676 ADD_CHANNEL(ic, i); 677 break; 678 case COUNTRY_FCC: /* 1-11 */ 679 case COUNTRY_IC: /* 1-11 */ 680 for (i = 1; i <= 11; i++) 681 ADD_CHANNEL(ic, i); 682 break; 683 case COUNTRY_MMK: /* 14 */ 684 ADD_CHANNEL(ic, 14); 685 break; 686 case COUNTRY_FRANCE: /* 10-13 */ 687 for (i = 10; i <= 13; i++) 688 ADD_CHANNEL(ic, i); 689 break; 690 default: /* assume channels 10-11 */ 691 case COUNTRY_SPAIN: /* 10-11 */ 692 for (i = 10; i <= 11; i++) 693 ADD_CHANNEL(ic, i); 694 break; 695 } 696 697 /* Read the MAC address. */ 698 reg = ATW_READ(sc, ATW_PAR0); 699 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 700 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 701 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 702 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 703 reg = ATW_READ(sc, ATW_PAR1); 704 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 705 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 706 707 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 708 printf(" could not get mac address, attach failed\n"); 709 return; 710 } 711 712 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 713 714 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 715 ifp->if_softc = sc; 716 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 717 IFF_NOTRAILERS; 718 ifp->if_ioctl = atw_ioctl; 719 ifp->if_start = atw_start; 720 ifp->if_watchdog = atw_watchdog; 721 ifp->if_init = atw_init; 722 ifp->if_stop = atw_stop; 723 IFQ_SET_READY(&ifp->if_snd); 724 725 ic->ic_phytype = IEEE80211_T_DS; 726 ic->ic_opmode = IEEE80211_M_STA; 727 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 728 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 729 730 nrate = 0; 731 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 735 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 736 737 /* 738 * Call MI attach routines. 739 */ 740 741 if_attach(ifp); 742 ieee80211_ifattach(ifp); 743 744 sc->sc_newstate = ic->ic_newstate; 745 ic->ic_newstate = atw_newstate; 746 747 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 748 ic->ic_recv_mgmt = atw_recv_mgmt; 749 750 sc->sc_node_free = ic->ic_node_free; 751 ic->ic_node_free = atw_node_free; 752 753 sc->sc_node_alloc = ic->ic_node_alloc; 754 ic->ic_node_alloc = atw_node_alloc; 755 756 /* possibly we should fill in our own sc_send_prresp, since 757 * the ADM8211 is probably sending probe responses in ad hoc 758 * mode. 759 */ 760 761 /* complete initialization */ 762 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 763 callout_init(&sc->sc_scan_ch); 764 765 #if NBPFILTER > 0 766 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 767 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 768 #endif 769 770 /* 771 * Make sure the interface is shutdown during reboot. 772 */ 773 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 774 if (sc->sc_sdhook == NULL) 775 printf("%s: WARNING: unable to establish shutdown hook\n", 776 sc->sc_dev.dv_xname); 777 778 /* 779 * Add a suspend hook to make sure we come back up after a 780 * resume. 781 */ 782 sc->sc_powerhook = powerhook_establish(atw_power, sc); 783 if (sc->sc_powerhook == NULL) 784 printf("%s: WARNING: unable to establish power hook\n", 785 sc->sc_dev.dv_xname); 786 787 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 788 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 789 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 790 791 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 792 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 793 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 794 795 return; 796 797 /* 798 * Free any resources we've allocated during the failed attach 799 * attempt. Do this in reverse order and fall through. 800 */ 801 fail_5: 802 for (i = 0; i < ATW_NRXDESC; i++) { 803 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 806 } 807 fail_4: 808 for (i = 0; i < ATW_TXQUEUELEN; i++) { 809 if (sc->sc_txsoft[i].txs_dmamap == NULL) 810 continue; 811 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 812 } 813 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 814 fail_3: 815 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 816 fail_2: 817 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 818 sizeof(struct atw_control_data)); 819 fail_1: 820 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 821 fail_0: 822 return; 823 } 824 825 static struct ieee80211_node * 826 atw_node_alloc(struct ieee80211com *ic) 827 { 828 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 829 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 830 831 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 832 return ni; 833 } 834 835 static void 836 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 837 { 838 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 839 840 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 841 ether_sprintf(ni->ni_bssid))); 842 (*sc->sc_node_free)(ic, ni); 843 } 844 845 /* 846 * atw_reset: 847 * 848 * Perform a soft reset on the ADM8211. 849 */ 850 void 851 atw_reset(struct atw_softc *sc) 852 { 853 int i; 854 855 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 856 857 for (i = 0; i < 10000; i++) { 858 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 859 break; 860 DELAY(1); 861 } 862 863 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 864 865 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 866 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 867 868 /* Turn off maximum power saving. */ 869 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 870 871 /* Recall EEPROM. */ 872 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 873 874 DELAY(10 * 1000); 875 876 /* A reset seems to affect the SRAM contents, so put them into 877 * a known state. 878 */ 879 atw_clear_sram(sc); 880 881 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 882 } 883 884 static void 885 atw_clear_sram(struct atw_softc *sc) 886 { 887 #if 0 888 for (addr = 0; addr < 448; addr++) { 889 ATW_WRITE(sc, ATW_WEPCTL, 890 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 891 DELAY(1000); 892 ATW_WRITE(sc, ATW_WESK, 0); 893 DELAY(1000); /* paranoia */ 894 } 895 return; 896 #endif 897 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 898 /* XXX not for revision 0x20. */ 899 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 900 } 901 902 /* TBD atw_init 903 * 904 * set MAC based on ic->ic_bss->myaddr 905 * write WEP keys 906 * set TX rate 907 */ 908 909 /* 910 * atw_init: [ ifnet interface function ] 911 * 912 * Initialize the interface. Must be called at splnet(). 913 */ 914 int 915 atw_init(struct ifnet *ifp) 916 { 917 struct atw_softc *sc = ifp->if_softc; 918 struct ieee80211com *ic = &sc->sc_ic; 919 struct atw_txsoft *txs; 920 struct atw_rxsoft *rxs; 921 u_int32_t reg; 922 int i, error = 0; 923 924 if ((error = atw_enable(sc)) != 0) 925 goto out; 926 927 /* 928 * Cancel any pending I/O. This also resets. 929 */ 930 atw_stop(ifp, 0); 931 932 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 933 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 934 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 935 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 936 937 /* Turn off APM??? (A binary-only driver does this.) 938 * 939 * Set Rx store-and-forward mode. 940 */ 941 reg = ATW_READ(sc, ATW_CMDR); 942 reg &= ~ATW_CMDR_APM; 943 reg &= ~ATW_CMDR_DRT_MASK; 944 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 945 946 ATW_WRITE(sc, ATW_CMDR, reg); 947 948 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 949 * 950 * XXX a binary-only driver sets a different service field than 951 * 0. why? 952 */ 953 reg = ATW_READ(sc, ATW_PLCPHD); 954 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 955 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 956 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 957 ATW_WRITE(sc, ATW_PLCPHD, reg); 958 959 /* XXX this magic can probably be figured out from the RFMD docs */ 960 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 961 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 962 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 963 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 964 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 965 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 966 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 967 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 968 ATW_WRITE(sc, ATW_TOFS2, reg); 969 970 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 971 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 972 973 /* XXX this resets an Intersil RF front-end? */ 974 /* TBD condition on Intersil RFType? */ 975 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 976 DELAY(10 * 1000); 977 ATW_WRITE(sc, ATW_SYNRF, 0); 978 DELAY(5 * 1000); 979 980 /* 16 TU max duration for contention-free period */ 981 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 982 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 983 984 /* XXX I guess that the Cardbus clock is 22MHz? 985 * I am assuming that the role of ATW_TOFS0_USCNT is 986 * to divide the bus clock to get a 1MHz clock---the datasheet is not 987 * very clear on this point. It says in the datasheet that it is 988 * possible for the ADM8211 to accomodate bus speeds between 22MHz 989 * and 33MHz; maybe this is the way? I see a binary-only driver write 990 * these values. These values are also the power-on default. 991 */ 992 ATW_WRITE(sc, ATW_TOFS0, 993 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 994 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 995 996 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 997 * driver. Go figure. 998 */ 999 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1000 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1001 ATW_IFST_SIFS_MASK) | 1002 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1003 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1004 1005 ATW_WRITE(sc, ATW_IFST, reg); 1006 1007 /* XXX More magic. Might relate to ACK timing. */ 1008 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1009 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1010 1011 /* Set up the MMI read/write addresses for the BBP. 1012 * 1013 * TBD find out the Marvel settings. 1014 */ 1015 switch (sc->sc_bbptype) { 1016 case ATW_BBPTYPE_INTERSIL: 1017 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1018 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1019 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1020 break; 1021 case ATW_BBPTYPE_MARVEL: 1022 break; 1023 case ATW_BBPTYPE_RFMD: 1024 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1025 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1026 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1027 default: 1028 break; 1029 } 1030 1031 sc->sc_wepctl = 0; 1032 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1033 1034 if ((error = atw_rf3000_init(sc)) != 0) 1035 goto out; 1036 1037 /* 1038 * Initialize the PCI Access Register. 1039 */ 1040 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1041 1042 /* 1043 * If we're allowed to do so, use Memory Read Line 1044 * and Memory Read Multiple. 1045 * 1046 * XXX Should we use Memory Write and Invalidate? 1047 */ 1048 if (sc->sc_flags & ATWF_MRL) 1049 sc->sc_busmode |= ATW_PAR_MRLE; 1050 if (sc->sc_flags & ATWF_MRM) 1051 sc->sc_busmode |= ATW_PAR_MRME; 1052 if (sc->sc_flags & ATWF_MWI) 1053 sc->sc_busmode |= ATW_PAR_MWIE; 1054 if (sc->sc_maxburst == 0) 1055 sc->sc_maxburst = 8; /* ADM8211 default */ 1056 1057 switch (sc->sc_cacheline) { 1058 default: 1059 /* Use burst length. */ 1060 break; 1061 case 8: 1062 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1063 break; 1064 case 16: 1065 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1066 break; 1067 case 32: 1068 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1069 break; 1070 } 1071 switch (sc->sc_maxburst) { 1072 case 1: 1073 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1074 break; 1075 case 2: 1076 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1077 break; 1078 case 4: 1079 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1080 break; 1081 case 8: 1082 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1083 break; 1084 case 16: 1085 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1086 break; 1087 case 32: 1088 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1089 break; 1090 default: 1091 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1092 break; 1093 } 1094 1095 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1096 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1097 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1098 1099 /* 1100 * Initialize the OPMODE register. We don't write it until 1101 * we're ready to begin the transmit and receive processes. 1102 */ 1103 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1104 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1105 1106 /* 1107 * Initialize the transmit descriptor ring. 1108 */ 1109 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1110 for (i = 0; i < ATW_NTXDESC; i++) { 1111 /* no transmit chaining */ 1112 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1113 sc->sc_txdescs[i].at_buf2 = 1114 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1115 } 1116 /* use ring mode */ 1117 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1118 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1119 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1120 sc->sc_txfree = ATW_NTXDESC; 1121 sc->sc_txnext = 0; 1122 1123 /* 1124 * Initialize the transmit job descriptors. 1125 */ 1126 SIMPLEQ_INIT(&sc->sc_txfreeq); 1127 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1128 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1129 txs = &sc->sc_txsoft[i]; 1130 txs->txs_mbuf = NULL; 1131 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1132 } 1133 1134 /* 1135 * Initialize the receive descriptor and receive job 1136 * descriptor rings. 1137 */ 1138 for (i = 0; i < ATW_NRXDESC; i++) { 1139 rxs = &sc->sc_rxsoft[i]; 1140 if (rxs->rxs_mbuf == NULL) { 1141 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1142 printf("%s: unable to allocate or map rx " 1143 "buffer %d, error = %d\n", 1144 sc->sc_dev.dv_xname, i, error); 1145 /* 1146 * XXX Should attempt to run with fewer receive 1147 * XXX buffers instead of just failing. 1148 */ 1149 atw_rxdrain(sc); 1150 goto out; 1151 } 1152 } else 1153 ATW_INIT_RXDESC(sc, i); 1154 } 1155 sc->sc_rxptr = 0; 1156 1157 /* disable all wake-up events */ 1158 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1159 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1160 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1161 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1162 1163 /* ack all wake-up events */ 1164 ATW_SET(sc, ATW_WCSR, 0); 1165 1166 /* 1167 * Initialize the interrupt mask and enable interrupts. 1168 */ 1169 /* normal interrupts */ 1170 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1171 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1172 1173 /* abnormal interrupts */ 1174 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1175 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1176 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1177 1178 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1179 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1180 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1181 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1182 ATW_INTR_TRT; 1183 1184 sc->sc_linkint_mask &= sc->sc_inten; 1185 sc->sc_rxint_mask &= sc->sc_inten; 1186 sc->sc_txint_mask &= sc->sc_inten; 1187 1188 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1189 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1190 if (sc->sc_intr_ack != NULL) 1191 (*sc->sc_intr_ack)(sc); 1192 1193 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1194 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1195 1196 /* 1197 * Give the transmit and receive rings to the ADM8211. 1198 */ 1199 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1200 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1201 1202 /* common 802.11 configuration */ 1203 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1204 switch (ic->ic_opmode) { 1205 case IEEE80211_M_STA: 1206 break; 1207 case IEEE80211_M_AHDEMO: /* XXX */ 1208 case IEEE80211_M_IBSS: 1209 ic->ic_flags |= IEEE80211_F_IBSSON; 1210 /*FALLTHROUGH*/ 1211 case IEEE80211_M_HOSTAP: /* XXX */ 1212 break; 1213 case IEEE80211_M_MONITOR: /* XXX */ 1214 break; 1215 } 1216 1217 atw_start_beacon(sc, 0); 1218 1219 switch (ic->ic_opmode) { 1220 case IEEE80211_M_AHDEMO: 1221 case IEEE80211_M_HOSTAP: 1222 ic->ic_bss->ni_intval = ic->ic_lintval; 1223 ic->ic_bss->ni_rssi = 0; 1224 ic->ic_bss->ni_rstamp = 0; 1225 break; 1226 default: /* XXX */ 1227 break; 1228 } 1229 1230 atw_write_ssid(sc); 1231 atw_write_sup_rates(sc); 1232 if (ic->ic_caps & IEEE80211_C_WEP) 1233 atw_write_wep(sc); 1234 1235 /* 1236 * Set the receive filter. This will start the transmit and 1237 * receive processes. 1238 */ 1239 atw_filter_setup(sc); 1240 1241 /* 1242 * Start the receive process. 1243 */ 1244 ATW_WRITE(sc, ATW_RDR, 0x1); 1245 1246 /* 1247 * Note that the interface is now running. 1248 */ 1249 ifp->if_flags |= IFF_RUNNING; 1250 ifp->if_flags &= ~IFF_OACTIVE; 1251 ic->ic_state = IEEE80211_S_INIT; 1252 1253 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1254 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1255 else 1256 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1257 out: 1258 if (error) { 1259 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1260 ifp->if_timer = 0; 1261 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1262 } 1263 #ifdef ATW_DEBUG 1264 atw_print_regs(sc, "end of init"); 1265 #endif /* ATW_DEBUG */ 1266 1267 return (error); 1268 } 1269 1270 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1271 * 0: MAC control of RF3000/Si4126. 1272 * 1273 * Applies power, or selects RF front-end? Sets reset condition. 1274 * 1275 * TBD support non-RFMD BBP, non-SiLabs synth. 1276 */ 1277 static void 1278 atw_rfio_enable(struct atw_softc *sc, int enable) 1279 { 1280 if (enable) { 1281 ATW_WRITE(sc, ATW_SYNRF, 1282 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1283 DELAY(atw_rfio_enable_delay); 1284 } else { 1285 ATW_WRITE(sc, ATW_SYNRF, 0); 1286 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1287 } 1288 } 1289 1290 static int 1291 atw_tune(struct atw_softc *sc) 1292 { 1293 int rc; 1294 u_int32_t reg; 1295 int chan; 1296 struct ieee80211com *ic = &sc->sc_ic; 1297 1298 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1299 if (chan == IEEE80211_CHAN_ANY) 1300 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1301 1302 if (chan == sc->sc_cur_chan) 1303 return 0; 1304 1305 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1306 sc->sc_cur_chan, chan)); 1307 1308 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1309 1310 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1311 (rc = atw_rf3000_tune(sc, chan)) != 0) 1312 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1313 chan); 1314 1315 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1316 ATW_WRITE(sc, ATW_CAP0, 1317 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1318 1319 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1320 1321 if (rc == 0) 1322 sc->sc_cur_chan = chan; 1323 1324 return rc; 1325 } 1326 1327 #ifdef ATW_DEBUG 1328 static void 1329 atw_si4126_print(struct atw_softc *sc) 1330 { 1331 struct ifnet *ifp = &sc->sc_ic.ic_if; 1332 u_int addr, val; 1333 1334 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1335 return; 1336 1337 for (addr = 0; addr <= 8; addr++) { 1338 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1339 if (atw_si4126_read(sc, addr, &val) == 0) { 1340 printf("<unknown> (quitting print-out)\n"); 1341 break; 1342 } 1343 printf("%05x\n", val); 1344 } 1345 } 1346 #endif /* ATW_DEBUG */ 1347 1348 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1349 * 1350 * The RF/IF synthesizer produces two reference frequencies for 1351 * the RF2948B transceiver. The first frequency the RF2948B requires 1352 * is two times the so-called "intermediate frequency" (IF). Since 1353 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1354 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1355 * frequency required by the transceiver is the radio frequency 1356 * (RF). This is a superheterodyne transceiver; for f(chan) the 1357 * center frequency of the channel we are tuning, RF = f(chan) - 1358 * IF. 1359 * 1360 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1361 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1362 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1363 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1364 */ 1365 static int 1366 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1367 { 1368 int rc = 0; 1369 u_int mhz; 1370 u_int R; 1371 u_int32_t reg; 1372 u_int16_t gain; 1373 1374 #ifdef ATW_DEBUG 1375 atw_si4126_print(sc); 1376 #endif /* ATW_DEBUG */ 1377 1378 if (chan == 14) 1379 mhz = 2484; 1380 else 1381 mhz = 2412 + 5 * (chan - 1); 1382 1383 /* Tune IF to 748MHz to suit the IF LO input of the 1384 * RF2494B, which is 2 x IF. No need to set an IF divider 1385 * because an IF in 526MHz - 952MHz is allowed. 1386 * 1387 * XIN is 44.000MHz, so divide it by two to get allowable 1388 * range of 2-25MHz. SiLabs tells me that this is not 1389 * strictly necessary. 1390 */ 1391 1392 R = 44; 1393 1394 atw_rfio_enable(sc, 1); 1395 1396 /* Power-up RF, IF synthesizers. */ 1397 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1398 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1399 goto out; 1400 1401 /* If RF2 N > 2047, then set KP2 to 1. */ 1402 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1403 1404 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1405 goto out; 1406 1407 /* set LPWR, too? */ 1408 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1409 SI4126_MAIN_XINDIV2)) != 0) 1410 goto out; 1411 1412 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1413 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1414 */ 1415 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1416 goto out; 1417 1418 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1419 goto out; 1420 1421 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1422 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1423 * which has no RF1! 1424 */ 1425 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1426 goto out; 1427 1428 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1429 goto out; 1430 1431 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1432 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1433 * Now let's multiply it to mhz. So mhz - IF = N. 1434 */ 1435 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1436 goto out; 1437 1438 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1439 goto out; 1440 1441 /* wait 100us from power-up for RF, IF to settle */ 1442 DELAY(100); 1443 1444 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1445 /* XXX there is a binary driver which sends 1446 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1447 * that this enables the Si4126 by raising its PWDN#, but I 1448 * think that it actually sets the Prism RF front-end 1449 * to a special mode for channel 14. 1450 */ 1451 reg = ATW_READ(sc, ATW_GPIO); 1452 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1453 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1454 ATW_WRITE(sc, ATW_GPIO, reg); 1455 } 1456 1457 #ifdef ATW_DEBUG 1458 atw_si4126_print(sc); 1459 #endif /* ATW_DEBUG */ 1460 1461 out: 1462 atw_rfio_enable(sc, 0); 1463 1464 return rc; 1465 } 1466 1467 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1468 * diversity. 1469 * 1470 * Call this w/ Tx/Rx suspended. 1471 */ 1472 static int 1473 atw_rf3000_init(struct atw_softc *sc) 1474 { 1475 int rc = 0; 1476 1477 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1478 1479 atw_rfio_enable(sc, 1); 1480 1481 /* enable diversity */ 1482 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1483 1484 if (rc != 0) 1485 goto out; 1486 1487 /* sensible setting from a binary-only driver */ 1488 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1489 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1490 1491 if (rc != 0) 1492 goto out; 1493 1494 /* magic from a binary-only driver */ 1495 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1496 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1502 1503 if (rc != 0) 1504 goto out; 1505 1506 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1507 1508 if (rc != 0) 1509 goto out; 1510 1511 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1512 1513 if (rc != 0) 1514 goto out; 1515 1516 /* CCA is acquisition sensitive */ 1517 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1518 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1519 1520 if (rc != 0) 1521 goto out; 1522 1523 out: 1524 atw_rfio_enable(sc, 0); 1525 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1526 return rc; 1527 } 1528 1529 #ifdef ATW_DEBUG 1530 static void 1531 atw_rf3000_print(struct atw_softc *sc) 1532 { 1533 struct ifnet *ifp = &sc->sc_ic.ic_if; 1534 u_int addr, val; 1535 1536 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1537 return; 1538 1539 for (addr = 0x01; addr <= 0x15; addr++) { 1540 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1541 if (atw_rf3000_read(sc, addr, &val) != 0) { 1542 printf("<unknown> (quitting print-out)\n"); 1543 break; 1544 } 1545 printf("%08x\n", val); 1546 } 1547 } 1548 #endif /* ATW_DEBUG */ 1549 1550 /* Set the power settings on the BBP for channel `chan'. */ 1551 static int 1552 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1553 { 1554 int rc = 0; 1555 u_int32_t reg; 1556 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1557 1558 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1559 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1560 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1561 1562 /* odd channels: LSB, even channels: MSB */ 1563 if (chan % 2 == 1) { 1564 txpower &= 0xFF; 1565 lpf_cutoff &= 0xFF; 1566 lna_gs_thresh &= 0xFF; 1567 } else { 1568 txpower >>= 8; 1569 lpf_cutoff >>= 8; 1570 lna_gs_thresh >>= 8; 1571 } 1572 1573 #ifdef ATW_DEBUG 1574 atw_rf3000_print(sc); 1575 #endif /* ATW_DEBUG */ 1576 1577 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1578 "lna_gs_thresh %02x\n", 1579 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1580 1581 atw_rfio_enable(sc, 1); 1582 1583 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1584 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1585 goto out; 1586 1587 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1588 goto out; 1589 1590 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1591 goto out; 1592 1593 /* from a binary-only driver. */ 1594 reg = ATW_READ(sc, ATW_PLCPHD); 1595 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1596 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1597 ATW_PLCPHD_SERVICE_MASK); 1598 ATW_WRITE(sc, ATW_PLCPHD, reg); 1599 1600 #ifdef ATW_DEBUG 1601 atw_rf3000_print(sc); 1602 #endif /* ATW_DEBUG */ 1603 1604 out: 1605 atw_rfio_enable(sc, 0); 1606 1607 return rc; 1608 } 1609 1610 /* Write a register on the RF3000 baseband processor using the 1611 * registers provided by the ADM8211 for this purpose. 1612 * 1613 * Return 0 on success. 1614 */ 1615 static int 1616 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1617 { 1618 u_int32_t reg; 1619 int i; 1620 1621 for (i = 1000; --i >= 0; ) { 1622 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1623 break; 1624 DELAY(100); 1625 } 1626 1627 if (i < 0) { 1628 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1629 return ETIMEDOUT; 1630 } 1631 1632 reg = sc->sc_bbpctl_wr | 1633 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1634 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1635 1636 ATW_WRITE(sc, ATW_BBPCTL, reg); 1637 1638 for (i = 1000; --i >= 0; ) { 1639 DELAY(100); 1640 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1641 break; 1642 } 1643 1644 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1645 1646 if (i < 0) { 1647 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1648 return ETIMEDOUT; 1649 } 1650 return 0; 1651 } 1652 1653 /* Read a register on the RF3000 baseband processor using the registers 1654 * the ADM8211 provides for this purpose. 1655 * 1656 * The 7-bit register address is addr. Record the 8-bit data in the register 1657 * in *val. 1658 * 1659 * Return 0 on success. 1660 * 1661 * XXX This does not seem to work. The ADM8211 must require more or 1662 * different magic to read the chip than to write it. Possibly some 1663 * of the magic I have derived from a binary-only driver concerns 1664 * the "chip address" (see the RF3000 manual). 1665 */ 1666 #ifdef ATW_DEBUG 1667 static int 1668 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1669 { 1670 u_int32_t reg; 1671 int i; 1672 1673 for (i = 1000; --i >= 0; ) { 1674 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1675 break; 1676 DELAY(100); 1677 } 1678 1679 if (i < 0) { 1680 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1681 sc->sc_dev.dv_xname); 1682 return ETIMEDOUT; 1683 } 1684 1685 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1686 1687 ATW_WRITE(sc, ATW_BBPCTL, reg); 1688 1689 for (i = 1000; --i >= 0; ) { 1690 DELAY(100); 1691 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1692 break; 1693 } 1694 1695 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1696 1697 if (i < 0) { 1698 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1699 sc->sc_dev.dv_xname, reg); 1700 return ETIMEDOUT; 1701 } 1702 if (val != NULL) 1703 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1704 return 0; 1705 } 1706 #endif /* ATW_DEBUG */ 1707 1708 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1709 * provided by the ADM8211 for that purpose. 1710 * 1711 * val is 18 bits of data, and val is the 4-bit address of the register. 1712 * 1713 * Return 0 on success. 1714 */ 1715 static int 1716 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1717 { 1718 u_int32_t bits, reg; 1719 int i; 1720 1721 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1722 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1723 1724 for (i = 1000; --i >= 0; ) { 1725 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1726 break; 1727 DELAY(100); 1728 } 1729 1730 if (i < 0) { 1731 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1732 sc->sc_dev.dv_xname); 1733 return ETIMEDOUT; 1734 } 1735 1736 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1737 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1738 1739 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1740 1741 ATW_WRITE(sc, ATW_SYNCTL, reg); 1742 1743 for (i = 1000; --i >= 0; ) { 1744 DELAY(100); 1745 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1746 break; 1747 } 1748 1749 /* restore to acceptable starting condition */ 1750 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1751 1752 if (i < 0) { 1753 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1754 sc->sc_dev.dv_xname, reg); 1755 return ETIMEDOUT; 1756 } 1757 return 0; 1758 } 1759 1760 /* Read 18-bit data from the 4-bit address addr in Si4126 1761 * RF synthesizer and write the data to *val. Return 0 on success. 1762 * 1763 * XXX This does not seem to work. The ADM8211 must require more or 1764 * different magic to read the chip than to write it. 1765 */ 1766 #ifdef ATW_DEBUG 1767 static int 1768 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1769 { 1770 u_int32_t reg; 1771 int i; 1772 1773 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1774 1775 for (i = 1000; --i >= 0; ) { 1776 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1777 break; 1778 DELAY(100); 1779 } 1780 1781 if (i < 0) { 1782 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1783 sc->sc_dev.dv_xname); 1784 return ETIMEDOUT; 1785 } 1786 1787 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1788 1789 ATW_WRITE(sc, ATW_SYNCTL, reg); 1790 1791 for (i = 1000; --i >= 0; ) { 1792 DELAY(100); 1793 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1794 break; 1795 } 1796 1797 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1798 1799 if (i < 0) { 1800 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1801 sc->sc_dev.dv_xname, reg); 1802 return ETIMEDOUT; 1803 } 1804 if (val != NULL) 1805 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1806 ATW_SYNCTL_DATA_MASK); 1807 return 0; 1808 } 1809 #endif /* ATW_DEBUG */ 1810 1811 /* XXX is the endianness correct? test. */ 1812 #define atw_calchash(addr) \ 1813 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1814 1815 /* 1816 * atw_filter_setup: 1817 * 1818 * Set the ADM8211's receive filter. 1819 */ 1820 static void 1821 atw_filter_setup(struct atw_softc *sc) 1822 { 1823 struct ieee80211com *ic = &sc->sc_ic; 1824 struct ethercom *ec = &ic->ic_ec; 1825 struct ifnet *ifp = &sc->sc_ic.ic_if; 1826 int hash; 1827 u_int32_t hashes[2] = { 0, 0 }; 1828 struct ether_multi *enm; 1829 struct ether_multistep step; 1830 1831 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1832 sc->sc_dev.dv_xname, sc->sc_flags)); 1833 1834 /* 1835 * If we're running, idle the receive engine. If we're NOT running, 1836 * we're being called from atw_init(), and our writing ATW_NAR will 1837 * start the transmit and receive processes in motion. 1838 */ 1839 if (ifp->if_flags & IFF_RUNNING) 1840 atw_idle(sc, ATW_NAR_SR); 1841 1842 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1843 1844 ifp->if_flags &= ~IFF_ALLMULTI; 1845 1846 if (ifp->if_flags & IFF_PROMISC) { 1847 sc->sc_opmode |= ATW_NAR_PR; 1848 allmulti: 1849 ifp->if_flags |= IFF_ALLMULTI; 1850 goto setit; 1851 } 1852 1853 /* 1854 * Program the 64-bit multicast hash filter. 1855 */ 1856 ETHER_FIRST_MULTI(step, ec, enm); 1857 while (enm != NULL) { 1858 /* XXX */ 1859 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1860 ETHER_ADDR_LEN) != 0) 1861 goto allmulti; 1862 1863 hash = atw_calchash(enm->enm_addrlo); 1864 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1865 ETHER_NEXT_MULTI(step, enm); 1866 } 1867 1868 if (ifp->if_flags & IFF_BROADCAST) { 1869 hash = atw_calchash(etherbroadcastaddr); 1870 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1871 } 1872 1873 /* all bits set => hash is useless */ 1874 if (~(hashes[0] & hashes[1]) == 0) 1875 goto allmulti; 1876 1877 setit: 1878 if (ifp->if_flags & IFF_ALLMULTI) 1879 sc->sc_opmode |= ATW_NAR_MM; 1880 1881 /* XXX in scan mode, do not filter packets. maybe this is 1882 * unnecessary. 1883 */ 1884 if (ic->ic_state == IEEE80211_S_SCAN) 1885 sc->sc_opmode |= ATW_NAR_PR; 1886 1887 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1888 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1889 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1890 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1891 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1892 1893 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1894 } 1895 1896 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1897 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1898 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1899 * no beacon with the preferred BSSID and SSID in the number of 1900 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1901 */ 1902 static void 1903 atw_write_bssid(struct atw_softc *sc) 1904 { 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 u_int8_t *bssid; 1907 1908 bssid = ic->ic_bss->ni_bssid; 1909 1910 ATW_WRITE(sc, ATW_ABDA1, 1911 (ATW_READ(sc, ATW_ABDA1) & 1912 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1913 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1914 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1915 1916 ATW_WRITE(sc, ATW_BSSID0, 1917 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1918 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1919 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1920 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1921 1922 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1923 ether_sprintf(sc->sc_bssid))); 1924 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1925 1926 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1927 } 1928 1929 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1930 * 16-bit word. 1931 */ 1932 static void 1933 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1934 { 1935 u_int i; 1936 u_int8_t *ptr; 1937 1938 memcpy(&sc->sc_sram[ofs], buf, buflen); 1939 1940 if (ofs % 2 != 0) { 1941 ofs--; 1942 buflen++; 1943 } 1944 1945 if (buflen % 2 != 0) 1946 buflen++; 1947 1948 assert(buflen + ofs <= ATW_SRAM_SIZE); 1949 1950 ptr = &sc->sc_sram[ofs]; 1951 1952 for (i = 0; i < buflen; i += 2) { 1953 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1954 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1955 DELAY(atw_writewep_delay); 1956 1957 ATW_WRITE(sc, ATW_WESK, 1958 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1959 DELAY(atw_writewep_delay); 1960 } 1961 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1962 1963 if (sc->sc_if.if_flags & IFF_DEBUG) { 1964 int n_octets = 0; 1965 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1966 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1967 for (i = 0; i < buflen; i++) { 1968 printf(" %02x", ptr[i]); 1969 if (++n_octets % 24 == 0) 1970 printf("\n"); 1971 } 1972 if (n_octets % 24 != 0) 1973 printf("\n"); 1974 } 1975 } 1976 1977 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 1978 static void 1979 atw_write_wep(struct atw_softc *sc) 1980 { 1981 struct ieee80211com *ic = &sc->sc_ic; 1982 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 1983 u_int8_t buf[IEEE80211_WEP_NKID] 1984 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 1985 u_int32_t reg; 1986 int i; 1987 1988 sc->sc_wepctl = 0; 1989 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 1990 1991 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 1992 return; 1993 1994 memset(&buf[0][0], 0, sizeof(buf)); 1995 1996 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1997 if (ic->ic_nw_keys[i].wk_len > 5) { 1998 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 1999 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2000 buf[i][1] = ATW_WEP_ENABLED; 2001 } else { 2002 buf[i][1] = 0; 2003 continue; 2004 } 2005 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2006 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2007 ic->ic_nw_keys[i].wk_len - 1); 2008 } 2009 2010 reg = ATW_READ(sc, ATW_MACTEST); 2011 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2012 reg &= ~ATW_MACTEST_KEYID_MASK; 2013 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2014 ATW_WRITE(sc, ATW_MACTEST, reg); 2015 2016 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2017 * throughout.) 2018 */ 2019 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2020 if (sc->sc_if.if_flags & IFF_LINK2) 2021 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2022 2023 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2024 sizeof(buf)); 2025 } 2026 2027 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2028 2029 static void 2030 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2031 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2032 { 2033 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2034 2035 switch (subtype) { 2036 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2037 /* do nothing: hardware answers probe request */ 2038 break; 2039 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2040 case IEEE80211_FC0_SUBTYPE_BEACON: 2041 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2042 break; 2043 default: 2044 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2045 break; 2046 } 2047 return; 2048 } 2049 2050 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2051 * of IBSSs with like SSID/channel but different BSSID. It joins the 2052 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2053 * convention. Possibly the ADMtek chip does this for us; I will have 2054 * to test to find out. 2055 * 2056 * XXX we should add the duration field of the received beacon to 2057 * the TSF time it contains before comparing it with the ADM8211's 2058 * TSF. 2059 */ 2060 static void 2061 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2062 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2063 { 2064 struct atw_softc *sc; 2065 struct ieee80211_frame *wh; 2066 u_int64_t tsft, bcn_tsft; 2067 u_int32_t tsftl, tsfth; 2068 int do_print = 0; 2069 2070 sc = (struct atw_softc*)ic->ic_if.if_softc; 2071 2072 if (ic->ic_if.if_flags & IFF_DEBUG) 2073 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2074 ? 1 : ratecheck(&sc->sc_last_beacon, 2075 &atw_beacon_mininterval); 2076 2077 wh = mtod(m0, struct ieee80211_frame *); 2078 2079 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2080 2081 if (ic->ic_state != IEEE80211_S_RUN) { 2082 if (do_print) 2083 printf("%s: atw_recv_beacon: not running\n", 2084 sc->sc_dev.dv_xname); 2085 return; 2086 } 2087 2088 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2089 ic->ic_bss->ni_chan)) == NULL) { 2090 if (do_print) 2091 printf("%s: atw_recv_beacon: no node %s\n", 2092 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2093 return; 2094 } 2095 2096 if (ieee80211_match_bss(ic, ni) != 0) { 2097 if (do_print) 2098 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2099 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2100 return; 2101 } 2102 2103 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2104 return; 2105 2106 if (do_print) 2107 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2108 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2109 2110 if (ic->ic_opmode != IEEE80211_M_IBSS) 2111 return; 2112 2113 /* If we read TSFTL right before rollover, we read a TSF timer 2114 * that is too high rather than too low. This prevents a spurious 2115 * synchronization down the line, however, our IBSS could suffer 2116 * from a creeping TSF.... 2117 */ 2118 tsftl = ATW_READ(sc, ATW_TSFTL); 2119 tsfth = ATW_READ(sc, ATW_TSFTH); 2120 2121 tsft = (u_int64_t)tsfth << 32 | tsftl; 2122 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2123 2124 if (do_print) 2125 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2126 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2127 2128 /* we are faster, let the other guy catch up */ 2129 if (bcn_tsft < tsft) 2130 return; 2131 2132 if (do_print) 2133 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2134 ether_sprintf(wh->i_addr2)); 2135 2136 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2137 2138 #if 0 2139 atw_tsf(sc); 2140 #endif 2141 2142 /* negotiate rates with new IBSS */ 2143 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2144 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2145 if (ni->ni_rates.rs_nrates == 0) { 2146 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2147 ether_sprintf(ni->ni_bssid)); 2148 return; 2149 } 2150 2151 if (do_print) { 2152 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2153 ether_sprintf(ic->ic_bss->ni_bssid)); 2154 printf("%s ", ether_sprintf(ni->ni_bssid)); 2155 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2156 } 2157 2158 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2159 2160 atw_write_bssid(sc); 2161 atw_start_beacon(sc, 1); 2162 } 2163 2164 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2165 * In ad hoc mode, the SSID is written to the beacons sent by the 2166 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2167 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2168 * indications. 2169 */ 2170 static void 2171 atw_write_ssid(struct atw_softc *sc) 2172 { 2173 struct ieee80211com *ic = &sc->sc_ic; 2174 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2175 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2176 2177 memset(buf, 0, sizeof(buf)); 2178 buf[0] = ic->ic_bss->ni_esslen; 2179 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2180 2181 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2182 } 2183 2184 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2185 * In ad hoc mode, the supported rates are written to beacons sent by the 2186 * ADM8211. 2187 */ 2188 static void 2189 atw_write_sup_rates(struct atw_softc *sc) 2190 { 2191 struct ieee80211com *ic = &sc->sc_ic; 2192 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2193 * supported rates 2194 */ 2195 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2196 2197 memset(buf, 0, sizeof(buf)); 2198 2199 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2200 2201 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2202 ic->ic_bss->ni_rates.rs_nrates); 2203 2204 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2205 } 2206 2207 /* Start/stop sending beacons. */ 2208 void 2209 atw_start_beacon(struct atw_softc *sc, int start) 2210 { 2211 struct ieee80211com *ic = &sc->sc_ic; 2212 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2213 2214 if (ATW_IS_ENABLED(sc) == 0) 2215 return; 2216 2217 len = capinfo = 0; 2218 2219 /* start beacons */ 2220 len = sizeof(struct ieee80211_frame) + 2221 8 /* timestamp */ + 2 /* beacon interval */ + 2222 2 /* capability info */ + 2223 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2224 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2225 3 /* DS parameters */ + 2226 IEEE80211_CRC_LEN; 2227 2228 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2229 2230 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2231 2232 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2233 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2234 2235 if (!start) 2236 return; 2237 2238 /* TBD use ni_capinfo */ 2239 2240 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2241 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2242 if (ic->ic_flags & IEEE80211_F_WEPON) 2243 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2244 2245 switch (ic->ic_opmode) { 2246 case IEEE80211_M_IBSS: 2247 len += 4; /* IBSS parameters */ 2248 capinfo |= IEEE80211_CAPINFO_IBSS; 2249 break; 2250 case IEEE80211_M_HOSTAP: 2251 /* XXX 6-byte minimum TIM */ 2252 len += atw_beacon_len_adjust; 2253 capinfo |= IEEE80211_CAPINFO_ESS; 2254 break; 2255 default: 2256 return; 2257 } 2258 2259 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2260 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2261 2262 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2263 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2264 2265 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2266 sc->sc_dev.dv_xname, reg_bcnt)); 2267 2268 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2269 sc->sc_dev.dv_xname, reg_cap1)); 2270 } 2271 2272 /* First beacon was sent at time 0 microseconds, current time is 2273 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2274 * microseconds. Return the expected time in microseconds for the 2275 * beacon after next. 2276 */ 2277 static __inline u_int64_t 2278 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2279 { 2280 return tsft + (tbtt - tsft % tbtt); 2281 } 2282 2283 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2284 * the ieee80211com. 2285 * 2286 * Predict the next target beacon transmission time (TBTT) and 2287 * write it to the ADM8211. 2288 */ 2289 static void 2290 atw_tsf(struct atw_softc *sc) 2291 { 2292 #define TBTTOFS 20 /* TU */ 2293 2294 struct ieee80211com *ic = &sc->sc_ic; 2295 u_int64_t tsft, tbtt; 2296 2297 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2298 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2299 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2300 tsft = ATW_READ(sc, ATW_TSFTH); 2301 tsft <<= 32; 2302 tsft |= ATW_READ(sc, ATW_TSFTL); 2303 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2304 } else 2305 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2306 2307 tbtt = atw_predict_beacon(tsft, 2308 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2309 2310 /* skip one more beacon so that the TBTT cannot pass before 2311 * we've programmed it, and also so that we can subtract a 2312 * few TU so that we wake a little before TBTT. 2313 */ 2314 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2315 2316 /* wake up a little early */ 2317 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2318 2319 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2320 sc->sc_dev.dv_xname, tsft, tbtt)); 2321 2322 ATW_WRITE(sc, ATW_TOFS1, 2323 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2324 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2325 LSHIFT( 2326 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2327 ATW_TOFS1_TBTTPRE_MASK)); 2328 #undef TBTTOFS 2329 } 2330 2331 static void 2332 atw_next_scan(void *arg) 2333 { 2334 struct atw_softc *sc = arg; 2335 struct ieee80211com *ic = &sc->sc_ic; 2336 struct ifnet *ifp = &ic->ic_if; 2337 int s; 2338 2339 /* don't call atw_start w/o network interrupts blocked */ 2340 s = splnet(); 2341 if (ic->ic_state == IEEE80211_S_SCAN) 2342 ieee80211_next_scan(ifp); 2343 splx(s); 2344 } 2345 2346 /* Synchronize the hardware state with the software state. */ 2347 static int 2348 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2349 { 2350 struct ifnet *ifp = &ic->ic_if; 2351 struct atw_softc *sc = ifp->if_softc; 2352 enum ieee80211_state ostate; 2353 int error; 2354 2355 ostate = ic->ic_state; 2356 2357 if (nstate == IEEE80211_S_INIT) { 2358 callout_stop(&sc->sc_scan_ch); 2359 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2360 atw_start_beacon(sc, 0); 2361 return (*sc->sc_newstate)(ic, nstate, arg); 2362 } 2363 2364 if ((error = atw_tune(sc)) != 0) 2365 return error; 2366 2367 switch (nstate) { 2368 case IEEE80211_S_ASSOC: 2369 break; 2370 case IEEE80211_S_INIT: 2371 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2372 break; 2373 case IEEE80211_S_SCAN: 2374 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2375 atw_write_bssid(sc); 2376 2377 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2378 atw_next_scan, sc); 2379 2380 break; 2381 case IEEE80211_S_RUN: 2382 if (ic->ic_opmode == IEEE80211_M_STA) 2383 break; 2384 /*FALLTHROUGH*/ 2385 case IEEE80211_S_AUTH: 2386 atw_write_bssid(sc); 2387 atw_write_ssid(sc); 2388 atw_write_sup_rates(sc); 2389 2390 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2391 ic->ic_opmode == IEEE80211_M_MONITOR) 2392 break; 2393 2394 /* set listen interval 2395 * XXX do software units agree w/ hardware? 2396 */ 2397 ATW_WRITE(sc, ATW_BPLI, 2398 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2399 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2400 ATW_BPLI_LI_MASK)); 2401 2402 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2403 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2404 2405 atw_tsf(sc); 2406 break; 2407 } 2408 2409 if (nstate != IEEE80211_S_SCAN) 2410 callout_stop(&sc->sc_scan_ch); 2411 2412 if (nstate == IEEE80211_S_RUN && 2413 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2414 ic->ic_opmode == IEEE80211_M_IBSS)) 2415 atw_start_beacon(sc, 1); 2416 else 2417 atw_start_beacon(sc, 0); 2418 2419 return (*sc->sc_newstate)(ic, nstate, arg); 2420 } 2421 2422 /* 2423 * atw_add_rxbuf: 2424 * 2425 * Add a receive buffer to the indicated descriptor. 2426 */ 2427 int 2428 atw_add_rxbuf(struct atw_softc *sc, int idx) 2429 { 2430 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2431 struct mbuf *m; 2432 int error; 2433 2434 MGETHDR(m, M_DONTWAIT, MT_DATA); 2435 if (m == NULL) 2436 return (ENOBUFS); 2437 2438 MCLGET(m, M_DONTWAIT); 2439 if ((m->m_flags & M_EXT) == 0) { 2440 m_freem(m); 2441 return (ENOBUFS); 2442 } 2443 2444 if (rxs->rxs_mbuf != NULL) 2445 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2446 2447 rxs->rxs_mbuf = m; 2448 2449 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2450 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2451 BUS_DMA_READ|BUS_DMA_NOWAIT); 2452 if (error) { 2453 printf("%s: can't load rx DMA map %d, error = %d\n", 2454 sc->sc_dev.dv_xname, idx, error); 2455 panic("atw_add_rxbuf"); /* XXX */ 2456 } 2457 2458 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2459 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2460 2461 ATW_INIT_RXDESC(sc, idx); 2462 2463 return (0); 2464 } 2465 2466 /* 2467 * Release any queued transmit buffers. 2468 */ 2469 void 2470 atw_txdrain(struct atw_softc *sc) 2471 { 2472 struct atw_txsoft *txs; 2473 2474 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2475 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2476 if (txs->txs_mbuf != NULL) { 2477 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2478 m_freem(txs->txs_mbuf); 2479 txs->txs_mbuf = NULL; 2480 } 2481 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2482 } 2483 sc->sc_tx_timer = 0; 2484 } 2485 2486 /* 2487 * atw_stop: [ ifnet interface function ] 2488 * 2489 * Stop transmission on the interface. 2490 */ 2491 void 2492 atw_stop(struct ifnet *ifp, int disable) 2493 { 2494 struct atw_softc *sc = ifp->if_softc; 2495 struct ieee80211com *ic = &sc->sc_ic; 2496 2497 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2498 2499 /* Disable interrupts. */ 2500 ATW_WRITE(sc, ATW_IER, 0); 2501 2502 /* Stop the transmit and receive processes. */ 2503 sc->sc_opmode = 0; 2504 ATW_WRITE(sc, ATW_NAR, 0); 2505 ATW_WRITE(sc, ATW_TDBD, 0); 2506 ATW_WRITE(sc, ATW_TDBP, 0); 2507 ATW_WRITE(sc, ATW_RDB, 0); 2508 2509 atw_txdrain(sc); 2510 2511 if (disable) { 2512 atw_rxdrain(sc); 2513 atw_disable(sc); 2514 } 2515 2516 /* 2517 * Mark the interface down and cancel the watchdog timer. 2518 */ 2519 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2520 ifp->if_timer = 0; 2521 2522 if (!disable) 2523 atw_reset(sc); 2524 } 2525 2526 /* 2527 * atw_rxdrain: 2528 * 2529 * Drain the receive queue. 2530 */ 2531 void 2532 atw_rxdrain(struct atw_softc *sc) 2533 { 2534 struct atw_rxsoft *rxs; 2535 int i; 2536 2537 for (i = 0; i < ATW_NRXDESC; i++) { 2538 rxs = &sc->sc_rxsoft[i]; 2539 if (rxs->rxs_mbuf == NULL) 2540 continue; 2541 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2542 m_freem(rxs->rxs_mbuf); 2543 rxs->rxs_mbuf = NULL; 2544 } 2545 } 2546 2547 /* 2548 * atw_detach: 2549 * 2550 * Detach an ADM8211 interface. 2551 */ 2552 int 2553 atw_detach(struct atw_softc *sc) 2554 { 2555 struct ifnet *ifp = &sc->sc_ic.ic_if; 2556 struct atw_rxsoft *rxs; 2557 struct atw_txsoft *txs; 2558 int i; 2559 2560 /* 2561 * Succeed now if there isn't any work to do. 2562 */ 2563 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2564 return (0); 2565 2566 ieee80211_ifdetach(ifp); 2567 if_detach(ifp); 2568 2569 for (i = 0; i < ATW_NRXDESC; i++) { 2570 rxs = &sc->sc_rxsoft[i]; 2571 if (rxs->rxs_mbuf != NULL) { 2572 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2573 m_freem(rxs->rxs_mbuf); 2574 rxs->rxs_mbuf = NULL; 2575 } 2576 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2577 } 2578 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2579 txs = &sc->sc_txsoft[i]; 2580 if (txs->txs_mbuf != NULL) { 2581 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2582 m_freem(txs->txs_mbuf); 2583 txs->txs_mbuf = NULL; 2584 } 2585 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2586 } 2587 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2588 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2589 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2590 sizeof(struct atw_control_data)); 2591 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2592 2593 shutdownhook_disestablish(sc->sc_sdhook); 2594 powerhook_disestablish(sc->sc_powerhook); 2595 2596 if (sc->sc_srom) 2597 free(sc->sc_srom, M_DEVBUF); 2598 2599 return (0); 2600 } 2601 2602 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2603 void 2604 atw_shutdown(void *arg) 2605 { 2606 struct atw_softc *sc = arg; 2607 2608 atw_stop(&sc->sc_ic.ic_if, 1); 2609 } 2610 2611 int 2612 atw_intr(void *arg) 2613 { 2614 struct atw_softc *sc = arg; 2615 struct ifnet *ifp = &sc->sc_ic.ic_if; 2616 u_int32_t status, rxstatus, txstatus, linkstatus; 2617 int handled = 0, txthresh; 2618 2619 #ifdef DEBUG 2620 if (ATW_IS_ENABLED(sc) == 0) 2621 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2622 #endif 2623 2624 /* 2625 * If the interface isn't running, the interrupt couldn't 2626 * possibly have come from us. 2627 */ 2628 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2629 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2630 return (0); 2631 2632 for (;;) { 2633 status = ATW_READ(sc, ATW_STSR); 2634 2635 if (status) 2636 ATW_WRITE(sc, ATW_STSR, status); 2637 2638 if (sc->sc_intr_ack != NULL) 2639 (*sc->sc_intr_ack)(sc); 2640 2641 #ifdef ATW_DEBUG 2642 #define PRINTINTR(flag) do { \ 2643 if ((status & flag) != 0) { \ 2644 printf("%s" #flag, delim); \ 2645 delim = ","; \ 2646 } \ 2647 } while (0) 2648 2649 if (atw_debug > 1 && status) { 2650 const char *delim = "<"; 2651 2652 printf("%s: reg[STSR] = %x", 2653 sc->sc_dev.dv_xname, status); 2654 2655 PRINTINTR(ATW_INTR_FBE); 2656 PRINTINTR(ATW_INTR_LINKOFF); 2657 PRINTINTR(ATW_INTR_LINKON); 2658 PRINTINTR(ATW_INTR_RCI); 2659 PRINTINTR(ATW_INTR_RDU); 2660 PRINTINTR(ATW_INTR_REIS); 2661 PRINTINTR(ATW_INTR_RPS); 2662 PRINTINTR(ATW_INTR_TCI); 2663 PRINTINTR(ATW_INTR_TDU); 2664 PRINTINTR(ATW_INTR_TLT); 2665 PRINTINTR(ATW_INTR_TPS); 2666 PRINTINTR(ATW_INTR_TRT); 2667 PRINTINTR(ATW_INTR_TUF); 2668 PRINTINTR(ATW_INTR_BCNTC); 2669 PRINTINTR(ATW_INTR_ATIME); 2670 PRINTINTR(ATW_INTR_TBTT); 2671 PRINTINTR(ATW_INTR_TSCZ); 2672 PRINTINTR(ATW_INTR_TSFTF); 2673 printf(">\n"); 2674 } 2675 #undef PRINTINTR 2676 #endif /* ATW_DEBUG */ 2677 2678 if ((status & sc->sc_inten) == 0) 2679 break; 2680 2681 handled = 1; 2682 2683 rxstatus = status & sc->sc_rxint_mask; 2684 txstatus = status & sc->sc_txint_mask; 2685 linkstatus = status & sc->sc_linkint_mask; 2686 2687 if (linkstatus) { 2688 atw_linkintr(sc, linkstatus); 2689 } 2690 2691 if (rxstatus) { 2692 /* Grab any new packets. */ 2693 atw_rxintr(sc); 2694 2695 if (rxstatus & ATW_INTR_RDU) { 2696 printf("%s: receive ring overrun\n", 2697 sc->sc_dev.dv_xname); 2698 /* Get the receive process going again. */ 2699 ATW_WRITE(sc, ATW_RDR, 0x1); 2700 break; 2701 } 2702 } 2703 2704 if (txstatus) { 2705 /* Sweep up transmit descriptors. */ 2706 atw_txintr(sc); 2707 2708 if (txstatus & ATW_INTR_TLT) 2709 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2710 sc->sc_dev.dv_xname)); 2711 2712 if (txstatus & ATW_INTR_TRT) 2713 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2714 sc->sc_dev.dv_xname)); 2715 2716 /* If Tx under-run, increase our transmit threshold 2717 * if another is available. 2718 */ 2719 txthresh = sc->sc_txthresh + 1; 2720 if ((txstatus & ATW_INTR_TUF) && 2721 sc->sc_txth[txthresh].txth_name != NULL) { 2722 /* Idle the transmit process. */ 2723 atw_idle(sc, ATW_NAR_ST); 2724 2725 sc->sc_txthresh = txthresh; 2726 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2727 sc->sc_opmode |= 2728 sc->sc_txth[txthresh].txth_opmode; 2729 printf("%s: transmit underrun; new " 2730 "threshold: %s\n", sc->sc_dev.dv_xname, 2731 sc->sc_txth[txthresh].txth_name); 2732 2733 /* Set the new threshold and restart 2734 * the transmit process. 2735 */ 2736 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2737 /* XXX Log every Nth underrun from 2738 * XXX now on? 2739 */ 2740 } 2741 } 2742 2743 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2744 if (status & ATW_INTR_TPS) 2745 printf("%s: transmit process stopped\n", 2746 sc->sc_dev.dv_xname); 2747 if (status & ATW_INTR_RPS) 2748 printf("%s: receive process stopped\n", 2749 sc->sc_dev.dv_xname); 2750 (void)atw_init(ifp); 2751 break; 2752 } 2753 2754 if (status & ATW_INTR_FBE) { 2755 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2756 (void)atw_init(ifp); 2757 break; 2758 } 2759 2760 /* 2761 * Not handled: 2762 * 2763 * Transmit buffer unavailable -- normal 2764 * condition, nothing to do, really. 2765 * 2766 * Early receive interrupt -- not available on 2767 * all chips, we just use RI. We also only 2768 * use single-segment receive DMA, so this 2769 * is mostly useless. 2770 * 2771 * TBD others 2772 */ 2773 } 2774 2775 /* Try to get more packets going. */ 2776 atw_start(ifp); 2777 2778 return (handled); 2779 } 2780 2781 /* 2782 * atw_idle: 2783 * 2784 * Cause the transmit and/or receive processes to go idle. 2785 * 2786 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2787 * process in STSR if I clear SR or ST after the process has already 2788 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2789 * do not seem to be too reliable. Perhaps I have the sense of the 2790 * Rx bits switched with the Tx bits? 2791 */ 2792 void 2793 atw_idle(struct atw_softc *sc, u_int32_t bits) 2794 { 2795 u_int32_t ackmask = 0, opmode, stsr, test0; 2796 int i, s; 2797 2798 /* without this, somehow we run concurrently w/ interrupt handler */ 2799 s = splnet(); 2800 2801 opmode = sc->sc_opmode & ~bits; 2802 2803 if (bits & ATW_NAR_SR) 2804 ackmask |= ATW_INTR_RPS; 2805 2806 if (bits & ATW_NAR_ST) { 2807 ackmask |= ATW_INTR_TPS; 2808 /* set ATW_NAR_HF to flush TX FIFO. */ 2809 opmode |= ATW_NAR_HF; 2810 } 2811 2812 ATW_WRITE(sc, ATW_NAR, opmode); 2813 2814 for (i = 0; i < 1000; i++) { 2815 stsr = ATW_READ(sc, ATW_STSR); 2816 if ((stsr & ackmask) == ackmask) 2817 break; 2818 DELAY(10); 2819 } 2820 2821 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2822 2823 if ((stsr & ackmask) == ackmask) 2824 goto out; 2825 2826 test0 = ATW_READ(sc, ATW_TEST0); 2827 2828 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2829 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2830 printf("%s: transmit process not idle [%s]\n", 2831 sc->sc_dev.dv_xname, 2832 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2833 printf("%s: bits %08x test0 %08x stsr %08x\n", 2834 sc->sc_dev.dv_xname, bits, test0, stsr); 2835 } 2836 2837 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2838 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2839 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2840 sc->sc_dev.dv_xname, 2841 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2842 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2843 sc->sc_dev.dv_xname, bits, test0, stsr)); 2844 } 2845 out: 2846 if ((bits & ATW_NAR_ST) != 0) 2847 atw_txdrain(sc); 2848 splx(s); 2849 return; 2850 } 2851 2852 /* 2853 * atw_linkintr: 2854 * 2855 * Helper; handle link-status interrupts. 2856 */ 2857 void 2858 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2859 { 2860 struct ieee80211com *ic = &sc->sc_ic; 2861 2862 if (ic->ic_state != IEEE80211_S_RUN) 2863 return; 2864 2865 if (linkstatus & ATW_INTR_LINKON) { 2866 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2867 sc->sc_rescan_timer = 0; 2868 } else if (linkstatus & ATW_INTR_LINKOFF) { 2869 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2870 if (ic->ic_opmode != IEEE80211_M_STA) 2871 return; 2872 sc->sc_rescan_timer = 3; 2873 ic->ic_if.if_timer = 1; 2874 } 2875 } 2876 2877 /* 2878 * atw_rxintr: 2879 * 2880 * Helper; handle receive interrupts. 2881 */ 2882 void 2883 atw_rxintr(struct atw_softc *sc) 2884 { 2885 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2886 struct ieee80211com *ic = &sc->sc_ic; 2887 struct ieee80211_node *ni; 2888 struct ieee80211_frame *wh; 2889 struct ifnet *ifp = &ic->ic_if; 2890 struct atw_rxsoft *rxs; 2891 struct mbuf *m; 2892 u_int32_t rxstat; 2893 int i, len, rate, rate0; 2894 u_int32_t rssi; 2895 2896 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2897 rxs = &sc->sc_rxsoft[i]; 2898 2899 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2900 2901 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2902 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2903 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2904 2905 if (rxstat & ATW_RXSTAT_OWN) 2906 break; /* We have processed all receive buffers. */ 2907 2908 DPRINTF3(sc, 2909 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2910 sc->sc_dev.dv_xname, 2911 sc->sc_rxdescs[i].ar_stat, 2912 sc->sc_rxdescs[i].ar_rssi, 2913 sc->sc_rxdescs[i].ar_buf1, 2914 sc->sc_rxdescs[i].ar_buf2)); 2915 2916 /* 2917 * Make sure the packet fits in one buffer. This should 2918 * always be the case. 2919 */ 2920 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2921 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2922 printf("%s: incoming packet spilled, resetting\n", 2923 sc->sc_dev.dv_xname); 2924 (void)atw_init(ifp); 2925 return; 2926 } 2927 2928 /* 2929 * If an error occurred, update stats, clear the status 2930 * word, and leave the packet buffer in place. It will 2931 * simply be reused the next time the ring comes around. 2932 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2933 * error. 2934 */ 2935 2936 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2937 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2938 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2939 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2940 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2941 ATW_RXSTAT_ICVE)) != 0)) { 2942 #define PRINTERR(bit, str) \ 2943 if (rxstat & (bit)) \ 2944 printf("%s: receive error: %s\n", \ 2945 sc->sc_dev.dv_xname, str) 2946 ifp->if_ierrors++; 2947 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2948 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2949 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2950 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2951 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2952 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2953 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2954 #undef PRINTERR 2955 ATW_INIT_RXDESC(sc, i); 2956 continue; 2957 } 2958 2959 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2960 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2961 2962 /* 2963 * No errors; receive the packet. Note the ADM8211 2964 * includes the CRC in promiscuous mode. 2965 */ 2966 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2967 2968 /* 2969 * Allocate a new mbuf cluster. If that fails, we are 2970 * out of memory, and must drop the packet and recycle 2971 * the buffer that's already attached to this descriptor. 2972 */ 2973 m = rxs->rxs_mbuf; 2974 if (atw_add_rxbuf(sc, i) != 0) { 2975 ifp->if_ierrors++; 2976 ATW_INIT_RXDESC(sc, i); 2977 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2978 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2979 continue; 2980 } 2981 2982 ifp->if_ipackets++; 2983 if (sc->sc_opmode & ATW_NAR_PR) 2984 m->m_flags |= M_HASFCS; 2985 m->m_pkthdr.rcvif = ifp; 2986 m->m_pkthdr.len = m->m_len = len; 2987 2988 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 2989 rate = 0; 2990 else 2991 rate = rate_tbl[rate0]; 2992 2993 #if NBPFILTER > 0 2994 /* Pass this up to any BPF listeners. */ 2995 if (sc->sc_radiobpf != NULL) { 2996 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 2997 2998 tap->ar_rate = rate; 2999 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3000 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3001 3002 /* TBD verify units are dB */ 3003 tap->ar_antsignal = (int)rssi; 3004 /* TBD tap->ar_flags */ 3005 3006 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3007 tap->ar_ihdr.it_len, m); 3008 } 3009 #endif /* NPBFILTER > 0 */ 3010 3011 wh = mtod(m, struct ieee80211_frame *); 3012 ni = ieee80211_find_rxnode(ic, wh); 3013 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3014 /* 3015 * The frame may have caused the node to be marked for 3016 * reclamation (e.g. in response to a DEAUTH message) 3017 * so use free_node here instead of unref_node. 3018 */ 3019 if (ni == ic->ic_bss) 3020 ieee80211_unref_node(&ni); 3021 else 3022 ieee80211_free_node(ic, ni); 3023 } 3024 3025 /* Update the receive pointer. */ 3026 sc->sc_rxptr = i; 3027 } 3028 3029 /* 3030 * atw_txintr: 3031 * 3032 * Helper; handle transmit interrupts. 3033 */ 3034 void 3035 atw_txintr(struct atw_softc *sc) 3036 { 3037 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3038 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3039 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3040 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3041 3042 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3043 struct ifnet *ifp = &sc->sc_ic.ic_if; 3044 struct atw_txsoft *txs; 3045 u_int32_t txstat; 3046 3047 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3048 sc->sc_dev.dv_xname, sc->sc_flags)); 3049 3050 ifp->if_flags &= ~IFF_OACTIVE; 3051 3052 /* 3053 * Go through our Tx list and free mbufs for those 3054 * frames that have been transmitted. 3055 */ 3056 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3057 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3058 txs->txs_ndescs, 3059 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3060 3061 #ifdef ATW_DEBUG 3062 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3063 int i; 3064 printf(" txsoft %p transmit chain:\n", txs); 3065 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3066 printf(" descriptor %d:\n", i); 3067 printf(" at_status: 0x%08x\n", 3068 le32toh(sc->sc_txdescs[i].at_stat)); 3069 printf(" at_flags: 0x%08x\n", 3070 le32toh(sc->sc_txdescs[i].at_flags)); 3071 printf(" at_buf1: 0x%08x\n", 3072 le32toh(sc->sc_txdescs[i].at_buf1)); 3073 printf(" at_buf2: 0x%08x\n", 3074 le32toh(sc->sc_txdescs[i].at_buf2)); 3075 if (i == txs->txs_lastdesc) 3076 break; 3077 } 3078 } 3079 #endif 3080 3081 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3082 if (txstat & ATW_TXSTAT_OWN) 3083 break; 3084 3085 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3086 3087 sc->sc_txfree += txs->txs_ndescs; 3088 3089 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3090 0, txs->txs_dmamap->dm_mapsize, 3091 BUS_DMASYNC_POSTWRITE); 3092 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3093 m_freem(txs->txs_mbuf); 3094 txs->txs_mbuf = NULL; 3095 3096 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3097 3098 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3099 (txstat & TXSTAT_ERRMASK) != 0) { 3100 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3101 txstat_buf, sizeof(txstat_buf)); 3102 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3103 txstat_buf, 3104 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3105 } 3106 3107 /* 3108 * Check for errors and collisions. 3109 */ 3110 if (txstat & ATW_TXSTAT_TUF) 3111 sc->sc_stats.ts_tx_tuf++; 3112 if (txstat & ATW_TXSTAT_TLT) 3113 sc->sc_stats.ts_tx_tlt++; 3114 if (txstat & ATW_TXSTAT_TRT) 3115 sc->sc_stats.ts_tx_trt++; 3116 if (txstat & ATW_TXSTAT_TRO) 3117 sc->sc_stats.ts_tx_tro++; 3118 if (txstat & ATW_TXSTAT_SOFBR) { 3119 sc->sc_stats.ts_tx_sofbr++; 3120 } 3121 3122 if ((txstat & ATW_TXSTAT_ES) == 0) 3123 ifp->if_collisions += 3124 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3125 else 3126 ifp->if_oerrors++; 3127 3128 ifp->if_opackets++; 3129 } 3130 3131 /* 3132 * If there are no more pending transmissions, cancel the watchdog 3133 * timer. 3134 */ 3135 if (txs == NULL) 3136 sc->sc_tx_timer = 0; 3137 #undef TXSTAT_ERRMASK 3138 #undef TXSTAT_FMT 3139 } 3140 3141 /* 3142 * atw_watchdog: [ifnet interface function] 3143 * 3144 * Watchdog timer handler. 3145 */ 3146 void 3147 atw_watchdog(struct ifnet *ifp) 3148 { 3149 struct atw_softc *sc = ifp->if_softc; 3150 struct ieee80211com *ic = &sc->sc_ic; 3151 3152 ifp->if_timer = 0; 3153 if (ATW_IS_ENABLED(sc) == 0) 3154 return; 3155 3156 if (sc->sc_rescan_timer) { 3157 if (--sc->sc_rescan_timer == 0) 3158 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3159 } 3160 if (sc->sc_tx_timer) { 3161 if (--sc->sc_tx_timer == 0 && 3162 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3163 printf("%s: transmit timeout\n", ifp->if_xname); 3164 ifp->if_oerrors++; 3165 (void)atw_init(ifp); 3166 atw_start(ifp); 3167 } 3168 } 3169 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3170 ifp->if_timer = 1; 3171 ieee80211_watchdog(ifp); 3172 } 3173 3174 /* Compute the 802.11 Duration field and the PLCP Length fields for 3175 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3176 * Write the fields to the ADM8211 Tx header, frm. 3177 * 3178 * TBD use the fragmentation threshold to find the right duration for 3179 * the first & last fragments. 3180 * 3181 * TBD make certain of the duration fields applied by the ADM8211 to each 3182 * fragment. I think that the ADM8211 knows how to subtract the CTS 3183 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3184 * I also think that the ADM8211 does *some* arithmetic for us, because 3185 * otherwise I think we would have to set a first duration for CTS/first 3186 * fragment, a second duration for fragments between the first and the 3187 * last, and a third duration for the last fragment. 3188 * 3189 * TBD make certain that duration fields reflect addition of FCS/WEP 3190 * and correct duration arithmetic as necessary. 3191 */ 3192 static void 3193 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3194 int len) 3195 { 3196 int remainder; 3197 3198 /* deal also with encrypted fragments */ 3199 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3200 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3201 sc->sc_dev.dv_xname)); 3202 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3203 IEEE80211_WEP_CRCLEN; 3204 } 3205 3206 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3207 * duration (XXX added by MAC?). 3208 */ 3209 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3210 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3211 3212 if (rate <= 4) 3213 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3214 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3215 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3216 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3217 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3218 else 3219 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3220 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3221 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3222 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3223 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3224 3225 /* lengthen duration if long preamble */ 3226 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3227 frm->atw_head_dur += 3228 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3229 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3230 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3231 IEEE80211_DUR_DS_FAST_PLCPHDR); 3232 3233 if (remainder != 0) 3234 frm->atw_head_dur++; 3235 3236 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3237 (rate == 2 || rate == 4)) { 3238 /* derived from Linux: how could this be right? */ 3239 frm->atw_head_plcplen = frm->atw_head_dur; 3240 } else { 3241 frm->atw_head_plcplen = (16 * len) / rate; 3242 remainder = (80 * len) % (rate * 5); 3243 3244 if (remainder != 0) { 3245 frm->atw_head_plcplen++; 3246 3247 /* XXX magic */ 3248 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3249 rate == 22 && remainder <= 30) 3250 frm->atw_head_plcplen |= 0x8000; 3251 } 3252 } 3253 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3254 htole16(frm->atw_head_plcplen); 3255 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3256 } 3257 3258 #ifdef ATW_DEBUG 3259 static void 3260 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3261 { 3262 struct atw_softc *sc = ifp->if_softc; 3263 struct mbuf *m; 3264 int i, noctets = 0; 3265 3266 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3267 m0->m_pkthdr.len); 3268 3269 for (m = m0; m; m = m->m_next) { 3270 if (m->m_len == 0) 3271 continue; 3272 for (i = 0; i < m->m_len; i++) { 3273 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3274 if (++noctets % 24 == 0) 3275 printf("\n"); 3276 } 3277 } 3278 printf("%s%s: %d bytes emitted\n", 3279 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3280 } 3281 #endif /* ATW_DEBUG */ 3282 3283 /* 3284 * atw_start: [ifnet interface function] 3285 * 3286 * Start packet transmission on the interface. 3287 */ 3288 void 3289 atw_start(struct ifnet *ifp) 3290 { 3291 struct atw_softc *sc = ifp->if_softc; 3292 struct ieee80211com *ic = &sc->sc_ic; 3293 struct ieee80211_node *ni; 3294 struct ieee80211_frame *wh; 3295 struct atw_frame *hh; 3296 struct mbuf *m0, *m; 3297 struct atw_txsoft *txs, *last_txs; 3298 struct atw_txdesc *txd; 3299 int do_encrypt, rate; 3300 bus_dmamap_t dmamap; 3301 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3302 3303 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3304 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3305 3306 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3307 return; 3308 3309 #if 0 /* TBD ??? */ 3310 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3311 return; 3312 #endif 3313 3314 /* 3315 * Remember the previous number of free descriptors and 3316 * the first descriptor we'll use. 3317 */ 3318 ofree = sc->sc_txfree; 3319 firsttx = sc->sc_txnext; 3320 3321 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3322 sc->sc_dev.dv_xname, ofree, firsttx)); 3323 3324 /* 3325 * Loop through the send queue, setting up transmit descriptors 3326 * until we drain the queue, or use up all available transmit 3327 * descriptors. 3328 */ 3329 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3330 sc->sc_txfree != 0) { 3331 3332 /* 3333 * Grab a packet off the management queue, if it 3334 * is not empty. Otherwise, from the data queue. 3335 */ 3336 IF_DEQUEUE(&ic->ic_mgtq, m0); 3337 if (m0 != NULL) { 3338 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3339 m0->m_pkthdr.rcvif = NULL; 3340 } else { 3341 /* send no data packets until we are associated */ 3342 if (ic->ic_state != IEEE80211_S_RUN) 3343 break; 3344 IFQ_DEQUEUE(&ifp->if_snd, m0); 3345 if (m0 == NULL) 3346 break; 3347 #if NBPFILTER > 0 3348 if (ifp->if_bpf != NULL) 3349 bpf_mtap(ifp->if_bpf, m0); 3350 #endif /* NBPFILTER > 0 */ 3351 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3352 ifp->if_oerrors++; 3353 break; 3354 } 3355 } 3356 3357 rate = MAX(ieee80211_get_rate(ic), 2); 3358 3359 #if NBPFILTER > 0 3360 /* 3361 * Pass the packet to any BPF listeners. 3362 */ 3363 if (ic->ic_rawbpf != NULL) 3364 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3365 3366 if (sc->sc_radiobpf != NULL) { 3367 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3368 3369 tap->at_rate = rate; 3370 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3371 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3372 3373 /* TBD tap->at_flags */ 3374 3375 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3376 tap->at_ihdr.it_len, m0); 3377 } 3378 #endif /* NBPFILTER > 0 */ 3379 3380 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3381 3382 if (ni != NULL && ni != ic->ic_bss) 3383 ieee80211_free_node(ic, ni); 3384 3385 if (m0 == NULL) { 3386 ifp->if_oerrors++; 3387 break; 3388 } 3389 3390 /* just to make sure. */ 3391 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3392 3393 if (m0 == NULL) { 3394 ifp->if_oerrors++; 3395 break; 3396 } 3397 3398 hh = mtod(m0, struct atw_frame *); 3399 wh = &hh->atw_ihdr; 3400 3401 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3402 3403 /* Copy everything we need from the 802.11 header: 3404 * Frame Control; address 1, address 3, or addresses 3405 * 3 and 4. NIC fills in BSSID, SA. 3406 */ 3407 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3408 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3409 panic("%s: illegal WDS frame", 3410 sc->sc_dev.dv_xname); 3411 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3412 } else 3413 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3414 3415 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3416 3417 /* initialize remaining Tx parameters */ 3418 memset(&hh->u, 0, sizeof(hh->u)); 3419 3420 hh->atw_rate = rate * 5; 3421 /* XXX this could be incorrect if M_FCS. _encap should 3422 * probably strip FCS just in case it sticks around in 3423 * bridged packets. 3424 */ 3425 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3426 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3427 sizeof(struct atw_frame)); 3428 3429 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3430 hh->atw_rtylmt = 3; 3431 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3432 if (do_encrypt) { 3433 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3434 hh->atw_keyid = ic->ic_wep_txkey; 3435 } 3436 3437 /* TBD 4-addr frames */ 3438 atw_frame_setdurs(sc, hh, rate, 3439 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3440 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3441 3442 /* never fragment multicast frames */ 3443 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3444 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3445 } else if (sc->sc_flags & ATWF_RTSCTS) { 3446 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3447 } 3448 3449 #ifdef ATW_DEBUG 3450 hh->atw_fragnum = 0; 3451 3452 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3453 printf("%s: dst = %s, rate = 0x%02x, " 3454 "service = 0x%02x, paylen = 0x%04x\n", 3455 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3456 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3457 3458 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3459 "dur1 = 0x%04x, dur2 = 0x%04x, " 3460 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3461 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3462 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3463 hh->atw_tail_dur, hh->atw_head_dur); 3464 3465 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3466 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3467 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3468 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3469 3470 printf("%s: keyid = %d\n", 3471 sc->sc_dev.dv_xname, hh->atw_keyid); 3472 3473 atw_dump_pkt(ifp, m0); 3474 } 3475 #endif /* ATW_DEBUG */ 3476 3477 dmamap = txs->txs_dmamap; 3478 3479 /* 3480 * Load the DMA map. Copy and try (once) again if the packet 3481 * didn't fit in the alloted number of segments. 3482 */ 3483 for (first = 1; 3484 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3485 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3486 first = 0) { 3487 MGETHDR(m, M_DONTWAIT, MT_DATA); 3488 if (m == NULL) { 3489 printf("%s: unable to allocate Tx mbuf\n", 3490 sc->sc_dev.dv_xname); 3491 break; 3492 } 3493 if (m0->m_pkthdr.len > MHLEN) { 3494 MCLGET(m, M_DONTWAIT); 3495 if ((m->m_flags & M_EXT) == 0) { 3496 printf("%s: unable to allocate Tx " 3497 "cluster\n", sc->sc_dev.dv_xname); 3498 m_freem(m); 3499 break; 3500 } 3501 } 3502 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3503 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3504 m_freem(m0); 3505 m0 = m; 3506 m = NULL; 3507 } 3508 if (error != 0) { 3509 printf("%s: unable to load Tx buffer, " 3510 "error = %d\n", sc->sc_dev.dv_xname, error); 3511 m_freem(m0); 3512 break; 3513 } 3514 3515 /* 3516 * Ensure we have enough descriptors free to describe 3517 * the packet. 3518 */ 3519 if (dmamap->dm_nsegs > sc->sc_txfree) { 3520 /* 3521 * Not enough free descriptors to transmit 3522 * this packet. Unload the DMA map and 3523 * drop the packet. Notify the upper layer 3524 * that there are no more slots left. 3525 * 3526 * XXX We could allocate an mbuf and copy, but 3527 * XXX it is worth it? 3528 */ 3529 ifp->if_flags |= IFF_OACTIVE; 3530 bus_dmamap_unload(sc->sc_dmat, dmamap); 3531 m_freem(m0); 3532 break; 3533 } 3534 3535 /* 3536 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3537 */ 3538 3539 /* Sync the DMA map. */ 3540 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3541 BUS_DMASYNC_PREWRITE); 3542 3543 /* XXX arbitrary retry limit; 8 because I have seen it in 3544 * use already and maybe 0 means "no tries" ! 3545 */ 3546 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3547 3548 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3549 sc->sc_dev.dv_xname, rate * 5)); 3550 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3551 3552 /* 3553 * Initialize the transmit descriptors. 3554 */ 3555 for (nexttx = sc->sc_txnext, seg = 0; 3556 seg < dmamap->dm_nsegs; 3557 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3558 /* 3559 * If this is the first descriptor we're 3560 * enqueueing, don't set the OWN bit just 3561 * yet. That could cause a race condition. 3562 * We'll do it below. 3563 */ 3564 txd = &sc->sc_txdescs[nexttx]; 3565 txd->at_ctl = ctl | 3566 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3567 3568 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3569 txd->at_flags = 3570 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3571 ATW_TXFLAG_TBS1_MASK)) | 3572 ((nexttx == (ATW_NTXDESC - 1)) 3573 ? htole32(ATW_TXFLAG_TER) : 0); 3574 lasttx = nexttx; 3575 } 3576 3577 IASSERT(lasttx != -1, ("bad lastx")); 3578 /* Set `first segment' and `last segment' appropriately. */ 3579 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3580 htole32(ATW_TXFLAG_FS); 3581 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3582 3583 #ifdef ATW_DEBUG 3584 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3585 printf(" txsoft %p transmit chain:\n", txs); 3586 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3587 printf(" descriptor %d:\n", seg); 3588 printf(" at_ctl: 0x%08x\n", 3589 le32toh(sc->sc_txdescs[seg].at_ctl)); 3590 printf(" at_flags: 0x%08x\n", 3591 le32toh(sc->sc_txdescs[seg].at_flags)); 3592 printf(" at_buf1: 0x%08x\n", 3593 le32toh(sc->sc_txdescs[seg].at_buf1)); 3594 printf(" at_buf2: 0x%08x\n", 3595 le32toh(sc->sc_txdescs[seg].at_buf2)); 3596 if (seg == lasttx) 3597 break; 3598 } 3599 } 3600 #endif 3601 3602 /* Sync the descriptors we're using. */ 3603 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3604 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3605 3606 /* 3607 * Store a pointer to the packet so we can free it later, 3608 * and remember what txdirty will be once the packet is 3609 * done. 3610 */ 3611 txs->txs_mbuf = m0; 3612 txs->txs_firstdesc = sc->sc_txnext; 3613 txs->txs_lastdesc = lasttx; 3614 txs->txs_ndescs = dmamap->dm_nsegs; 3615 3616 /* Advance the tx pointer. */ 3617 sc->sc_txfree -= dmamap->dm_nsegs; 3618 sc->sc_txnext = nexttx; 3619 3620 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3621 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3622 3623 last_txs = txs; 3624 } 3625 3626 if (txs == NULL || sc->sc_txfree == 0) { 3627 /* No more slots left; notify upper layer. */ 3628 ifp->if_flags |= IFF_OACTIVE; 3629 } 3630 3631 if (sc->sc_txfree != ofree) { 3632 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3633 sc->sc_dev.dv_xname, lasttx, firsttx)); 3634 /* 3635 * Cause a transmit interrupt to happen on the 3636 * last packet we enqueued. 3637 */ 3638 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3639 ATW_CDTXSYNC(sc, lasttx, 1, 3640 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3641 3642 /* 3643 * The entire packet chain is set up. Give the 3644 * first descriptor to the chip now. 3645 */ 3646 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3647 ATW_CDTXSYNC(sc, firsttx, 1, 3648 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3649 3650 /* Wake up the transmitter. */ 3651 ATW_WRITE(sc, ATW_TDR, 0x1); 3652 3653 /* Set a watchdog timer in case the chip flakes out. */ 3654 sc->sc_tx_timer = 5; 3655 ifp->if_timer = 1; 3656 } 3657 } 3658 3659 /* 3660 * atw_power: 3661 * 3662 * Power management (suspend/resume) hook. 3663 */ 3664 void 3665 atw_power(int why, void *arg) 3666 { 3667 struct atw_softc *sc = arg; 3668 struct ifnet *ifp = &sc->sc_ic.ic_if; 3669 int s; 3670 3671 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3672 3673 s = splnet(); 3674 switch (why) { 3675 case PWR_STANDBY: 3676 /* XXX do nothing. */ 3677 break; 3678 case PWR_SUSPEND: 3679 atw_stop(ifp, 0); 3680 if (sc->sc_power != NULL) 3681 (*sc->sc_power)(sc, why); 3682 break; 3683 case PWR_RESUME: 3684 if (ifp->if_flags & IFF_UP) { 3685 if (sc->sc_power != NULL) 3686 (*sc->sc_power)(sc, why); 3687 atw_init(ifp); 3688 } 3689 break; 3690 case PWR_SOFTSUSPEND: 3691 case PWR_SOFTSTANDBY: 3692 case PWR_SOFTRESUME: 3693 break; 3694 } 3695 splx(s); 3696 } 3697 3698 /* 3699 * atw_ioctl: [ifnet interface function] 3700 * 3701 * Handle control requests from the operator. 3702 */ 3703 int 3704 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3705 { 3706 struct atw_softc *sc = ifp->if_softc; 3707 struct ifreq *ifr = (struct ifreq *)data; 3708 int s, error = 0; 3709 3710 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3711 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3712 return ENXIO; 3713 3714 s = splnet(); 3715 3716 switch (cmd) { 3717 case SIOCSIFFLAGS: 3718 if (ifp->if_flags & IFF_UP) { 3719 if (ATW_IS_ENABLED(sc)) { 3720 /* 3721 * To avoid rescanning another access point, 3722 * do not call atw_init() here. Instead, 3723 * only reflect media settings. 3724 */ 3725 atw_filter_setup(sc); 3726 } else 3727 error = atw_init(ifp); 3728 } else if (ATW_IS_ENABLED(sc)) 3729 atw_stop(ifp, 1); 3730 break; 3731 case SIOCADDMULTI: 3732 case SIOCDELMULTI: 3733 error = (cmd == SIOCADDMULTI) ? 3734 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3735 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3736 if (error == ENETRESET) { 3737 if (ATW_IS_ENABLED(sc)) 3738 atw_filter_setup(sc); /* do not rescan */ 3739 error = 0; 3740 } 3741 break; 3742 default: 3743 error = ieee80211_ioctl(ifp, cmd, data); 3744 if (error == ENETRESET) { 3745 if (ATW_IS_ENABLED(sc)) 3746 error = atw_init(ifp); 3747 else 3748 error = 0; 3749 } 3750 break; 3751 } 3752 3753 /* Try to get more packets going. */ 3754 if (ATW_IS_ENABLED(sc)) 3755 atw_start(ifp); 3756 3757 splx(s); 3758 return (error); 3759 } 3760 3761 static int 3762 atw_media_change(struct ifnet *ifp) 3763 { 3764 int error; 3765 3766 error = ieee80211_media_change(ifp); 3767 if (error == ENETRESET) { 3768 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3769 (IFF_RUNNING|IFF_UP)) 3770 atw_init(ifp); /* XXX lose error */ 3771 error = 0; 3772 } 3773 return error; 3774 } 3775 3776 static void 3777 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3778 { 3779 struct atw_softc *sc = ifp->if_softc; 3780 3781 if (ATW_IS_ENABLED(sc) == 0) { 3782 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3783 imr->ifm_status = 0; 3784 return; 3785 } 3786 ieee80211_media_status(ifp, imr); 3787 } 3788
Indexes created Wed Sep 24 02:09:48 GMT 2025