atw.c revision 1.49
1 /* $NetBSD: atw.c,v 1.49 2004/07/15 06:38:46 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.49 2004/07/15 06:38:46 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 139 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 140 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 141 142 int atw_rfio_enable_delay = 20 * 1000; 143 int atw_rfio_disable_delay = 2 * 1000; 144 int atw_writewep_delay = 5; 145 int atw_beacon_len_adjust = 4; 146 int atw_dwelltime = 200; 147 148 #ifdef ATW_DEBUG 149 int atw_debug = 0; 150 151 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 155 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158 static void atw_print_regs(struct atw_softc *, const char *); 159 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 160 161 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162 # ifdef ATW_BBPDEBUG 163 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 164 static void atw_rf3000_print(struct atw_softc *); 165 # endif /* ATW_BBPDEBUG */ 166 167 # ifdef ATW_SYNDEBUG 168 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 169 static void atw_si4126_print(struct atw_softc *); 170 # endif /* ATW_SYNDEBUG */ 171 172 #else 173 #define ATW_DPRINTF(x) 174 #define ATW_DPRINTF2(x) 175 #define ATW_DPRINTF3(x) 176 #define DPRINTF(sc, x) /* nothing */ 177 #define DPRINTF2(sc, x) /* nothing */ 178 #define DPRINTF3(sc, x) /* nothing */ 179 #endif 180 181 #ifdef ATW_STATS 182 void atw_print_stats(struct atw_softc *); 183 #endif 184 185 void atw_start(struct ifnet *); 186 void atw_watchdog(struct ifnet *); 187 int atw_ioctl(struct ifnet *, u_long, caddr_t); 188 int atw_init(struct ifnet *); 189 void atw_txdrain(struct atw_softc *); 190 void atw_stop(struct ifnet *, int); 191 192 void atw_reset(struct atw_softc *); 193 int atw_read_srom(struct atw_softc *); 194 195 void atw_shutdown(void *); 196 197 void atw_rxdrain(struct atw_softc *); 198 int atw_add_rxbuf(struct atw_softc *, int); 199 void atw_idle(struct atw_softc *, u_int32_t); 200 201 int atw_enable(struct atw_softc *); 202 void atw_disable(struct atw_softc *); 203 void atw_power(int, void *); 204 205 void atw_rxintr(struct atw_softc *); 206 void atw_txintr(struct atw_softc *); 207 void atw_linkintr(struct atw_softc *, u_int32_t); 208 209 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 210 static void atw_tsf(struct atw_softc *); 211 static void atw_start_beacon(struct atw_softc *, int); 212 static void atw_write_wep(struct atw_softc *); 213 static void atw_write_bssid(struct atw_softc *); 214 static void atw_write_ssid(struct atw_softc *); 215 static void atw_write_sup_rates(struct atw_softc *); 216 static void atw_clear_sram(struct atw_softc *); 217 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 218 static int atw_media_change(struct ifnet *); 219 static void atw_media_status(struct ifnet *, struct ifmediareq *); 220 static void atw_filter_setup(struct atw_softc *); 221 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 222 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 223 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 228 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 229 230 static int atw_tune(struct atw_softc *); 231 232 static void atw_rfio_enable(struct atw_softc *, int); 233 234 /* RFMD RF3000 Baseband Processor */ 235 static int atw_rf3000_init(struct atw_softc *); 236 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 237 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 238 #ifdef ATW_DEBUG 239 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 240 #endif /* ATW_DEBUG */ 241 242 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 243 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 244 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 245 #ifdef ATW_DEBUG 246 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 247 #endif /* ATW_DEBUG */ 248 249 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 250 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 251 252 const char *atw_tx_state[] = { 253 "STOPPED", 254 "RUNNING - read descriptor", 255 "RUNNING - transmitting", 256 "RUNNING - filling fifo", /* XXX */ 257 "SUSPENDED", 258 "RUNNING -- write descriptor", 259 "RUNNING -- write last descriptor", 260 "RUNNING - fifo full" 261 }; 262 263 const char *atw_rx_state[] = { 264 "STOPPED", 265 "RUNNING - read descriptor", 266 "RUNNING - check this packet, pre-fetch next", 267 "RUNNING - wait for reception", 268 "SUSPENDED", 269 "RUNNING - write descriptor", 270 "RUNNING - flush fifo", 271 "RUNNING - fifo drain" 272 }; 273 274 int 275 atw_activate(struct device *self, enum devact act) 276 { 277 struct atw_softc *sc = (struct atw_softc *)self; 278 int rv = 0, s; 279 280 s = splnet(); 281 switch (act) { 282 case DVACT_ACTIVATE: 283 rv = EOPNOTSUPP; 284 break; 285 286 case DVACT_DEACTIVATE: 287 if_deactivate(&sc->sc_ic.ic_if); 288 break; 289 } 290 splx(s); 291 return rv; 292 } 293 294 /* 295 * atw_enable: 296 * 297 * Enable the ADM8211 chip. 298 */ 299 int 300 atw_enable(struct atw_softc *sc) 301 { 302 303 if (ATW_IS_ENABLED(sc) == 0) { 304 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 305 printf("%s: device enable failed\n", 306 sc->sc_dev.dv_xname); 307 return (EIO); 308 } 309 sc->sc_flags |= ATWF_ENABLED; 310 } 311 return (0); 312 } 313 314 /* 315 * atw_disable: 316 * 317 * Disable the ADM8211 chip. 318 */ 319 void 320 atw_disable(struct atw_softc *sc) 321 { 322 if (!ATW_IS_ENABLED(sc)) 323 return; 324 if (sc->sc_disable != NULL) 325 (*sc->sc_disable)(sc); 326 sc->sc_flags &= ~ATWF_ENABLED; 327 } 328 329 /* Returns -1 on failure. */ 330 int 331 atw_read_srom(struct atw_softc *sc) 332 { 333 struct seeprom_descriptor sd; 334 u_int32_t reg; 335 336 (void)memset(&sd, 0, sizeof(sd)); 337 338 reg = ATW_READ(sc, ATW_TEST0); 339 340 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 341 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 342 return -1; 343 } 344 345 switch (reg & ATW_TEST0_EPTYP_MASK) { 346 case ATW_TEST0_EPTYP_93c66: 347 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 348 sc->sc_sromsz = 512; 349 sd.sd_chip = C56_66; 350 break; 351 case ATW_TEST0_EPTYP_93c46: 352 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 353 sc->sc_sromsz = 128; 354 sd.sd_chip = C46; 355 break; 356 default: 357 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 358 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 359 return -1; 360 } 361 362 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 363 364 if (sc->sc_srom == NULL) { 365 printf("%s: unable to allocate SROM buffer\n", 366 sc->sc_dev.dv_xname); 367 return -1; 368 } 369 370 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 371 372 /* ADM8211 has a single 32-bit register for controlling the 373 * 93cx6 SROM. Bit SRS enables the serial port. There is no 374 * "ready" bit. The ADM8211 input/output sense is the reverse 375 * of read_seeprom's. 376 */ 377 sd.sd_tag = sc->sc_st; 378 sd.sd_bsh = sc->sc_sh; 379 sd.sd_regsize = 4; 380 sd.sd_control_offset = ATW_SPR; 381 sd.sd_status_offset = ATW_SPR; 382 sd.sd_dataout_offset = ATW_SPR; 383 sd.sd_CK = ATW_SPR_SCLK; 384 sd.sd_CS = ATW_SPR_SCS; 385 sd.sd_DI = ATW_SPR_SDO; 386 sd.sd_DO = ATW_SPR_SDI; 387 sd.sd_MS = ATW_SPR_SRS; 388 sd.sd_RDY = 0; 389 390 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 391 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 392 free(sc->sc_srom, M_DEVBUF); 393 return -1; 394 } 395 #ifdef ATW_DEBUG 396 { 397 int i; 398 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 399 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 400 if (((i % 8) == 0) && (i != 0)) { 401 ATW_DPRINTF(("\n\t")); 402 } 403 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 404 } 405 ATW_DPRINTF(("\n")); 406 } 407 #endif /* ATW_DEBUG */ 408 return 0; 409 } 410 411 #ifdef ATW_DEBUG 412 static void 413 atw_print_regs(struct atw_softc *sc, const char *where) 414 { 415 #define PRINTREG(sc, reg) \ 416 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 417 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 418 419 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 420 421 PRINTREG(sc, ATW_PAR); 422 PRINTREG(sc, ATW_FRCTL); 423 PRINTREG(sc, ATW_TDR); 424 PRINTREG(sc, ATW_WTDP); 425 PRINTREG(sc, ATW_RDR); 426 PRINTREG(sc, ATW_WRDP); 427 PRINTREG(sc, ATW_RDB); 428 PRINTREG(sc, ATW_CSR3A); 429 PRINTREG(sc, ATW_TDBD); 430 PRINTREG(sc, ATW_TDBP); 431 PRINTREG(sc, ATW_STSR); 432 PRINTREG(sc, ATW_CSR5A); 433 PRINTREG(sc, ATW_NAR); 434 PRINTREG(sc, ATW_CSR6A); 435 PRINTREG(sc, ATW_IER); 436 PRINTREG(sc, ATW_CSR7A); 437 PRINTREG(sc, ATW_LPC); 438 PRINTREG(sc, ATW_TEST1); 439 PRINTREG(sc, ATW_SPR); 440 PRINTREG(sc, ATW_TEST0); 441 PRINTREG(sc, ATW_WCSR); 442 PRINTREG(sc, ATW_WPDR); 443 PRINTREG(sc, ATW_GPTMR); 444 PRINTREG(sc, ATW_GPIO); 445 PRINTREG(sc, ATW_BBPCTL); 446 PRINTREG(sc, ATW_SYNCTL); 447 PRINTREG(sc, ATW_PLCPHD); 448 PRINTREG(sc, ATW_MMIWADDR); 449 PRINTREG(sc, ATW_MMIRADDR1); 450 PRINTREG(sc, ATW_MMIRADDR2); 451 PRINTREG(sc, ATW_TXBR); 452 PRINTREG(sc, ATW_CSR15A); 453 PRINTREG(sc, ATW_ALCSTAT); 454 PRINTREG(sc, ATW_TOFS2); 455 PRINTREG(sc, ATW_CMDR); 456 PRINTREG(sc, ATW_PCIC); 457 PRINTREG(sc, ATW_PMCSR); 458 PRINTREG(sc, ATW_PAR0); 459 PRINTREG(sc, ATW_PAR1); 460 PRINTREG(sc, ATW_MAR0); 461 PRINTREG(sc, ATW_MAR1); 462 PRINTREG(sc, ATW_ATIMDA0); 463 PRINTREG(sc, ATW_ABDA1); 464 PRINTREG(sc, ATW_BSSID0); 465 PRINTREG(sc, ATW_TXLMT); 466 PRINTREG(sc, ATW_MIBCNT); 467 PRINTREG(sc, ATW_BCNT); 468 PRINTREG(sc, ATW_TSFTH); 469 PRINTREG(sc, ATW_TSC); 470 PRINTREG(sc, ATW_SYNRF); 471 PRINTREG(sc, ATW_BPLI); 472 PRINTREG(sc, ATW_CAP0); 473 PRINTREG(sc, ATW_CAP1); 474 PRINTREG(sc, ATW_RMD); 475 PRINTREG(sc, ATW_CFPP); 476 PRINTREG(sc, ATW_TOFS0); 477 PRINTREG(sc, ATW_TOFS1); 478 PRINTREG(sc, ATW_IFST); 479 PRINTREG(sc, ATW_RSPT); 480 PRINTREG(sc, ATW_TSFTL); 481 PRINTREG(sc, ATW_WEPCTL); 482 PRINTREG(sc, ATW_WESK); 483 PRINTREG(sc, ATW_WEPCNT); 484 PRINTREG(sc, ATW_MACTEST); 485 PRINTREG(sc, ATW_FER); 486 PRINTREG(sc, ATW_FEMR); 487 PRINTREG(sc, ATW_FPSR); 488 PRINTREG(sc, ATW_FFER); 489 #undef PRINTREG 490 } 491 #endif /* ATW_DEBUG */ 492 493 /* 494 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 495 */ 496 void 497 atw_attach(struct atw_softc *sc) 498 { 499 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 500 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 501 }; 502 struct ieee80211com *ic = &sc->sc_ic; 503 struct ifnet *ifp = &ic->ic_if; 504 int country_code, error, i, nrate; 505 u_int32_t reg; 506 static const char *type_strings[] = {"Intersil (not supported)", 507 "RFMD", "Marvel (not supported)"}; 508 509 sc->sc_txth = atw_txthresh_tab_lo; 510 511 SIMPLEQ_INIT(&sc->sc_txfreeq); 512 SIMPLEQ_INIT(&sc->sc_txdirtyq); 513 514 #ifdef ATW_DEBUG 515 atw_print_regs(sc, "atw_attach"); 516 #endif /* ATW_DEBUG */ 517 518 /* 519 * Allocate the control data structures, and create and load the 520 * DMA map for it. 521 */ 522 if ((error = bus_dmamem_alloc(sc->sc_dmat, 523 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 524 1, &sc->sc_cdnseg, 0)) != 0) { 525 printf("%s: unable to allocate control data, error = %d\n", 526 sc->sc_dev.dv_xname, error); 527 goto fail_0; 528 } 529 530 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 531 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 532 BUS_DMA_COHERENT)) != 0) { 533 printf("%s: unable to map control data, error = %d\n", 534 sc->sc_dev.dv_xname, error); 535 goto fail_1; 536 } 537 538 if ((error = bus_dmamap_create(sc->sc_dmat, 539 sizeof(struct atw_control_data), 1, 540 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 541 printf("%s: unable to create control data DMA map, " 542 "error = %d\n", sc->sc_dev.dv_xname, error); 543 goto fail_2; 544 } 545 546 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 547 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 548 0)) != 0) { 549 printf("%s: unable to load control data DMA map, error = %d\n", 550 sc->sc_dev.dv_xname, error); 551 goto fail_3; 552 } 553 554 /* 555 * Create the transmit buffer DMA maps. 556 */ 557 sc->sc_ntxsegs = ATW_NTXSEGS; 558 for (i = 0; i < ATW_TXQUEUELEN; i++) { 559 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 560 sc->sc_ntxsegs, MCLBYTES, 0, 0, 561 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 562 printf("%s: unable to create tx DMA map %d, " 563 "error = %d\n", sc->sc_dev.dv_xname, i, error); 564 goto fail_4; 565 } 566 } 567 568 /* 569 * Create the receive buffer DMA maps. 570 */ 571 for (i = 0; i < ATW_NRXDESC; i++) { 572 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 573 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 574 printf("%s: unable to create rx DMA map %d, " 575 "error = %d\n", sc->sc_dev.dv_xname, i, error); 576 goto fail_5; 577 } 578 } 579 for (i = 0; i < ATW_NRXDESC; i++) { 580 sc->sc_rxsoft[i].rxs_mbuf = NULL; 581 } 582 583 /* Reset the chip to a known state. */ 584 atw_reset(sc); 585 586 if (atw_read_srom(sc) == -1) 587 return; 588 589 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 590 ATW_SR_RFTYPE_MASK); 591 592 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 593 ATW_SR_BBPTYPE_MASK); 594 595 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 600 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 601 return; 602 } 603 604 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 605 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 606 607 /* XXX There exists a Linux driver which seems to use RFType = 0 for 608 * MARVEL. My bug, or theirs? 609 */ 610 611 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 612 613 switch (sc->sc_rftype) { 614 case ATW_RFTYPE_INTERSIL: 615 reg |= ATW_SYNCTL_CS1; 616 break; 617 case ATW_RFTYPE_RFMD: 618 reg |= ATW_SYNCTL_CS0; 619 break; 620 case ATW_RFTYPE_MARVEL: 621 break; 622 } 623 624 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 625 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 626 627 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 628 629 switch (sc->sc_bbptype) { 630 case ATW_BBPTYPE_INTERSIL: 631 reg |= ATW_BBPCTL_TWI; 632 break; 633 case ATW_BBPTYPE_RFMD: 634 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 635 ATW_BBPCTL_CCA_ACTLO; 636 break; 637 case ATW_BBPTYPE_MARVEL: 638 break; 639 case ATW_C_BBPTYPE_RFMD: 640 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 641 sc->sc_dev.dv_xname); 642 break; 643 } 644 645 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 646 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 647 648 /* 649 * From this point forward, the attachment cannot fail. A failure 650 * before this point releases all resources that may have been 651 * allocated. 652 */ 653 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 654 655 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 656 htole16(sc->sc_srom[ATW_SR_MAC00]), 657 htole16(sc->sc_srom[ATW_SR_MAC01]), 658 htole16(sc->sc_srom[ATW_SR_MAC10]))); 659 660 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 661 ATW_SR_CTRY_MASK); 662 663 #define ADD_CHANNEL(_ic, _chan) do { \ 664 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 665 _ic->ic_channels[_chan].ic_freq = \ 666 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 667 } while (0) 668 669 /* Find available channels */ 670 switch (country_code) { 671 case COUNTRY_MMK2: /* 1-14 */ 672 ADD_CHANNEL(ic, 14); 673 /*FALLTHROUGH*/ 674 case COUNTRY_ETSI: /* 1-13 */ 675 for (i = 1; i <= 13; i++) 676 ADD_CHANNEL(ic, i); 677 break; 678 case COUNTRY_FCC: /* 1-11 */ 679 case COUNTRY_IC: /* 1-11 */ 680 for (i = 1; i <= 11; i++) 681 ADD_CHANNEL(ic, i); 682 break; 683 case COUNTRY_MMK: /* 14 */ 684 ADD_CHANNEL(ic, 14); 685 break; 686 case COUNTRY_FRANCE: /* 10-13 */ 687 for (i = 10; i <= 13; i++) 688 ADD_CHANNEL(ic, i); 689 break; 690 default: /* assume channels 10-11 */ 691 case COUNTRY_SPAIN: /* 10-11 */ 692 for (i = 10; i <= 11; i++) 693 ADD_CHANNEL(ic, i); 694 break; 695 } 696 697 /* Read the MAC address. */ 698 reg = ATW_READ(sc, ATW_PAR0); 699 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 700 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 701 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 702 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 703 reg = ATW_READ(sc, ATW_PAR1); 704 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 705 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 706 707 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 708 printf(" could not get mac address, attach failed\n"); 709 return; 710 } 711 712 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 713 714 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 715 ifp->if_softc = sc; 716 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 717 IFF_NOTRAILERS; 718 ifp->if_ioctl = atw_ioctl; 719 ifp->if_start = atw_start; 720 ifp->if_watchdog = atw_watchdog; 721 ifp->if_init = atw_init; 722 ifp->if_stop = atw_stop; 723 IFQ_SET_READY(&ifp->if_snd); 724 725 ic->ic_phytype = IEEE80211_T_DS; 726 ic->ic_opmode = IEEE80211_M_STA; 727 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 728 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 729 730 nrate = 0; 731 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 735 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 736 737 /* 738 * Call MI attach routines. 739 */ 740 741 if_attach(ifp); 742 ieee80211_ifattach(ifp); 743 744 sc->sc_newstate = ic->ic_newstate; 745 ic->ic_newstate = atw_newstate; 746 747 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 748 ic->ic_recv_mgmt = atw_recv_mgmt; 749 750 sc->sc_node_free = ic->ic_node_free; 751 ic->ic_node_free = atw_node_free; 752 753 sc->sc_node_alloc = ic->ic_node_alloc; 754 ic->ic_node_alloc = atw_node_alloc; 755 756 /* possibly we should fill in our own sc_send_prresp, since 757 * the ADM8211 is probably sending probe responses in ad hoc 758 * mode. 759 */ 760 761 /* complete initialization */ 762 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 763 callout_init(&sc->sc_scan_ch); 764 765 #if NBPFILTER > 0 766 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 767 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 768 #endif 769 770 /* 771 * Make sure the interface is shutdown during reboot. 772 */ 773 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 774 if (sc->sc_sdhook == NULL) 775 printf("%s: WARNING: unable to establish shutdown hook\n", 776 sc->sc_dev.dv_xname); 777 778 /* 779 * Add a suspend hook to make sure we come back up after a 780 * resume. 781 */ 782 sc->sc_powerhook = powerhook_establish(atw_power, sc); 783 if (sc->sc_powerhook == NULL) 784 printf("%s: WARNING: unable to establish power hook\n", 785 sc->sc_dev.dv_xname); 786 787 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 788 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 789 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 790 791 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 792 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 793 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 794 795 return; 796 797 /* 798 * Free any resources we've allocated during the failed attach 799 * attempt. Do this in reverse order and fall through. 800 */ 801 fail_5: 802 for (i = 0; i < ATW_NRXDESC; i++) { 803 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 806 } 807 fail_4: 808 for (i = 0; i < ATW_TXQUEUELEN; i++) { 809 if (sc->sc_txsoft[i].txs_dmamap == NULL) 810 continue; 811 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 812 } 813 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 814 fail_3: 815 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 816 fail_2: 817 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 818 sizeof(struct atw_control_data)); 819 fail_1: 820 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 821 fail_0: 822 return; 823 } 824 825 static struct ieee80211_node * 826 atw_node_alloc(struct ieee80211com *ic) 827 { 828 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 829 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 830 831 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 832 return ni; 833 } 834 835 static void 836 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 837 { 838 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 839 840 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 841 ether_sprintf(ni->ni_bssid))); 842 (*sc->sc_node_free)(ic, ni); 843 } 844 845 /* 846 * atw_reset: 847 * 848 * Perform a soft reset on the ADM8211. 849 */ 850 void 851 atw_reset(struct atw_softc *sc) 852 { 853 int i; 854 855 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 856 857 for (i = 0; i < 10000; i++) { 858 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 859 break; 860 DELAY(1); 861 } 862 863 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 864 865 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 866 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 867 868 /* Turn off maximum power saving. */ 869 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 870 871 /* Recall EEPROM. */ 872 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 873 874 DELAY(10 * 1000); 875 876 /* A reset seems to affect the SRAM contents, so put them into 877 * a known state. 878 */ 879 atw_clear_sram(sc); 880 881 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 882 } 883 884 static void 885 atw_clear_sram(struct atw_softc *sc) 886 { 887 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 888 /* XXX not for revision 0x20. */ 889 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 890 } 891 892 /* TBD atw_init 893 * 894 * set MAC based on ic->ic_bss->myaddr 895 * write WEP keys 896 * set TX rate 897 */ 898 899 /* 900 * atw_init: [ ifnet interface function ] 901 * 902 * Initialize the interface. Must be called at splnet(). 903 */ 904 int 905 atw_init(struct ifnet *ifp) 906 { 907 struct atw_softc *sc = ifp->if_softc; 908 struct ieee80211com *ic = &sc->sc_ic; 909 struct atw_txsoft *txs; 910 struct atw_rxsoft *rxs; 911 u_int32_t reg; 912 int i, error = 0; 913 914 if ((error = atw_enable(sc)) != 0) 915 goto out; 916 917 /* 918 * Cancel any pending I/O. This also resets. 919 */ 920 atw_stop(ifp, 0); 921 922 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 923 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 924 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 925 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 926 927 /* Turn off APM??? (A binary-only driver does this.) 928 * 929 * Set Rx store-and-forward mode. 930 */ 931 reg = ATW_READ(sc, ATW_CMDR); 932 reg &= ~ATW_CMDR_APM; 933 reg &= ~ATW_CMDR_DRT_MASK; 934 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 935 936 ATW_WRITE(sc, ATW_CMDR, reg); 937 938 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 939 * 940 * XXX a binary-only driver sets a different service field than 941 * 0. why? 942 */ 943 reg = ATW_READ(sc, ATW_PLCPHD); 944 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 945 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 946 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 947 ATW_WRITE(sc, ATW_PLCPHD, reg); 948 949 /* XXX this magic can probably be figured out from the RFMD docs */ 950 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 951 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 952 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 953 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 954 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 955 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 956 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 957 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 958 ATW_WRITE(sc, ATW_TOFS2, reg); 959 960 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 961 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 962 963 /* XXX this resets an Intersil RF front-end? */ 964 /* TBD condition on Intersil RFType? */ 965 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 966 DELAY(10 * 1000); 967 ATW_WRITE(sc, ATW_SYNRF, 0); 968 DELAY(5 * 1000); 969 970 /* 16 TU max duration for contention-free period */ 971 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 972 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 973 974 /* XXX I guess that the Cardbus clock is 22MHz? 975 * I am assuming that the role of ATW_TOFS0_USCNT is 976 * to divide the bus clock to get a 1MHz clock---the datasheet is not 977 * very clear on this point. It says in the datasheet that it is 978 * possible for the ADM8211 to accomodate bus speeds between 22MHz 979 * and 33MHz; maybe this is the way? I see a binary-only driver write 980 * these values. These values are also the power-on default. 981 */ 982 ATW_WRITE(sc, ATW_TOFS0, 983 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 984 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 985 986 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 987 * driver. Go figure. 988 */ 989 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 990 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 991 ATW_IFST_SIFS_MASK) | 992 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 993 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 994 995 ATW_WRITE(sc, ATW_IFST, reg); 996 997 /* XXX More magic. Might relate to ACK timing. */ 998 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 999 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1000 1001 /* Set up the MMI read/write addresses for the BBP. 1002 * 1003 * TBD find out the Marvel settings. 1004 */ 1005 switch (sc->sc_bbptype) { 1006 case ATW_BBPTYPE_INTERSIL: 1007 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1008 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1009 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1010 break; 1011 case ATW_BBPTYPE_MARVEL: 1012 break; 1013 case ATW_BBPTYPE_RFMD: 1014 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1015 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1016 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1017 default: 1018 break; 1019 } 1020 1021 sc->sc_wepctl = 0; 1022 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1023 1024 if ((error = atw_rf3000_init(sc)) != 0) 1025 goto out; 1026 1027 /* 1028 * Initialize the PCI Access Register. 1029 */ 1030 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1031 1032 /* 1033 * If we're allowed to do so, use Memory Read Line 1034 * and Memory Read Multiple. 1035 * 1036 * XXX Should we use Memory Write and Invalidate? 1037 */ 1038 if (sc->sc_flags & ATWF_MRL) 1039 sc->sc_busmode |= ATW_PAR_MRLE; 1040 if (sc->sc_flags & ATWF_MRM) 1041 sc->sc_busmode |= ATW_PAR_MRME; 1042 if (sc->sc_flags & ATWF_MWI) 1043 sc->sc_busmode |= ATW_PAR_MWIE; 1044 if (sc->sc_maxburst == 0) 1045 sc->sc_maxburst = 8; /* ADM8211 default */ 1046 1047 switch (sc->sc_cacheline) { 1048 default: 1049 /* Use burst length. */ 1050 break; 1051 case 8: 1052 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1053 break; 1054 case 16: 1055 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1056 break; 1057 case 32: 1058 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1059 break; 1060 } 1061 switch (sc->sc_maxburst) { 1062 case 1: 1063 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1064 break; 1065 case 2: 1066 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1067 break; 1068 case 4: 1069 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1070 break; 1071 case 8: 1072 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1073 break; 1074 case 16: 1075 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1076 break; 1077 case 32: 1078 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1079 break; 1080 default: 1081 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1082 break; 1083 } 1084 1085 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1086 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1087 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1088 1089 /* 1090 * Initialize the OPMODE register. We don't write it until 1091 * we're ready to begin the transmit and receive processes. 1092 */ 1093 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1094 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1095 1096 /* 1097 * Initialize the transmit descriptor ring. 1098 */ 1099 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1100 for (i = 0; i < ATW_NTXDESC; i++) { 1101 /* no transmit chaining */ 1102 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1103 sc->sc_txdescs[i].at_buf2 = 1104 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1105 } 1106 /* use ring mode */ 1107 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1108 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1109 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1110 sc->sc_txfree = ATW_NTXDESC; 1111 sc->sc_txnext = 0; 1112 1113 /* 1114 * Initialize the transmit job descriptors. 1115 */ 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1119 txs = &sc->sc_txsoft[i]; 1120 txs->txs_mbuf = NULL; 1121 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1122 } 1123 1124 /* 1125 * Initialize the receive descriptor and receive job 1126 * descriptor rings. 1127 */ 1128 for (i = 0; i < ATW_NRXDESC; i++) { 1129 rxs = &sc->sc_rxsoft[i]; 1130 if (rxs->rxs_mbuf == NULL) { 1131 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1132 printf("%s: unable to allocate or map rx " 1133 "buffer %d, error = %d\n", 1134 sc->sc_dev.dv_xname, i, error); 1135 /* 1136 * XXX Should attempt to run with fewer receive 1137 * XXX buffers instead of just failing. 1138 */ 1139 atw_rxdrain(sc); 1140 goto out; 1141 } 1142 } else 1143 ATW_INIT_RXDESC(sc, i); 1144 } 1145 sc->sc_rxptr = 0; 1146 1147 /* disable all wake-up events */ 1148 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1149 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1150 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1151 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1152 1153 /* ack all wake-up events */ 1154 ATW_SET(sc, ATW_WCSR, 0); 1155 1156 /* 1157 * Initialize the interrupt mask and enable interrupts. 1158 */ 1159 /* normal interrupts */ 1160 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1161 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1162 1163 /* abnormal interrupts */ 1164 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1165 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1166 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1167 1168 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1169 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1170 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1171 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1172 ATW_INTR_TRT; 1173 1174 sc->sc_linkint_mask &= sc->sc_inten; 1175 sc->sc_rxint_mask &= sc->sc_inten; 1176 sc->sc_txint_mask &= sc->sc_inten; 1177 1178 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1179 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1180 if (sc->sc_intr_ack != NULL) 1181 (*sc->sc_intr_ack)(sc); 1182 1183 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1184 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1185 1186 /* 1187 * Give the transmit and receive rings to the ADM8211. 1188 */ 1189 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1190 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1191 1192 /* common 802.11 configuration */ 1193 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1194 switch (ic->ic_opmode) { 1195 case IEEE80211_M_STA: 1196 break; 1197 case IEEE80211_M_AHDEMO: /* XXX */ 1198 case IEEE80211_M_IBSS: 1199 ic->ic_flags |= IEEE80211_F_IBSSON; 1200 /*FALLTHROUGH*/ 1201 case IEEE80211_M_HOSTAP: /* XXX */ 1202 break; 1203 case IEEE80211_M_MONITOR: /* XXX */ 1204 break; 1205 } 1206 1207 atw_start_beacon(sc, 0); 1208 1209 switch (ic->ic_opmode) { 1210 case IEEE80211_M_AHDEMO: 1211 case IEEE80211_M_HOSTAP: 1212 ic->ic_bss->ni_intval = ic->ic_lintval; 1213 ic->ic_bss->ni_rssi = 0; 1214 ic->ic_bss->ni_rstamp = 0; 1215 break; 1216 default: /* XXX */ 1217 break; 1218 } 1219 1220 atw_write_ssid(sc); 1221 atw_write_sup_rates(sc); 1222 if (ic->ic_caps & IEEE80211_C_WEP) 1223 atw_write_wep(sc); 1224 1225 /* 1226 * Set the receive filter. This will start the transmit and 1227 * receive processes. 1228 */ 1229 atw_filter_setup(sc); 1230 1231 /* 1232 * Start the receive process. 1233 */ 1234 ATW_WRITE(sc, ATW_RDR, 0x1); 1235 1236 /* 1237 * Note that the interface is now running. 1238 */ 1239 ifp->if_flags |= IFF_RUNNING; 1240 ifp->if_flags &= ~IFF_OACTIVE; 1241 ic->ic_state = IEEE80211_S_INIT; 1242 1243 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1244 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1245 else 1246 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1247 out: 1248 if (error) { 1249 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1250 ifp->if_timer = 0; 1251 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1252 } 1253 #ifdef ATW_DEBUG 1254 atw_print_regs(sc, "end of init"); 1255 #endif /* ATW_DEBUG */ 1256 1257 return (error); 1258 } 1259 1260 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1261 * 0: MAC control of RF3000/Si4126. 1262 * 1263 * Applies power, or selects RF front-end? Sets reset condition. 1264 * 1265 * TBD support non-RFMD BBP, non-SiLabs synth. 1266 */ 1267 static void 1268 atw_rfio_enable(struct atw_softc *sc, int enable) 1269 { 1270 if (enable) { 1271 ATW_WRITE(sc, ATW_SYNRF, 1272 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1273 DELAY(atw_rfio_enable_delay); 1274 } else { 1275 ATW_WRITE(sc, ATW_SYNRF, 0); 1276 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1277 } 1278 } 1279 1280 static int 1281 atw_tune(struct atw_softc *sc) 1282 { 1283 int rc; 1284 u_int32_t reg; 1285 int chan; 1286 struct ieee80211com *ic = &sc->sc_ic; 1287 1288 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1289 if (chan == IEEE80211_CHAN_ANY) 1290 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1291 1292 if (chan == sc->sc_cur_chan) 1293 return 0; 1294 1295 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1296 sc->sc_cur_chan, chan)); 1297 1298 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1299 1300 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1301 (rc = atw_rf3000_tune(sc, chan)) != 0) 1302 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1303 chan); 1304 1305 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1306 ATW_WRITE(sc, ATW_CAP0, 1307 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1308 1309 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1310 1311 if (rc == 0) 1312 sc->sc_cur_chan = chan; 1313 1314 return rc; 1315 } 1316 1317 #ifdef ATW_DEBUG 1318 static void 1319 atw_si4126_print(struct atw_softc *sc) 1320 { 1321 struct ifnet *ifp = &sc->sc_ic.ic_if; 1322 u_int addr, val; 1323 1324 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1325 return; 1326 1327 for (addr = 0; addr <= 8; addr++) { 1328 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1329 if (atw_si4126_read(sc, addr, &val) == 0) { 1330 printf("<unknown> (quitting print-out)\n"); 1331 break; 1332 } 1333 printf("%05x\n", val); 1334 } 1335 } 1336 #endif /* ATW_DEBUG */ 1337 1338 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1339 * 1340 * The RF/IF synthesizer produces two reference frequencies for 1341 * the RF2948B transceiver. The first frequency the RF2948B requires 1342 * is two times the so-called "intermediate frequency" (IF). Since 1343 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1344 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1345 * frequency required by the transceiver is the radio frequency 1346 * (RF). This is a superheterodyne transceiver; for f(chan) the 1347 * center frequency of the channel we are tuning, RF = f(chan) - 1348 * IF. 1349 * 1350 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1351 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1352 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1353 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1354 */ 1355 static int 1356 atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1357 { 1358 int rc = 0; 1359 u_int mhz; 1360 u_int R; 1361 u_int32_t reg; 1362 u_int16_t gain; 1363 1364 #ifdef ATW_DEBUG 1365 atw_si4126_print(sc); 1366 #endif /* ATW_DEBUG */ 1367 1368 if (chan == 14) 1369 mhz = 2484; 1370 else 1371 mhz = 2412 + 5 * (chan - 1); 1372 1373 /* Tune IF to 748MHz to suit the IF LO input of the 1374 * RF2494B, which is 2 x IF. No need to set an IF divider 1375 * because an IF in 526MHz - 952MHz is allowed. 1376 * 1377 * XIN is 44.000MHz, so divide it by two to get allowable 1378 * range of 2-25MHz. SiLabs tells me that this is not 1379 * strictly necessary. 1380 */ 1381 1382 R = 44; 1383 1384 atw_rfio_enable(sc, 1); 1385 1386 /* Power-up RF, IF synthesizers. */ 1387 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1388 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1389 goto out; 1390 1391 /* If RF2 N > 2047, then set KP2 to 1. */ 1392 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1393 1394 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1395 goto out; 1396 1397 /* set LPWR, too? */ 1398 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1399 SI4126_MAIN_XINDIV2)) != 0) 1400 goto out; 1401 1402 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1403 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1404 */ 1405 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1406 goto out; 1407 1408 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1409 goto out; 1410 1411 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1412 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1413 * which has no RF1! 1414 */ 1415 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1416 goto out; 1417 1418 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1419 goto out; 1420 1421 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1422 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1423 * Now let's multiply it to mhz. So mhz - IF = N. 1424 */ 1425 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1426 goto out; 1427 1428 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1429 goto out; 1430 1431 /* wait 100us from power-up for RF, IF to settle */ 1432 DELAY(100); 1433 1434 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1435 /* XXX there is a binary driver which sends 1436 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1437 * that this enables the Si4126 by raising its PWDN#, but I 1438 * think that it actually sets the Prism RF front-end 1439 * to a special mode for channel 14. 1440 */ 1441 reg = ATW_READ(sc, ATW_GPIO); 1442 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1443 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1444 ATW_WRITE(sc, ATW_GPIO, reg); 1445 } 1446 1447 #ifdef ATW_DEBUG 1448 atw_si4126_print(sc); 1449 #endif /* ATW_DEBUG */ 1450 1451 out: 1452 atw_rfio_enable(sc, 0); 1453 1454 return rc; 1455 } 1456 1457 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1458 * diversity. 1459 * 1460 * Call this w/ Tx/Rx suspended. 1461 */ 1462 static int 1463 atw_rf3000_init(struct atw_softc *sc) 1464 { 1465 int rc = 0; 1466 1467 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1468 1469 atw_rfio_enable(sc, 1); 1470 1471 /* enable diversity */ 1472 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1473 1474 if (rc != 0) 1475 goto out; 1476 1477 /* sensible setting from a binary-only driver */ 1478 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1479 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1480 1481 if (rc != 0) 1482 goto out; 1483 1484 /* magic from a binary-only driver */ 1485 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1486 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1487 1488 if (rc != 0) 1489 goto out; 1490 1491 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1492 1493 if (rc != 0) 1494 goto out; 1495 1496 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1497 1498 if (rc != 0) 1499 goto out; 1500 1501 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1502 1503 if (rc != 0) 1504 goto out; 1505 1506 /* CCA is acquisition sensitive */ 1507 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1508 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1509 1510 if (rc != 0) 1511 goto out; 1512 1513 out: 1514 atw_rfio_enable(sc, 0); 1515 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1516 return rc; 1517 } 1518 1519 #ifdef ATW_DEBUG 1520 static void 1521 atw_rf3000_print(struct atw_softc *sc) 1522 { 1523 struct ifnet *ifp = &sc->sc_ic.ic_if; 1524 u_int addr, val; 1525 1526 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1527 return; 1528 1529 for (addr = 0x01; addr <= 0x15; addr++) { 1530 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1531 if (atw_rf3000_read(sc, addr, &val) != 0) { 1532 printf("<unknown> (quitting print-out)\n"); 1533 break; 1534 } 1535 printf("%08x\n", val); 1536 } 1537 } 1538 #endif /* ATW_DEBUG */ 1539 1540 /* Set the power settings on the BBP for channel `chan'. */ 1541 static int 1542 atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1543 { 1544 int rc = 0; 1545 u_int32_t reg; 1546 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1547 1548 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1549 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1550 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1551 1552 /* odd channels: LSB, even channels: MSB */ 1553 if (chan % 2 == 1) { 1554 txpower &= 0xFF; 1555 lpf_cutoff &= 0xFF; 1556 lna_gs_thresh &= 0xFF; 1557 } else { 1558 txpower >>= 8; 1559 lpf_cutoff >>= 8; 1560 lna_gs_thresh >>= 8; 1561 } 1562 1563 #ifdef ATW_DEBUG 1564 atw_rf3000_print(sc); 1565 #endif /* ATW_DEBUG */ 1566 1567 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1568 "lna_gs_thresh %02x\n", 1569 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1570 1571 atw_rfio_enable(sc, 1); 1572 1573 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1574 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1575 goto out; 1576 1577 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1578 goto out; 1579 1580 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1581 goto out; 1582 1583 /* from a binary-only driver. */ 1584 reg = ATW_READ(sc, ATW_PLCPHD); 1585 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1586 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1587 ATW_PLCPHD_SERVICE_MASK); 1588 ATW_WRITE(sc, ATW_PLCPHD, reg); 1589 1590 #ifdef ATW_DEBUG 1591 atw_rf3000_print(sc); 1592 #endif /* ATW_DEBUG */ 1593 1594 out: 1595 atw_rfio_enable(sc, 0); 1596 1597 return rc; 1598 } 1599 1600 /* Write a register on the RF3000 baseband processor using the 1601 * registers provided by the ADM8211 for this purpose. 1602 * 1603 * Return 0 on success. 1604 */ 1605 static int 1606 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1607 { 1608 u_int32_t reg; 1609 int i; 1610 1611 for (i = 1000; --i >= 0; ) { 1612 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1613 break; 1614 DELAY(100); 1615 } 1616 1617 if (i < 0) { 1618 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1619 return ETIMEDOUT; 1620 } 1621 1622 reg = sc->sc_bbpctl_wr | 1623 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1624 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1625 1626 ATW_WRITE(sc, ATW_BBPCTL, reg); 1627 1628 for (i = 1000; --i >= 0; ) { 1629 DELAY(100); 1630 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1631 break; 1632 } 1633 1634 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1635 1636 if (i < 0) { 1637 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1638 return ETIMEDOUT; 1639 } 1640 return 0; 1641 } 1642 1643 /* Read a register on the RF3000 baseband processor using the registers 1644 * the ADM8211 provides for this purpose. 1645 * 1646 * The 7-bit register address is addr. Record the 8-bit data in the register 1647 * in *val. 1648 * 1649 * Return 0 on success. 1650 * 1651 * XXX This does not seem to work. The ADM8211 must require more or 1652 * different magic to read the chip than to write it. Possibly some 1653 * of the magic I have derived from a binary-only driver concerns 1654 * the "chip address" (see the RF3000 manual). 1655 */ 1656 #ifdef ATW_DEBUG 1657 static int 1658 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1659 { 1660 u_int32_t reg; 1661 int i; 1662 1663 for (i = 1000; --i >= 0; ) { 1664 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1665 break; 1666 DELAY(100); 1667 } 1668 1669 if (i < 0) { 1670 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1671 sc->sc_dev.dv_xname); 1672 return ETIMEDOUT; 1673 } 1674 1675 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1676 1677 ATW_WRITE(sc, ATW_BBPCTL, reg); 1678 1679 for (i = 1000; --i >= 0; ) { 1680 DELAY(100); 1681 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1682 break; 1683 } 1684 1685 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1686 1687 if (i < 0) { 1688 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1689 sc->sc_dev.dv_xname, reg); 1690 return ETIMEDOUT; 1691 } 1692 if (val != NULL) 1693 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1694 return 0; 1695 } 1696 #endif /* ATW_DEBUG */ 1697 1698 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1699 * provided by the ADM8211 for that purpose. 1700 * 1701 * val is 18 bits of data, and val is the 4-bit address of the register. 1702 * 1703 * Return 0 on success. 1704 */ 1705 static int 1706 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1707 { 1708 u_int32_t bits, reg; 1709 int i; 1710 1711 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1712 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1713 1714 for (i = 1000; --i >= 0; ) { 1715 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1716 break; 1717 DELAY(100); 1718 } 1719 1720 if (i < 0) { 1721 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1722 sc->sc_dev.dv_xname); 1723 return ETIMEDOUT; 1724 } 1725 1726 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1727 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1728 1729 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1730 1731 ATW_WRITE(sc, ATW_SYNCTL, reg); 1732 1733 for (i = 1000; --i >= 0; ) { 1734 DELAY(100); 1735 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1736 break; 1737 } 1738 1739 /* restore to acceptable starting condition */ 1740 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1741 1742 if (i < 0) { 1743 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1744 sc->sc_dev.dv_xname, reg); 1745 return ETIMEDOUT; 1746 } 1747 return 0; 1748 } 1749 1750 /* Read 18-bit data from the 4-bit address addr in Si4126 1751 * RF synthesizer and write the data to *val. Return 0 on success. 1752 * 1753 * XXX This does not seem to work. The ADM8211 must require more or 1754 * different magic to read the chip than to write it. 1755 */ 1756 #ifdef ATW_DEBUG 1757 static int 1758 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1759 { 1760 u_int32_t reg; 1761 int i; 1762 1763 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1764 1765 for (i = 1000; --i >= 0; ) { 1766 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1767 break; 1768 DELAY(100); 1769 } 1770 1771 if (i < 0) { 1772 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1773 sc->sc_dev.dv_xname); 1774 return ETIMEDOUT; 1775 } 1776 1777 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1778 1779 ATW_WRITE(sc, ATW_SYNCTL, reg); 1780 1781 for (i = 1000; --i >= 0; ) { 1782 DELAY(100); 1783 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1784 break; 1785 } 1786 1787 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1788 1789 if (i < 0) { 1790 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1791 sc->sc_dev.dv_xname, reg); 1792 return ETIMEDOUT; 1793 } 1794 if (val != NULL) 1795 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1796 ATW_SYNCTL_DATA_MASK); 1797 return 0; 1798 } 1799 #endif /* ATW_DEBUG */ 1800 1801 /* XXX is the endianness correct? test. */ 1802 #define atw_calchash(addr) \ 1803 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1804 1805 /* 1806 * atw_filter_setup: 1807 * 1808 * Set the ADM8211's receive filter. 1809 */ 1810 static void 1811 atw_filter_setup(struct atw_softc *sc) 1812 { 1813 struct ieee80211com *ic = &sc->sc_ic; 1814 struct ethercom *ec = &ic->ic_ec; 1815 struct ifnet *ifp = &sc->sc_ic.ic_if; 1816 int hash; 1817 u_int32_t hashes[2] = { 0, 0 }; 1818 struct ether_multi *enm; 1819 struct ether_multistep step; 1820 1821 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1822 sc->sc_dev.dv_xname, sc->sc_flags)); 1823 1824 /* 1825 * If we're running, idle the receive engine. If we're NOT running, 1826 * we're being called from atw_init(), and our writing ATW_NAR will 1827 * start the transmit and receive processes in motion. 1828 */ 1829 if (ifp->if_flags & IFF_RUNNING) 1830 atw_idle(sc, ATW_NAR_SR); 1831 1832 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1833 1834 ifp->if_flags &= ~IFF_ALLMULTI; 1835 1836 if (ifp->if_flags & IFF_PROMISC) { 1837 sc->sc_opmode |= ATW_NAR_PR; 1838 allmulti: 1839 ifp->if_flags |= IFF_ALLMULTI; 1840 goto setit; 1841 } 1842 1843 /* 1844 * Program the 64-bit multicast hash filter. 1845 */ 1846 ETHER_FIRST_MULTI(step, ec, enm); 1847 while (enm != NULL) { 1848 /* XXX */ 1849 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1850 ETHER_ADDR_LEN) != 0) 1851 goto allmulti; 1852 1853 hash = atw_calchash(enm->enm_addrlo); 1854 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1855 ETHER_NEXT_MULTI(step, enm); 1856 } 1857 1858 if (ifp->if_flags & IFF_BROADCAST) { 1859 hash = atw_calchash(etherbroadcastaddr); 1860 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1861 } 1862 1863 /* all bits set => hash is useless */ 1864 if (~(hashes[0] & hashes[1]) == 0) 1865 goto allmulti; 1866 1867 setit: 1868 if (ifp->if_flags & IFF_ALLMULTI) 1869 sc->sc_opmode |= ATW_NAR_MM; 1870 1871 /* XXX in scan mode, do not filter packets. maybe this is 1872 * unnecessary. 1873 */ 1874 if (ic->ic_state == IEEE80211_S_SCAN) 1875 sc->sc_opmode |= ATW_NAR_PR; 1876 1877 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1878 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1879 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1880 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1881 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1882 1883 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1884 } 1885 1886 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1887 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1888 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1889 * no beacon with the preferred BSSID and SSID in the number of 1890 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1891 */ 1892 static void 1893 atw_write_bssid(struct atw_softc *sc) 1894 { 1895 struct ieee80211com *ic = &sc->sc_ic; 1896 u_int8_t *bssid; 1897 1898 bssid = ic->ic_bss->ni_bssid; 1899 1900 ATW_WRITE(sc, ATW_ABDA1, 1901 (ATW_READ(sc, ATW_ABDA1) & 1902 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1903 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1904 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1905 1906 ATW_WRITE(sc, ATW_BSSID0, 1907 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1908 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1909 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1910 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1911 1912 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1913 ether_sprintf(sc->sc_bssid))); 1914 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1915 1916 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1917 } 1918 1919 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1920 * 16-bit word. 1921 */ 1922 static void 1923 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1924 { 1925 u_int i; 1926 u_int8_t *ptr; 1927 1928 memcpy(&sc->sc_sram[ofs], buf, buflen); 1929 1930 if (ofs % 2 != 0) { 1931 ofs--; 1932 buflen++; 1933 } 1934 1935 if (buflen % 2 != 0) 1936 buflen++; 1937 1938 assert(buflen + ofs <= ATW_SRAM_SIZE); 1939 1940 ptr = &sc->sc_sram[ofs]; 1941 1942 for (i = 0; i < buflen; i += 2) { 1943 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1944 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1945 DELAY(atw_writewep_delay); 1946 1947 ATW_WRITE(sc, ATW_WESK, 1948 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1949 DELAY(atw_writewep_delay); 1950 } 1951 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1952 1953 if (sc->sc_if.if_flags & IFF_DEBUG) { 1954 int n_octets = 0; 1955 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1956 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1957 for (i = 0; i < buflen; i++) { 1958 printf(" %02x", ptr[i]); 1959 if (++n_octets % 24 == 0) 1960 printf("\n"); 1961 } 1962 if (n_octets % 24 != 0) 1963 printf("\n"); 1964 } 1965 } 1966 1967 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 1968 static void 1969 atw_write_wep(struct atw_softc *sc) 1970 { 1971 struct ieee80211com *ic = &sc->sc_ic; 1972 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 1973 u_int8_t buf[IEEE80211_WEP_NKID] 1974 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 1975 u_int32_t reg; 1976 int i; 1977 1978 sc->sc_wepctl = 0; 1979 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 1980 1981 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 1982 return; 1983 1984 memset(&buf[0][0], 0, sizeof(buf)); 1985 1986 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1987 if (ic->ic_nw_keys[i].wk_len > 5) { 1988 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 1989 } else if (ic->ic_nw_keys[i].wk_len != 0) { 1990 buf[i][1] = ATW_WEP_ENABLED; 1991 } else { 1992 buf[i][1] = 0; 1993 continue; 1994 } 1995 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 1996 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 1997 ic->ic_nw_keys[i].wk_len - 1); 1998 } 1999 2000 reg = ATW_READ(sc, ATW_MACTEST); 2001 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2002 reg &= ~ATW_MACTEST_KEYID_MASK; 2003 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2004 ATW_WRITE(sc, ATW_MACTEST, reg); 2005 2006 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2007 * throughout.) 2008 */ 2009 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2010 if (sc->sc_if.if_flags & IFF_LINK2) 2011 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2012 2013 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2014 sizeof(buf)); 2015 } 2016 2017 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2018 2019 static void 2020 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2021 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2022 { 2023 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2024 2025 switch (subtype) { 2026 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2027 /* do nothing: hardware answers probe request */ 2028 break; 2029 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2030 case IEEE80211_FC0_SUBTYPE_BEACON: 2031 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2032 break; 2033 default: 2034 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2035 break; 2036 } 2037 return; 2038 } 2039 2040 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2041 * of IBSSs with like SSID/channel but different BSSID. It joins the 2042 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2043 * convention. Possibly the ADMtek chip does this for us; I will have 2044 * to test to find out. 2045 * 2046 * XXX we should add the duration field of the received beacon to 2047 * the TSF time it contains before comparing it with the ADM8211's 2048 * TSF. 2049 */ 2050 static void 2051 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2052 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2053 { 2054 struct atw_softc *sc; 2055 struct ieee80211_frame *wh; 2056 u_int64_t tsft, bcn_tsft; 2057 u_int32_t tsftl, tsfth; 2058 int do_print = 0; 2059 2060 sc = (struct atw_softc*)ic->ic_if.if_softc; 2061 2062 if (ic->ic_if.if_flags & IFF_DEBUG) 2063 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2064 ? 1 : ratecheck(&sc->sc_last_beacon, 2065 &atw_beacon_mininterval); 2066 2067 wh = mtod(m0, struct ieee80211_frame *); 2068 2069 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2070 2071 if (ic->ic_state != IEEE80211_S_RUN) { 2072 if (do_print) 2073 printf("%s: atw_recv_beacon: not running\n", 2074 sc->sc_dev.dv_xname); 2075 return; 2076 } 2077 2078 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2079 ic->ic_bss->ni_chan)) == NULL) { 2080 if (do_print) 2081 printf("%s: atw_recv_beacon: no node %s\n", 2082 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2083 return; 2084 } 2085 2086 if (ieee80211_match_bss(ic, ni) != 0) { 2087 if (do_print) 2088 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2089 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2090 return; 2091 } 2092 2093 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2094 return; 2095 2096 if (do_print) 2097 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2098 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2099 2100 if (ic->ic_opmode != IEEE80211_M_IBSS) 2101 return; 2102 2103 /* If we read TSFTL right before rollover, we read a TSF timer 2104 * that is too high rather than too low. This prevents a spurious 2105 * synchronization down the line, however, our IBSS could suffer 2106 * from a creeping TSF.... 2107 */ 2108 tsftl = ATW_READ(sc, ATW_TSFTL); 2109 tsfth = ATW_READ(sc, ATW_TSFTH); 2110 2111 tsft = (u_int64_t)tsfth << 32 | tsftl; 2112 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2113 2114 if (do_print) 2115 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2116 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2117 2118 /* we are faster, let the other guy catch up */ 2119 if (bcn_tsft < tsft) 2120 return; 2121 2122 if (do_print) 2123 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2124 ether_sprintf(wh->i_addr2)); 2125 2126 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2127 2128 #if 0 2129 atw_tsf(sc); 2130 #endif 2131 2132 /* negotiate rates with new IBSS */ 2133 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2134 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2135 if (ni->ni_rates.rs_nrates == 0) { 2136 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2137 ether_sprintf(ni->ni_bssid)); 2138 return; 2139 } 2140 2141 if (do_print) { 2142 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2143 ether_sprintf(ic->ic_bss->ni_bssid)); 2144 printf("%s ", ether_sprintf(ni->ni_bssid)); 2145 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2146 } 2147 2148 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2149 2150 atw_write_bssid(sc); 2151 atw_start_beacon(sc, 1); 2152 } 2153 2154 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2155 * In ad hoc mode, the SSID is written to the beacons sent by the 2156 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2157 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2158 * indications. 2159 */ 2160 static void 2161 atw_write_ssid(struct atw_softc *sc) 2162 { 2163 struct ieee80211com *ic = &sc->sc_ic; 2164 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2165 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2166 2167 memset(buf, 0, sizeof(buf)); 2168 buf[0] = ic->ic_bss->ni_esslen; 2169 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2170 2171 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2172 } 2173 2174 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2175 * In ad hoc mode, the supported rates are written to beacons sent by the 2176 * ADM8211. 2177 */ 2178 static void 2179 atw_write_sup_rates(struct atw_softc *sc) 2180 { 2181 struct ieee80211com *ic = &sc->sc_ic; 2182 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2183 * supported rates 2184 */ 2185 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2186 2187 memset(buf, 0, sizeof(buf)); 2188 2189 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2190 2191 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2192 ic->ic_bss->ni_rates.rs_nrates); 2193 2194 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2195 } 2196 2197 /* Start/stop sending beacons. */ 2198 void 2199 atw_start_beacon(struct atw_softc *sc, int start) 2200 { 2201 struct ieee80211com *ic = &sc->sc_ic; 2202 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2203 2204 if (ATW_IS_ENABLED(sc) == 0) 2205 return; 2206 2207 len = capinfo = 0; 2208 2209 /* start beacons */ 2210 len = sizeof(struct ieee80211_frame) + 2211 8 /* timestamp */ + 2 /* beacon interval */ + 2212 2 /* capability info */ + 2213 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2214 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2215 3 /* DS parameters */ + 2216 IEEE80211_CRC_LEN; 2217 2218 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2219 2220 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2221 2222 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2223 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2224 2225 if (!start) 2226 return; 2227 2228 /* TBD use ni_capinfo */ 2229 2230 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2231 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2232 if (ic->ic_flags & IEEE80211_F_WEPON) 2233 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2234 2235 switch (ic->ic_opmode) { 2236 case IEEE80211_M_IBSS: 2237 len += 4; /* IBSS parameters */ 2238 capinfo |= IEEE80211_CAPINFO_IBSS; 2239 break; 2240 case IEEE80211_M_HOSTAP: 2241 /* XXX 6-byte minimum TIM */ 2242 len += atw_beacon_len_adjust; 2243 capinfo |= IEEE80211_CAPINFO_ESS; 2244 break; 2245 default: 2246 return; 2247 } 2248 2249 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2250 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2251 2252 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2253 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2254 2255 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2256 sc->sc_dev.dv_xname, reg_bcnt)); 2257 2258 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2259 sc->sc_dev.dv_xname, reg_cap1)); 2260 } 2261 2262 /* First beacon was sent at time 0 microseconds, current time is 2263 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2264 * microseconds. Return the expected time in microseconds for the 2265 * beacon after next. 2266 */ 2267 static __inline u_int64_t 2268 atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2269 { 2270 return tsft + (tbtt - tsft % tbtt); 2271 } 2272 2273 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2274 * the ieee80211com. 2275 * 2276 * Predict the next target beacon transmission time (TBTT) and 2277 * write it to the ADM8211. 2278 */ 2279 static void 2280 atw_tsf(struct atw_softc *sc) 2281 { 2282 #define TBTTOFS 20 /* TU */ 2283 2284 struct ieee80211com *ic = &sc->sc_ic; 2285 u_int64_t tsft, tbtt; 2286 2287 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2288 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2289 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2290 tsft = ATW_READ(sc, ATW_TSFTH); 2291 tsft <<= 32; 2292 tsft |= ATW_READ(sc, ATW_TSFTL); 2293 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2294 } else 2295 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2296 2297 tbtt = atw_predict_beacon(tsft, 2298 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2299 2300 /* skip one more beacon so that the TBTT cannot pass before 2301 * we've programmed it, and also so that we can subtract a 2302 * few TU so that we wake a little before TBTT. 2303 */ 2304 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2305 2306 /* wake up a little early */ 2307 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2308 2309 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2310 sc->sc_dev.dv_xname, tsft, tbtt)); 2311 2312 ATW_WRITE(sc, ATW_TOFS1, 2313 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2314 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2315 LSHIFT( 2316 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2317 ATW_TOFS1_TBTTPRE_MASK)); 2318 #undef TBTTOFS 2319 } 2320 2321 static void 2322 atw_next_scan(void *arg) 2323 { 2324 struct atw_softc *sc = arg; 2325 struct ieee80211com *ic = &sc->sc_ic; 2326 struct ifnet *ifp = &ic->ic_if; 2327 int s; 2328 2329 /* don't call atw_start w/o network interrupts blocked */ 2330 s = splnet(); 2331 if (ic->ic_state == IEEE80211_S_SCAN) 2332 ieee80211_next_scan(ifp); 2333 splx(s); 2334 } 2335 2336 /* Synchronize the hardware state with the software state. */ 2337 static int 2338 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2339 { 2340 struct ifnet *ifp = &ic->ic_if; 2341 struct atw_softc *sc = ifp->if_softc; 2342 enum ieee80211_state ostate; 2343 int error; 2344 2345 ostate = ic->ic_state; 2346 2347 if (nstate == IEEE80211_S_INIT) { 2348 callout_stop(&sc->sc_scan_ch); 2349 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2350 atw_start_beacon(sc, 0); 2351 return (*sc->sc_newstate)(ic, nstate, arg); 2352 } 2353 2354 if ((error = atw_tune(sc)) != 0) 2355 return error; 2356 2357 switch (nstate) { 2358 case IEEE80211_S_ASSOC: 2359 break; 2360 case IEEE80211_S_INIT: 2361 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2362 break; 2363 case IEEE80211_S_SCAN: 2364 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2365 atw_next_scan, sc); 2366 2367 break; 2368 case IEEE80211_S_RUN: 2369 if (ic->ic_opmode == IEEE80211_M_STA) 2370 break; 2371 /*FALLTHROUGH*/ 2372 case IEEE80211_S_AUTH: 2373 atw_write_bssid(sc); 2374 atw_write_ssid(sc); 2375 atw_write_sup_rates(sc); 2376 2377 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2378 ic->ic_opmode == IEEE80211_M_MONITOR) 2379 break; 2380 2381 /* set listen interval 2382 * XXX do software units agree w/ hardware? 2383 */ 2384 ATW_WRITE(sc, ATW_BPLI, 2385 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2386 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2387 ATW_BPLI_LI_MASK)); 2388 2389 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2390 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2391 2392 atw_tsf(sc); 2393 break; 2394 } 2395 2396 if (nstate != IEEE80211_S_SCAN) 2397 callout_stop(&sc->sc_scan_ch); 2398 2399 if (nstate == IEEE80211_S_RUN && 2400 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2401 ic->ic_opmode == IEEE80211_M_IBSS)) 2402 atw_start_beacon(sc, 1); 2403 else 2404 atw_start_beacon(sc, 0); 2405 2406 error = (*sc->sc_newstate)(ic, nstate, arg); 2407 2408 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2409 atw_write_bssid(sc); 2410 2411 return error; 2412 } 2413 2414 /* 2415 * atw_add_rxbuf: 2416 * 2417 * Add a receive buffer to the indicated descriptor. 2418 */ 2419 int 2420 atw_add_rxbuf(struct atw_softc *sc, int idx) 2421 { 2422 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2423 struct mbuf *m; 2424 int error; 2425 2426 MGETHDR(m, M_DONTWAIT, MT_DATA); 2427 if (m == NULL) 2428 return (ENOBUFS); 2429 2430 MCLGET(m, M_DONTWAIT); 2431 if ((m->m_flags & M_EXT) == 0) { 2432 m_freem(m); 2433 return (ENOBUFS); 2434 } 2435 2436 if (rxs->rxs_mbuf != NULL) 2437 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2438 2439 rxs->rxs_mbuf = m; 2440 2441 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2442 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2443 BUS_DMA_READ|BUS_DMA_NOWAIT); 2444 if (error) { 2445 printf("%s: can't load rx DMA map %d, error = %d\n", 2446 sc->sc_dev.dv_xname, idx, error); 2447 panic("atw_add_rxbuf"); /* XXX */ 2448 } 2449 2450 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2451 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2452 2453 ATW_INIT_RXDESC(sc, idx); 2454 2455 return (0); 2456 } 2457 2458 /* 2459 * Release any queued transmit buffers. 2460 */ 2461 void 2462 atw_txdrain(struct atw_softc *sc) 2463 { 2464 struct atw_txsoft *txs; 2465 2466 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2467 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2468 if (txs->txs_mbuf != NULL) { 2469 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2470 m_freem(txs->txs_mbuf); 2471 txs->txs_mbuf = NULL; 2472 } 2473 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2474 } 2475 sc->sc_tx_timer = 0; 2476 } 2477 2478 /* 2479 * atw_stop: [ ifnet interface function ] 2480 * 2481 * Stop transmission on the interface. 2482 */ 2483 void 2484 atw_stop(struct ifnet *ifp, int disable) 2485 { 2486 struct atw_softc *sc = ifp->if_softc; 2487 struct ieee80211com *ic = &sc->sc_ic; 2488 2489 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2490 2491 /* Disable interrupts. */ 2492 ATW_WRITE(sc, ATW_IER, 0); 2493 2494 /* Stop the transmit and receive processes. */ 2495 sc->sc_opmode = 0; 2496 ATW_WRITE(sc, ATW_NAR, 0); 2497 DELAY(20 * 1000); 2498 ATW_WRITE(sc, ATW_TDBD, 0); 2499 ATW_WRITE(sc, ATW_TDBP, 0); 2500 ATW_WRITE(sc, ATW_RDB, 0); 2501 2502 atw_txdrain(sc); 2503 2504 if (disable) { 2505 atw_rxdrain(sc); 2506 atw_disable(sc); 2507 } 2508 2509 /* 2510 * Mark the interface down and cancel the watchdog timer. 2511 */ 2512 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2513 ifp->if_timer = 0; 2514 2515 if (!disable) 2516 atw_reset(sc); 2517 } 2518 2519 /* 2520 * atw_rxdrain: 2521 * 2522 * Drain the receive queue. 2523 */ 2524 void 2525 atw_rxdrain(struct atw_softc *sc) 2526 { 2527 struct atw_rxsoft *rxs; 2528 int i; 2529 2530 for (i = 0; i < ATW_NRXDESC; i++) { 2531 rxs = &sc->sc_rxsoft[i]; 2532 if (rxs->rxs_mbuf == NULL) 2533 continue; 2534 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2535 m_freem(rxs->rxs_mbuf); 2536 rxs->rxs_mbuf = NULL; 2537 } 2538 } 2539 2540 /* 2541 * atw_detach: 2542 * 2543 * Detach an ADM8211 interface. 2544 */ 2545 int 2546 atw_detach(struct atw_softc *sc) 2547 { 2548 struct ifnet *ifp = &sc->sc_ic.ic_if; 2549 struct atw_rxsoft *rxs; 2550 struct atw_txsoft *txs; 2551 int i; 2552 2553 /* 2554 * Succeed now if there isn't any work to do. 2555 */ 2556 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2557 return (0); 2558 2559 ieee80211_ifdetach(ifp); 2560 if_detach(ifp); 2561 2562 for (i = 0; i < ATW_NRXDESC; i++) { 2563 rxs = &sc->sc_rxsoft[i]; 2564 if (rxs->rxs_mbuf != NULL) { 2565 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2566 m_freem(rxs->rxs_mbuf); 2567 rxs->rxs_mbuf = NULL; 2568 } 2569 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2570 } 2571 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2572 txs = &sc->sc_txsoft[i]; 2573 if (txs->txs_mbuf != NULL) { 2574 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2575 m_freem(txs->txs_mbuf); 2576 txs->txs_mbuf = NULL; 2577 } 2578 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2579 } 2580 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2581 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2582 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2583 sizeof(struct atw_control_data)); 2584 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2585 2586 shutdownhook_disestablish(sc->sc_sdhook); 2587 powerhook_disestablish(sc->sc_powerhook); 2588 2589 if (sc->sc_srom) 2590 free(sc->sc_srom, M_DEVBUF); 2591 2592 return (0); 2593 } 2594 2595 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2596 void 2597 atw_shutdown(void *arg) 2598 { 2599 struct atw_softc *sc = arg; 2600 2601 atw_stop(&sc->sc_ic.ic_if, 1); 2602 } 2603 2604 int 2605 atw_intr(void *arg) 2606 { 2607 struct atw_softc *sc = arg; 2608 struct ifnet *ifp = &sc->sc_ic.ic_if; 2609 u_int32_t status, rxstatus, txstatus, linkstatus; 2610 int handled = 0, txthresh; 2611 2612 #ifdef DEBUG 2613 if (ATW_IS_ENABLED(sc) == 0) 2614 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2615 #endif 2616 2617 /* 2618 * If the interface isn't running, the interrupt couldn't 2619 * possibly have come from us. 2620 */ 2621 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2622 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2623 return (0); 2624 2625 for (;;) { 2626 status = ATW_READ(sc, ATW_STSR); 2627 2628 if (status) 2629 ATW_WRITE(sc, ATW_STSR, status); 2630 2631 #ifdef ATW_DEBUG 2632 #define PRINTINTR(flag) do { \ 2633 if ((status & flag) != 0) { \ 2634 printf("%s" #flag, delim); \ 2635 delim = ","; \ 2636 } \ 2637 } while (0) 2638 2639 if (atw_debug > 1 && status) { 2640 const char *delim = "<"; 2641 2642 printf("%s: reg[STSR] = %x", 2643 sc->sc_dev.dv_xname, status); 2644 2645 PRINTINTR(ATW_INTR_FBE); 2646 PRINTINTR(ATW_INTR_LINKOFF); 2647 PRINTINTR(ATW_INTR_LINKON); 2648 PRINTINTR(ATW_INTR_RCI); 2649 PRINTINTR(ATW_INTR_RDU); 2650 PRINTINTR(ATW_INTR_REIS); 2651 PRINTINTR(ATW_INTR_RPS); 2652 PRINTINTR(ATW_INTR_TCI); 2653 PRINTINTR(ATW_INTR_TDU); 2654 PRINTINTR(ATW_INTR_TLT); 2655 PRINTINTR(ATW_INTR_TPS); 2656 PRINTINTR(ATW_INTR_TRT); 2657 PRINTINTR(ATW_INTR_TUF); 2658 PRINTINTR(ATW_INTR_BCNTC); 2659 PRINTINTR(ATW_INTR_ATIME); 2660 PRINTINTR(ATW_INTR_TBTT); 2661 PRINTINTR(ATW_INTR_TSCZ); 2662 PRINTINTR(ATW_INTR_TSFTF); 2663 printf(">\n"); 2664 } 2665 #undef PRINTINTR 2666 #endif /* ATW_DEBUG */ 2667 2668 if ((status & sc->sc_inten) == 0) 2669 break; 2670 2671 handled = 1; 2672 2673 rxstatus = status & sc->sc_rxint_mask; 2674 txstatus = status & sc->sc_txint_mask; 2675 linkstatus = status & sc->sc_linkint_mask; 2676 2677 if (linkstatus) { 2678 atw_linkintr(sc, linkstatus); 2679 } 2680 2681 if (rxstatus) { 2682 /* Grab any new packets. */ 2683 atw_rxintr(sc); 2684 2685 if (rxstatus & ATW_INTR_RDU) { 2686 printf("%s: receive ring overrun\n", 2687 sc->sc_dev.dv_xname); 2688 /* Get the receive process going again. */ 2689 ATW_WRITE(sc, ATW_RDR, 0x1); 2690 break; 2691 } 2692 } 2693 2694 if (txstatus) { 2695 /* Sweep up transmit descriptors. */ 2696 atw_txintr(sc); 2697 2698 if (txstatus & ATW_INTR_TLT) 2699 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2700 sc->sc_dev.dv_xname)); 2701 2702 if (txstatus & ATW_INTR_TRT) 2703 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2704 sc->sc_dev.dv_xname)); 2705 2706 /* If Tx under-run, increase our transmit threshold 2707 * if another is available. 2708 */ 2709 txthresh = sc->sc_txthresh + 1; 2710 if ((txstatus & ATW_INTR_TUF) && 2711 sc->sc_txth[txthresh].txth_name != NULL) { 2712 /* Idle the transmit process. */ 2713 atw_idle(sc, ATW_NAR_ST); 2714 2715 sc->sc_txthresh = txthresh; 2716 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2717 sc->sc_opmode |= 2718 sc->sc_txth[txthresh].txth_opmode; 2719 printf("%s: transmit underrun; new " 2720 "threshold: %s\n", sc->sc_dev.dv_xname, 2721 sc->sc_txth[txthresh].txth_name); 2722 2723 /* Set the new threshold and restart 2724 * the transmit process. 2725 */ 2726 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2727 DELAY(20 * 1000); 2728 ATW_WRITE(sc, ATW_RDR, 0x1); 2729 /* XXX Log every Nth underrun from 2730 * XXX now on? 2731 */ 2732 } 2733 } 2734 2735 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2736 if (status & ATW_INTR_TPS) 2737 printf("%s: transmit process stopped\n", 2738 sc->sc_dev.dv_xname); 2739 if (status & ATW_INTR_RPS) 2740 printf("%s: receive process stopped\n", 2741 sc->sc_dev.dv_xname); 2742 (void)atw_init(ifp); 2743 break; 2744 } 2745 2746 if (status & ATW_INTR_FBE) { 2747 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2748 (void)atw_init(ifp); 2749 break; 2750 } 2751 2752 /* 2753 * Not handled: 2754 * 2755 * Transmit buffer unavailable -- normal 2756 * condition, nothing to do, really. 2757 * 2758 * Early receive interrupt -- not available on 2759 * all chips, we just use RI. We also only 2760 * use single-segment receive DMA, so this 2761 * is mostly useless. 2762 * 2763 * TBD others 2764 */ 2765 } 2766 2767 /* Try to get more packets going. */ 2768 atw_start(ifp); 2769 2770 return (handled); 2771 } 2772 2773 /* 2774 * atw_idle: 2775 * 2776 * Cause the transmit and/or receive processes to go idle. 2777 * 2778 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2779 * process in STSR if I clear SR or ST after the process has already 2780 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2781 * do not seem to be too reliable. Perhaps I have the sense of the 2782 * Rx bits switched with the Tx bits? 2783 */ 2784 void 2785 atw_idle(struct atw_softc *sc, u_int32_t bits) 2786 { 2787 u_int32_t ackmask = 0, opmode, stsr, test0; 2788 int i, s; 2789 2790 s = splnet(); 2791 2792 opmode = sc->sc_opmode & ~bits; 2793 2794 if (bits & ATW_NAR_SR) 2795 ackmask |= ATW_INTR_RPS; 2796 2797 if (bits & ATW_NAR_ST) { 2798 ackmask |= ATW_INTR_TPS; 2799 /* set ATW_NAR_HF to flush TX FIFO. */ 2800 opmode |= ATW_NAR_HF; 2801 } 2802 2803 ATW_WRITE(sc, ATW_NAR, opmode); 2804 DELAY(20 * 1000); 2805 2806 for (i = 0; i < 10; i++) { 2807 stsr = ATW_READ(sc, ATW_STSR); 2808 if ((stsr & ackmask) == ackmask) 2809 break; 2810 DELAY(1000); 2811 } 2812 2813 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2814 2815 if ((stsr & ackmask) == ackmask) 2816 goto out; 2817 2818 test0 = ATW_READ(sc, ATW_TEST0); 2819 2820 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2821 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2822 printf("%s: transmit process not idle [%s]\n", 2823 sc->sc_dev.dv_xname, 2824 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2825 printf("%s: bits %08x test0 %08x stsr %08x\n", 2826 sc->sc_dev.dv_xname, bits, test0, stsr); 2827 } 2828 2829 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2830 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2831 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2832 sc->sc_dev.dv_xname, 2833 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2834 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2835 sc->sc_dev.dv_xname, bits, test0, stsr)); 2836 } 2837 out: 2838 if ((bits & ATW_NAR_ST) != 0) 2839 atw_txdrain(sc); 2840 splx(s); 2841 return; 2842 } 2843 2844 /* 2845 * atw_linkintr: 2846 * 2847 * Helper; handle link-status interrupts. 2848 */ 2849 void 2850 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2851 { 2852 struct ieee80211com *ic = &sc->sc_ic; 2853 2854 if (ic->ic_state != IEEE80211_S_RUN) 2855 return; 2856 2857 if (linkstatus & ATW_INTR_LINKON) { 2858 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2859 sc->sc_rescan_timer = 0; 2860 } else if (linkstatus & ATW_INTR_LINKOFF) { 2861 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2862 if (ic->ic_opmode != IEEE80211_M_STA) 2863 return; 2864 sc->sc_rescan_timer = 3; 2865 ic->ic_if.if_timer = 1; 2866 } 2867 } 2868 2869 /* 2870 * atw_rxintr: 2871 * 2872 * Helper; handle receive interrupts. 2873 */ 2874 void 2875 atw_rxintr(struct atw_softc *sc) 2876 { 2877 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2878 struct ieee80211com *ic = &sc->sc_ic; 2879 struct ieee80211_node *ni; 2880 struct ieee80211_frame *wh; 2881 struct ifnet *ifp = &ic->ic_if; 2882 struct atw_rxsoft *rxs; 2883 struct mbuf *m; 2884 u_int32_t rxstat; 2885 int i, len, rate, rate0; 2886 u_int32_t rssi; 2887 2888 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2889 rxs = &sc->sc_rxsoft[i]; 2890 2891 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2892 2893 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2894 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2895 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2896 2897 if (rxstat & ATW_RXSTAT_OWN) 2898 break; /* We have processed all receive buffers. */ 2899 2900 DPRINTF3(sc, 2901 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2902 sc->sc_dev.dv_xname, 2903 le32toh(sc->sc_rxdescs[i].ar_stat), 2904 le32toh(sc->sc_rxdescs[i].ar_rssi), 2905 le32toh(sc->sc_rxdescs[i].ar_buf1), 2906 le32toh(sc->sc_rxdescs[i].ar_buf2))); 2907 2908 /* 2909 * Make sure the packet fits in one buffer. This should 2910 * always be the case. 2911 */ 2912 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2913 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2914 printf("%s: incoming packet spilled, resetting\n", 2915 sc->sc_dev.dv_xname); 2916 (void)atw_init(ifp); 2917 return; 2918 } 2919 2920 /* 2921 * If an error occurred, update stats, clear the status 2922 * word, and leave the packet buffer in place. It will 2923 * simply be reused the next time the ring comes around. 2924 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2925 * error. 2926 */ 2927 2928 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2929 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2930 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2931 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2932 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2933 ATW_RXSTAT_ICVE)) != 0)) { 2934 #define PRINTERR(bit, str) \ 2935 if (rxstat & (bit)) \ 2936 printf("%s: receive error: %s\n", \ 2937 sc->sc_dev.dv_xname, str) 2938 ifp->if_ierrors++; 2939 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2940 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2941 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2942 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2943 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2944 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2945 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2946 #undef PRINTERR 2947 ATW_INIT_RXDESC(sc, i); 2948 continue; 2949 } 2950 2951 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2952 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2953 2954 /* 2955 * No errors; receive the packet. Note the ADM8211 2956 * includes the CRC in promiscuous mode. 2957 */ 2958 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2959 2960 /* 2961 * Allocate a new mbuf cluster. If that fails, we are 2962 * out of memory, and must drop the packet and recycle 2963 * the buffer that's already attached to this descriptor. 2964 */ 2965 m = rxs->rxs_mbuf; 2966 if (atw_add_rxbuf(sc, i) != 0) { 2967 ifp->if_ierrors++; 2968 ATW_INIT_RXDESC(sc, i); 2969 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2970 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2971 continue; 2972 } 2973 2974 ifp->if_ipackets++; 2975 if (sc->sc_opmode & ATW_NAR_PR) 2976 m->m_flags |= M_HASFCS; 2977 m->m_pkthdr.rcvif = ifp; 2978 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 2979 2980 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 2981 rate = 0; 2982 else 2983 rate = rate_tbl[rate0]; 2984 2985 #if NBPFILTER > 0 2986 /* Pass this up to any BPF listeners. */ 2987 if (sc->sc_radiobpf != NULL) { 2988 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 2989 2990 tap->ar_rate = rate; 2991 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 2992 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 2993 2994 /* TBD verify units are dB */ 2995 tap->ar_antsignal = (int)rssi; 2996 /* TBD tap->ar_flags */ 2997 2998 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 2999 tap->ar_ihdr.it_len, m); 3000 } 3001 #endif /* NPBFILTER > 0 */ 3002 3003 wh = mtod(m, struct ieee80211_frame *); 3004 ni = ieee80211_find_rxnode(ic, wh); 3005 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3006 /* 3007 * The frame may have caused the node to be marked for 3008 * reclamation (e.g. in response to a DEAUTH message) 3009 * so use free_node here instead of unref_node. 3010 */ 3011 if (ni == ic->ic_bss) 3012 ieee80211_unref_node(&ni); 3013 else 3014 ieee80211_free_node(ic, ni); 3015 } 3016 3017 /* Update the receive pointer. */ 3018 sc->sc_rxptr = i; 3019 } 3020 3021 /* 3022 * atw_txintr: 3023 * 3024 * Helper; handle transmit interrupts. 3025 */ 3026 void 3027 atw_txintr(struct atw_softc *sc) 3028 { 3029 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3030 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3031 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3032 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3033 3034 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3035 struct ifnet *ifp = &sc->sc_ic.ic_if; 3036 struct atw_txsoft *txs; 3037 u_int32_t txstat; 3038 3039 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3040 sc->sc_dev.dv_xname, sc->sc_flags)); 3041 3042 ifp->if_flags &= ~IFF_OACTIVE; 3043 3044 /* 3045 * Go through our Tx list and free mbufs for those 3046 * frames that have been transmitted. 3047 */ 3048 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3049 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3050 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3051 3052 #ifdef ATW_DEBUG 3053 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3054 int i; 3055 printf(" txsoft %p transmit chain:\n", txs); 3056 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3057 txs->txs_ndescs - 1, 3058 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3059 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3060 printf(" descriptor %d:\n", i); 3061 printf(" at_status: 0x%08x\n", 3062 le32toh(sc->sc_txdescs[i].at_stat)); 3063 printf(" at_flags: 0x%08x\n", 3064 le32toh(sc->sc_txdescs[i].at_flags)); 3065 printf(" at_buf1: 0x%08x\n", 3066 le32toh(sc->sc_txdescs[i].at_buf1)); 3067 printf(" at_buf2: 0x%08x\n", 3068 le32toh(sc->sc_txdescs[i].at_buf2)); 3069 if (i == txs->txs_lastdesc) 3070 break; 3071 } 3072 } 3073 #endif 3074 3075 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3076 if (txstat & ATW_TXSTAT_OWN) 3077 break; 3078 3079 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3080 3081 sc->sc_txfree += txs->txs_ndescs; 3082 3083 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3084 0, txs->txs_dmamap->dm_mapsize, 3085 BUS_DMASYNC_POSTWRITE); 3086 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3087 m_freem(txs->txs_mbuf); 3088 txs->txs_mbuf = NULL; 3089 3090 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3091 3092 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3093 (txstat & TXSTAT_ERRMASK) != 0) { 3094 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3095 txstat_buf, sizeof(txstat_buf)); 3096 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3097 txstat_buf, 3098 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3099 } 3100 3101 /* 3102 * Check for errors and collisions. 3103 */ 3104 if (txstat & ATW_TXSTAT_TUF) 3105 sc->sc_stats.ts_tx_tuf++; 3106 if (txstat & ATW_TXSTAT_TLT) 3107 sc->sc_stats.ts_tx_tlt++; 3108 if (txstat & ATW_TXSTAT_TRT) 3109 sc->sc_stats.ts_tx_trt++; 3110 if (txstat & ATW_TXSTAT_TRO) 3111 sc->sc_stats.ts_tx_tro++; 3112 if (txstat & ATW_TXSTAT_SOFBR) { 3113 sc->sc_stats.ts_tx_sofbr++; 3114 } 3115 3116 if ((txstat & ATW_TXSTAT_ES) == 0) 3117 ifp->if_collisions += 3118 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3119 else 3120 ifp->if_oerrors++; 3121 3122 ifp->if_opackets++; 3123 } 3124 3125 /* 3126 * If there are no more pending transmissions, cancel the watchdog 3127 * timer. 3128 */ 3129 if (txs == NULL) 3130 sc->sc_tx_timer = 0; 3131 #undef TXSTAT_ERRMASK 3132 #undef TXSTAT_FMT 3133 } 3134 3135 /* 3136 * atw_watchdog: [ifnet interface function] 3137 * 3138 * Watchdog timer handler. 3139 */ 3140 void 3141 atw_watchdog(struct ifnet *ifp) 3142 { 3143 struct atw_softc *sc = ifp->if_softc; 3144 struct ieee80211com *ic = &sc->sc_ic; 3145 3146 ifp->if_timer = 0; 3147 if (ATW_IS_ENABLED(sc) == 0) 3148 return; 3149 3150 if (sc->sc_rescan_timer) { 3151 if (--sc->sc_rescan_timer == 0) 3152 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3153 } 3154 if (sc->sc_tx_timer) { 3155 if (--sc->sc_tx_timer == 0 && 3156 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3157 printf("%s: transmit timeout\n", ifp->if_xname); 3158 ifp->if_oerrors++; 3159 (void)atw_init(ifp); 3160 atw_start(ifp); 3161 } 3162 } 3163 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3164 ifp->if_timer = 1; 3165 ieee80211_watchdog(ifp); 3166 } 3167 3168 /* Compute the 802.11 Duration field and the PLCP Length fields for 3169 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3170 * Write the fields to the ADM8211 Tx header, frm. 3171 * 3172 * TBD use the fragmentation threshold to find the right duration for 3173 * the first & last fragments. 3174 * 3175 * TBD make certain of the duration fields applied by the ADM8211 to each 3176 * fragment. I think that the ADM8211 knows how to subtract the CTS 3177 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3178 * I also think that the ADM8211 does *some* arithmetic for us, because 3179 * otherwise I think we would have to set a first duration for CTS/first 3180 * fragment, a second duration for fragments between the first and the 3181 * last, and a third duration for the last fragment. 3182 * 3183 * TBD make certain that duration fields reflect addition of FCS/WEP 3184 * and correct duration arithmetic as necessary. 3185 */ 3186 static void 3187 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3188 int len) 3189 { 3190 int remainder; 3191 3192 /* deal also with encrypted fragments */ 3193 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3194 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3195 sc->sc_dev.dv_xname)); 3196 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3197 IEEE80211_WEP_CRCLEN; 3198 } 3199 3200 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3201 * duration (XXX added by MAC?). 3202 */ 3203 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3204 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3205 3206 if (rate <= 4) 3207 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3208 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3209 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3210 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3211 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3212 else 3213 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3214 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3215 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3216 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3217 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3218 3219 /* lengthen duration if long preamble */ 3220 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3221 frm->atw_head_dur += 3222 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3223 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3224 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3225 IEEE80211_DUR_DS_FAST_PLCPHDR); 3226 3227 if (remainder != 0) 3228 frm->atw_head_dur++; 3229 3230 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3231 (rate == 2 || rate == 4)) { 3232 /* derived from Linux: how could this be right? */ 3233 frm->atw_head_plcplen = frm->atw_head_dur; 3234 } else { 3235 frm->atw_head_plcplen = (16 * len) / rate; 3236 remainder = (80 * len) % (rate * 5); 3237 3238 if (remainder != 0) { 3239 frm->atw_head_plcplen++; 3240 3241 /* XXX magic */ 3242 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3243 rate == 22 && remainder <= 30) 3244 frm->atw_head_plcplen |= 0x8000; 3245 } 3246 } 3247 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3248 htole16(frm->atw_head_plcplen); 3249 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3250 } 3251 3252 #ifdef ATW_DEBUG 3253 static void 3254 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3255 { 3256 struct atw_softc *sc = ifp->if_softc; 3257 struct mbuf *m; 3258 int i, noctets = 0; 3259 3260 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3261 m0->m_pkthdr.len); 3262 3263 for (m = m0; m; m = m->m_next) { 3264 if (m->m_len == 0) 3265 continue; 3266 for (i = 0; i < m->m_len; i++) { 3267 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3268 if (++noctets % 24 == 0) 3269 printf("\n"); 3270 } 3271 } 3272 printf("%s%s: %d bytes emitted\n", 3273 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3274 } 3275 #endif /* ATW_DEBUG */ 3276 3277 /* 3278 * atw_start: [ifnet interface function] 3279 * 3280 * Start packet transmission on the interface. 3281 */ 3282 void 3283 atw_start(struct ifnet *ifp) 3284 { 3285 struct atw_softc *sc = ifp->if_softc; 3286 struct ieee80211com *ic = &sc->sc_ic; 3287 struct ieee80211_node *ni; 3288 struct ieee80211_frame *wh; 3289 struct atw_frame *hh; 3290 struct mbuf *m0, *m; 3291 struct atw_txsoft *txs, *last_txs; 3292 struct atw_txdesc *txd; 3293 int do_encrypt, rate; 3294 bus_dmamap_t dmamap; 3295 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3296 3297 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3298 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3299 3300 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3301 return; 3302 3303 /* 3304 * Remember the previous number of free descriptors and 3305 * the first descriptor we'll use. 3306 */ 3307 ofree = sc->sc_txfree; 3308 firsttx = sc->sc_txnext; 3309 3310 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3311 sc->sc_dev.dv_xname, ofree, firsttx)); 3312 3313 /* 3314 * Loop through the send queue, setting up transmit descriptors 3315 * until we drain the queue, or use up all available transmit 3316 * descriptors. 3317 */ 3318 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3319 sc->sc_txfree != 0) { 3320 3321 /* 3322 * Grab a packet off the management queue, if it 3323 * is not empty. Otherwise, from the data queue. 3324 */ 3325 IF_DEQUEUE(&ic->ic_mgtq, m0); 3326 if (m0 != NULL) { 3327 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3328 m0->m_pkthdr.rcvif = NULL; 3329 } else { 3330 /* send no data packets until we are associated */ 3331 if (ic->ic_state != IEEE80211_S_RUN) 3332 break; 3333 IFQ_DEQUEUE(&ifp->if_snd, m0); 3334 if (m0 == NULL) 3335 break; 3336 #if NBPFILTER > 0 3337 if (ifp->if_bpf != NULL) 3338 bpf_mtap(ifp->if_bpf, m0); 3339 #endif /* NBPFILTER > 0 */ 3340 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3341 ifp->if_oerrors++; 3342 break; 3343 } 3344 } 3345 3346 rate = MAX(ieee80211_get_rate(ic), 2); 3347 3348 #if NBPFILTER > 0 3349 /* 3350 * Pass the packet to any BPF listeners. 3351 */ 3352 if (ic->ic_rawbpf != NULL) 3353 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3354 3355 if (sc->sc_radiobpf != NULL) { 3356 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3357 3358 tap->at_rate = rate; 3359 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3360 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3361 3362 /* TBD tap->at_flags */ 3363 3364 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3365 tap->at_ihdr.it_len, m0); 3366 } 3367 #endif /* NBPFILTER > 0 */ 3368 3369 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3370 3371 if (ni != NULL && ni != ic->ic_bss) 3372 ieee80211_free_node(ic, ni); 3373 3374 if (m0 == NULL) { 3375 ifp->if_oerrors++; 3376 break; 3377 } 3378 3379 /* just to make sure. */ 3380 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3381 3382 if (m0 == NULL) { 3383 ifp->if_oerrors++; 3384 break; 3385 } 3386 3387 hh = mtod(m0, struct atw_frame *); 3388 wh = &hh->atw_ihdr; 3389 3390 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3391 3392 /* Copy everything we need from the 802.11 header: 3393 * Frame Control; address 1, address 3, or addresses 3394 * 3 and 4. NIC fills in BSSID, SA. 3395 */ 3396 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3397 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3398 panic("%s: illegal WDS frame", 3399 sc->sc_dev.dv_xname); 3400 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3401 } else 3402 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3403 3404 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3405 3406 /* initialize remaining Tx parameters */ 3407 memset(&hh->u, 0, sizeof(hh->u)); 3408 3409 hh->atw_rate = rate * 5; 3410 /* XXX this could be incorrect if M_FCS. _encap should 3411 * probably strip FCS just in case it sticks around in 3412 * bridged packets. 3413 */ 3414 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3415 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3416 sizeof(struct atw_frame)); 3417 3418 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3419 hh->atw_rtylmt = 3; 3420 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3421 if (do_encrypt) { 3422 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3423 hh->atw_keyid = ic->ic_wep_txkey; 3424 } 3425 3426 /* TBD 4-addr frames */ 3427 atw_frame_setdurs(sc, hh, rate, 3428 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3429 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3430 3431 /* never fragment multicast frames */ 3432 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3433 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3434 } else if (sc->sc_flags & ATWF_RTSCTS) { 3435 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3436 } 3437 3438 #ifdef ATW_DEBUG 3439 hh->atw_fragnum = 0; 3440 3441 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3442 printf("%s: dst = %s, rate = 0x%02x, " 3443 "service = 0x%02x, paylen = 0x%04x\n", 3444 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3445 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3446 3447 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3448 "dur1 = 0x%04x, dur2 = 0x%04x, " 3449 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3450 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3451 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3452 hh->atw_tail_dur, hh->atw_head_dur); 3453 3454 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3455 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3456 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3457 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3458 3459 printf("%s: keyid = %d\n", 3460 sc->sc_dev.dv_xname, hh->atw_keyid); 3461 3462 atw_dump_pkt(ifp, m0); 3463 } 3464 #endif /* ATW_DEBUG */ 3465 3466 dmamap = txs->txs_dmamap; 3467 3468 /* 3469 * Load the DMA map. Copy and try (once) again if the packet 3470 * didn't fit in the alloted number of segments. 3471 */ 3472 for (first = 1; 3473 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3474 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3475 first = 0) { 3476 MGETHDR(m, M_DONTWAIT, MT_DATA); 3477 if (m == NULL) { 3478 printf("%s: unable to allocate Tx mbuf\n", 3479 sc->sc_dev.dv_xname); 3480 break; 3481 } 3482 if (m0->m_pkthdr.len > MHLEN) { 3483 MCLGET(m, M_DONTWAIT); 3484 if ((m->m_flags & M_EXT) == 0) { 3485 printf("%s: unable to allocate Tx " 3486 "cluster\n", sc->sc_dev.dv_xname); 3487 m_freem(m); 3488 break; 3489 } 3490 } 3491 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3492 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3493 m_freem(m0); 3494 m0 = m; 3495 m = NULL; 3496 } 3497 if (error != 0) { 3498 printf("%s: unable to load Tx buffer, " 3499 "error = %d\n", sc->sc_dev.dv_xname, error); 3500 m_freem(m0); 3501 break; 3502 } 3503 3504 /* 3505 * Ensure we have enough descriptors free to describe 3506 * the packet. 3507 */ 3508 if (dmamap->dm_nsegs > sc->sc_txfree) { 3509 /* 3510 * Not enough free descriptors to transmit 3511 * this packet. Unload the DMA map and 3512 * drop the packet. Notify the upper layer 3513 * that there are no more slots left. 3514 * 3515 * XXX We could allocate an mbuf and copy, but 3516 * XXX it is worth it? 3517 */ 3518 ifp->if_flags |= IFF_OACTIVE; 3519 bus_dmamap_unload(sc->sc_dmat, dmamap); 3520 m_freem(m0); 3521 break; 3522 } 3523 3524 /* 3525 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3526 */ 3527 3528 /* Sync the DMA map. */ 3529 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3530 BUS_DMASYNC_PREWRITE); 3531 3532 /* XXX arbitrary retry limit; 8 because I have seen it in 3533 * use already and maybe 0 means "no tries" ! 3534 */ 3535 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3536 3537 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3538 sc->sc_dev.dv_xname, rate * 5)); 3539 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3540 3541 /* 3542 * Initialize the transmit descriptors. 3543 */ 3544 for (nexttx = sc->sc_txnext, seg = 0; 3545 seg < dmamap->dm_nsegs; 3546 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3547 /* 3548 * If this is the first descriptor we're 3549 * enqueueing, don't set the OWN bit just 3550 * yet. That could cause a race condition. 3551 * We'll do it below. 3552 */ 3553 txd = &sc->sc_txdescs[nexttx]; 3554 txd->at_ctl = ctl | 3555 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3556 3557 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3558 txd->at_flags = 3559 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3560 ATW_TXFLAG_TBS1_MASK)) | 3561 ((nexttx == (ATW_NTXDESC - 1)) 3562 ? htole32(ATW_TXFLAG_TER) : 0); 3563 lasttx = nexttx; 3564 } 3565 3566 IASSERT(lasttx != -1, ("bad lastx")); 3567 /* Set `first segment' and `last segment' appropriately. */ 3568 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3569 htole32(ATW_TXFLAG_FS); 3570 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3571 3572 #ifdef ATW_DEBUG 3573 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3574 printf(" txsoft %p transmit chain:\n", txs); 3575 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3576 printf(" descriptor %d:\n", seg); 3577 printf(" at_ctl: 0x%08x\n", 3578 le32toh(sc->sc_txdescs[seg].at_ctl)); 3579 printf(" at_flags: 0x%08x\n", 3580 le32toh(sc->sc_txdescs[seg].at_flags)); 3581 printf(" at_buf1: 0x%08x\n", 3582 le32toh(sc->sc_txdescs[seg].at_buf1)); 3583 printf(" at_buf2: 0x%08x\n", 3584 le32toh(sc->sc_txdescs[seg].at_buf2)); 3585 if (seg == lasttx) 3586 break; 3587 } 3588 } 3589 #endif 3590 3591 /* Sync the descriptors we're using. */ 3592 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3593 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3594 3595 /* 3596 * Store a pointer to the packet so we can free it later, 3597 * and remember what txdirty will be once the packet is 3598 * done. 3599 */ 3600 txs->txs_mbuf = m0; 3601 txs->txs_firstdesc = sc->sc_txnext; 3602 txs->txs_lastdesc = lasttx; 3603 txs->txs_ndescs = dmamap->dm_nsegs; 3604 3605 /* Advance the tx pointer. */ 3606 sc->sc_txfree -= dmamap->dm_nsegs; 3607 sc->sc_txnext = nexttx; 3608 3609 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3610 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3611 3612 last_txs = txs; 3613 } 3614 3615 if (txs == NULL || sc->sc_txfree == 0) { 3616 /* No more slots left; notify upper layer. */ 3617 ifp->if_flags |= IFF_OACTIVE; 3618 } 3619 3620 if (sc->sc_txfree != ofree) { 3621 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3622 sc->sc_dev.dv_xname, lasttx, firsttx)); 3623 /* 3624 * Cause a transmit interrupt to happen on the 3625 * last packet we enqueued. 3626 */ 3627 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3628 ATW_CDTXSYNC(sc, lasttx, 1, 3629 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3630 3631 /* 3632 * The entire packet chain is set up. Give the 3633 * first descriptor to the chip now. 3634 */ 3635 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3636 ATW_CDTXSYNC(sc, firsttx, 1, 3637 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3638 3639 /* Wake up the transmitter. */ 3640 ATW_WRITE(sc, ATW_TDR, 0x1); 3641 3642 /* Set a watchdog timer in case the chip flakes out. */ 3643 sc->sc_tx_timer = 5; 3644 ifp->if_timer = 1; 3645 } 3646 } 3647 3648 /* 3649 * atw_power: 3650 * 3651 * Power management (suspend/resume) hook. 3652 */ 3653 void 3654 atw_power(int why, void *arg) 3655 { 3656 struct atw_softc *sc = arg; 3657 struct ifnet *ifp = &sc->sc_ic.ic_if; 3658 int s; 3659 3660 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3661 3662 s = splnet(); 3663 switch (why) { 3664 case PWR_STANDBY: 3665 /* XXX do nothing. */ 3666 break; 3667 case PWR_SUSPEND: 3668 atw_stop(ifp, 0); 3669 if (sc->sc_power != NULL) 3670 (*sc->sc_power)(sc, why); 3671 break; 3672 case PWR_RESUME: 3673 if (ifp->if_flags & IFF_UP) { 3674 if (sc->sc_power != NULL) 3675 (*sc->sc_power)(sc, why); 3676 atw_init(ifp); 3677 } 3678 break; 3679 case PWR_SOFTSUSPEND: 3680 case PWR_SOFTSTANDBY: 3681 case PWR_SOFTRESUME: 3682 break; 3683 } 3684 splx(s); 3685 } 3686 3687 /* 3688 * atw_ioctl: [ifnet interface function] 3689 * 3690 * Handle control requests from the operator. 3691 */ 3692 int 3693 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3694 { 3695 struct atw_softc *sc = ifp->if_softc; 3696 struct ifreq *ifr = (struct ifreq *)data; 3697 int s, error = 0; 3698 3699 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3700 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3701 return ENXIO; 3702 3703 s = splnet(); 3704 3705 switch (cmd) { 3706 case SIOCSIFFLAGS: 3707 if (ifp->if_flags & IFF_UP) { 3708 if (ATW_IS_ENABLED(sc)) { 3709 /* 3710 * To avoid rescanning another access point, 3711 * do not call atw_init() here. Instead, 3712 * only reflect media settings. 3713 */ 3714 atw_filter_setup(sc); 3715 } else 3716 error = atw_init(ifp); 3717 } else if (ATW_IS_ENABLED(sc)) 3718 atw_stop(ifp, 1); 3719 break; 3720 case SIOCADDMULTI: 3721 case SIOCDELMULTI: 3722 error = (cmd == SIOCADDMULTI) ? 3723 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3724 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3725 if (error == ENETRESET) { 3726 if (ATW_IS_ENABLED(sc)) 3727 atw_filter_setup(sc); /* do not rescan */ 3728 error = 0; 3729 } 3730 break; 3731 default: 3732 error = ieee80211_ioctl(ifp, cmd, data); 3733 if (error == ENETRESET) { 3734 if (ATW_IS_ENABLED(sc)) 3735 error = atw_init(ifp); 3736 else 3737 error = 0; 3738 } 3739 break; 3740 } 3741 3742 /* Try to get more packets going. */ 3743 if (ATW_IS_ENABLED(sc)) 3744 atw_start(ifp); 3745 3746 splx(s); 3747 return (error); 3748 } 3749 3750 static int 3751 atw_media_change(struct ifnet *ifp) 3752 { 3753 int error; 3754 3755 error = ieee80211_media_change(ifp); 3756 if (error == ENETRESET) { 3757 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3758 (IFF_RUNNING|IFF_UP)) 3759 atw_init(ifp); /* XXX lose error */ 3760 error = 0; 3761 } 3762 return error; 3763 } 3764 3765 static void 3766 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3767 { 3768 struct atw_softc *sc = ifp->if_softc; 3769 3770 if (ATW_IS_ENABLED(sc) == 0) { 3771 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3772 imr->ifm_status = 0; 3773 return; 3774 } 3775 ieee80211_media_status(ifp, imr); 3776 } 3777
Indexes created Wed Sep 24 05:09:52 GMT 2025