atw.c revision 1.59
1 /* $NetBSD: atw.c,v 1.59 2004/07/15 07:19:46 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.59 2004/07/15 07:19:46 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_bbp_io_enable_delay = 20 * 1000; 145 int atw_bbp_io_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 1000; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 int atw_xindiv2 = 0; 150 151 #ifdef ATW_DEBUG 152 int atw_debug = 0; 153 154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 157 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 158 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 159 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 160 161 static void atw_print_regs(struct atw_softc *, const char *); 162 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 163 164 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 165 # ifdef ATW_BBPDEBUG 166 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 167 static void atw_rf3000_print(struct atw_softc *); 168 # endif /* ATW_BBPDEBUG */ 169 170 # ifdef ATW_SYNDEBUG 171 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 172 static void atw_si4126_print(struct atw_softc *); 173 # endif /* ATW_SYNDEBUG */ 174 175 #else 176 #define ATW_DPRINTF(x) 177 #define ATW_DPRINTF2(x) 178 #define ATW_DPRINTF3(x) 179 #define DPRINTF(sc, x) /* nothing */ 180 #define DPRINTF2(sc, x) /* nothing */ 181 #define DPRINTF3(sc, x) /* nothing */ 182 #endif 183 184 #ifdef ATW_STATS 185 void atw_print_stats(struct atw_softc *); 186 #endif 187 188 void atw_start(struct ifnet *); 189 void atw_watchdog(struct ifnet *); 190 int atw_ioctl(struct ifnet *, u_long, caddr_t); 191 int atw_init(struct ifnet *); 192 void atw_txdrain(struct atw_softc *); 193 void atw_stop(struct ifnet *, int); 194 195 void atw_reset(struct atw_softc *); 196 int atw_read_srom(struct atw_softc *); 197 198 void atw_shutdown(void *); 199 200 void atw_rxdrain(struct atw_softc *); 201 int atw_add_rxbuf(struct atw_softc *, int); 202 void atw_idle(struct atw_softc *, u_int32_t); 203 204 int atw_enable(struct atw_softc *); 205 void atw_disable(struct atw_softc *); 206 void atw_power(int, void *); 207 208 void atw_rxintr(struct atw_softc *); 209 void atw_txintr(struct atw_softc *); 210 void atw_linkintr(struct atw_softc *, u_int32_t); 211 212 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 213 static void atw_tsf(struct atw_softc *); 214 static void atw_start_beacon(struct atw_softc *, int); 215 static void atw_write_wep(struct atw_softc *); 216 static void atw_write_bssid(struct atw_softc *); 217 static void atw_write_ssid(struct atw_softc *); 218 static void atw_write_sup_rates(struct atw_softc *); 219 static void atw_clear_sram(struct atw_softc *); 220 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 221 static int atw_media_change(struct ifnet *); 222 static void atw_media_status(struct ifnet *, struct ifmediareq *); 223 static void atw_filter_setup(struct atw_softc *); 224 static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 225 static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 226 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 227 struct ieee80211_node *, int, int, u_int32_t); 228 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 229 struct ieee80211_node *, int, int, u_int32_t); 230 static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 231 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 232 233 static int atw_tune(struct atw_softc *); 234 235 static void atw_rfio_enable(struct atw_softc *, int); 236 237 /* RFMD RF3000 Baseband Processor */ 238 static int atw_rf3000_init(struct atw_softc *); 239 static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 240 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 241 #ifdef ATW_DEBUG 242 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 243 #endif /* ATW_DEBUG */ 244 245 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 246 static int atw_si4126_tune(struct atw_softc *, u_int8_t); 247 static int atw_si4126_write(struct atw_softc *, u_int, u_int); 248 #ifdef ATW_DEBUG 249 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 250 #endif /* ATW_DEBUG */ 251 252 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 253 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 254 255 const char *atw_tx_state[] = { 256 "STOPPED", 257 "RUNNING - read descriptor", 258 "RUNNING - transmitting", 259 "RUNNING - filling fifo", /* XXX */ 260 "SUSPENDED", 261 "RUNNING -- write descriptor", 262 "RUNNING -- write last descriptor", 263 "RUNNING - fifo full" 264 }; 265 266 const char *atw_rx_state[] = { 267 "STOPPED", 268 "RUNNING - read descriptor", 269 "RUNNING - check this packet, pre-fetch next", 270 "RUNNING - wait for reception", 271 "SUSPENDED", 272 "RUNNING - write descriptor", 273 "RUNNING - flush fifo", 274 "RUNNING - fifo drain" 275 }; 276 277 int 278 atw_activate(struct device *self, enum devact act) 279 { 280 struct atw_softc *sc = (struct atw_softc *)self; 281 int rv = 0, s; 282 283 s = splnet(); 284 switch (act) { 285 case DVACT_ACTIVATE: 286 rv = EOPNOTSUPP; 287 break; 288 289 case DVACT_DEACTIVATE: 290 if_deactivate(&sc->sc_ic.ic_if); 291 break; 292 } 293 splx(s); 294 return rv; 295 } 296 297 /* 298 * atw_enable: 299 * 300 * Enable the ADM8211 chip. 301 */ 302 int 303 atw_enable(struct atw_softc *sc) 304 { 305 306 if (ATW_IS_ENABLED(sc) == 0) { 307 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 308 printf("%s: device enable failed\n", 309 sc->sc_dev.dv_xname); 310 return (EIO); 311 } 312 sc->sc_flags |= ATWF_ENABLED; 313 } 314 return (0); 315 } 316 317 /* 318 * atw_disable: 319 * 320 * Disable the ADM8211 chip. 321 */ 322 void 323 atw_disable(struct atw_softc *sc) 324 { 325 if (!ATW_IS_ENABLED(sc)) 326 return; 327 if (sc->sc_disable != NULL) 328 (*sc->sc_disable)(sc); 329 sc->sc_flags &= ~ATWF_ENABLED; 330 } 331 332 /* Returns -1 on failure. */ 333 int 334 atw_read_srom(struct atw_softc *sc) 335 { 336 struct seeprom_descriptor sd; 337 u_int32_t reg; 338 339 (void)memset(&sd, 0, sizeof(sd)); 340 341 reg = ATW_READ(sc, ATW_TEST0); 342 343 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 344 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 345 return -1; 346 } 347 348 switch (reg & ATW_TEST0_EPTYP_MASK) { 349 case ATW_TEST0_EPTYP_93c66: 350 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 512; 352 sd.sd_chip = C56_66; 353 break; 354 case ATW_TEST0_EPTYP_93c46: 355 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 356 sc->sc_sromsz = 128; 357 sd.sd_chip = C46; 358 break; 359 default: 360 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 361 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 362 return -1; 363 } 364 365 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 366 367 if (sc->sc_srom == NULL) { 368 printf("%s: unable to allocate SROM buffer\n", 369 sc->sc_dev.dv_xname); 370 return -1; 371 } 372 373 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 374 375 /* ADM8211 has a single 32-bit register for controlling the 376 * 93cx6 SROM. Bit SRS enables the serial port. There is no 377 * "ready" bit. The ADM8211 input/output sense is the reverse 378 * of read_seeprom's. 379 */ 380 sd.sd_tag = sc->sc_st; 381 sd.sd_bsh = sc->sc_sh; 382 sd.sd_regsize = 4; 383 sd.sd_control_offset = ATW_SPR; 384 sd.sd_status_offset = ATW_SPR; 385 sd.sd_dataout_offset = ATW_SPR; 386 sd.sd_CK = ATW_SPR_SCLK; 387 sd.sd_CS = ATW_SPR_SCS; 388 sd.sd_DI = ATW_SPR_SDO; 389 sd.sd_DO = ATW_SPR_SDI; 390 sd.sd_MS = ATW_SPR_SRS; 391 sd.sd_RDY = 0; 392 393 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 394 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 395 free(sc->sc_srom, M_DEVBUF); 396 return -1; 397 } 398 #ifdef ATW_DEBUG 399 { 400 int i; 401 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 402 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 403 if (((i % 8) == 0) && (i != 0)) { 404 ATW_DPRINTF(("\n\t")); 405 } 406 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 407 } 408 ATW_DPRINTF(("\n")); 409 } 410 #endif /* ATW_DEBUG */ 411 return 0; 412 } 413 414 #ifdef ATW_DEBUG 415 static void 416 atw_print_regs(struct atw_softc *sc, const char *where) 417 { 418 #define PRINTREG(sc, reg) \ 419 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 420 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 421 422 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 423 424 PRINTREG(sc, ATW_PAR); 425 PRINTREG(sc, ATW_FRCTL); 426 PRINTREG(sc, ATW_TDR); 427 PRINTREG(sc, ATW_WTDP); 428 PRINTREG(sc, ATW_RDR); 429 PRINTREG(sc, ATW_WRDP); 430 PRINTREG(sc, ATW_RDB); 431 PRINTREG(sc, ATW_CSR3A); 432 PRINTREG(sc, ATW_TDBD); 433 PRINTREG(sc, ATW_TDBP); 434 PRINTREG(sc, ATW_STSR); 435 PRINTREG(sc, ATW_CSR5A); 436 PRINTREG(sc, ATW_NAR); 437 PRINTREG(sc, ATW_CSR6A); 438 PRINTREG(sc, ATW_IER); 439 PRINTREG(sc, ATW_CSR7A); 440 PRINTREG(sc, ATW_LPC); 441 PRINTREG(sc, ATW_TEST1); 442 PRINTREG(sc, ATW_SPR); 443 PRINTREG(sc, ATW_TEST0); 444 PRINTREG(sc, ATW_WCSR); 445 PRINTREG(sc, ATW_WPDR); 446 PRINTREG(sc, ATW_GPTMR); 447 PRINTREG(sc, ATW_GPIO); 448 PRINTREG(sc, ATW_BBPCTL); 449 PRINTREG(sc, ATW_SYNCTL); 450 PRINTREG(sc, ATW_PLCPHD); 451 PRINTREG(sc, ATW_MMIWADDR); 452 PRINTREG(sc, ATW_MMIRADDR1); 453 PRINTREG(sc, ATW_MMIRADDR2); 454 PRINTREG(sc, ATW_TXBR); 455 PRINTREG(sc, ATW_CSR15A); 456 PRINTREG(sc, ATW_ALCSTAT); 457 PRINTREG(sc, ATW_TOFS2); 458 PRINTREG(sc, ATW_CMDR); 459 PRINTREG(sc, ATW_PCIC); 460 PRINTREG(sc, ATW_PMCSR); 461 PRINTREG(sc, ATW_PAR0); 462 PRINTREG(sc, ATW_PAR1); 463 PRINTREG(sc, ATW_MAR0); 464 PRINTREG(sc, ATW_MAR1); 465 PRINTREG(sc, ATW_ATIMDA0); 466 PRINTREG(sc, ATW_ABDA1); 467 PRINTREG(sc, ATW_BSSID0); 468 PRINTREG(sc, ATW_TXLMT); 469 PRINTREG(sc, ATW_MIBCNT); 470 PRINTREG(sc, ATW_BCNT); 471 PRINTREG(sc, ATW_TSFTH); 472 PRINTREG(sc, ATW_TSC); 473 PRINTREG(sc, ATW_SYNRF); 474 PRINTREG(sc, ATW_BPLI); 475 PRINTREG(sc, ATW_CAP0); 476 PRINTREG(sc, ATW_CAP1); 477 PRINTREG(sc, ATW_RMD); 478 PRINTREG(sc, ATW_CFPP); 479 PRINTREG(sc, ATW_TOFS0); 480 PRINTREG(sc, ATW_TOFS1); 481 PRINTREG(sc, ATW_IFST); 482 PRINTREG(sc, ATW_RSPT); 483 PRINTREG(sc, ATW_TSFTL); 484 PRINTREG(sc, ATW_WEPCTL); 485 PRINTREG(sc, ATW_WESK); 486 PRINTREG(sc, ATW_WEPCNT); 487 PRINTREG(sc, ATW_MACTEST); 488 PRINTREG(sc, ATW_FER); 489 PRINTREG(sc, ATW_FEMR); 490 PRINTREG(sc, ATW_FPSR); 491 PRINTREG(sc, ATW_FFER); 492 #undef PRINTREG 493 } 494 #endif /* ATW_DEBUG */ 495 496 /* 497 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 498 */ 499 void 500 atw_attach(struct atw_softc *sc) 501 { 502 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 503 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 504 }; 505 struct ieee80211com *ic = &sc->sc_ic; 506 struct ifnet *ifp = &ic->ic_if; 507 int country_code, error, i, nrate; 508 u_int32_t reg; 509 static const char *type_strings[] = {"Intersil (not supported)", 510 "RFMD", "Marvel (not supported)"}; 511 512 sc->sc_txth = atw_txthresh_tab_lo; 513 514 SIMPLEQ_INIT(&sc->sc_txfreeq); 515 SIMPLEQ_INIT(&sc->sc_txdirtyq); 516 517 #ifdef ATW_DEBUG 518 atw_print_regs(sc, "atw_attach"); 519 #endif /* ATW_DEBUG */ 520 521 /* 522 * Allocate the control data structures, and create and load the 523 * DMA map for it. 524 */ 525 if ((error = bus_dmamem_alloc(sc->sc_dmat, 526 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 527 1, &sc->sc_cdnseg, 0)) != 0) { 528 printf("%s: unable to allocate control data, error = %d\n", 529 sc->sc_dev.dv_xname, error); 530 goto fail_0; 531 } 532 533 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 534 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 535 BUS_DMA_COHERENT)) != 0) { 536 printf("%s: unable to map control data, error = %d\n", 537 sc->sc_dev.dv_xname, error); 538 goto fail_1; 539 } 540 541 if ((error = bus_dmamap_create(sc->sc_dmat, 542 sizeof(struct atw_control_data), 1, 543 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 544 printf("%s: unable to create control data DMA map, " 545 "error = %d\n", sc->sc_dev.dv_xname, error); 546 goto fail_2; 547 } 548 549 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 550 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 551 0)) != 0) { 552 printf("%s: unable to load control data DMA map, error = %d\n", 553 sc->sc_dev.dv_xname, error); 554 goto fail_3; 555 } 556 557 /* 558 * Create the transmit buffer DMA maps. 559 */ 560 sc->sc_ntxsegs = ATW_NTXSEGS; 561 for (i = 0; i < ATW_TXQUEUELEN; i++) { 562 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 563 sc->sc_ntxsegs, MCLBYTES, 0, 0, 564 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 565 printf("%s: unable to create tx DMA map %d, " 566 "error = %d\n", sc->sc_dev.dv_xname, i, error); 567 goto fail_4; 568 } 569 } 570 571 /* 572 * Create the receive buffer DMA maps. 573 */ 574 for (i = 0; i < ATW_NRXDESC; i++) { 575 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 576 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 577 printf("%s: unable to create rx DMA map %d, " 578 "error = %d\n", sc->sc_dev.dv_xname, i, error); 579 goto fail_5; 580 } 581 } 582 for (i = 0; i < ATW_NRXDESC; i++) { 583 sc->sc_rxsoft[i].rxs_mbuf = NULL; 584 } 585 586 /* Reset the chip to a known state. */ 587 atw_reset(sc); 588 589 if (atw_read_srom(sc) == -1) 590 return; 591 592 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 593 ATW_SR_RFTYPE_MASK); 594 595 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 596 ATW_SR_BBPTYPE_MASK); 597 598 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 599 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 600 return; 601 } 602 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 603 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 604 return; 605 } 606 607 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 608 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 609 610 /* XXX There exists a Linux driver which seems to use RFType = 0 for 611 * MARVEL. My bug, or theirs? 612 */ 613 614 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 615 616 switch (sc->sc_rftype) { 617 case ATW_RFTYPE_INTERSIL: 618 reg |= ATW_SYNCTL_CS1; 619 break; 620 case ATW_RFTYPE_RFMD: 621 reg |= ATW_SYNCTL_CS0; 622 break; 623 case ATW_RFTYPE_MARVEL: 624 break; 625 } 626 627 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 628 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 629 630 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 631 632 switch (sc->sc_bbptype) { 633 case ATW_BBPTYPE_INTERSIL: 634 reg |= ATW_BBPCTL_TWI; 635 break; 636 case ATW_BBPTYPE_RFMD: 637 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 638 ATW_BBPCTL_CCA_ACTLO; 639 break; 640 case ATW_BBPTYPE_MARVEL: 641 break; 642 case ATW_C_BBPTYPE_RFMD: 643 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 644 sc->sc_dev.dv_xname); 645 break; 646 } 647 648 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 649 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 650 651 /* 652 * From this point forward, the attachment cannot fail. A failure 653 * before this point releases all resources that may have been 654 * allocated. 655 */ 656 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 657 658 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 659 htole16(sc->sc_srom[ATW_SR_MAC00]), 660 htole16(sc->sc_srom[ATW_SR_MAC01]), 661 htole16(sc->sc_srom[ATW_SR_MAC10]))); 662 663 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 664 ATW_SR_CTRY_MASK); 665 666 #define ADD_CHANNEL(_ic, _chan) do { \ 667 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 668 _ic->ic_channels[_chan].ic_freq = \ 669 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 670 } while (0) 671 672 /* Find available channels */ 673 switch (country_code) { 674 case COUNTRY_MMK2: /* 1-14 */ 675 ADD_CHANNEL(ic, 14); 676 /*FALLTHROUGH*/ 677 case COUNTRY_ETSI: /* 1-13 */ 678 for (i = 1; i <= 13; i++) 679 ADD_CHANNEL(ic, i); 680 break; 681 case COUNTRY_FCC: /* 1-11 */ 682 case COUNTRY_IC: /* 1-11 */ 683 for (i = 1; i <= 11; i++) 684 ADD_CHANNEL(ic, i); 685 break; 686 case COUNTRY_MMK: /* 14 */ 687 ADD_CHANNEL(ic, 14); 688 break; 689 case COUNTRY_FRANCE: /* 10-13 */ 690 for (i = 10; i <= 13; i++) 691 ADD_CHANNEL(ic, i); 692 break; 693 default: /* assume channels 10-11 */ 694 case COUNTRY_SPAIN: /* 10-11 */ 695 for (i = 10; i <= 11; i++) 696 ADD_CHANNEL(ic, i); 697 break; 698 } 699 700 /* Read the MAC address. */ 701 reg = ATW_READ(sc, ATW_PAR0); 702 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 703 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 704 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 705 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 706 reg = ATW_READ(sc, ATW_PAR1); 707 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 708 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 709 710 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 711 printf(" could not get mac address, attach failed\n"); 712 return; 713 } 714 715 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 716 717 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 718 ifp->if_softc = sc; 719 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 720 IFF_NOTRAILERS; 721 ifp->if_ioctl = atw_ioctl; 722 ifp->if_start = atw_start; 723 ifp->if_watchdog = atw_watchdog; 724 ifp->if_init = atw_init; 725 ifp->if_stop = atw_stop; 726 IFQ_SET_READY(&ifp->if_snd); 727 728 ic->ic_phytype = IEEE80211_T_DS; 729 ic->ic_opmode = IEEE80211_M_STA; 730 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 731 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 732 733 nrate = 0; 734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 735 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 736 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 737 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 738 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 739 740 /* 741 * Call MI attach routines. 742 */ 743 744 if_attach(ifp); 745 ieee80211_ifattach(ifp); 746 747 sc->sc_newstate = ic->ic_newstate; 748 ic->ic_newstate = atw_newstate; 749 750 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 751 ic->ic_recv_mgmt = atw_recv_mgmt; 752 753 sc->sc_node_free = ic->ic_node_free; 754 ic->ic_node_free = atw_node_free; 755 756 sc->sc_node_alloc = ic->ic_node_alloc; 757 ic->ic_node_alloc = atw_node_alloc; 758 759 /* possibly we should fill in our own sc_send_prresp, since 760 * the ADM8211 is probably sending probe responses in ad hoc 761 * mode. 762 */ 763 764 /* complete initialization */ 765 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 766 callout_init(&sc->sc_scan_ch); 767 768 #if NBPFILTER > 0 769 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 770 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 771 #endif 772 773 /* 774 * Make sure the interface is shutdown during reboot. 775 */ 776 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 777 if (sc->sc_sdhook == NULL) 778 printf("%s: WARNING: unable to establish shutdown hook\n", 779 sc->sc_dev.dv_xname); 780 781 /* 782 * Add a suspend hook to make sure we come back up after a 783 * resume. 784 */ 785 sc->sc_powerhook = powerhook_establish(atw_power, sc); 786 if (sc->sc_powerhook == NULL) 787 printf("%s: WARNING: unable to establish power hook\n", 788 sc->sc_dev.dv_xname); 789 790 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 791 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 792 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 793 794 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 795 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 796 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 797 798 return; 799 800 /* 801 * Free any resources we've allocated during the failed attach 802 * attempt. Do this in reverse order and fall through. 803 */ 804 fail_5: 805 for (i = 0; i < ATW_NRXDESC; i++) { 806 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 807 continue; 808 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 809 } 810 fail_4: 811 for (i = 0; i < ATW_TXQUEUELEN; i++) { 812 if (sc->sc_txsoft[i].txs_dmamap == NULL) 813 continue; 814 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 815 } 816 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 817 fail_3: 818 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 819 fail_2: 820 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 821 sizeof(struct atw_control_data)); 822 fail_1: 823 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 824 fail_0: 825 return; 826 } 827 828 static struct ieee80211_node * 829 atw_node_alloc(struct ieee80211com *ic) 830 { 831 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 832 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 833 834 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 835 return ni; 836 } 837 838 static void 839 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 840 { 841 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 842 843 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 844 ether_sprintf(ni->ni_bssid))); 845 (*sc->sc_node_free)(ic, ni); 846 } 847 848 /* 849 * atw_reset: 850 * 851 * Perform a soft reset on the ADM8211. 852 */ 853 void 854 atw_reset(struct atw_softc *sc) 855 { 856 int i; 857 858 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 859 860 for (i = 0; i < 10000; i++) { 861 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 862 break; 863 DELAY(1); 864 } 865 866 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 867 868 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 869 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 870 871 /* Turn off maximum power saving. */ 872 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 873 874 /* Recall EEPROM. */ 875 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 876 877 DELAY(10 * 1000); 878 879 /* A reset seems to affect the SRAM contents, so put them into 880 * a known state. 881 */ 882 atw_clear_sram(sc); 883 884 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 885 } 886 887 static void 888 atw_clear_sram(struct atw_softc *sc) 889 { 890 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 891 /* XXX not for revision 0x20. */ 892 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 893 } 894 895 /* TBD atw_init 896 * 897 * set MAC based on ic->ic_bss->myaddr 898 * write WEP keys 899 * set TX rate 900 */ 901 902 /* 903 * atw_init: [ ifnet interface function ] 904 * 905 * Initialize the interface. Must be called at splnet(). 906 */ 907 int 908 atw_init(struct ifnet *ifp) 909 { 910 struct atw_softc *sc = ifp->if_softc; 911 struct ieee80211com *ic = &sc->sc_ic; 912 struct atw_txsoft *txs; 913 struct atw_rxsoft *rxs; 914 u_int32_t reg; 915 int i, error = 0; 916 917 if ((error = atw_enable(sc)) != 0) 918 goto out; 919 920 /* 921 * Cancel any pending I/O. This also resets. 922 */ 923 atw_stop(ifp, 0); 924 925 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 926 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 927 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 928 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 929 930 /* Turn off APM??? (A binary-only driver does this.) 931 * 932 * Set Rx store-and-forward mode. 933 */ 934 reg = ATW_READ(sc, ATW_CMDR); 935 reg &= ~ATW_CMDR_APM; 936 reg &= ~ATW_CMDR_DRT_MASK; 937 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 938 939 ATW_WRITE(sc, ATW_CMDR, reg); 940 941 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 942 * 943 * XXX a binary-only driver sets a different service field than 944 * 0. why? 945 */ 946 reg = ATW_READ(sc, ATW_PLCPHD); 947 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 948 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 949 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 950 ATW_WRITE(sc, ATW_PLCPHD, reg); 951 952 /* XXX this magic can probably be figured out from the RFMD docs */ 953 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 954 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 955 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 956 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 957 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 958 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 959 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 960 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 961 ATW_WRITE(sc, ATW_TOFS2, reg); 962 963 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 964 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 965 966 /* XXX this resets an Intersil RF front-end? */ 967 /* TBD condition on Intersil RFType? */ 968 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 969 DELAY(10 * 1000); 970 ATW_WRITE(sc, ATW_SYNRF, 0); 971 DELAY(5 * 1000); 972 973 /* 16 TU max duration for contention-free period */ 974 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 975 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 976 977 /* XXX I guess that the Cardbus clock is 22MHz? 978 * I am assuming that the role of ATW_TOFS0_USCNT is 979 * to divide the bus clock to get a 1MHz clock---the datasheet is not 980 * very clear on this point. It says in the datasheet that it is 981 * possible for the ADM8211 to accomodate bus speeds between 22MHz 982 * and 33MHz; maybe this is the way? I see a binary-only driver write 983 * these values. These values are also the power-on default. 984 */ 985 ATW_WRITE(sc, ATW_TOFS0, 986 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 987 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 988 989 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 990 * driver. Go figure. 991 */ 992 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 993 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 994 ATW_IFST_SIFS_MASK) | 995 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 996 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 997 998 ATW_WRITE(sc, ATW_IFST, reg); 999 1000 /* XXX More magic. Might relate to ACK timing. */ 1001 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1002 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1003 1004 /* Set up the MMI read/write addresses for the BBP. 1005 * 1006 * TBD find out the Marvel settings. 1007 */ 1008 switch (sc->sc_bbptype) { 1009 case ATW_BBPTYPE_INTERSIL: 1010 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1011 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1012 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1013 break; 1014 case ATW_BBPTYPE_MARVEL: 1015 break; 1016 case ATW_BBPTYPE_RFMD: 1017 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1018 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1019 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1020 default: 1021 break; 1022 } 1023 1024 sc->sc_wepctl = 0; 1025 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1026 1027 if ((error = atw_rf3000_init(sc)) != 0) 1028 goto out; 1029 1030 /* 1031 * Initialize the PCI Access Register. 1032 */ 1033 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1034 1035 /* 1036 * If we're allowed to do so, use Memory Read Line 1037 * and Memory Read Multiple. 1038 * 1039 * XXX Should we use Memory Write and Invalidate? 1040 */ 1041 if (sc->sc_flags & ATWF_MRL) 1042 sc->sc_busmode |= ATW_PAR_MRLE; 1043 if (sc->sc_flags & ATWF_MRM) 1044 sc->sc_busmode |= ATW_PAR_MRME; 1045 if (sc->sc_flags & ATWF_MWI) 1046 sc->sc_busmode |= ATW_PAR_MWIE; 1047 if (sc->sc_maxburst == 0) 1048 sc->sc_maxburst = 8; /* ADM8211 default */ 1049 1050 switch (sc->sc_cacheline) { 1051 default: 1052 /* Use burst length. */ 1053 break; 1054 case 8: 1055 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1056 break; 1057 case 16: 1058 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1059 break; 1060 case 32: 1061 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1062 break; 1063 } 1064 switch (sc->sc_maxburst) { 1065 case 1: 1066 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1067 break; 1068 case 2: 1069 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1070 break; 1071 case 4: 1072 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1073 break; 1074 case 8: 1075 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1076 break; 1077 case 16: 1078 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1079 break; 1080 case 32: 1081 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1082 break; 1083 default: 1084 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1085 break; 1086 } 1087 1088 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1089 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1090 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1091 1092 /* 1093 * Initialize the OPMODE register. We don't write it until 1094 * we're ready to begin the transmit and receive processes. 1095 */ 1096 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1097 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1098 1099 /* 1100 * Initialize the transmit descriptor ring. 1101 */ 1102 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1103 for (i = 0; i < ATW_NTXDESC; i++) { 1104 sc->sc_txdescs[i].at_ctl = 0; 1105 /* no transmit chaining */ 1106 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1107 sc->sc_txdescs[i].at_buf2 = 1108 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1109 } 1110 /* use ring mode */ 1111 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1112 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 sc->sc_txfree = ATW_NTXDESC; 1115 sc->sc_txnext = 0; 1116 1117 /* 1118 * Initialize the transmit job descriptors. 1119 */ 1120 SIMPLEQ_INIT(&sc->sc_txfreeq); 1121 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1122 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1123 txs = &sc->sc_txsoft[i]; 1124 txs->txs_mbuf = NULL; 1125 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1126 } 1127 1128 /* 1129 * Initialize the receive descriptor and receive job 1130 * descriptor rings. 1131 */ 1132 for (i = 0; i < ATW_NRXDESC; i++) { 1133 rxs = &sc->sc_rxsoft[i]; 1134 if (rxs->rxs_mbuf == NULL) { 1135 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1136 printf("%s: unable to allocate or map rx " 1137 "buffer %d, error = %d\n", 1138 sc->sc_dev.dv_xname, i, error); 1139 /* 1140 * XXX Should attempt to run with fewer receive 1141 * XXX buffers instead of just failing. 1142 */ 1143 atw_rxdrain(sc); 1144 goto out; 1145 } 1146 } else 1147 ATW_INIT_RXDESC(sc, i); 1148 } 1149 sc->sc_rxptr = 0; 1150 1151 /* disable all wake-up events */ 1152 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1153 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1154 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1155 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1156 1157 /* ack all wake-up events */ 1158 ATW_SET(sc, ATW_WCSR, 0); 1159 1160 /* 1161 * Initialize the interrupt mask and enable interrupts. 1162 */ 1163 /* normal interrupts */ 1164 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1165 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1166 1167 /* abnormal interrupts */ 1168 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1169 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1170 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1171 1172 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1173 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1174 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1175 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1176 ATW_INTR_TRT; 1177 1178 sc->sc_linkint_mask &= sc->sc_inten; 1179 sc->sc_rxint_mask &= sc->sc_inten; 1180 sc->sc_txint_mask &= sc->sc_inten; 1181 1182 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1183 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1184 if (sc->sc_intr_ack != NULL) 1185 (*sc->sc_intr_ack)(sc); 1186 1187 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1188 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1189 1190 /* 1191 * Give the transmit and receive rings to the ADM8211. 1192 */ 1193 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1194 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1195 1196 /* common 802.11 configuration */ 1197 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1198 switch (ic->ic_opmode) { 1199 case IEEE80211_M_STA: 1200 break; 1201 case IEEE80211_M_AHDEMO: /* XXX */ 1202 case IEEE80211_M_IBSS: 1203 ic->ic_flags |= IEEE80211_F_IBSSON; 1204 /*FALLTHROUGH*/ 1205 case IEEE80211_M_HOSTAP: /* XXX */ 1206 break; 1207 case IEEE80211_M_MONITOR: /* XXX */ 1208 break; 1209 } 1210 1211 atw_start_beacon(sc, 0); 1212 1213 switch (ic->ic_opmode) { 1214 case IEEE80211_M_AHDEMO: 1215 case IEEE80211_M_HOSTAP: 1216 ic->ic_bss->ni_intval = ic->ic_lintval; 1217 ic->ic_bss->ni_rssi = 0; 1218 ic->ic_bss->ni_rstamp = 0; 1219 break; 1220 default: /* XXX */ 1221 break; 1222 } 1223 1224 atw_write_ssid(sc); 1225 atw_write_sup_rates(sc); 1226 if (ic->ic_caps & IEEE80211_C_WEP) 1227 atw_write_wep(sc); 1228 1229 /* 1230 * Set the receive filter. This will start the transmit and 1231 * receive processes. 1232 */ 1233 atw_filter_setup(sc); 1234 1235 /* 1236 * Start the receive process. 1237 */ 1238 ATW_WRITE(sc, ATW_RDR, 0x1); 1239 1240 /* 1241 * Note that the interface is now running. 1242 */ 1243 ifp->if_flags |= IFF_RUNNING; 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 ic->ic_state = IEEE80211_S_INIT; 1246 1247 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1248 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1249 else 1250 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1251 out: 1252 if (error) { 1253 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1254 ifp->if_timer = 0; 1255 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1256 } 1257 #ifdef ATW_DEBUG 1258 atw_print_regs(sc, "end of init"); 1259 #endif /* ATW_DEBUG */ 1260 1261 return (error); 1262 } 1263 1264 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1265 * 0: MAC control of RF3000/Si4126. 1266 * 1267 * Applies power, or selects RF front-end? Sets reset condition. 1268 * 1269 * TBD support non-RFMD BBP, non-SiLabs synth. 1270 */ 1271 static void 1272 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1273 { 1274 if (enable) { 1275 ATW_WRITE(sc, ATW_SYNRF, 1276 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1277 DELAY(atw_bbp_io_enable_delay); 1278 } else { 1279 ATW_WRITE(sc, ATW_SYNRF, 0); 1280 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1281 } 1282 } 1283 1284 static int 1285 atw_tune(struct atw_softc *sc) 1286 { 1287 int rc; 1288 u_int chan; 1289 struct ieee80211com *ic = &sc->sc_ic; 1290 1291 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1292 if (chan == IEEE80211_CHAN_ANY) 1293 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1294 1295 if (chan == sc->sc_cur_chan) 1296 return 0; 1297 1298 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1299 sc->sc_cur_chan, chan)); 1300 1301 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1302 1303 atw_si4126_tune(sc, chan); 1304 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1305 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1306 chan); 1307 1308 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1309 DELAY(20 * 1000); 1310 ATW_WRITE(sc, ATW_RDR, 0x1); 1311 1312 if (rc == 0) 1313 sc->sc_cur_chan = chan; 1314 1315 return rc; 1316 } 1317 1318 #ifdef ATW_SYNDEBUG 1319 static void 1320 atw_si4126_print(struct atw_softc *sc) 1321 { 1322 struct ifnet *ifp = &sc->sc_ic.ic_if; 1323 u_int addr, val; 1324 1325 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1326 return; 1327 1328 for (addr = 0; addr <= 8; addr++) { 1329 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1330 if (atw_si4126_read(sc, addr, &val) == 0) { 1331 printf("<unknown> (quitting print-out)\n"); 1332 break; 1333 } 1334 printf("%05x\n", val); 1335 } 1336 } 1337 #endif /* ATW_SYNDEBUG */ 1338 1339 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1340 * 1341 * The RF/IF synthesizer produces two reference frequencies for 1342 * the RF2948B transceiver. The first frequency the RF2948B requires 1343 * is two times the so-called "intermediate frequency" (IF). Since 1344 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1345 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1346 * frequency required by the transceiver is the radio frequency 1347 * (RF). This is a superheterodyne transceiver; for f(chan) the 1348 * center frequency of the channel we are tuning, RF = f(chan) - 1349 * IF. 1350 * 1351 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1352 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1353 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1354 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1355 */ 1356 static void 1357 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1358 { 1359 u_int mhz; 1360 u_int R; 1361 u_int32_t gpio; 1362 u_int16_t gain; 1363 1364 #ifdef ATW_SYNDEBUG 1365 atw_si4126_print(sc); 1366 #endif /* ATW_SYNDEBUG */ 1367 1368 if (chan == 14) 1369 mhz = 2484; 1370 else 1371 mhz = 2412 + 5 * (chan - 1); 1372 1373 /* Tune IF to 748MHz to suit the IF LO input of the 1374 * RF2494B, which is 2 x IF. No need to set an IF divider 1375 * because an IF in 526MHz - 952MHz is allowed. 1376 * 1377 * XIN is 44.000MHz, so divide it by two to get allowable 1378 * range of 2-25MHz. SiLabs tells me that this is not 1379 * strictly necessary. 1380 */ 1381 1382 if (atw_xindiv2) 1383 R = 44; 1384 else 1385 R = 88; 1386 1387 /* Power-up RF, IF synthesizers. */ 1388 atw_si4126_write(sc, SI4126_POWER, 1389 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1390 1391 /* set LPWR, too? */ 1392 atw_si4126_write(sc, SI4126_MAIN, 1393 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1394 1395 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1396 * set KP2 to 1. 1397 * 1398 * REFDIF This is different from the reference driver, which 1399 * always sets SI4126_GAIN to 0. 1400 */ 1401 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1402 1403 atw_si4126_write(sc, SI4126_GAIN, gain); 1404 1405 /* XIN = 44MHz. 1406 * 1407 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1408 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1409 * 1410 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1411 * so that 1496/88 * 44MHz = 748MHz. 1412 */ 1413 atw_si4126_write(sc, SI4126_IFN, 1496); 1414 1415 atw_si4126_write(sc, SI4126_IFR, R); 1416 1417 #ifndef ATW_REFSLAVE 1418 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1419 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1420 * which has no RF1! 1421 */ 1422 atw_si4126_write(sc, SI4126_RF1R, R); 1423 1424 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1425 #endif 1426 1427 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1428 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1429 * Now let's multiply it to mhz. So mhz - IF = N. 1430 */ 1431 atw_si4126_write(sc, SI4126_RF2R, R); 1432 1433 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1434 1435 /* wait 100us from power-up for RF, IF to settle */ 1436 DELAY(100); 1437 1438 gpio = ATW_READ(sc, ATW_GPIO); 1439 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1440 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1441 1442 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1443 /* Set a Prism RF front-end to a special mode for channel 14? 1444 * 1445 * Apparently the SMC2635W needs this, although I don't think 1446 * it has a Prism RF. 1447 */ 1448 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1449 } 1450 ATW_WRITE(sc, ATW_GPIO, gpio); 1451 1452 #ifdef ATW_SYNDEBUG 1453 atw_si4126_print(sc); 1454 #endif /* ATW_SYNDEBUG */ 1455 } 1456 1457 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1458 * diversity. 1459 * 1460 * !!! 1461 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1462 * !!! 1463 */ 1464 static int 1465 atw_rf3000_init(struct atw_softc *sc) 1466 { 1467 int rc = 0; 1468 1469 atw_bbp_io_enable(sc, 1); 1470 1471 /* CCA is acquisition sensitive */ 1472 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1473 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1474 1475 if (rc != 0) 1476 goto out; 1477 1478 /* enable diversity */ 1479 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1480 1481 if (rc != 0) 1482 goto out; 1483 1484 /* sensible setting from a binary-only driver */ 1485 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1486 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1487 1488 if (rc != 0) 1489 goto out; 1490 1491 /* magic from a binary-only driver */ 1492 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1493 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1494 1495 if (rc != 0) 1496 goto out; 1497 1498 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1499 1500 if (rc != 0) 1501 goto out; 1502 1503 /* XXX Reference driver remarks that Abocom sets this to 50. 1504 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1505 * in the "reserved" area of register RF3000_OPTIONS1. 1506 * 1507 * EEPROMs for the ADM8211B contain a setting for this register. 1508 */ 1509 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1510 1511 if (rc != 0) 1512 goto out; 1513 1514 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1515 1516 if (rc != 0) 1517 goto out; 1518 1519 out: 1520 atw_bbp_io_enable(sc, 0); 1521 return rc; 1522 } 1523 1524 #ifdef ATW_BBPDEBUG 1525 static void 1526 atw_rf3000_print(struct atw_softc *sc) 1527 { 1528 struct ifnet *ifp = &sc->sc_ic.ic_if; 1529 u_int addr, val; 1530 1531 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1532 return; 1533 1534 for (addr = 0x01; addr <= 0x15; addr++) { 1535 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1536 if (atw_rf3000_read(sc, addr, &val) != 0) { 1537 printf("<unknown> (quitting print-out)\n"); 1538 break; 1539 } 1540 printf("%08x\n", val); 1541 } 1542 } 1543 #endif /* ATW_BBPDEBUG */ 1544 1545 /* Set the power settings on the BBP for channel `chan'. */ 1546 static int 1547 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1548 { 1549 int rc = 0; 1550 u_int32_t reg; 1551 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1552 1553 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1554 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1555 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1556 1557 /* odd channels: LSB, even channels: MSB */ 1558 if (chan % 2 == 1) { 1559 txpower &= 0xFF; 1560 lpf_cutoff &= 0xFF; 1561 lna_gs_thresh &= 0xFF; 1562 } else { 1563 txpower >>= 8; 1564 lpf_cutoff >>= 8; 1565 lna_gs_thresh >>= 8; 1566 } 1567 1568 #ifdef ATW_BBPDEBUG 1569 atw_rf3000_print(sc); 1570 #endif /* ATW_BBPDEBUG */ 1571 1572 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1573 "lna_gs_thresh %02x\n", 1574 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1575 1576 atw_bbp_io_enable(sc, 1); 1577 1578 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1579 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1580 goto out; 1581 1582 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1583 goto out; 1584 1585 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1586 goto out; 1587 1588 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1589 1590 if (rc != 0) 1591 goto out; 1592 1593 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1594 1595 if (rc != 0) 1596 goto out; 1597 1598 #ifdef ATW_BBPDEBUG 1599 atw_rf3000_print(sc); 1600 #endif /* ATW_BBPDEBUG */ 1601 1602 out: 1603 atw_bbp_io_enable(sc, 0); 1604 1605 /* set beacon, rts, atim transmit power */ 1606 reg = ATW_READ(sc, ATW_PLCPHD); 1607 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1608 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1609 ATW_PLCPHD_SERVICE_MASK); 1610 ATW_WRITE(sc, ATW_PLCPHD, reg); 1611 DELAY(2 * 1000); 1612 1613 return rc; 1614 } 1615 1616 /* Write a register on the RF3000 baseband processor using the 1617 * registers provided by the ADM8211 for this purpose. 1618 * 1619 * Return 0 on success. 1620 */ 1621 static int 1622 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1623 { 1624 u_int32_t reg; 1625 int i; 1626 1627 reg = sc->sc_bbpctl_wr | 1628 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1629 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1630 1631 for (i = 10; --i >= 0; ) { 1632 ATW_WRITE(sc, ATW_BBPCTL, reg); 1633 DELAY(2000); 1634 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1635 break; 1636 } 1637 1638 if (i < 0) { 1639 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1640 return ETIMEDOUT; 1641 } 1642 return 0; 1643 } 1644 1645 /* Read a register on the RF3000 baseband processor using the registers 1646 * the ADM8211 provides for this purpose. 1647 * 1648 * The 7-bit register address is addr. Record the 8-bit data in the register 1649 * in *val. 1650 * 1651 * Return 0 on success. 1652 * 1653 * XXX This does not seem to work. The ADM8211 must require more or 1654 * different magic to read the chip than to write it. Possibly some 1655 * of the magic I have derived from a binary-only driver concerns 1656 * the "chip address" (see the RF3000 manual). 1657 */ 1658 #ifdef ATW_BBPDEBUG 1659 static int 1660 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1661 { 1662 u_int32_t reg; 1663 int i; 1664 1665 for (i = 1000; --i >= 0; ) { 1666 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1667 break; 1668 DELAY(100); 1669 } 1670 1671 if (i < 0) { 1672 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1673 sc->sc_dev.dv_xname); 1674 return ETIMEDOUT; 1675 } 1676 1677 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1678 1679 ATW_WRITE(sc, ATW_BBPCTL, reg); 1680 1681 for (i = 1000; --i >= 0; ) { 1682 DELAY(100); 1683 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1684 break; 1685 } 1686 1687 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1688 1689 if (i < 0) { 1690 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1691 sc->sc_dev.dv_xname, reg); 1692 return ETIMEDOUT; 1693 } 1694 if (val != NULL) 1695 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1696 return 0; 1697 } 1698 #endif /* ATW_BBPDEBUG */ 1699 1700 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1701 * provided by the ADM8211 for that purpose. 1702 * 1703 * val is 18 bits of data, and val is the 4-bit address of the register. 1704 * 1705 * Return 0 on success. 1706 */ 1707 static void 1708 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1709 { 1710 uint32_t bits, mask, reg; 1711 const int nbits = 22; 1712 1713 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1714 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1715 1716 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1717 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1718 1719 reg = ATW_SYNRF_SELSYN; 1720 /* reference driver: reset Si4126 serial bus to initial 1721 * conditions? 1722 */ 1723 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1724 ATW_WRITE(sc, ATW_SYNRF, reg); 1725 1726 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1727 if ((bits & mask) != 0) 1728 reg |= ATW_SYNRF_SYNDATA; 1729 else 1730 reg &= ~ATW_SYNRF_SYNDATA; 1731 ATW_WRITE(sc, ATW_SYNRF, reg); 1732 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1733 ATW_WRITE(sc, ATW_SYNRF, reg); 1734 } 1735 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1736 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1737 } 1738 1739 /* Read 18-bit data from the 4-bit address addr in Si4126 1740 * RF synthesizer and write the data to *val. Return 0 on success. 1741 * 1742 * XXX This does not seem to work. The ADM8211 must require more or 1743 * different magic to read the chip than to write it. 1744 */ 1745 #ifdef ATW_SYNDEBUG 1746 static int 1747 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1748 { 1749 u_int32_t reg; 1750 int i; 1751 1752 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1753 1754 for (i = 1000; --i >= 0; ) { 1755 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1756 break; 1757 DELAY(100); 1758 } 1759 1760 if (i < 0) { 1761 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1762 sc->sc_dev.dv_xname); 1763 return ETIMEDOUT; 1764 } 1765 1766 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1767 1768 ATW_WRITE(sc, ATW_SYNCTL, reg); 1769 1770 for (i = 1000; --i >= 0; ) { 1771 DELAY(100); 1772 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1773 break; 1774 } 1775 1776 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1777 1778 if (i < 0) { 1779 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1780 sc->sc_dev.dv_xname, reg); 1781 return ETIMEDOUT; 1782 } 1783 if (val != NULL) 1784 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1785 ATW_SYNCTL_DATA_MASK); 1786 return 0; 1787 } 1788 #endif /* ATW_SYNDEBUG */ 1789 1790 /* XXX is the endianness correct? test. */ 1791 #define atw_calchash(addr) \ 1792 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1793 1794 /* 1795 * atw_filter_setup: 1796 * 1797 * Set the ADM8211's receive filter. 1798 */ 1799 static void 1800 atw_filter_setup(struct atw_softc *sc) 1801 { 1802 struct ieee80211com *ic = &sc->sc_ic; 1803 struct ethercom *ec = &ic->ic_ec; 1804 struct ifnet *ifp = &sc->sc_ic.ic_if; 1805 int hash; 1806 u_int32_t hashes[2]; 1807 struct ether_multi *enm; 1808 struct ether_multistep step; 1809 1810 /* According to comments in tlp_al981_filter_setup 1811 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1812 * multicast filter to be set while it is running. Hopefully 1813 * the ADM8211 is not the same! 1814 */ 1815 if ((ifp->if_flags & IFF_RUNNING) != 0) 1816 atw_idle(sc, ATW_NAR_SR); 1817 1818 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1819 1820 /* XXX in scan mode, do not filter packets. Maybe this is 1821 * unnecessary. 1822 */ 1823 if (ic->ic_state == IEEE80211_S_SCAN || 1824 (ifp->if_flags & IFF_PROMISC) != 0) { 1825 sc->sc_opmode |= ATW_NAR_PR; 1826 goto allmulti; 1827 } 1828 1829 hashes[0] = hashes[1] = 0x0; 1830 1831 /* 1832 * Program the 64-bit multicast hash filter. 1833 */ 1834 ETHER_FIRST_MULTI(step, ec, enm); 1835 while (enm != NULL) { 1836 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1837 ETHER_ADDR_LEN) != 0) 1838 goto allmulti; 1839 1840 hash = atw_calchash(enm->enm_addrlo); 1841 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1842 ETHER_NEXT_MULTI(step, enm); 1843 } 1844 ifp->if_flags &= ~IFF_ALLMULTI; 1845 goto setit; 1846 1847 allmulti: 1848 ifp->if_flags |= IFF_ALLMULTI; 1849 hashes[0] = hashes[1] = 0xffffffff; 1850 1851 setit: 1852 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1853 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1854 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1855 DELAY(20 * 1000); 1856 1857 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1858 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1859 } 1860 1861 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1862 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1863 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1864 * no beacon with the preferred BSSID and SSID in the number of 1865 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1866 */ 1867 static void 1868 atw_write_bssid(struct atw_softc *sc) 1869 { 1870 struct ieee80211com *ic = &sc->sc_ic; 1871 u_int8_t *bssid; 1872 1873 bssid = ic->ic_bss->ni_bssid; 1874 1875 ATW_WRITE(sc, ATW_BSSID0, 1876 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1877 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1878 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1879 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1880 1881 ATW_WRITE(sc, ATW_ABDA1, 1882 (ATW_READ(sc, ATW_ABDA1) & 1883 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1884 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1885 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1886 1887 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1888 ether_sprintf(sc->sc_bssid))); 1889 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1890 1891 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1892 } 1893 1894 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1895 * 16-bit word. 1896 */ 1897 static void 1898 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1899 { 1900 u_int i; 1901 u_int8_t *ptr; 1902 1903 memcpy(&sc->sc_sram[ofs], buf, buflen); 1904 1905 if (ofs % 2 != 0) { 1906 ofs--; 1907 buflen++; 1908 } 1909 1910 if (buflen % 2 != 0) 1911 buflen++; 1912 1913 assert(buflen + ofs <= ATW_SRAM_SIZE); 1914 1915 ptr = &sc->sc_sram[ofs]; 1916 1917 for (i = 0; i < buflen; i += 2) { 1918 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1919 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1920 DELAY(atw_writewep_delay); 1921 1922 ATW_WRITE(sc, ATW_WESK, 1923 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1924 DELAY(atw_writewep_delay); 1925 } 1926 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1927 1928 if (sc->sc_if.if_flags & IFF_DEBUG) { 1929 int n_octets = 0; 1930 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1931 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1932 for (i = 0; i < buflen; i++) { 1933 printf(" %02x", ptr[i]); 1934 if (++n_octets % 24 == 0) 1935 printf("\n"); 1936 } 1937 if (n_octets % 24 != 0) 1938 printf("\n"); 1939 } 1940 } 1941 1942 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 1943 static void 1944 atw_write_wep(struct atw_softc *sc) 1945 { 1946 struct ieee80211com *ic = &sc->sc_ic; 1947 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 1948 u_int8_t buf[IEEE80211_WEP_NKID] 1949 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 1950 u_int32_t reg; 1951 int i; 1952 1953 sc->sc_wepctl = 0; 1954 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 1955 1956 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 1957 return; 1958 1959 memset(&buf[0][0], 0, sizeof(buf)); 1960 1961 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1962 if (ic->ic_nw_keys[i].wk_len > 5) { 1963 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 1964 } else if (ic->ic_nw_keys[i].wk_len != 0) { 1965 buf[i][1] = ATW_WEP_ENABLED; 1966 } else { 1967 buf[i][1] = 0; 1968 continue; 1969 } 1970 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 1971 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 1972 ic->ic_nw_keys[i].wk_len - 1); 1973 } 1974 1975 reg = ATW_READ(sc, ATW_MACTEST); 1976 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 1977 reg &= ~ATW_MACTEST_KEYID_MASK; 1978 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 1979 ATW_WRITE(sc, ATW_MACTEST, reg); 1980 1981 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 1982 * throughout.) 1983 */ 1984 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 1985 if (sc->sc_if.if_flags & IFF_LINK2) 1986 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 1987 1988 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 1989 sizeof(buf)); 1990 } 1991 1992 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 1993 1994 static void 1995 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 1996 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 1997 { 1998 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 1999 2000 switch (subtype) { 2001 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2002 /* do nothing: hardware answers probe request */ 2003 break; 2004 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2005 case IEEE80211_FC0_SUBTYPE_BEACON: 2006 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2007 break; 2008 default: 2009 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2010 break; 2011 } 2012 return; 2013 } 2014 2015 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2016 * of IBSSs with like SSID/channel but different BSSID. It joins the 2017 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2018 * convention. Possibly the ADMtek chip does this for us; I will have 2019 * to test to find out. 2020 * 2021 * XXX we should add the duration field of the received beacon to 2022 * the TSF time it contains before comparing it with the ADM8211's 2023 * TSF. 2024 */ 2025 static void 2026 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2027 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2028 { 2029 struct atw_softc *sc; 2030 struct ieee80211_frame *wh; 2031 uint32_t tsftl, tsfth; 2032 uint32_t bcn_tsftl, bcn_tsfth; 2033 int do_print = 0; 2034 union { 2035 uint32_t words[2]; 2036 uint8_t tstamp[8]; 2037 } u; 2038 2039 sc = (struct atw_softc*)ic->ic_if.if_softc; 2040 2041 if (ic->ic_if.if_flags & IFF_LINK0) { 2042 do_print = (ic->ic_if.if_flags & IFF_DEBUG) 2043 ? 1 : ratecheck(&sc->sc_last_beacon, 2044 &atw_beacon_mininterval); 2045 } 2046 2047 wh = mtod(m0, struct ieee80211_frame *); 2048 2049 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2050 2051 if (ic->ic_state != IEEE80211_S_RUN) 2052 return; 2053 2054 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2055 ic->ic_bss->ni_chan)) == NULL) { 2056 if (do_print) 2057 printf("%s: atw_recv_beacon: no node %s\n", 2058 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2059 return; 2060 } 2061 2062 if (ieee80211_match_bss(ic, ni) != 0) 2063 return; 2064 2065 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2066 return; 2067 2068 if (do_print) 2069 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2070 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2071 2072 if (ic->ic_opmode != IEEE80211_M_IBSS) 2073 return; 2074 2075 atw_tsft(sc, &tsfth, &tsftl); 2076 2077 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2078 bcn_tsftl = le32toh(u.words[0]); 2079 bcn_tsfth = le32toh(u.words[1]); 2080 2081 if (do_print) 2082 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2083 sc->sc_dev.dv_xname, ((uint64_t)tsfth << 32) | tsftl, 2084 ((uint64_t)bcn_tsfth << 32) | bcn_tsftl); 2085 2086 /* we are faster, let the other guy catch up */ 2087 if (bcn_tsfth < tsfth) 2088 return; 2089 else if (bcn_tsfth == tsfth && bcn_tsftl < tsftl) 2090 return; 2091 2092 if (do_print) 2093 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2094 ether_sprintf(wh->i_addr2)); 2095 2096 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2097 2098 atw_tsf(sc); 2099 2100 /* negotiate rates with new IBSS */ 2101 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2102 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2103 if (ni->ni_rates.rs_nrates == 0) { 2104 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2105 ether_sprintf(ni->ni_bssid)); 2106 return; 2107 } 2108 2109 if (do_print) { 2110 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2111 ether_sprintf(ic->ic_bss->ni_bssid)); 2112 printf("%s ", ether_sprintf(ni->ni_bssid)); 2113 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2114 } 2115 2116 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2117 2118 atw_write_bssid(sc); 2119 atw_start_beacon(sc, 1); 2120 } 2121 2122 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2123 * In ad hoc mode, the SSID is written to the beacons sent by the 2124 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2125 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2126 * indications. 2127 */ 2128 static void 2129 atw_write_ssid(struct atw_softc *sc) 2130 { 2131 struct ieee80211com *ic = &sc->sc_ic; 2132 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2133 * it only expects the element length, not its ID. 2134 */ 2135 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2136 2137 memset(buf, 0, sizeof(buf)); 2138 buf[0] = ic->ic_bss->ni_esslen; 2139 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2140 2141 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2142 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2143 } 2144 2145 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2146 * In ad hoc mode, the supported rates are written to beacons sent by the 2147 * ADM8211. 2148 */ 2149 static void 2150 atw_write_sup_rates(struct atw_softc *sc) 2151 { 2152 struct ieee80211com *ic = &sc->sc_ic; 2153 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2154 * supported rates 2155 */ 2156 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2157 2158 memset(buf, 0, sizeof(buf)); 2159 2160 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2161 2162 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2163 ic->ic_bss->ni_rates.rs_nrates); 2164 2165 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2166 } 2167 2168 /* Start/stop sending beacons. */ 2169 void 2170 atw_start_beacon(struct atw_softc *sc, int start) 2171 { 2172 struct ieee80211com *ic = &sc->sc_ic; 2173 uint16_t chan; 2174 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2175 size_t len; 2176 2177 if (ATW_IS_ENABLED(sc) == 0) 2178 return; 2179 2180 /* start beacons */ 2181 len = sizeof(struct ieee80211_frame) + 2182 8 /* timestamp */ + 2 /* beacon interval */ + 2183 2 /* capability info */ + 2184 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2185 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2186 3 /* DS parameters */ + 2187 IEEE80211_CRC_LEN; 2188 2189 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2190 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2191 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2192 2193 ATW_WRITE(sc, ATW_BCNT, bcnt); 2194 ATW_WRITE(sc, ATW_CAP1, cap1); 2195 2196 if (!start) 2197 return; 2198 2199 /* TBD use ni_capinfo */ 2200 2201 capinfo = 0; 2202 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2203 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2204 if (ic->ic_flags & IEEE80211_F_WEPON) 2205 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2206 2207 switch (ic->ic_opmode) { 2208 case IEEE80211_M_IBSS: 2209 len += 4; /* IBSS parameters */ 2210 capinfo |= IEEE80211_CAPINFO_IBSS; 2211 break; 2212 case IEEE80211_M_HOSTAP: 2213 /* XXX 6-byte minimum TIM */ 2214 len += atw_beacon_len_adjust; 2215 capinfo |= IEEE80211_CAPINFO_ESS; 2216 break; 2217 default: 2218 return; 2219 } 2220 2221 /* set listen interval 2222 * XXX do software units agree w/ hardware? 2223 */ 2224 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2225 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2226 2227 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2228 2229 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2230 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2231 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2232 2233 ATW_WRITE(sc, ATW_BCNT, bcnt); 2234 ATW_WRITE(sc, ATW_BPLI, bpli); 2235 ATW_WRITE(sc, ATW_CAP0, cap0); 2236 ATW_WRITE(sc, ATW_CAP1, cap1); 2237 2238 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2239 sc->sc_dev.dv_xname, bcnt)); 2240 2241 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2242 sc->sc_dev.dv_xname, cap1)); 2243 } 2244 2245 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2246 static __inline uint32_t 2247 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2248 { 2249 /* Following the reference driver's lead, I compute 2250 * 2251 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2252 * 2253 * without using 64-bit arithmetic, using the following 2254 * relationship: 2255 * 2256 * (0x100000000 * H + L) % m 2257 * = ((0x100000000 % m) * H + L) % m 2258 * = (((0xffffffff + 1) % m) * H + L) % m 2259 * = ((0xffffffff % m + 1 % m) * H + L) % m 2260 * = ((0xffffffff % m + 1) * H + L) % m 2261 */ 2262 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2263 } 2264 2265 static __inline void 2266 atw_tsft(struct atw_softc *sc, uint32_t *tsfth, uint32_t *tsftl) 2267 { 2268 int i; 2269 for (i = 0; i < 2; i++) { 2270 *tsfth = ATW_READ(sc, ATW_TSFTH); 2271 *tsftl = ATW_READ(sc, ATW_TSFTL); 2272 if (ATW_READ(sc, ATW_TSFTH) == *tsfth) 2273 break; 2274 } 2275 } 2276 2277 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2278 * the ieee80211com. 2279 * 2280 * Predict the next target beacon transmission time (TBTT) and 2281 * write it to the ADM8211. 2282 */ 2283 static void 2284 atw_tsf(struct atw_softc *sc) 2285 { 2286 #define TBTTOFS 20 /* TU */ 2287 2288 struct ieee80211com *ic = &sc->sc_ic; 2289 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2290 union { 2291 uint32_t words[2]; 2292 uint8_t tstamp[8]; 2293 } u; 2294 2295 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2296 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2297 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2298 atw_tsft(sc, &tsfth, &tsftl); 2299 u.words[0] = htole32(tsftl); 2300 u.words[1] = htole32(tsfth); 2301 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u, 2302 sizeof(ic->ic_bss->ni_tstamp)); 2303 } else { 2304 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2305 tsftl = le32toh(u.words[0]); 2306 tsfth = le32toh(u.words[1]); 2307 } 2308 2309 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2310 2311 /* We sent/received the last beacon `past' microseconds 2312 * after the interval divided the TSF timer. 2313 */ 2314 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2315 2316 /* Skip ten beacons so that the TBTT cannot pass before 2317 * we've programmed it. Ten is an arbitrary number. 2318 */ 2319 tbtt = past_even + ival * 10; 2320 2321 ATW_WRITE(sc, ATW_TOFS1, 2322 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2323 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2324 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2325 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2326 #undef TBTTOFS 2327 } 2328 2329 static void 2330 atw_next_scan(void *arg) 2331 { 2332 struct atw_softc *sc = arg; 2333 struct ieee80211com *ic = &sc->sc_ic; 2334 struct ifnet *ifp = &ic->ic_if; 2335 int s; 2336 2337 /* don't call atw_start w/o network interrupts blocked */ 2338 s = splnet(); 2339 if (ic->ic_state == IEEE80211_S_SCAN) 2340 ieee80211_next_scan(ifp); 2341 splx(s); 2342 } 2343 2344 /* Synchronize the hardware state with the software state. */ 2345 static int 2346 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2347 { 2348 struct ifnet *ifp = &ic->ic_if; 2349 struct atw_softc *sc = ifp->if_softc; 2350 enum ieee80211_state ostate; 2351 int error; 2352 2353 ostate = ic->ic_state; 2354 2355 if (nstate == IEEE80211_S_INIT) { 2356 callout_stop(&sc->sc_scan_ch); 2357 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2358 atw_start_beacon(sc, 0); 2359 return (*sc->sc_newstate)(ic, nstate, arg); 2360 } 2361 2362 if ((error = atw_tune(sc)) != 0) 2363 return error; 2364 2365 switch (nstate) { 2366 case IEEE80211_S_ASSOC: 2367 break; 2368 case IEEE80211_S_INIT: 2369 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2370 break; 2371 case IEEE80211_S_SCAN: 2372 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2373 atw_next_scan, sc); 2374 2375 break; 2376 case IEEE80211_S_RUN: 2377 if (ic->ic_opmode == IEEE80211_M_STA) 2378 break; 2379 /*FALLTHROUGH*/ 2380 case IEEE80211_S_AUTH: 2381 atw_write_bssid(sc); 2382 atw_write_ssid(sc); 2383 atw_write_sup_rates(sc); 2384 2385 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2386 ic->ic_opmode == IEEE80211_M_MONITOR) 2387 break; 2388 2389 /* set listen interval 2390 * XXX do software units agree w/ hardware? 2391 */ 2392 ATW_WRITE(sc, ATW_BPLI, 2393 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2394 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2395 ATW_BPLI_LI_MASK)); 2396 2397 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2398 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2399 2400 atw_tsf(sc); 2401 break; 2402 } 2403 2404 if (nstate != IEEE80211_S_SCAN) 2405 callout_stop(&sc->sc_scan_ch); 2406 2407 if (nstate == IEEE80211_S_RUN && 2408 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2409 ic->ic_opmode == IEEE80211_M_IBSS)) 2410 atw_start_beacon(sc, 1); 2411 else 2412 atw_start_beacon(sc, 0); 2413 2414 error = (*sc->sc_newstate)(ic, nstate, arg); 2415 2416 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2417 atw_write_bssid(sc); 2418 2419 return error; 2420 } 2421 2422 /* 2423 * atw_add_rxbuf: 2424 * 2425 * Add a receive buffer to the indicated descriptor. 2426 */ 2427 int 2428 atw_add_rxbuf(struct atw_softc *sc, int idx) 2429 { 2430 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2431 struct mbuf *m; 2432 int error; 2433 2434 MGETHDR(m, M_DONTWAIT, MT_DATA); 2435 if (m == NULL) 2436 return (ENOBUFS); 2437 2438 MCLGET(m, M_DONTWAIT); 2439 if ((m->m_flags & M_EXT) == 0) { 2440 m_freem(m); 2441 return (ENOBUFS); 2442 } 2443 2444 if (rxs->rxs_mbuf != NULL) 2445 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2446 2447 rxs->rxs_mbuf = m; 2448 2449 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2450 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2451 BUS_DMA_READ|BUS_DMA_NOWAIT); 2452 if (error) { 2453 printf("%s: can't load rx DMA map %d, error = %d\n", 2454 sc->sc_dev.dv_xname, idx, error); 2455 panic("atw_add_rxbuf"); /* XXX */ 2456 } 2457 2458 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2459 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2460 2461 ATW_INIT_RXDESC(sc, idx); 2462 2463 return (0); 2464 } 2465 2466 /* 2467 * Release any queued transmit buffers. 2468 */ 2469 void 2470 atw_txdrain(struct atw_softc *sc) 2471 { 2472 struct atw_txsoft *txs; 2473 2474 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2475 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2476 if (txs->txs_mbuf != NULL) { 2477 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2478 m_freem(txs->txs_mbuf); 2479 txs->txs_mbuf = NULL; 2480 } 2481 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2482 } 2483 sc->sc_tx_timer = 0; 2484 } 2485 2486 /* 2487 * atw_stop: [ ifnet interface function ] 2488 * 2489 * Stop transmission on the interface. 2490 */ 2491 void 2492 atw_stop(struct ifnet *ifp, int disable) 2493 { 2494 struct atw_softc *sc = ifp->if_softc; 2495 struct ieee80211com *ic = &sc->sc_ic; 2496 2497 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2498 2499 /* Disable interrupts. */ 2500 ATW_WRITE(sc, ATW_IER, 0); 2501 2502 /* Stop the transmit and receive processes. */ 2503 sc->sc_opmode = 0; 2504 ATW_WRITE(sc, ATW_NAR, 0); 2505 DELAY(20 * 1000); 2506 ATW_WRITE(sc, ATW_TDBD, 0); 2507 ATW_WRITE(sc, ATW_TDBP, 0); 2508 ATW_WRITE(sc, ATW_RDB, 0); 2509 2510 atw_txdrain(sc); 2511 2512 if (disable) { 2513 atw_rxdrain(sc); 2514 atw_disable(sc); 2515 } 2516 2517 /* 2518 * Mark the interface down and cancel the watchdog timer. 2519 */ 2520 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2521 ifp->if_timer = 0; 2522 2523 if (!disable) 2524 atw_reset(sc); 2525 } 2526 2527 /* 2528 * atw_rxdrain: 2529 * 2530 * Drain the receive queue. 2531 */ 2532 void 2533 atw_rxdrain(struct atw_softc *sc) 2534 { 2535 struct atw_rxsoft *rxs; 2536 int i; 2537 2538 for (i = 0; i < ATW_NRXDESC; i++) { 2539 rxs = &sc->sc_rxsoft[i]; 2540 if (rxs->rxs_mbuf == NULL) 2541 continue; 2542 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2543 m_freem(rxs->rxs_mbuf); 2544 rxs->rxs_mbuf = NULL; 2545 } 2546 } 2547 2548 /* 2549 * atw_detach: 2550 * 2551 * Detach an ADM8211 interface. 2552 */ 2553 int 2554 atw_detach(struct atw_softc *sc) 2555 { 2556 struct ifnet *ifp = &sc->sc_ic.ic_if; 2557 struct atw_rxsoft *rxs; 2558 struct atw_txsoft *txs; 2559 int i; 2560 2561 /* 2562 * Succeed now if there isn't any work to do. 2563 */ 2564 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2565 return (0); 2566 2567 ieee80211_ifdetach(ifp); 2568 if_detach(ifp); 2569 2570 for (i = 0; i < ATW_NRXDESC; i++) { 2571 rxs = &sc->sc_rxsoft[i]; 2572 if (rxs->rxs_mbuf != NULL) { 2573 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2574 m_freem(rxs->rxs_mbuf); 2575 rxs->rxs_mbuf = NULL; 2576 } 2577 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2578 } 2579 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2580 txs = &sc->sc_txsoft[i]; 2581 if (txs->txs_mbuf != NULL) { 2582 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2583 m_freem(txs->txs_mbuf); 2584 txs->txs_mbuf = NULL; 2585 } 2586 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2587 } 2588 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2589 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2590 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2591 sizeof(struct atw_control_data)); 2592 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2593 2594 shutdownhook_disestablish(sc->sc_sdhook); 2595 powerhook_disestablish(sc->sc_powerhook); 2596 2597 if (sc->sc_srom) 2598 free(sc->sc_srom, M_DEVBUF); 2599 2600 return (0); 2601 } 2602 2603 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2604 void 2605 atw_shutdown(void *arg) 2606 { 2607 struct atw_softc *sc = arg; 2608 2609 atw_stop(&sc->sc_ic.ic_if, 1); 2610 } 2611 2612 int 2613 atw_intr(void *arg) 2614 { 2615 struct atw_softc *sc = arg; 2616 struct ifnet *ifp = &sc->sc_ic.ic_if; 2617 u_int32_t status, rxstatus, txstatus, linkstatus; 2618 int handled = 0, txthresh; 2619 2620 #ifdef DEBUG 2621 if (ATW_IS_ENABLED(sc) == 0) 2622 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2623 #endif 2624 2625 /* 2626 * If the interface isn't running, the interrupt couldn't 2627 * possibly have come from us. 2628 */ 2629 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2630 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2631 return (0); 2632 2633 for (;;) { 2634 status = ATW_READ(sc, ATW_STSR); 2635 2636 if (status) 2637 ATW_WRITE(sc, ATW_STSR, status); 2638 2639 #ifdef ATW_DEBUG 2640 #define PRINTINTR(flag) do { \ 2641 if ((status & flag) != 0) { \ 2642 printf("%s" #flag, delim); \ 2643 delim = ","; \ 2644 } \ 2645 } while (0) 2646 2647 if (atw_debug > 1 && status) { 2648 const char *delim = "<"; 2649 2650 printf("%s: reg[STSR] = %x", 2651 sc->sc_dev.dv_xname, status); 2652 2653 PRINTINTR(ATW_INTR_FBE); 2654 PRINTINTR(ATW_INTR_LINKOFF); 2655 PRINTINTR(ATW_INTR_LINKON); 2656 PRINTINTR(ATW_INTR_RCI); 2657 PRINTINTR(ATW_INTR_RDU); 2658 PRINTINTR(ATW_INTR_REIS); 2659 PRINTINTR(ATW_INTR_RPS); 2660 PRINTINTR(ATW_INTR_TCI); 2661 PRINTINTR(ATW_INTR_TDU); 2662 PRINTINTR(ATW_INTR_TLT); 2663 PRINTINTR(ATW_INTR_TPS); 2664 PRINTINTR(ATW_INTR_TRT); 2665 PRINTINTR(ATW_INTR_TUF); 2666 PRINTINTR(ATW_INTR_BCNTC); 2667 PRINTINTR(ATW_INTR_ATIME); 2668 PRINTINTR(ATW_INTR_TBTT); 2669 PRINTINTR(ATW_INTR_TSCZ); 2670 PRINTINTR(ATW_INTR_TSFTF); 2671 printf(">\n"); 2672 } 2673 #undef PRINTINTR 2674 #endif /* ATW_DEBUG */ 2675 2676 if ((status & sc->sc_inten) == 0) 2677 break; 2678 2679 handled = 1; 2680 2681 rxstatus = status & sc->sc_rxint_mask; 2682 txstatus = status & sc->sc_txint_mask; 2683 linkstatus = status & sc->sc_linkint_mask; 2684 2685 if (linkstatus) { 2686 atw_linkintr(sc, linkstatus); 2687 } 2688 2689 if (rxstatus) { 2690 /* Grab any new packets. */ 2691 atw_rxintr(sc); 2692 2693 if (rxstatus & ATW_INTR_RDU) { 2694 printf("%s: receive ring overrun\n", 2695 sc->sc_dev.dv_xname); 2696 /* Get the receive process going again. */ 2697 ATW_WRITE(sc, ATW_RDR, 0x1); 2698 break; 2699 } 2700 } 2701 2702 if (txstatus) { 2703 /* Sweep up transmit descriptors. */ 2704 atw_txintr(sc); 2705 2706 if (txstatus & ATW_INTR_TLT) 2707 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2708 sc->sc_dev.dv_xname)); 2709 2710 if (txstatus & ATW_INTR_TRT) 2711 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2712 sc->sc_dev.dv_xname)); 2713 2714 /* If Tx under-run, increase our transmit threshold 2715 * if another is available. 2716 */ 2717 txthresh = sc->sc_txthresh + 1; 2718 if ((txstatus & ATW_INTR_TUF) && 2719 sc->sc_txth[txthresh].txth_name != NULL) { 2720 /* Idle the transmit process. */ 2721 atw_idle(sc, ATW_NAR_ST); 2722 2723 sc->sc_txthresh = txthresh; 2724 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2725 sc->sc_opmode |= 2726 sc->sc_txth[txthresh].txth_opmode; 2727 printf("%s: transmit underrun; new " 2728 "threshold: %s\n", sc->sc_dev.dv_xname, 2729 sc->sc_txth[txthresh].txth_name); 2730 2731 /* Set the new threshold and restart 2732 * the transmit process. 2733 */ 2734 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2735 DELAY(20 * 1000); 2736 ATW_WRITE(sc, ATW_RDR, 0x1); 2737 /* XXX Log every Nth underrun from 2738 * XXX now on? 2739 */ 2740 } 2741 } 2742 2743 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2744 if (status & ATW_INTR_TPS) 2745 printf("%s: transmit process stopped\n", 2746 sc->sc_dev.dv_xname); 2747 if (status & ATW_INTR_RPS) 2748 printf("%s: receive process stopped\n", 2749 sc->sc_dev.dv_xname); 2750 (void)atw_init(ifp); 2751 break; 2752 } 2753 2754 if (status & ATW_INTR_FBE) { 2755 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2756 (void)atw_init(ifp); 2757 break; 2758 } 2759 2760 /* 2761 * Not handled: 2762 * 2763 * Transmit buffer unavailable -- normal 2764 * condition, nothing to do, really. 2765 * 2766 * Early receive interrupt -- not available on 2767 * all chips, we just use RI. We also only 2768 * use single-segment receive DMA, so this 2769 * is mostly useless. 2770 * 2771 * TBD others 2772 */ 2773 } 2774 2775 /* Try to get more packets going. */ 2776 atw_start(ifp); 2777 2778 return (handled); 2779 } 2780 2781 /* 2782 * atw_idle: 2783 * 2784 * Cause the transmit and/or receive processes to go idle. 2785 * 2786 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2787 * process in STSR if I clear SR or ST after the process has already 2788 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2789 * do not seem to be too reliable. Perhaps I have the sense of the 2790 * Rx bits switched with the Tx bits? 2791 */ 2792 void 2793 atw_idle(struct atw_softc *sc, u_int32_t bits) 2794 { 2795 u_int32_t ackmask = 0, opmode, stsr, test0; 2796 int i, s; 2797 2798 s = splnet(); 2799 2800 opmode = sc->sc_opmode & ~bits; 2801 2802 if (bits & ATW_NAR_SR) 2803 ackmask |= ATW_INTR_RPS; 2804 2805 if (bits & ATW_NAR_ST) { 2806 ackmask |= ATW_INTR_TPS; 2807 /* set ATW_NAR_HF to flush TX FIFO. */ 2808 opmode |= ATW_NAR_HF; 2809 } 2810 2811 ATW_WRITE(sc, ATW_NAR, opmode); 2812 DELAY(20 * 1000); 2813 2814 for (i = 0; i < 10; i++) { 2815 stsr = ATW_READ(sc, ATW_STSR); 2816 if ((stsr & ackmask) == ackmask) 2817 break; 2818 DELAY(1000); 2819 } 2820 2821 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2822 2823 if ((stsr & ackmask) == ackmask) 2824 goto out; 2825 2826 test0 = ATW_READ(sc, ATW_TEST0); 2827 2828 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2829 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2830 printf("%s: transmit process not idle [%s]\n", 2831 sc->sc_dev.dv_xname, 2832 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2833 printf("%s: bits %08x test0 %08x stsr %08x\n", 2834 sc->sc_dev.dv_xname, bits, test0, stsr); 2835 } 2836 2837 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2838 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2839 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2840 sc->sc_dev.dv_xname, 2841 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2842 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2843 sc->sc_dev.dv_xname, bits, test0, stsr)); 2844 } 2845 out: 2846 if ((bits & ATW_NAR_ST) != 0) 2847 atw_txdrain(sc); 2848 splx(s); 2849 return; 2850 } 2851 2852 /* 2853 * atw_linkintr: 2854 * 2855 * Helper; handle link-status interrupts. 2856 */ 2857 void 2858 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2859 { 2860 struct ieee80211com *ic = &sc->sc_ic; 2861 2862 if (ic->ic_state != IEEE80211_S_RUN) 2863 return; 2864 2865 if (linkstatus & ATW_INTR_LINKON) { 2866 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2867 sc->sc_rescan_timer = 0; 2868 } else if (linkstatus & ATW_INTR_LINKOFF) { 2869 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2870 if (ic->ic_opmode != IEEE80211_M_STA) 2871 return; 2872 sc->sc_rescan_timer = 3; 2873 ic->ic_if.if_timer = 1; 2874 } 2875 } 2876 2877 /* 2878 * atw_rxintr: 2879 * 2880 * Helper; handle receive interrupts. 2881 */ 2882 void 2883 atw_rxintr(struct atw_softc *sc) 2884 { 2885 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2886 struct ieee80211com *ic = &sc->sc_ic; 2887 struct ieee80211_node *ni; 2888 struct ieee80211_frame *wh; 2889 struct ifnet *ifp = &ic->ic_if; 2890 struct atw_rxsoft *rxs; 2891 struct mbuf *m; 2892 u_int32_t rxstat; 2893 int i, len, rate, rate0; 2894 u_int32_t rssi; 2895 2896 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2897 rxs = &sc->sc_rxsoft[i]; 2898 2899 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2900 2901 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2902 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2903 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2904 2905 if (rxstat & ATW_RXSTAT_OWN) 2906 break; /* We have processed all receive buffers. */ 2907 2908 DPRINTF3(sc, 2909 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2910 sc->sc_dev.dv_xname, 2911 le32toh(sc->sc_rxdescs[i].ar_stat), 2912 le32toh(sc->sc_rxdescs[i].ar_rssi), 2913 le32toh(sc->sc_rxdescs[i].ar_buf1), 2914 le32toh(sc->sc_rxdescs[i].ar_buf2))); 2915 2916 /* 2917 * Make sure the packet fits in one buffer. This should 2918 * always be the case. 2919 */ 2920 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2921 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2922 printf("%s: incoming packet spilled, resetting\n", 2923 sc->sc_dev.dv_xname); 2924 (void)atw_init(ifp); 2925 return; 2926 } 2927 2928 /* 2929 * If an error occurred, update stats, clear the status 2930 * word, and leave the packet buffer in place. It will 2931 * simply be reused the next time the ring comes around. 2932 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2933 * error. 2934 */ 2935 2936 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2937 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2938 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2939 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2940 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2941 ATW_RXSTAT_ICVE)) != 0)) { 2942 #define PRINTERR(bit, str) \ 2943 if (rxstat & (bit)) \ 2944 printf("%s: receive error: %s\n", \ 2945 sc->sc_dev.dv_xname, str) 2946 ifp->if_ierrors++; 2947 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2948 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2949 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2950 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2951 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2952 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2953 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2954 #undef PRINTERR 2955 ATW_INIT_RXDESC(sc, i); 2956 continue; 2957 } 2958 2959 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2960 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2961 2962 /* 2963 * No errors; receive the packet. Note the ADM8211 2964 * includes the CRC in promiscuous mode. 2965 */ 2966 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2967 2968 /* 2969 * Allocate a new mbuf cluster. If that fails, we are 2970 * out of memory, and must drop the packet and recycle 2971 * the buffer that's already attached to this descriptor. 2972 */ 2973 m = rxs->rxs_mbuf; 2974 if (atw_add_rxbuf(sc, i) != 0) { 2975 ifp->if_ierrors++; 2976 ATW_INIT_RXDESC(sc, i); 2977 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2978 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2979 continue; 2980 } 2981 2982 ifp->if_ipackets++; 2983 if (sc->sc_opmode & ATW_NAR_PR) 2984 m->m_flags |= M_HASFCS; 2985 m->m_pkthdr.rcvif = ifp; 2986 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 2987 2988 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 2989 rate = 0; 2990 else 2991 rate = rate_tbl[rate0]; 2992 2993 #if NBPFILTER > 0 2994 /* Pass this up to any BPF listeners. */ 2995 if (sc->sc_radiobpf != NULL) { 2996 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 2997 2998 tap->ar_rate = rate; 2999 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3000 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3001 3002 /* TBD verify units are dB */ 3003 tap->ar_antsignal = (int)rssi; 3004 /* TBD tap->ar_flags */ 3005 3006 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3007 tap->ar_ihdr.it_len, m); 3008 } 3009 #endif /* NPBFILTER > 0 */ 3010 3011 wh = mtod(m, struct ieee80211_frame *); 3012 ni = ieee80211_find_rxnode(ic, wh); 3013 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3014 /* 3015 * The frame may have caused the node to be marked for 3016 * reclamation (e.g. in response to a DEAUTH message) 3017 * so use free_node here instead of unref_node. 3018 */ 3019 if (ni == ic->ic_bss) 3020 ieee80211_unref_node(&ni); 3021 else 3022 ieee80211_free_node(ic, ni); 3023 } 3024 3025 /* Update the receive pointer. */ 3026 sc->sc_rxptr = i; 3027 } 3028 3029 /* 3030 * atw_txintr: 3031 * 3032 * Helper; handle transmit interrupts. 3033 */ 3034 void 3035 atw_txintr(struct atw_softc *sc) 3036 { 3037 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3038 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3039 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3040 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3041 3042 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3043 struct ifnet *ifp = &sc->sc_ic.ic_if; 3044 struct atw_txsoft *txs; 3045 u_int32_t txstat; 3046 3047 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3048 sc->sc_dev.dv_xname, sc->sc_flags)); 3049 3050 ifp->if_flags &= ~IFF_OACTIVE; 3051 3052 /* 3053 * Go through our Tx list and free mbufs for those 3054 * frames that have been transmitted. 3055 */ 3056 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3057 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3058 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3059 3060 #ifdef ATW_DEBUG 3061 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3062 int i; 3063 printf(" txsoft %p transmit chain:\n", txs); 3064 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3065 txs->txs_ndescs - 1, 3066 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3067 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3068 printf(" descriptor %d:\n", i); 3069 printf(" at_status: 0x%08x\n", 3070 le32toh(sc->sc_txdescs[i].at_stat)); 3071 printf(" at_flags: 0x%08x\n", 3072 le32toh(sc->sc_txdescs[i].at_flags)); 3073 printf(" at_buf1: 0x%08x\n", 3074 le32toh(sc->sc_txdescs[i].at_buf1)); 3075 printf(" at_buf2: 0x%08x\n", 3076 le32toh(sc->sc_txdescs[i].at_buf2)); 3077 if (i == txs->txs_lastdesc) 3078 break; 3079 } 3080 } 3081 #endif 3082 3083 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3084 if (txstat & ATW_TXSTAT_OWN) 3085 break; 3086 3087 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3088 3089 sc->sc_txfree += txs->txs_ndescs; 3090 3091 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3092 0, txs->txs_dmamap->dm_mapsize, 3093 BUS_DMASYNC_POSTWRITE); 3094 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3095 m_freem(txs->txs_mbuf); 3096 txs->txs_mbuf = NULL; 3097 3098 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3099 3100 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3101 (txstat & TXSTAT_ERRMASK) != 0) { 3102 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3103 txstat_buf, sizeof(txstat_buf)); 3104 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3105 txstat_buf, 3106 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3107 } 3108 3109 /* 3110 * Check for errors and collisions. 3111 */ 3112 if (txstat & ATW_TXSTAT_TUF) 3113 sc->sc_stats.ts_tx_tuf++; 3114 if (txstat & ATW_TXSTAT_TLT) 3115 sc->sc_stats.ts_tx_tlt++; 3116 if (txstat & ATW_TXSTAT_TRT) 3117 sc->sc_stats.ts_tx_trt++; 3118 if (txstat & ATW_TXSTAT_TRO) 3119 sc->sc_stats.ts_tx_tro++; 3120 if (txstat & ATW_TXSTAT_SOFBR) { 3121 sc->sc_stats.ts_tx_sofbr++; 3122 } 3123 3124 if ((txstat & ATW_TXSTAT_ES) == 0) 3125 ifp->if_collisions += 3126 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3127 else 3128 ifp->if_oerrors++; 3129 3130 ifp->if_opackets++; 3131 } 3132 3133 /* 3134 * If there are no more pending transmissions, cancel the watchdog 3135 * timer. 3136 */ 3137 if (txs == NULL) 3138 sc->sc_tx_timer = 0; 3139 #undef TXSTAT_ERRMASK 3140 #undef TXSTAT_FMT 3141 } 3142 3143 /* 3144 * atw_watchdog: [ifnet interface function] 3145 * 3146 * Watchdog timer handler. 3147 */ 3148 void 3149 atw_watchdog(struct ifnet *ifp) 3150 { 3151 struct atw_softc *sc = ifp->if_softc; 3152 struct ieee80211com *ic = &sc->sc_ic; 3153 3154 ifp->if_timer = 0; 3155 if (ATW_IS_ENABLED(sc) == 0) 3156 return; 3157 3158 if (sc->sc_rescan_timer) { 3159 if (--sc->sc_rescan_timer == 0) 3160 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3161 } 3162 if (sc->sc_tx_timer) { 3163 if (--sc->sc_tx_timer == 0 && 3164 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3165 printf("%s: transmit timeout\n", ifp->if_xname); 3166 ifp->if_oerrors++; 3167 (void)atw_init(ifp); 3168 atw_start(ifp); 3169 } 3170 } 3171 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3172 ifp->if_timer = 1; 3173 ieee80211_watchdog(ifp); 3174 } 3175 3176 /* Compute the 802.11 Duration field and the PLCP Length fields for 3177 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3178 * Write the fields to the ADM8211 Tx header, frm. 3179 * 3180 * TBD use the fragmentation threshold to find the right duration for 3181 * the first & last fragments. 3182 * 3183 * TBD make certain of the duration fields applied by the ADM8211 to each 3184 * fragment. I think that the ADM8211 knows how to subtract the CTS 3185 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3186 * I also think that the ADM8211 does *some* arithmetic for us, because 3187 * otherwise I think we would have to set a first duration for CTS/first 3188 * fragment, a second duration for fragments between the first and the 3189 * last, and a third duration for the last fragment. 3190 * 3191 * TBD make certain that duration fields reflect addition of FCS/WEP 3192 * and correct duration arithmetic as necessary. 3193 */ 3194 static void 3195 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3196 int len) 3197 { 3198 int remainder; 3199 3200 /* deal also with encrypted fragments */ 3201 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3202 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3203 sc->sc_dev.dv_xname)); 3204 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3205 IEEE80211_WEP_CRCLEN; 3206 } 3207 3208 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3209 * duration (XXX added by MAC?). 3210 */ 3211 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3212 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3213 3214 if (rate <= 4) 3215 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3216 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3217 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3218 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3219 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3220 else 3221 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3222 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3223 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3224 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3225 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3226 3227 /* lengthen duration if long preamble */ 3228 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3229 frm->atw_head_dur += 3230 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3231 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3232 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3233 IEEE80211_DUR_DS_FAST_PLCPHDR); 3234 3235 if (remainder != 0) 3236 frm->atw_head_dur++; 3237 3238 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3239 (rate == 2 || rate == 4)) { 3240 /* derived from Linux: how could this be right? */ 3241 frm->atw_head_plcplen = frm->atw_head_dur; 3242 } else { 3243 frm->atw_head_plcplen = (16 * len) / rate; 3244 remainder = (80 * len) % (rate * 5); 3245 3246 if (remainder != 0) { 3247 frm->atw_head_plcplen++; 3248 3249 /* XXX magic */ 3250 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3251 rate == 22 && remainder <= 30) 3252 frm->atw_head_plcplen |= 0x8000; 3253 } 3254 } 3255 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3256 htole16(frm->atw_head_plcplen); 3257 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3258 } 3259 3260 #ifdef ATW_DEBUG 3261 static void 3262 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3263 { 3264 struct atw_softc *sc = ifp->if_softc; 3265 struct mbuf *m; 3266 int i, noctets = 0; 3267 3268 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3269 m0->m_pkthdr.len); 3270 3271 for (m = m0; m; m = m->m_next) { 3272 if (m->m_len == 0) 3273 continue; 3274 for (i = 0; i < m->m_len; i++) { 3275 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3276 if (++noctets % 24 == 0) 3277 printf("\n"); 3278 } 3279 } 3280 printf("%s%s: %d bytes emitted\n", 3281 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3282 } 3283 #endif /* ATW_DEBUG */ 3284 3285 /* 3286 * atw_start: [ifnet interface function] 3287 * 3288 * Start packet transmission on the interface. 3289 */ 3290 void 3291 atw_start(struct ifnet *ifp) 3292 { 3293 struct atw_softc *sc = ifp->if_softc; 3294 struct ieee80211com *ic = &sc->sc_ic; 3295 struct ieee80211_node *ni; 3296 struct ieee80211_frame *wh; 3297 struct atw_frame *hh; 3298 struct mbuf *m0, *m; 3299 struct atw_txsoft *txs, *last_txs; 3300 struct atw_txdesc *txd; 3301 int do_encrypt, rate; 3302 bus_dmamap_t dmamap; 3303 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3304 3305 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3306 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3307 3308 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3309 return; 3310 3311 /* 3312 * Remember the previous number of free descriptors and 3313 * the first descriptor we'll use. 3314 */ 3315 ofree = sc->sc_txfree; 3316 firsttx = sc->sc_txnext; 3317 3318 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3319 sc->sc_dev.dv_xname, ofree, firsttx)); 3320 3321 /* 3322 * Loop through the send queue, setting up transmit descriptors 3323 * until we drain the queue, or use up all available transmit 3324 * descriptors. 3325 */ 3326 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3327 sc->sc_txfree != 0) { 3328 3329 /* 3330 * Grab a packet off the management queue, if it 3331 * is not empty. Otherwise, from the data queue. 3332 */ 3333 IF_DEQUEUE(&ic->ic_mgtq, m0); 3334 if (m0 != NULL) { 3335 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3336 m0->m_pkthdr.rcvif = NULL; 3337 } else { 3338 /* send no data packets until we are associated */ 3339 if (ic->ic_state != IEEE80211_S_RUN) 3340 break; 3341 IFQ_DEQUEUE(&ifp->if_snd, m0); 3342 if (m0 == NULL) 3343 break; 3344 #if NBPFILTER > 0 3345 if (ifp->if_bpf != NULL) 3346 bpf_mtap(ifp->if_bpf, m0); 3347 #endif /* NBPFILTER > 0 */ 3348 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3349 ifp->if_oerrors++; 3350 break; 3351 } 3352 } 3353 3354 rate = MAX(ieee80211_get_rate(ic), 2); 3355 3356 #if NBPFILTER > 0 3357 /* 3358 * Pass the packet to any BPF listeners. 3359 */ 3360 if (ic->ic_rawbpf != NULL) 3361 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3362 3363 if (sc->sc_radiobpf != NULL) { 3364 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3365 3366 tap->at_rate = rate; 3367 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3368 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3369 3370 /* TBD tap->at_flags */ 3371 3372 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3373 tap->at_ihdr.it_len, m0); 3374 } 3375 #endif /* NBPFILTER > 0 */ 3376 3377 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3378 3379 if (ni != NULL && ni != ic->ic_bss) 3380 ieee80211_free_node(ic, ni); 3381 3382 if (m0 == NULL) { 3383 ifp->if_oerrors++; 3384 break; 3385 } 3386 3387 /* just to make sure. */ 3388 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3389 3390 if (m0 == NULL) { 3391 ifp->if_oerrors++; 3392 break; 3393 } 3394 3395 hh = mtod(m0, struct atw_frame *); 3396 wh = &hh->atw_ihdr; 3397 3398 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3399 3400 /* Copy everything we need from the 802.11 header: 3401 * Frame Control; address 1, address 3, or addresses 3402 * 3 and 4. NIC fills in BSSID, SA. 3403 */ 3404 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3405 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3406 panic("%s: illegal WDS frame", 3407 sc->sc_dev.dv_xname); 3408 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3409 } else 3410 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3411 3412 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3413 3414 /* initialize remaining Tx parameters */ 3415 memset(&hh->u, 0, sizeof(hh->u)); 3416 3417 hh->atw_rate = rate * 5; 3418 /* XXX this could be incorrect if M_FCS. _encap should 3419 * probably strip FCS just in case it sticks around in 3420 * bridged packets. 3421 */ 3422 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3423 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3424 sizeof(struct atw_frame)); 3425 3426 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3427 hh->atw_rtylmt = 3; 3428 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3429 if (do_encrypt) { 3430 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3431 hh->atw_keyid = ic->ic_wep_txkey; 3432 } 3433 3434 /* TBD 4-addr frames */ 3435 atw_frame_setdurs(sc, hh, rate, 3436 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3437 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3438 3439 /* never fragment multicast frames */ 3440 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3441 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3442 } else if (sc->sc_flags & ATWF_RTSCTS) { 3443 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3444 } 3445 3446 #ifdef ATW_DEBUG 3447 hh->atw_fragnum = 0; 3448 3449 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3450 printf("%s: dst = %s, rate = 0x%02x, " 3451 "service = 0x%02x, paylen = 0x%04x\n", 3452 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3453 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3454 3455 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3456 "dur1 = 0x%04x, dur2 = 0x%04x, " 3457 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3458 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3459 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3460 hh->atw_tail_dur, hh->atw_head_dur); 3461 3462 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3463 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3464 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3465 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3466 3467 printf("%s: keyid = %d\n", 3468 sc->sc_dev.dv_xname, hh->atw_keyid); 3469 3470 atw_dump_pkt(ifp, m0); 3471 } 3472 #endif /* ATW_DEBUG */ 3473 3474 dmamap = txs->txs_dmamap; 3475 3476 /* 3477 * Load the DMA map. Copy and try (once) again if the packet 3478 * didn't fit in the alloted number of segments. 3479 */ 3480 for (first = 1; 3481 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3482 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3483 first = 0) { 3484 MGETHDR(m, M_DONTWAIT, MT_DATA); 3485 if (m == NULL) { 3486 printf("%s: unable to allocate Tx mbuf\n", 3487 sc->sc_dev.dv_xname); 3488 break; 3489 } 3490 if (m0->m_pkthdr.len > MHLEN) { 3491 MCLGET(m, M_DONTWAIT); 3492 if ((m->m_flags & M_EXT) == 0) { 3493 printf("%s: unable to allocate Tx " 3494 "cluster\n", sc->sc_dev.dv_xname); 3495 m_freem(m); 3496 break; 3497 } 3498 } 3499 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3500 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3501 m_freem(m0); 3502 m0 = m; 3503 m = NULL; 3504 } 3505 if (error != 0) { 3506 printf("%s: unable to load Tx buffer, " 3507 "error = %d\n", sc->sc_dev.dv_xname, error); 3508 m_freem(m0); 3509 break; 3510 } 3511 3512 /* 3513 * Ensure we have enough descriptors free to describe 3514 * the packet. 3515 */ 3516 if (dmamap->dm_nsegs > sc->sc_txfree) { 3517 /* 3518 * Not enough free descriptors to transmit 3519 * this packet. Unload the DMA map and 3520 * drop the packet. Notify the upper layer 3521 * that there are no more slots left. 3522 * 3523 * XXX We could allocate an mbuf and copy, but 3524 * XXX it is worth it? 3525 */ 3526 ifp->if_flags |= IFF_OACTIVE; 3527 bus_dmamap_unload(sc->sc_dmat, dmamap); 3528 m_freem(m0); 3529 break; 3530 } 3531 3532 /* 3533 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3534 */ 3535 3536 /* Sync the DMA map. */ 3537 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3538 BUS_DMASYNC_PREWRITE); 3539 3540 /* XXX arbitrary retry limit; 8 because I have seen it in 3541 * use already and maybe 0 means "no tries" ! 3542 */ 3543 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3544 3545 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3546 sc->sc_dev.dv_xname, rate * 5)); 3547 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3548 3549 /* 3550 * Initialize the transmit descriptors. 3551 */ 3552 for (nexttx = sc->sc_txnext, seg = 0; 3553 seg < dmamap->dm_nsegs; 3554 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3555 /* 3556 * If this is the first descriptor we're 3557 * enqueueing, don't set the OWN bit just 3558 * yet. That could cause a race condition. 3559 * We'll do it below. 3560 */ 3561 txd = &sc->sc_txdescs[nexttx]; 3562 txd->at_ctl = ctl | 3563 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3564 3565 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3566 txd->at_flags = 3567 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3568 ATW_TXFLAG_TBS1_MASK)) | 3569 ((nexttx == (ATW_NTXDESC - 1)) 3570 ? htole32(ATW_TXFLAG_TER) : 0); 3571 lasttx = nexttx; 3572 } 3573 3574 IASSERT(lasttx != -1, ("bad lastx")); 3575 /* Set `first segment' and `last segment' appropriately. */ 3576 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3577 htole32(ATW_TXFLAG_FS); 3578 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3579 3580 #ifdef ATW_DEBUG 3581 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3582 printf(" txsoft %p transmit chain:\n", txs); 3583 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3584 printf(" descriptor %d:\n", seg); 3585 printf(" at_ctl: 0x%08x\n", 3586 le32toh(sc->sc_txdescs[seg].at_ctl)); 3587 printf(" at_flags: 0x%08x\n", 3588 le32toh(sc->sc_txdescs[seg].at_flags)); 3589 printf(" at_buf1: 0x%08x\n", 3590 le32toh(sc->sc_txdescs[seg].at_buf1)); 3591 printf(" at_buf2: 0x%08x\n", 3592 le32toh(sc->sc_txdescs[seg].at_buf2)); 3593 if (seg == lasttx) 3594 break; 3595 } 3596 } 3597 #endif 3598 3599 /* Sync the descriptors we're using. */ 3600 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3601 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3602 3603 /* 3604 * Store a pointer to the packet so we can free it later, 3605 * and remember what txdirty will be once the packet is 3606 * done. 3607 */ 3608 txs->txs_mbuf = m0; 3609 txs->txs_firstdesc = sc->sc_txnext; 3610 txs->txs_lastdesc = lasttx; 3611 txs->txs_ndescs = dmamap->dm_nsegs; 3612 3613 /* Advance the tx pointer. */ 3614 sc->sc_txfree -= dmamap->dm_nsegs; 3615 sc->sc_txnext = nexttx; 3616 3617 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3618 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3619 3620 last_txs = txs; 3621 } 3622 3623 if (txs == NULL || sc->sc_txfree == 0) { 3624 /* No more slots left; notify upper layer. */ 3625 ifp->if_flags |= IFF_OACTIVE; 3626 } 3627 3628 if (sc->sc_txfree != ofree) { 3629 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3630 sc->sc_dev.dv_xname, lasttx, firsttx)); 3631 /* 3632 * Cause a transmit interrupt to happen on the 3633 * last packet we enqueued. 3634 */ 3635 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3636 ATW_CDTXSYNC(sc, lasttx, 1, 3637 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3638 3639 /* 3640 * The entire packet chain is set up. Give the 3641 * first descriptor to the chip now. 3642 */ 3643 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3644 ATW_CDTXSYNC(sc, firsttx, 1, 3645 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3646 3647 /* Wake up the transmitter. */ 3648 ATW_WRITE(sc, ATW_TDR, 0x1); 3649 3650 /* Set a watchdog timer in case the chip flakes out. */ 3651 sc->sc_tx_timer = 5; 3652 ifp->if_timer = 1; 3653 } 3654 } 3655 3656 /* 3657 * atw_power: 3658 * 3659 * Power management (suspend/resume) hook. 3660 */ 3661 void 3662 atw_power(int why, void *arg) 3663 { 3664 struct atw_softc *sc = arg; 3665 struct ifnet *ifp = &sc->sc_ic.ic_if; 3666 int s; 3667 3668 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3669 3670 s = splnet(); 3671 switch (why) { 3672 case PWR_STANDBY: 3673 /* XXX do nothing. */ 3674 break; 3675 case PWR_SUSPEND: 3676 atw_stop(ifp, 0); 3677 if (sc->sc_power != NULL) 3678 (*sc->sc_power)(sc, why); 3679 break; 3680 case PWR_RESUME: 3681 if (ifp->if_flags & IFF_UP) { 3682 if (sc->sc_power != NULL) 3683 (*sc->sc_power)(sc, why); 3684 atw_init(ifp); 3685 } 3686 break; 3687 case PWR_SOFTSUSPEND: 3688 case PWR_SOFTSTANDBY: 3689 case PWR_SOFTRESUME: 3690 break; 3691 } 3692 splx(s); 3693 } 3694 3695 /* 3696 * atw_ioctl: [ifnet interface function] 3697 * 3698 * Handle control requests from the operator. 3699 */ 3700 int 3701 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3702 { 3703 struct atw_softc *sc = ifp->if_softc; 3704 struct ifreq *ifr = (struct ifreq *)data; 3705 int s, error = 0; 3706 3707 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3708 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3709 return ENXIO; 3710 3711 s = splnet(); 3712 3713 switch (cmd) { 3714 case SIOCSIFFLAGS: 3715 if (ifp->if_flags & IFF_UP) { 3716 if (ATW_IS_ENABLED(sc)) { 3717 /* 3718 * To avoid rescanning another access point, 3719 * do not call atw_init() here. Instead, 3720 * only reflect media settings. 3721 */ 3722 atw_filter_setup(sc); 3723 } else 3724 error = atw_init(ifp); 3725 } else if (ATW_IS_ENABLED(sc)) 3726 atw_stop(ifp, 1); 3727 break; 3728 case SIOCADDMULTI: 3729 case SIOCDELMULTI: 3730 error = (cmd == SIOCADDMULTI) ? 3731 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3732 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3733 if (error == ENETRESET) { 3734 if (ATW_IS_ENABLED(sc)) 3735 atw_filter_setup(sc); /* do not rescan */ 3736 error = 0; 3737 } 3738 break; 3739 default: 3740 error = ieee80211_ioctl(ifp, cmd, data); 3741 if (error == ENETRESET) { 3742 if (ATW_IS_ENABLED(sc)) 3743 error = atw_init(ifp); 3744 else 3745 error = 0; 3746 } 3747 break; 3748 } 3749 3750 /* Try to get more packets going. */ 3751 if (ATW_IS_ENABLED(sc)) 3752 atw_start(ifp); 3753 3754 splx(s); 3755 return (error); 3756 } 3757 3758 static int 3759 atw_media_change(struct ifnet *ifp) 3760 { 3761 int error; 3762 3763 error = ieee80211_media_change(ifp); 3764 if (error == ENETRESET) { 3765 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3766 (IFF_RUNNING|IFF_UP)) 3767 atw_init(ifp); /* XXX lose error */ 3768 error = 0; 3769 } 3770 return error; 3771 } 3772 3773 static void 3774 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3775 { 3776 struct atw_softc *sc = ifp->if_softc; 3777 3778 if (ATW_IS_ENABLED(sc) == 0) { 3779 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3780 imr->ifm_status = 0; 3781 return; 3782 } 3783 ieee80211_media_status(ifp, imr); 3784 } 3785
Indexes created Mon Sep 29 21:09:56 GMT 2025