atw.c revision 1.62
1 /* $NetBSD: atw.c,v 1.62 2004/07/15 07:25:06 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.62 2004/07/15 07:25:06 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_bbp_io_enable_delay = 20 * 1000; 145 int atw_bbp_io_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 1000; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 int atw_xindiv2 = 0; 150 151 #ifdef ATW_DEBUG 152 int atw_debug = 0; 153 154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 157 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 158 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 159 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 160 161 static void atw_print_regs(struct atw_softc *, const char *); 162 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 163 164 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 165 # ifdef ATW_BBPDEBUG 166 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 167 static void atw_rf3000_print(struct atw_softc *); 168 # endif /* ATW_BBPDEBUG */ 169 170 # ifdef ATW_SYNDEBUG 171 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 172 static void atw_si4126_print(struct atw_softc *); 173 # endif /* ATW_SYNDEBUG */ 174 175 #else 176 #define ATW_DPRINTF(x) 177 #define ATW_DPRINTF2(x) 178 #define ATW_DPRINTF3(x) 179 #define DPRINTF(sc, x) /* nothing */ 180 #define DPRINTF2(sc, x) /* nothing */ 181 #define DPRINTF3(sc, x) /* nothing */ 182 #endif 183 184 /* ifnet methods */ 185 void atw_start(struct ifnet *); 186 void atw_watchdog(struct ifnet *); 187 int atw_ioctl(struct ifnet *, u_long, caddr_t); 188 int atw_init(struct ifnet *); 189 void atw_stop(struct ifnet *, int); 190 191 /* Device attachment */ 192 void atw_attach(struct atw_softc *); 193 int atw_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 void atw_rxdrain(struct atw_softc *); 197 void atw_txdrain(struct atw_softc *); 198 int atw_add_rxbuf(struct atw_softc *, int); 199 void atw_idle(struct atw_softc *, u_int32_t); 200 201 /* Device (de)activation and power state */ 202 int atw_enable(struct atw_softc *); 203 void atw_disable(struct atw_softc *); 204 void atw_power(int, void *); 205 void atw_shutdown(void *); 206 void atw_reset(struct atw_softc *); 207 208 /* Interrupt handlers */ 209 void atw_rxintr(struct atw_softc *); 210 void atw_txintr(struct atw_softc *); 211 void atw_linkintr(struct atw_softc *, u_int32_t); 212 213 /* 802.11 state machine */ 214 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 215 static int atw_tune(struct atw_softc *); 216 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 217 struct ieee80211_node *, int, int, u_int32_t); 218 219 /* Device initialization */ 220 static void atw_wcsr_init(struct atw_softc *); 221 static void atw_cmdr_init(struct atw_softc *); 222 static void atw_tofs2_init(struct atw_softc *); 223 static void atw_txlmt_init(struct atw_softc *); 224 static void atw_test1_init(struct atw_softc *); 225 static void atw_rf_reset(struct atw_softc *); 226 static void atw_cfp_init(struct atw_softc *); 227 static void atw_tofs0_init(struct atw_softc *); 228 static void atw_ifs_init(struct atw_softc *); 229 static void atw_response_times_init(struct atw_softc *); 230 static void atw_bbp_io_init(struct atw_softc *); 231 232 /* RAM/ROM utilities */ 233 static void atw_clear_sram(struct atw_softc *); 234 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 235 static int atw_read_srom(struct atw_softc *); 236 237 /* BSS setup */ 238 static void atw_tsf(struct atw_softc *); 239 static void atw_start_beacon(struct atw_softc *, int); 240 static void atw_write_bssid(struct atw_softc *); 241 static void atw_write_ssid(struct atw_softc *); 242 static void atw_write_sup_rates(struct atw_softc *); 243 static void atw_write_wep(struct atw_softc *); 244 245 /* Media */ 246 static int atw_media_change(struct ifnet *); 247 static void atw_media_status(struct ifnet *, struct ifmediareq *); 248 249 static void atw_filter_setup(struct atw_softc *); 250 251 /* 802.11 utilities */ 252 static void atw_frame_setdurs(struct atw_softc *, 253 struct atw_frame *, int, int); 254 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 255 static void atw_node_free(struct ieee80211com *, 256 struct ieee80211_node *); 257 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 258 struct ieee80211_node *, int, int, 259 u_int32_t); 260 static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 261 uint32_t); 262 static __inline void atw_tsft(struct atw_softc *, uint32_t *, 263 uint32_t *); 264 265 /* 266 * Tuner/transceiver/modem 267 */ 268 static void atw_bbp_io_enable(struct atw_softc *, int); 269 270 /* RFMD RF3000 Baseband Processor */ 271 static int atw_rf3000_init(struct atw_softc *); 272 static int atw_rf3000_tune(struct atw_softc *, u_int); 273 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 274 275 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 276 static void atw_si4126_tune(struct atw_softc *, u_int); 277 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 278 279 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 280 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 281 282 const char *atw_tx_state[] = { 283 "STOPPED", 284 "RUNNING - read descriptor", 285 "RUNNING - transmitting", 286 "RUNNING - filling fifo", /* XXX */ 287 "SUSPENDED", 288 "RUNNING -- write descriptor", 289 "RUNNING -- write last descriptor", 290 "RUNNING - fifo full" 291 }; 292 293 const char *atw_rx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - check this packet, pre-fetch next", 297 "RUNNING - wait for reception", 298 "SUSPENDED", 299 "RUNNING - write descriptor", 300 "RUNNING - flush fifo", 301 "RUNNING - fifo drain" 302 }; 303 304 int 305 atw_activate(struct device *self, enum devact act) 306 { 307 struct atw_softc *sc = (struct atw_softc *)self; 308 int rv = 0, s; 309 310 s = splnet(); 311 switch (act) { 312 case DVACT_ACTIVATE: 313 rv = EOPNOTSUPP; 314 break; 315 316 case DVACT_DEACTIVATE: 317 if_deactivate(&sc->sc_ic.ic_if); 318 break; 319 } 320 splx(s); 321 return rv; 322 } 323 324 /* 325 * atw_enable: 326 * 327 * Enable the ADM8211 chip. 328 */ 329 int 330 atw_enable(struct atw_softc *sc) 331 { 332 333 if (ATW_IS_ENABLED(sc) == 0) { 334 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 335 printf("%s: device enable failed\n", 336 sc->sc_dev.dv_xname); 337 return (EIO); 338 } 339 sc->sc_flags |= ATWF_ENABLED; 340 } 341 return (0); 342 } 343 344 /* 345 * atw_disable: 346 * 347 * Disable the ADM8211 chip. 348 */ 349 void 350 atw_disable(struct atw_softc *sc) 351 { 352 if (!ATW_IS_ENABLED(sc)) 353 return; 354 if (sc->sc_disable != NULL) 355 (*sc->sc_disable)(sc); 356 sc->sc_flags &= ~ATWF_ENABLED; 357 } 358 359 /* Returns -1 on failure. */ 360 static int 361 atw_read_srom(struct atw_softc *sc) 362 { 363 struct seeprom_descriptor sd; 364 u_int32_t reg; 365 366 (void)memset(&sd, 0, sizeof(sd)); 367 368 reg = ATW_READ(sc, ATW_TEST0); 369 370 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 371 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 372 return -1; 373 } 374 375 switch (reg & ATW_TEST0_EPTYP_MASK) { 376 case ATW_TEST0_EPTYP_93c66: 377 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 378 sc->sc_sromsz = 512; 379 sd.sd_chip = C56_66; 380 break; 381 case ATW_TEST0_EPTYP_93c46: 382 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 383 sc->sc_sromsz = 128; 384 sd.sd_chip = C46; 385 break; 386 default: 387 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 388 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 389 return -1; 390 } 391 392 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 393 394 if (sc->sc_srom == NULL) { 395 printf("%s: unable to allocate SROM buffer\n", 396 sc->sc_dev.dv_xname); 397 return -1; 398 } 399 400 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 401 402 /* ADM8211 has a single 32-bit register for controlling the 403 * 93cx6 SROM. Bit SRS enables the serial port. There is no 404 * "ready" bit. The ADM8211 input/output sense is the reverse 405 * of read_seeprom's. 406 */ 407 sd.sd_tag = sc->sc_st; 408 sd.sd_bsh = sc->sc_sh; 409 sd.sd_regsize = 4; 410 sd.sd_control_offset = ATW_SPR; 411 sd.sd_status_offset = ATW_SPR; 412 sd.sd_dataout_offset = ATW_SPR; 413 sd.sd_CK = ATW_SPR_SCLK; 414 sd.sd_CS = ATW_SPR_SCS; 415 sd.sd_DI = ATW_SPR_SDO; 416 sd.sd_DO = ATW_SPR_SDI; 417 sd.sd_MS = ATW_SPR_SRS; 418 sd.sd_RDY = 0; 419 420 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 421 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 422 free(sc->sc_srom, M_DEVBUF); 423 return -1; 424 } 425 #ifdef ATW_DEBUG 426 { 427 int i; 428 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 429 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 430 if (((i % 8) == 0) && (i != 0)) { 431 ATW_DPRINTF(("\n\t")); 432 } 433 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 434 } 435 ATW_DPRINTF(("\n")); 436 } 437 #endif /* ATW_DEBUG */ 438 return 0; 439 } 440 441 #ifdef ATW_DEBUG 442 static void 443 atw_print_regs(struct atw_softc *sc, const char *where) 444 { 445 #define PRINTREG(sc, reg) \ 446 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 447 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 448 449 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 450 451 PRINTREG(sc, ATW_PAR); 452 PRINTREG(sc, ATW_FRCTL); 453 PRINTREG(sc, ATW_TDR); 454 PRINTREG(sc, ATW_WTDP); 455 PRINTREG(sc, ATW_RDR); 456 PRINTREG(sc, ATW_WRDP); 457 PRINTREG(sc, ATW_RDB); 458 PRINTREG(sc, ATW_CSR3A); 459 PRINTREG(sc, ATW_TDBD); 460 PRINTREG(sc, ATW_TDBP); 461 PRINTREG(sc, ATW_STSR); 462 PRINTREG(sc, ATW_CSR5A); 463 PRINTREG(sc, ATW_NAR); 464 PRINTREG(sc, ATW_CSR6A); 465 PRINTREG(sc, ATW_IER); 466 PRINTREG(sc, ATW_CSR7A); 467 PRINTREG(sc, ATW_LPC); 468 PRINTREG(sc, ATW_TEST1); 469 PRINTREG(sc, ATW_SPR); 470 PRINTREG(sc, ATW_TEST0); 471 PRINTREG(sc, ATW_WCSR); 472 PRINTREG(sc, ATW_WPDR); 473 PRINTREG(sc, ATW_GPTMR); 474 PRINTREG(sc, ATW_GPIO); 475 PRINTREG(sc, ATW_BBPCTL); 476 PRINTREG(sc, ATW_SYNCTL); 477 PRINTREG(sc, ATW_PLCPHD); 478 PRINTREG(sc, ATW_MMIWADDR); 479 PRINTREG(sc, ATW_MMIRADDR1); 480 PRINTREG(sc, ATW_MMIRADDR2); 481 PRINTREG(sc, ATW_TXBR); 482 PRINTREG(sc, ATW_CSR15A); 483 PRINTREG(sc, ATW_ALCSTAT); 484 PRINTREG(sc, ATW_TOFS2); 485 PRINTREG(sc, ATW_CMDR); 486 PRINTREG(sc, ATW_PCIC); 487 PRINTREG(sc, ATW_PMCSR); 488 PRINTREG(sc, ATW_PAR0); 489 PRINTREG(sc, ATW_PAR1); 490 PRINTREG(sc, ATW_MAR0); 491 PRINTREG(sc, ATW_MAR1); 492 PRINTREG(sc, ATW_ATIMDA0); 493 PRINTREG(sc, ATW_ABDA1); 494 PRINTREG(sc, ATW_BSSID0); 495 PRINTREG(sc, ATW_TXLMT); 496 PRINTREG(sc, ATW_MIBCNT); 497 PRINTREG(sc, ATW_BCNT); 498 PRINTREG(sc, ATW_TSFTH); 499 PRINTREG(sc, ATW_TSC); 500 PRINTREG(sc, ATW_SYNRF); 501 PRINTREG(sc, ATW_BPLI); 502 PRINTREG(sc, ATW_CAP0); 503 PRINTREG(sc, ATW_CAP1); 504 PRINTREG(sc, ATW_RMD); 505 PRINTREG(sc, ATW_CFPP); 506 PRINTREG(sc, ATW_TOFS0); 507 PRINTREG(sc, ATW_TOFS1); 508 PRINTREG(sc, ATW_IFST); 509 PRINTREG(sc, ATW_RSPT); 510 PRINTREG(sc, ATW_TSFTL); 511 PRINTREG(sc, ATW_WEPCTL); 512 PRINTREG(sc, ATW_WESK); 513 PRINTREG(sc, ATW_WEPCNT); 514 PRINTREG(sc, ATW_MACTEST); 515 PRINTREG(sc, ATW_FER); 516 PRINTREG(sc, ATW_FEMR); 517 PRINTREG(sc, ATW_FPSR); 518 PRINTREG(sc, ATW_FFER); 519 #undef PRINTREG 520 } 521 #endif /* ATW_DEBUG */ 522 523 /* 524 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 525 */ 526 void 527 atw_attach(struct atw_softc *sc) 528 { 529 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 530 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 531 }; 532 struct ieee80211com *ic = &sc->sc_ic; 533 struct ifnet *ifp = &ic->ic_if; 534 int country_code, error, i, nrate; 535 u_int32_t reg; 536 static const char *type_strings[] = {"Intersil (not supported)", 537 "RFMD", "Marvel (not supported)"}; 538 539 sc->sc_txth = atw_txthresh_tab_lo; 540 541 SIMPLEQ_INIT(&sc->sc_txfreeq); 542 SIMPLEQ_INIT(&sc->sc_txdirtyq); 543 544 #ifdef ATW_DEBUG 545 atw_print_regs(sc, "atw_attach"); 546 #endif /* ATW_DEBUG */ 547 548 /* 549 * Allocate the control data structures, and create and load the 550 * DMA map for it. 551 */ 552 if ((error = bus_dmamem_alloc(sc->sc_dmat, 553 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 554 1, &sc->sc_cdnseg, 0)) != 0) { 555 printf("%s: unable to allocate control data, error = %d\n", 556 sc->sc_dev.dv_xname, error); 557 goto fail_0; 558 } 559 560 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 561 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 562 BUS_DMA_COHERENT)) != 0) { 563 printf("%s: unable to map control data, error = %d\n", 564 sc->sc_dev.dv_xname, error); 565 goto fail_1; 566 } 567 568 if ((error = bus_dmamap_create(sc->sc_dmat, 569 sizeof(struct atw_control_data), 1, 570 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 571 printf("%s: unable to create control data DMA map, " 572 "error = %d\n", sc->sc_dev.dv_xname, error); 573 goto fail_2; 574 } 575 576 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 577 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 578 0)) != 0) { 579 printf("%s: unable to load control data DMA map, error = %d\n", 580 sc->sc_dev.dv_xname, error); 581 goto fail_3; 582 } 583 584 /* 585 * Create the transmit buffer DMA maps. 586 */ 587 sc->sc_ntxsegs = ATW_NTXSEGS; 588 for (i = 0; i < ATW_TXQUEUELEN; i++) { 589 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 590 sc->sc_ntxsegs, MCLBYTES, 0, 0, 591 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 592 printf("%s: unable to create tx DMA map %d, " 593 "error = %d\n", sc->sc_dev.dv_xname, i, error); 594 goto fail_4; 595 } 596 } 597 598 /* 599 * Create the receive buffer DMA maps. 600 */ 601 for (i = 0; i < ATW_NRXDESC; i++) { 602 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 603 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 604 printf("%s: unable to create rx DMA map %d, " 605 "error = %d\n", sc->sc_dev.dv_xname, i, error); 606 goto fail_5; 607 } 608 } 609 for (i = 0; i < ATW_NRXDESC; i++) { 610 sc->sc_rxsoft[i].rxs_mbuf = NULL; 611 } 612 613 /* Reset the chip to a known state. */ 614 atw_reset(sc); 615 616 if (atw_read_srom(sc) == -1) 617 return; 618 619 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 620 ATW_SR_RFTYPE_MASK); 621 622 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 623 ATW_SR_BBPTYPE_MASK); 624 625 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 626 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 627 return; 628 } 629 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 630 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 631 return; 632 } 633 634 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 635 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 636 637 /* XXX There exists a Linux driver which seems to use RFType = 0 for 638 * MARVEL. My bug, or theirs? 639 */ 640 641 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 642 643 switch (sc->sc_rftype) { 644 case ATW_RFTYPE_INTERSIL: 645 reg |= ATW_SYNCTL_CS1; 646 break; 647 case ATW_RFTYPE_RFMD: 648 reg |= ATW_SYNCTL_CS0; 649 break; 650 case ATW_RFTYPE_MARVEL: 651 break; 652 } 653 654 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 655 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 656 657 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 658 659 switch (sc->sc_bbptype) { 660 case ATW_BBPTYPE_INTERSIL: 661 reg |= ATW_BBPCTL_TWI; 662 break; 663 case ATW_BBPTYPE_RFMD: 664 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 665 ATW_BBPCTL_CCA_ACTLO; 666 break; 667 case ATW_BBPTYPE_MARVEL: 668 break; 669 case ATW_C_BBPTYPE_RFMD: 670 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 671 sc->sc_dev.dv_xname); 672 break; 673 } 674 675 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 676 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 677 678 /* 679 * From this point forward, the attachment cannot fail. A failure 680 * before this point releases all resources that may have been 681 * allocated. 682 */ 683 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 684 685 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 686 htole16(sc->sc_srom[ATW_SR_MAC00]), 687 htole16(sc->sc_srom[ATW_SR_MAC01]), 688 htole16(sc->sc_srom[ATW_SR_MAC10]))); 689 690 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 691 ATW_SR_CTRY_MASK); 692 693 #define ADD_CHANNEL(_ic, _chan) do { \ 694 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 695 _ic->ic_channels[_chan].ic_freq = \ 696 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 697 } while (0) 698 699 /* Find available channels */ 700 switch (country_code) { 701 case COUNTRY_MMK2: /* 1-14 */ 702 ADD_CHANNEL(ic, 14); 703 /*FALLTHROUGH*/ 704 case COUNTRY_ETSI: /* 1-13 */ 705 for (i = 1; i <= 13; i++) 706 ADD_CHANNEL(ic, i); 707 break; 708 case COUNTRY_FCC: /* 1-11 */ 709 case COUNTRY_IC: /* 1-11 */ 710 for (i = 1; i <= 11; i++) 711 ADD_CHANNEL(ic, i); 712 break; 713 case COUNTRY_MMK: /* 14 */ 714 ADD_CHANNEL(ic, 14); 715 break; 716 case COUNTRY_FRANCE: /* 10-13 */ 717 for (i = 10; i <= 13; i++) 718 ADD_CHANNEL(ic, i); 719 break; 720 default: /* assume channels 10-11 */ 721 case COUNTRY_SPAIN: /* 10-11 */ 722 for (i = 10; i <= 11; i++) 723 ADD_CHANNEL(ic, i); 724 break; 725 } 726 727 /* Read the MAC address. */ 728 reg = ATW_READ(sc, ATW_PAR0); 729 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 730 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 731 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 732 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 733 reg = ATW_READ(sc, ATW_PAR1); 734 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 735 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 736 737 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 738 printf(" could not get mac address, attach failed\n"); 739 return; 740 } 741 742 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 743 744 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 745 ifp->if_softc = sc; 746 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 747 IFF_NOTRAILERS; 748 ifp->if_ioctl = atw_ioctl; 749 ifp->if_start = atw_start; 750 ifp->if_watchdog = atw_watchdog; 751 ifp->if_init = atw_init; 752 ifp->if_stop = atw_stop; 753 IFQ_SET_READY(&ifp->if_snd); 754 755 ic->ic_phytype = IEEE80211_T_DS; 756 ic->ic_opmode = IEEE80211_M_STA; 757 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 758 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 759 760 nrate = 0; 761 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 762 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 763 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 764 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 765 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 766 767 /* 768 * Call MI attach routines. 769 */ 770 771 if_attach(ifp); 772 ieee80211_ifattach(ifp); 773 774 sc->sc_newstate = ic->ic_newstate; 775 ic->ic_newstate = atw_newstate; 776 777 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 778 ic->ic_recv_mgmt = atw_recv_mgmt; 779 780 sc->sc_node_free = ic->ic_node_free; 781 ic->ic_node_free = atw_node_free; 782 783 sc->sc_node_alloc = ic->ic_node_alloc; 784 ic->ic_node_alloc = atw_node_alloc; 785 786 /* possibly we should fill in our own sc_send_prresp, since 787 * the ADM8211 is probably sending probe responses in ad hoc 788 * mode. 789 */ 790 791 /* complete initialization */ 792 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 793 callout_init(&sc->sc_scan_ch); 794 795 #if NBPFILTER > 0 796 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 797 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 798 #endif 799 800 /* 801 * Make sure the interface is shutdown during reboot. 802 */ 803 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 804 if (sc->sc_sdhook == NULL) 805 printf("%s: WARNING: unable to establish shutdown hook\n", 806 sc->sc_dev.dv_xname); 807 808 /* 809 * Add a suspend hook to make sure we come back up after a 810 * resume. 811 */ 812 sc->sc_powerhook = powerhook_establish(atw_power, sc); 813 if (sc->sc_powerhook == NULL) 814 printf("%s: WARNING: unable to establish power hook\n", 815 sc->sc_dev.dv_xname); 816 817 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 818 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 819 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 820 821 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 822 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 823 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 824 825 return; 826 827 /* 828 * Free any resources we've allocated during the failed attach 829 * attempt. Do this in reverse order and fall through. 830 */ 831 fail_5: 832 for (i = 0; i < ATW_NRXDESC; i++) { 833 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 834 continue; 835 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 836 } 837 fail_4: 838 for (i = 0; i < ATW_TXQUEUELEN; i++) { 839 if (sc->sc_txsoft[i].txs_dmamap == NULL) 840 continue; 841 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 842 } 843 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 844 fail_3: 845 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 846 fail_2: 847 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 848 sizeof(struct atw_control_data)); 849 fail_1: 850 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 851 fail_0: 852 return; 853 } 854 855 static struct ieee80211_node * 856 atw_node_alloc(struct ieee80211com *ic) 857 { 858 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 859 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 860 861 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 862 return ni; 863 } 864 865 static void 866 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 867 { 868 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 869 870 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 871 ether_sprintf(ni->ni_bssid))); 872 (*sc->sc_node_free)(ic, ni); 873 } 874 875 /* 876 * atw_reset: 877 * 878 * Perform a soft reset on the ADM8211. 879 */ 880 void 881 atw_reset(struct atw_softc *sc) 882 { 883 int i; 884 885 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 886 887 for (i = 0; i < 10000; i++) { 888 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 889 break; 890 DELAY(1); 891 } 892 893 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 894 895 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 896 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 897 898 /* Turn off maximum power saving. */ 899 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 900 901 /* Recall EEPROM. */ 902 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 903 904 DELAY(10 * 1000); 905 906 /* A reset seems to affect the SRAM contents, so put them into 907 * a known state. 908 */ 909 atw_clear_sram(sc); 910 911 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 912 } 913 914 static void 915 atw_clear_sram(struct atw_softc *sc) 916 { 917 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 918 /* XXX not for revision 0x20. */ 919 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 920 } 921 922 /* TBD atw_init 923 * 924 * set MAC based on ic->ic_bss->myaddr 925 * write WEP keys 926 * set TX rate 927 */ 928 929 /* 930 * atw_init: [ ifnet interface function ] 931 * 932 * Initialize the interface. Must be called at splnet(). 933 */ 934 int 935 atw_init(struct ifnet *ifp) 936 { 937 struct atw_softc *sc = ifp->if_softc; 938 struct ieee80211com *ic = &sc->sc_ic; 939 struct atw_txsoft *txs; 940 struct atw_rxsoft *rxs; 941 u_int32_t reg; 942 int i, error = 0; 943 944 if ((error = atw_enable(sc)) != 0) 945 goto out; 946 947 /* 948 * Cancel any pending I/O. This also resets. 949 */ 950 atw_stop(ifp, 0); 951 952 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 953 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 954 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 955 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 956 957 /* Turn off APM??? (A binary-only driver does this.) 958 * 959 * Set Rx store-and-forward mode. 960 */ 961 reg = ATW_READ(sc, ATW_CMDR); 962 reg &= ~ATW_CMDR_APM; 963 reg &= ~ATW_CMDR_DRT_MASK; 964 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 965 966 ATW_WRITE(sc, ATW_CMDR, reg); 967 968 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 969 * 970 * XXX a binary-only driver sets a different service field than 971 * 0. why? 972 */ 973 reg = ATW_READ(sc, ATW_PLCPHD); 974 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 975 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 976 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 977 ATW_WRITE(sc, ATW_PLCPHD, reg); 978 979 /* XXX this magic can probably be figured out from the RFMD docs */ 980 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 981 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 982 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 983 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 984 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 985 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 986 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 987 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 988 ATW_WRITE(sc, ATW_TOFS2, reg); 989 990 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 991 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 992 993 /* XXX this resets an Intersil RF front-end? */ 994 /* TBD condition on Intersil RFType? */ 995 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 996 DELAY(10 * 1000); 997 ATW_WRITE(sc, ATW_SYNRF, 0); 998 DELAY(5 * 1000); 999 1000 /* 16 TU max duration for contention-free period */ 1001 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 1002 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 1003 1004 /* XXX I guess that the Cardbus clock is 22MHz? 1005 * I am assuming that the role of ATW_TOFS0_USCNT is 1006 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1007 * very clear on this point. It says in the datasheet that it is 1008 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1009 * and 33MHz; maybe this is the way? I see a binary-only driver write 1010 * these values. These values are also the power-on default. 1011 */ 1012 ATW_WRITE(sc, ATW_TOFS0, 1013 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1014 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1015 1016 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 1017 * driver. Go figure. 1018 */ 1019 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1020 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1021 ATW_IFST_SIFS_MASK) | 1022 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1023 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1024 1025 ATW_WRITE(sc, ATW_IFST, reg); 1026 1027 /* XXX More magic. Might relate to ACK timing. */ 1028 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1029 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1030 1031 /* Set up the MMI read/write addresses for the BBP. 1032 * 1033 * TBD find out the Marvel settings. 1034 */ 1035 switch (sc->sc_bbptype) { 1036 case ATW_BBPTYPE_INTERSIL: 1037 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1038 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1039 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1040 break; 1041 case ATW_BBPTYPE_MARVEL: 1042 break; 1043 case ATW_BBPTYPE_RFMD: 1044 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1045 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1046 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1047 default: 1048 break; 1049 } 1050 1051 sc->sc_wepctl = 0; 1052 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1053 1054 if ((error = atw_rf3000_init(sc)) != 0) 1055 goto out; 1056 1057 /* 1058 * Initialize the PCI Access Register. 1059 */ 1060 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1061 1062 /* 1063 * If we're allowed to do so, use Memory Read Line 1064 * and Memory Read Multiple. 1065 * 1066 * XXX Should we use Memory Write and Invalidate? 1067 */ 1068 if (sc->sc_flags & ATWF_MRL) 1069 sc->sc_busmode |= ATW_PAR_MRLE; 1070 if (sc->sc_flags & ATWF_MRM) 1071 sc->sc_busmode |= ATW_PAR_MRME; 1072 if (sc->sc_flags & ATWF_MWI) 1073 sc->sc_busmode |= ATW_PAR_MWIE; 1074 if (sc->sc_maxburst == 0) 1075 sc->sc_maxburst = 8; /* ADM8211 default */ 1076 1077 switch (sc->sc_cacheline) { 1078 default: 1079 /* Use burst length. */ 1080 break; 1081 case 8: 1082 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1083 break; 1084 case 16: 1085 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1086 break; 1087 case 32: 1088 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1089 break; 1090 } 1091 switch (sc->sc_maxburst) { 1092 case 1: 1093 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1094 break; 1095 case 2: 1096 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1097 break; 1098 case 4: 1099 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1100 break; 1101 case 8: 1102 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1103 break; 1104 case 16: 1105 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1106 break; 1107 case 32: 1108 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1109 break; 1110 default: 1111 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1112 break; 1113 } 1114 1115 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1116 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1117 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1118 1119 /* 1120 * Initialize the OPMODE register. We don't write it until 1121 * we're ready to begin the transmit and receive processes. 1122 */ 1123 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1124 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1125 1126 /* 1127 * Initialize the transmit descriptor ring. 1128 */ 1129 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1130 for (i = 0; i < ATW_NTXDESC; i++) { 1131 sc->sc_txdescs[i].at_ctl = 0; 1132 /* no transmit chaining */ 1133 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1134 sc->sc_txdescs[i].at_buf2 = 1135 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1136 } 1137 /* use ring mode */ 1138 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1139 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1140 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1141 sc->sc_txfree = ATW_NTXDESC; 1142 sc->sc_txnext = 0; 1143 1144 /* 1145 * Initialize the transmit job descriptors. 1146 */ 1147 SIMPLEQ_INIT(&sc->sc_txfreeq); 1148 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1149 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1150 txs = &sc->sc_txsoft[i]; 1151 txs->txs_mbuf = NULL; 1152 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1153 } 1154 1155 /* 1156 * Initialize the receive descriptor and receive job 1157 * descriptor rings. 1158 */ 1159 for (i = 0; i < ATW_NRXDESC; i++) { 1160 rxs = &sc->sc_rxsoft[i]; 1161 if (rxs->rxs_mbuf == NULL) { 1162 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1163 printf("%s: unable to allocate or map rx " 1164 "buffer %d, error = %d\n", 1165 sc->sc_dev.dv_xname, i, error); 1166 /* 1167 * XXX Should attempt to run with fewer receive 1168 * XXX buffers instead of just failing. 1169 */ 1170 atw_rxdrain(sc); 1171 goto out; 1172 } 1173 } else 1174 ATW_INIT_RXDESC(sc, i); 1175 } 1176 sc->sc_rxptr = 0; 1177 1178 /* disable all wake-up events */ 1179 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1180 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1181 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1182 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1183 1184 /* ack all wake-up events */ 1185 ATW_SET(sc, ATW_WCSR, 0); 1186 1187 /* 1188 * Initialize the interrupt mask and enable interrupts. 1189 */ 1190 /* normal interrupts */ 1191 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1192 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1193 1194 /* abnormal interrupts */ 1195 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1196 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1197 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1198 1199 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1200 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1201 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1202 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1203 ATW_INTR_TRT; 1204 1205 sc->sc_linkint_mask &= sc->sc_inten; 1206 sc->sc_rxint_mask &= sc->sc_inten; 1207 sc->sc_txint_mask &= sc->sc_inten; 1208 1209 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1210 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1211 1212 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1213 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1214 1215 /* 1216 * Give the transmit and receive rings to the ADM8211. 1217 */ 1218 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1219 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1220 1221 /* common 802.11 configuration */ 1222 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1223 switch (ic->ic_opmode) { 1224 case IEEE80211_M_STA: 1225 break; 1226 case IEEE80211_M_AHDEMO: /* XXX */ 1227 case IEEE80211_M_IBSS: 1228 ic->ic_flags |= IEEE80211_F_IBSSON; 1229 /*FALLTHROUGH*/ 1230 case IEEE80211_M_HOSTAP: /* XXX */ 1231 break; 1232 case IEEE80211_M_MONITOR: /* XXX */ 1233 break; 1234 } 1235 1236 atw_start_beacon(sc, 0); 1237 1238 switch (ic->ic_opmode) { 1239 case IEEE80211_M_AHDEMO: 1240 case IEEE80211_M_HOSTAP: 1241 ic->ic_bss->ni_intval = ic->ic_lintval; 1242 ic->ic_bss->ni_rssi = 0; 1243 ic->ic_bss->ni_rstamp = 0; 1244 break; 1245 default: /* XXX */ 1246 break; 1247 } 1248 1249 atw_write_ssid(sc); 1250 atw_write_sup_rates(sc); 1251 if (ic->ic_caps & IEEE80211_C_WEP) 1252 atw_write_wep(sc); 1253 1254 /* 1255 * Set the receive filter. This will start the transmit and 1256 * receive processes. 1257 */ 1258 atw_filter_setup(sc); 1259 1260 /* 1261 * Start the receive process. 1262 */ 1263 ATW_WRITE(sc, ATW_RDR, 0x1); 1264 1265 /* 1266 * Note that the interface is now running. 1267 */ 1268 ifp->if_flags |= IFF_RUNNING; 1269 ifp->if_flags &= ~IFF_OACTIVE; 1270 ic->ic_state = IEEE80211_S_INIT; 1271 1272 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1273 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1274 else 1275 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1276 out: 1277 if (error) { 1278 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1279 ifp->if_timer = 0; 1280 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1281 } 1282 #ifdef ATW_DEBUG 1283 atw_print_regs(sc, "end of init"); 1284 #endif /* ATW_DEBUG */ 1285 1286 return (error); 1287 } 1288 1289 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1290 * 0: MAC control of RF3000/Si4126. 1291 * 1292 * Applies power, or selects RF front-end? Sets reset condition. 1293 * 1294 * TBD support non-RFMD BBP, non-SiLabs synth. 1295 */ 1296 static void 1297 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1298 { 1299 if (enable) { 1300 ATW_WRITE(sc, ATW_SYNRF, 1301 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1302 DELAY(atw_bbp_io_enable_delay); 1303 } else { 1304 ATW_WRITE(sc, ATW_SYNRF, 0); 1305 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1306 } 1307 } 1308 1309 static int 1310 atw_tune(struct atw_softc *sc) 1311 { 1312 int rc; 1313 u_int chan; 1314 struct ieee80211com *ic = &sc->sc_ic; 1315 1316 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1317 if (chan == IEEE80211_CHAN_ANY) 1318 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1319 1320 if (chan == sc->sc_cur_chan) 1321 return 0; 1322 1323 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1324 sc->sc_cur_chan, chan)); 1325 1326 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1327 1328 atw_si4126_tune(sc, chan); 1329 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1330 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1331 chan); 1332 1333 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1334 DELAY(20 * 1000); 1335 ATW_WRITE(sc, ATW_RDR, 0x1); 1336 1337 if (rc == 0) 1338 sc->sc_cur_chan = chan; 1339 1340 return rc; 1341 } 1342 1343 #ifdef ATW_SYNDEBUG 1344 static void 1345 atw_si4126_print(struct atw_softc *sc) 1346 { 1347 struct ifnet *ifp = &sc->sc_ic.ic_if; 1348 u_int addr, val; 1349 1350 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1351 return; 1352 1353 for (addr = 0; addr <= 8; addr++) { 1354 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1355 if (atw_si4126_read(sc, addr, &val) == 0) { 1356 printf("<unknown> (quitting print-out)\n"); 1357 break; 1358 } 1359 printf("%05x\n", val); 1360 } 1361 } 1362 #endif /* ATW_SYNDEBUG */ 1363 1364 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1365 * 1366 * The RF/IF synthesizer produces two reference frequencies for 1367 * the RF2948B transceiver. The first frequency the RF2948B requires 1368 * is two times the so-called "intermediate frequency" (IF). Since 1369 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1370 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1371 * frequency required by the transceiver is the radio frequency 1372 * (RF). This is a superheterodyne transceiver; for f(chan) the 1373 * center frequency of the channel we are tuning, RF = f(chan) - 1374 * IF. 1375 * 1376 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1377 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1378 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1379 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1380 */ 1381 static void 1382 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1383 { 1384 u_int mhz; 1385 u_int R; 1386 u_int32_t gpio; 1387 u_int16_t gain; 1388 1389 #ifdef ATW_SYNDEBUG 1390 atw_si4126_print(sc); 1391 #endif /* ATW_SYNDEBUG */ 1392 1393 if (chan == 14) 1394 mhz = 2484; 1395 else 1396 mhz = 2412 + 5 * (chan - 1); 1397 1398 /* Tune IF to 748MHz to suit the IF LO input of the 1399 * RF2494B, which is 2 x IF. No need to set an IF divider 1400 * because an IF in 526MHz - 952MHz is allowed. 1401 * 1402 * XIN is 44.000MHz, so divide it by two to get allowable 1403 * range of 2-25MHz. SiLabs tells me that this is not 1404 * strictly necessary. 1405 */ 1406 1407 if (atw_xindiv2) 1408 R = 44; 1409 else 1410 R = 88; 1411 1412 /* Power-up RF, IF synthesizers. */ 1413 atw_si4126_write(sc, SI4126_POWER, 1414 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1415 1416 /* set LPWR, too? */ 1417 atw_si4126_write(sc, SI4126_MAIN, 1418 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1419 1420 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1421 * set KP2 to 1. 1422 * 1423 * REFDIF This is different from the reference driver, which 1424 * always sets SI4126_GAIN to 0. 1425 */ 1426 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1427 1428 atw_si4126_write(sc, SI4126_GAIN, gain); 1429 1430 /* XIN = 44MHz. 1431 * 1432 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1433 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1434 * 1435 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1436 * so that 1496/88 * 44MHz = 748MHz. 1437 */ 1438 atw_si4126_write(sc, SI4126_IFN, 1496); 1439 1440 atw_si4126_write(sc, SI4126_IFR, R); 1441 1442 #ifndef ATW_REFSLAVE 1443 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1444 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1445 * which has no RF1! 1446 */ 1447 atw_si4126_write(sc, SI4126_RF1R, R); 1448 1449 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1450 #endif 1451 1452 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1453 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1454 * Now let's multiply it to mhz. So mhz - IF = N. 1455 */ 1456 atw_si4126_write(sc, SI4126_RF2R, R); 1457 1458 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1459 1460 /* wait 100us from power-up for RF, IF to settle */ 1461 DELAY(100); 1462 1463 gpio = ATW_READ(sc, ATW_GPIO); 1464 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1465 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1466 1467 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1468 /* Set a Prism RF front-end to a special mode for channel 14? 1469 * 1470 * Apparently the SMC2635W needs this, although I don't think 1471 * it has a Prism RF. 1472 */ 1473 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1474 } 1475 ATW_WRITE(sc, ATW_GPIO, gpio); 1476 1477 #ifdef ATW_SYNDEBUG 1478 atw_si4126_print(sc); 1479 #endif /* ATW_SYNDEBUG */ 1480 } 1481 1482 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1483 * diversity. 1484 * 1485 * !!! 1486 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1487 * !!! 1488 */ 1489 static int 1490 atw_rf3000_init(struct atw_softc *sc) 1491 { 1492 int rc = 0; 1493 1494 atw_bbp_io_enable(sc, 1); 1495 1496 /* CCA is acquisition sensitive */ 1497 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1498 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1499 1500 if (rc != 0) 1501 goto out; 1502 1503 /* enable diversity */ 1504 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1505 1506 if (rc != 0) 1507 goto out; 1508 1509 /* sensible setting from a binary-only driver */ 1510 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1511 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1512 1513 if (rc != 0) 1514 goto out; 1515 1516 /* magic from a binary-only driver */ 1517 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1518 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1519 1520 if (rc != 0) 1521 goto out; 1522 1523 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1524 1525 if (rc != 0) 1526 goto out; 1527 1528 /* XXX Reference driver remarks that Abocom sets this to 50. 1529 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1530 * in the "reserved" area of register RF3000_OPTIONS1. 1531 * 1532 * EEPROMs for the ADM8211B contain a setting for this register. 1533 */ 1534 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1535 1536 if (rc != 0) 1537 goto out; 1538 1539 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1540 1541 if (rc != 0) 1542 goto out; 1543 1544 out: 1545 atw_bbp_io_enable(sc, 0); 1546 return rc; 1547 } 1548 1549 #ifdef ATW_BBPDEBUG 1550 static void 1551 atw_rf3000_print(struct atw_softc *sc) 1552 { 1553 struct ifnet *ifp = &sc->sc_ic.ic_if; 1554 u_int addr, val; 1555 1556 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1557 return; 1558 1559 for (addr = 0x01; addr <= 0x15; addr++) { 1560 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1561 if (atw_rf3000_read(sc, addr, &val) != 0) { 1562 printf("<unknown> (quitting print-out)\n"); 1563 break; 1564 } 1565 printf("%08x\n", val); 1566 } 1567 } 1568 #endif /* ATW_BBPDEBUG */ 1569 1570 /* Set the power settings on the BBP for channel `chan'. */ 1571 static int 1572 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1573 { 1574 int rc = 0; 1575 u_int32_t reg; 1576 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1577 1578 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1579 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1580 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1581 1582 /* odd channels: LSB, even channels: MSB */ 1583 if (chan % 2 == 1) { 1584 txpower &= 0xFF; 1585 lpf_cutoff &= 0xFF; 1586 lna_gs_thresh &= 0xFF; 1587 } else { 1588 txpower >>= 8; 1589 lpf_cutoff >>= 8; 1590 lna_gs_thresh >>= 8; 1591 } 1592 1593 #ifdef ATW_BBPDEBUG 1594 atw_rf3000_print(sc); 1595 #endif /* ATW_BBPDEBUG */ 1596 1597 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1598 "lna_gs_thresh %02x\n", 1599 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1600 1601 atw_bbp_io_enable(sc, 1); 1602 1603 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1604 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1605 goto out; 1606 1607 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1608 goto out; 1609 1610 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1611 goto out; 1612 1613 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1614 1615 if (rc != 0) 1616 goto out; 1617 1618 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1619 1620 if (rc != 0) 1621 goto out; 1622 1623 #ifdef ATW_BBPDEBUG 1624 atw_rf3000_print(sc); 1625 #endif /* ATW_BBPDEBUG */ 1626 1627 out: 1628 atw_bbp_io_enable(sc, 0); 1629 1630 /* set beacon, rts, atim transmit power */ 1631 reg = ATW_READ(sc, ATW_PLCPHD); 1632 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1633 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1634 ATW_PLCPHD_SERVICE_MASK); 1635 ATW_WRITE(sc, ATW_PLCPHD, reg); 1636 DELAY(2 * 1000); 1637 1638 return rc; 1639 } 1640 1641 /* Write a register on the RF3000 baseband processor using the 1642 * registers provided by the ADM8211 for this purpose. 1643 * 1644 * Return 0 on success. 1645 */ 1646 static int 1647 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1648 { 1649 u_int32_t reg; 1650 int i; 1651 1652 reg = sc->sc_bbpctl_wr | 1653 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1654 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1655 1656 for (i = 10; --i >= 0; ) { 1657 ATW_WRITE(sc, ATW_BBPCTL, reg); 1658 DELAY(2000); 1659 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1660 break; 1661 } 1662 1663 if (i < 0) { 1664 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1665 return ETIMEDOUT; 1666 } 1667 return 0; 1668 } 1669 1670 /* Read a register on the RF3000 baseband processor using the registers 1671 * the ADM8211 provides for this purpose. 1672 * 1673 * The 7-bit register address is addr. Record the 8-bit data in the register 1674 * in *val. 1675 * 1676 * Return 0 on success. 1677 * 1678 * XXX This does not seem to work. The ADM8211 must require more or 1679 * different magic to read the chip than to write it. Possibly some 1680 * of the magic I have derived from a binary-only driver concerns 1681 * the "chip address" (see the RF3000 manual). 1682 */ 1683 #ifdef ATW_BBPDEBUG 1684 static int 1685 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1686 { 1687 u_int32_t reg; 1688 int i; 1689 1690 for (i = 1000; --i >= 0; ) { 1691 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1692 break; 1693 DELAY(100); 1694 } 1695 1696 if (i < 0) { 1697 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1698 sc->sc_dev.dv_xname); 1699 return ETIMEDOUT; 1700 } 1701 1702 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1703 1704 ATW_WRITE(sc, ATW_BBPCTL, reg); 1705 1706 for (i = 1000; --i >= 0; ) { 1707 DELAY(100); 1708 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1709 break; 1710 } 1711 1712 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1713 1714 if (i < 0) { 1715 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1716 sc->sc_dev.dv_xname, reg); 1717 return ETIMEDOUT; 1718 } 1719 if (val != NULL) 1720 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1721 return 0; 1722 } 1723 #endif /* ATW_BBPDEBUG */ 1724 1725 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1726 * provided by the ADM8211 for that purpose. 1727 * 1728 * val is 18 bits of data, and val is the 4-bit address of the register. 1729 * 1730 * Return 0 on success. 1731 */ 1732 static void 1733 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1734 { 1735 uint32_t bits, mask, reg; 1736 const int nbits = 22; 1737 1738 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1739 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1740 1741 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1742 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1743 1744 reg = ATW_SYNRF_SELSYN; 1745 /* reference driver: reset Si4126 serial bus to initial 1746 * conditions? 1747 */ 1748 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1749 ATW_WRITE(sc, ATW_SYNRF, reg); 1750 1751 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1752 if ((bits & mask) != 0) 1753 reg |= ATW_SYNRF_SYNDATA; 1754 else 1755 reg &= ~ATW_SYNRF_SYNDATA; 1756 ATW_WRITE(sc, ATW_SYNRF, reg); 1757 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1758 ATW_WRITE(sc, ATW_SYNRF, reg); 1759 } 1760 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1761 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1762 } 1763 1764 /* Read 18-bit data from the 4-bit address addr in Si4126 1765 * RF synthesizer and write the data to *val. Return 0 on success. 1766 * 1767 * XXX This does not seem to work. The ADM8211 must require more or 1768 * different magic to read the chip than to write it. 1769 */ 1770 #ifdef ATW_SYNDEBUG 1771 static int 1772 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1773 { 1774 u_int32_t reg; 1775 int i; 1776 1777 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1778 1779 for (i = 1000; --i >= 0; ) { 1780 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1781 break; 1782 DELAY(100); 1783 } 1784 1785 if (i < 0) { 1786 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1787 sc->sc_dev.dv_xname); 1788 return ETIMEDOUT; 1789 } 1790 1791 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1792 1793 ATW_WRITE(sc, ATW_SYNCTL, reg); 1794 1795 for (i = 1000; --i >= 0; ) { 1796 DELAY(100); 1797 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1798 break; 1799 } 1800 1801 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1802 1803 if (i < 0) { 1804 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1805 sc->sc_dev.dv_xname, reg); 1806 return ETIMEDOUT; 1807 } 1808 if (val != NULL) 1809 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1810 ATW_SYNCTL_DATA_MASK); 1811 return 0; 1812 } 1813 #endif /* ATW_SYNDEBUG */ 1814 1815 /* XXX is the endianness correct? test. */ 1816 #define atw_calchash(addr) \ 1817 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1818 1819 /* 1820 * atw_filter_setup: 1821 * 1822 * Set the ADM8211's receive filter. 1823 */ 1824 static void 1825 atw_filter_setup(struct atw_softc *sc) 1826 { 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ethercom *ec = &ic->ic_ec; 1829 struct ifnet *ifp = &sc->sc_ic.ic_if; 1830 int hash; 1831 u_int32_t hashes[2]; 1832 struct ether_multi *enm; 1833 struct ether_multistep step; 1834 1835 /* According to comments in tlp_al981_filter_setup 1836 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1837 * multicast filter to be set while it is running. Hopefully 1838 * the ADM8211 is not the same! 1839 */ 1840 if ((ifp->if_flags & IFF_RUNNING) != 0) 1841 atw_idle(sc, ATW_NAR_SR); 1842 1843 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1844 1845 /* XXX in scan mode, do not filter packets. Maybe this is 1846 * unnecessary. 1847 */ 1848 if (ic->ic_state == IEEE80211_S_SCAN || 1849 (ifp->if_flags & IFF_PROMISC) != 0) { 1850 sc->sc_opmode |= ATW_NAR_PR; 1851 goto allmulti; 1852 } 1853 1854 hashes[0] = hashes[1] = 0x0; 1855 1856 /* 1857 * Program the 64-bit multicast hash filter. 1858 */ 1859 ETHER_FIRST_MULTI(step, ec, enm); 1860 while (enm != NULL) { 1861 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1862 ETHER_ADDR_LEN) != 0) 1863 goto allmulti; 1864 1865 hash = atw_calchash(enm->enm_addrlo); 1866 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1867 ETHER_NEXT_MULTI(step, enm); 1868 } 1869 ifp->if_flags &= ~IFF_ALLMULTI; 1870 goto setit; 1871 1872 allmulti: 1873 ifp->if_flags |= IFF_ALLMULTI; 1874 hashes[0] = hashes[1] = 0xffffffff; 1875 1876 setit: 1877 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1878 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1879 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1880 DELAY(20 * 1000); 1881 1882 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1883 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1884 } 1885 1886 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1887 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1888 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1889 * no beacon with the preferred BSSID and SSID in the number of 1890 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1891 */ 1892 static void 1893 atw_write_bssid(struct atw_softc *sc) 1894 { 1895 struct ieee80211com *ic = &sc->sc_ic; 1896 u_int8_t *bssid; 1897 1898 bssid = ic->ic_bss->ni_bssid; 1899 1900 ATW_WRITE(sc, ATW_BSSID0, 1901 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1902 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1903 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1904 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1905 1906 ATW_WRITE(sc, ATW_ABDA1, 1907 (ATW_READ(sc, ATW_ABDA1) & 1908 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1909 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1910 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1911 1912 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1913 ether_sprintf(sc->sc_bssid))); 1914 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1915 1916 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1917 } 1918 1919 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1920 * 16-bit word. 1921 */ 1922 static void 1923 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1924 { 1925 u_int i; 1926 u_int8_t *ptr; 1927 1928 memcpy(&sc->sc_sram[ofs], buf, buflen); 1929 1930 if (ofs % 2 != 0) { 1931 ofs--; 1932 buflen++; 1933 } 1934 1935 if (buflen % 2 != 0) 1936 buflen++; 1937 1938 assert(buflen + ofs <= ATW_SRAM_SIZE); 1939 1940 ptr = &sc->sc_sram[ofs]; 1941 1942 for (i = 0; i < buflen; i += 2) { 1943 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1944 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1945 DELAY(atw_writewep_delay); 1946 1947 ATW_WRITE(sc, ATW_WESK, 1948 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1949 DELAY(atw_writewep_delay); 1950 } 1951 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1952 1953 if (sc->sc_if.if_flags & IFF_DEBUG) { 1954 int n_octets = 0; 1955 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1956 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1957 for (i = 0; i < buflen; i++) { 1958 printf(" %02x", ptr[i]); 1959 if (++n_octets % 24 == 0) 1960 printf("\n"); 1961 } 1962 if (n_octets % 24 != 0) 1963 printf("\n"); 1964 } 1965 } 1966 1967 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 1968 static void 1969 atw_write_wep(struct atw_softc *sc) 1970 { 1971 struct ieee80211com *ic = &sc->sc_ic; 1972 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 1973 u_int8_t buf[IEEE80211_WEP_NKID] 1974 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 1975 u_int32_t reg; 1976 int i; 1977 1978 sc->sc_wepctl = 0; 1979 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 1980 1981 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 1982 return; 1983 1984 memset(&buf[0][0], 0, sizeof(buf)); 1985 1986 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1987 if (ic->ic_nw_keys[i].wk_len > 5) { 1988 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 1989 } else if (ic->ic_nw_keys[i].wk_len != 0) { 1990 buf[i][1] = ATW_WEP_ENABLED; 1991 } else { 1992 buf[i][1] = 0; 1993 continue; 1994 } 1995 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 1996 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 1997 ic->ic_nw_keys[i].wk_len - 1); 1998 } 1999 2000 reg = ATW_READ(sc, ATW_MACTEST); 2001 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2002 reg &= ~ATW_MACTEST_KEYID_MASK; 2003 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2004 ATW_WRITE(sc, ATW_MACTEST, reg); 2005 2006 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2007 * throughout.) 2008 */ 2009 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2010 if (sc->sc_if.if_flags & IFF_LINK2) 2011 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2012 2013 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2014 sizeof(buf)); 2015 } 2016 2017 const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2018 2019 static void 2020 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2021 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2022 { 2023 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2024 2025 switch (subtype) { 2026 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2027 /* do nothing: hardware answers probe request */ 2028 break; 2029 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2030 case IEEE80211_FC0_SUBTYPE_BEACON: 2031 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2032 break; 2033 default: 2034 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2035 break; 2036 } 2037 return; 2038 } 2039 2040 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2041 * of IBSSs with like SSID/channel but different BSSID. It joins the 2042 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2043 * convention. Possibly the ADMtek chip does this for us; I will have 2044 * to test to find out. 2045 * 2046 * XXX we should add the duration field of the received beacon to 2047 * the TSF time it contains before comparing it with the ADM8211's 2048 * TSF. 2049 */ 2050 static void 2051 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2052 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2053 { 2054 struct atw_softc *sc; 2055 struct ieee80211_frame *wh; 2056 uint32_t tsftl, tsfth; 2057 uint32_t bcn_tsftl, bcn_tsfth; 2058 int do_print = 0; 2059 union { 2060 uint32_t words[2]; 2061 uint8_t tstamp[8]; 2062 } u; 2063 2064 sc = (struct atw_softc*)ic->ic_if.if_softc; 2065 2066 if (ic->ic_if.if_flags & IFF_LINK0) { 2067 do_print = (ic->ic_if.if_flags & IFF_DEBUG) 2068 ? 1 : ratecheck(&sc->sc_last_beacon, 2069 &atw_beacon_mininterval); 2070 } 2071 2072 wh = mtod(m0, struct ieee80211_frame *); 2073 2074 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2075 2076 if (ic->ic_state != IEEE80211_S_RUN) 2077 return; 2078 2079 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2080 ic->ic_bss->ni_chan)) == NULL) { 2081 if (do_print) 2082 printf("%s: atw_recv_beacon: no node %s\n", 2083 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2084 return; 2085 } 2086 2087 if (ieee80211_match_bss(ic, ni) != 0) 2088 return; 2089 2090 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2091 return; 2092 2093 if (do_print) 2094 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2095 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2096 2097 if (ic->ic_opmode != IEEE80211_M_IBSS) 2098 return; 2099 2100 atw_tsft(sc, &tsfth, &tsftl); 2101 2102 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2103 bcn_tsftl = le32toh(u.words[0]); 2104 bcn_tsfth = le32toh(u.words[1]); 2105 2106 if (do_print) 2107 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2108 sc->sc_dev.dv_xname, ((uint64_t)tsfth << 32) | tsftl, 2109 ((uint64_t)bcn_tsfth << 32) | bcn_tsftl); 2110 2111 /* we are faster, let the other guy catch up */ 2112 if (bcn_tsfth < tsfth) 2113 return; 2114 else if (bcn_tsfth == tsfth && bcn_tsftl < tsftl) 2115 return; 2116 2117 if (do_print) 2118 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2119 ether_sprintf(wh->i_addr2)); 2120 2121 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2122 2123 atw_tsf(sc); 2124 2125 /* negotiate rates with new IBSS */ 2126 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2127 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2128 if (ni->ni_rates.rs_nrates == 0) { 2129 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2130 ether_sprintf(ni->ni_bssid)); 2131 return; 2132 } 2133 2134 if (do_print) { 2135 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2136 ether_sprintf(ic->ic_bss->ni_bssid)); 2137 printf("%s ", ether_sprintf(ni->ni_bssid)); 2138 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2139 } 2140 2141 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2142 2143 atw_write_bssid(sc); 2144 atw_start_beacon(sc, 1); 2145 } 2146 2147 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2148 * In ad hoc mode, the SSID is written to the beacons sent by the 2149 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2150 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2151 * indications. 2152 */ 2153 static void 2154 atw_write_ssid(struct atw_softc *sc) 2155 { 2156 struct ieee80211com *ic = &sc->sc_ic; 2157 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2158 * it only expects the element length, not its ID. 2159 */ 2160 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2161 2162 memset(buf, 0, sizeof(buf)); 2163 buf[0] = ic->ic_bss->ni_esslen; 2164 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2165 2166 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2167 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2168 } 2169 2170 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2171 * In ad hoc mode, the supported rates are written to beacons sent by the 2172 * ADM8211. 2173 */ 2174 static void 2175 atw_write_sup_rates(struct atw_softc *sc) 2176 { 2177 struct ieee80211com *ic = &sc->sc_ic; 2178 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2179 * supported rates 2180 */ 2181 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2182 2183 memset(buf, 0, sizeof(buf)); 2184 2185 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2186 2187 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2188 ic->ic_bss->ni_rates.rs_nrates); 2189 2190 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2191 } 2192 2193 /* Start/stop sending beacons. */ 2194 void 2195 atw_start_beacon(struct atw_softc *sc, int start) 2196 { 2197 struct ieee80211com *ic = &sc->sc_ic; 2198 uint16_t chan; 2199 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2200 size_t len; 2201 2202 if (ATW_IS_ENABLED(sc) == 0) 2203 return; 2204 2205 /* start beacons */ 2206 len = sizeof(struct ieee80211_frame) + 2207 8 /* timestamp */ + 2 /* beacon interval */ + 2208 2 /* capability info */ + 2209 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2210 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2211 3 /* DS parameters */ + 2212 IEEE80211_CRC_LEN; 2213 2214 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2215 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2216 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2217 2218 ATW_WRITE(sc, ATW_BCNT, bcnt); 2219 ATW_WRITE(sc, ATW_CAP1, cap1); 2220 2221 if (!start) 2222 return; 2223 2224 /* TBD use ni_capinfo */ 2225 2226 capinfo = 0; 2227 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2228 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2229 if (ic->ic_flags & IEEE80211_F_WEPON) 2230 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2231 2232 switch (ic->ic_opmode) { 2233 case IEEE80211_M_IBSS: 2234 len += 4; /* IBSS parameters */ 2235 capinfo |= IEEE80211_CAPINFO_IBSS; 2236 break; 2237 case IEEE80211_M_HOSTAP: 2238 /* XXX 6-byte minimum TIM */ 2239 len += atw_beacon_len_adjust; 2240 capinfo |= IEEE80211_CAPINFO_ESS; 2241 break; 2242 default: 2243 return; 2244 } 2245 2246 /* set listen interval 2247 * XXX do software units agree w/ hardware? 2248 */ 2249 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2250 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2251 2252 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2253 2254 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2255 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2256 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2257 2258 ATW_WRITE(sc, ATW_BCNT, bcnt); 2259 ATW_WRITE(sc, ATW_BPLI, bpli); 2260 ATW_WRITE(sc, ATW_CAP0, cap0); 2261 ATW_WRITE(sc, ATW_CAP1, cap1); 2262 2263 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2264 sc->sc_dev.dv_xname, bcnt)); 2265 2266 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2267 sc->sc_dev.dv_xname, cap1)); 2268 } 2269 2270 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2271 static __inline uint32_t 2272 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2273 { 2274 /* Following the reference driver's lead, I compute 2275 * 2276 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2277 * 2278 * without using 64-bit arithmetic, using the following 2279 * relationship: 2280 * 2281 * (0x100000000 * H + L) % m 2282 * = ((0x100000000 % m) * H + L) % m 2283 * = (((0xffffffff + 1) % m) * H + L) % m 2284 * = ((0xffffffff % m + 1 % m) * H + L) % m 2285 * = ((0xffffffff % m + 1) * H + L) % m 2286 */ 2287 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2288 } 2289 2290 static __inline void 2291 atw_tsft(struct atw_softc *sc, uint32_t *tsfth, uint32_t *tsftl) 2292 { 2293 int i; 2294 for (i = 0; i < 2; i++) { 2295 *tsfth = ATW_READ(sc, ATW_TSFTH); 2296 *tsftl = ATW_READ(sc, ATW_TSFTL); 2297 if (ATW_READ(sc, ATW_TSFTH) == *tsfth) 2298 break; 2299 } 2300 } 2301 2302 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2303 * the ieee80211com. 2304 * 2305 * Predict the next target beacon transmission time (TBTT) and 2306 * write it to the ADM8211. 2307 */ 2308 static void 2309 atw_tsf(struct atw_softc *sc) 2310 { 2311 #define TBTTOFS 20 /* TU */ 2312 2313 struct ieee80211com *ic = &sc->sc_ic; 2314 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2315 union { 2316 uint32_t words[2]; 2317 uint8_t tstamp[8]; 2318 } u; 2319 2320 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2321 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2322 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2323 atw_tsft(sc, &tsfth, &tsftl); 2324 u.words[0] = htole32(tsftl); 2325 u.words[1] = htole32(tsfth); 2326 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u, 2327 sizeof(ic->ic_bss->ni_tstamp)); 2328 } else { 2329 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2330 tsftl = le32toh(u.words[0]); 2331 tsfth = le32toh(u.words[1]); 2332 } 2333 2334 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2335 2336 /* We sent/received the last beacon `past' microseconds 2337 * after the interval divided the TSF timer. 2338 */ 2339 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2340 2341 /* Skip ten beacons so that the TBTT cannot pass before 2342 * we've programmed it. Ten is an arbitrary number. 2343 */ 2344 tbtt = past_even + ival * 10; 2345 2346 ATW_WRITE(sc, ATW_TOFS1, 2347 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2348 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2349 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2350 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2351 #undef TBTTOFS 2352 } 2353 2354 static void 2355 atw_next_scan(void *arg) 2356 { 2357 struct atw_softc *sc = arg; 2358 struct ieee80211com *ic = &sc->sc_ic; 2359 struct ifnet *ifp = &ic->ic_if; 2360 int s; 2361 2362 /* don't call atw_start w/o network interrupts blocked */ 2363 s = splnet(); 2364 if (ic->ic_state == IEEE80211_S_SCAN) 2365 ieee80211_next_scan(ifp); 2366 splx(s); 2367 } 2368 2369 /* Synchronize the hardware state with the software state. */ 2370 static int 2371 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2372 { 2373 struct ifnet *ifp = &ic->ic_if; 2374 struct atw_softc *sc = ifp->if_softc; 2375 enum ieee80211_state ostate; 2376 int error; 2377 2378 ostate = ic->ic_state; 2379 2380 if (nstate == IEEE80211_S_INIT) { 2381 callout_stop(&sc->sc_scan_ch); 2382 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2383 atw_start_beacon(sc, 0); 2384 return (*sc->sc_newstate)(ic, nstate, arg); 2385 } 2386 2387 if ((error = atw_tune(sc)) != 0) 2388 return error; 2389 2390 switch (nstate) { 2391 case IEEE80211_S_ASSOC: 2392 break; 2393 case IEEE80211_S_INIT: 2394 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2395 break; 2396 case IEEE80211_S_SCAN: 2397 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2398 atw_next_scan, sc); 2399 2400 break; 2401 case IEEE80211_S_RUN: 2402 if (ic->ic_opmode == IEEE80211_M_STA) 2403 break; 2404 /*FALLTHROUGH*/ 2405 case IEEE80211_S_AUTH: 2406 atw_write_bssid(sc); 2407 atw_write_ssid(sc); 2408 atw_write_sup_rates(sc); 2409 2410 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2411 ic->ic_opmode == IEEE80211_M_MONITOR) 2412 break; 2413 2414 /* set listen interval 2415 * XXX do software units agree w/ hardware? 2416 */ 2417 ATW_WRITE(sc, ATW_BPLI, 2418 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2419 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2420 ATW_BPLI_LI_MASK)); 2421 2422 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2423 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2424 2425 atw_tsf(sc); 2426 break; 2427 } 2428 2429 if (nstate != IEEE80211_S_SCAN) 2430 callout_stop(&sc->sc_scan_ch); 2431 2432 if (nstate == IEEE80211_S_RUN && 2433 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2434 ic->ic_opmode == IEEE80211_M_IBSS)) 2435 atw_start_beacon(sc, 1); 2436 else 2437 atw_start_beacon(sc, 0); 2438 2439 error = (*sc->sc_newstate)(ic, nstate, arg); 2440 2441 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2442 atw_write_bssid(sc); 2443 2444 return error; 2445 } 2446 2447 /* 2448 * atw_add_rxbuf: 2449 * 2450 * Add a receive buffer to the indicated descriptor. 2451 */ 2452 int 2453 atw_add_rxbuf(struct atw_softc *sc, int idx) 2454 { 2455 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2456 struct mbuf *m; 2457 int error; 2458 2459 MGETHDR(m, M_DONTWAIT, MT_DATA); 2460 if (m == NULL) 2461 return (ENOBUFS); 2462 2463 MCLGET(m, M_DONTWAIT); 2464 if ((m->m_flags & M_EXT) == 0) { 2465 m_freem(m); 2466 return (ENOBUFS); 2467 } 2468 2469 if (rxs->rxs_mbuf != NULL) 2470 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2471 2472 rxs->rxs_mbuf = m; 2473 2474 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2475 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2476 BUS_DMA_READ|BUS_DMA_NOWAIT); 2477 if (error) { 2478 printf("%s: can't load rx DMA map %d, error = %d\n", 2479 sc->sc_dev.dv_xname, idx, error); 2480 panic("atw_add_rxbuf"); /* XXX */ 2481 } 2482 2483 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2484 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2485 2486 ATW_INIT_RXDESC(sc, idx); 2487 2488 return (0); 2489 } 2490 2491 /* 2492 * Release any queued transmit buffers. 2493 */ 2494 void 2495 atw_txdrain(struct atw_softc *sc) 2496 { 2497 struct atw_txsoft *txs; 2498 2499 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2500 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2501 if (txs->txs_mbuf != NULL) { 2502 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2503 m_freem(txs->txs_mbuf); 2504 txs->txs_mbuf = NULL; 2505 } 2506 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2507 } 2508 sc->sc_tx_timer = 0; 2509 } 2510 2511 /* 2512 * atw_stop: [ ifnet interface function ] 2513 * 2514 * Stop transmission on the interface. 2515 */ 2516 void 2517 atw_stop(struct ifnet *ifp, int disable) 2518 { 2519 struct atw_softc *sc = ifp->if_softc; 2520 struct ieee80211com *ic = &sc->sc_ic; 2521 2522 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2523 2524 /* Disable interrupts. */ 2525 ATW_WRITE(sc, ATW_IER, 0); 2526 2527 /* Stop the transmit and receive processes. */ 2528 sc->sc_opmode = 0; 2529 ATW_WRITE(sc, ATW_NAR, 0); 2530 DELAY(20 * 1000); 2531 ATW_WRITE(sc, ATW_TDBD, 0); 2532 ATW_WRITE(sc, ATW_TDBP, 0); 2533 ATW_WRITE(sc, ATW_RDB, 0); 2534 2535 atw_txdrain(sc); 2536 2537 if (disable) { 2538 atw_rxdrain(sc); 2539 atw_disable(sc); 2540 } 2541 2542 /* 2543 * Mark the interface down and cancel the watchdog timer. 2544 */ 2545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2546 ifp->if_timer = 0; 2547 2548 if (!disable) 2549 atw_reset(sc); 2550 } 2551 2552 /* 2553 * atw_rxdrain: 2554 * 2555 * Drain the receive queue. 2556 */ 2557 void 2558 atw_rxdrain(struct atw_softc *sc) 2559 { 2560 struct atw_rxsoft *rxs; 2561 int i; 2562 2563 for (i = 0; i < ATW_NRXDESC; i++) { 2564 rxs = &sc->sc_rxsoft[i]; 2565 if (rxs->rxs_mbuf == NULL) 2566 continue; 2567 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2568 m_freem(rxs->rxs_mbuf); 2569 rxs->rxs_mbuf = NULL; 2570 } 2571 } 2572 2573 /* 2574 * atw_detach: 2575 * 2576 * Detach an ADM8211 interface. 2577 */ 2578 int 2579 atw_detach(struct atw_softc *sc) 2580 { 2581 struct ifnet *ifp = &sc->sc_ic.ic_if; 2582 struct atw_rxsoft *rxs; 2583 struct atw_txsoft *txs; 2584 int i; 2585 2586 /* 2587 * Succeed now if there isn't any work to do. 2588 */ 2589 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2590 return (0); 2591 2592 ieee80211_ifdetach(ifp); 2593 if_detach(ifp); 2594 2595 for (i = 0; i < ATW_NRXDESC; i++) { 2596 rxs = &sc->sc_rxsoft[i]; 2597 if (rxs->rxs_mbuf != NULL) { 2598 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2599 m_freem(rxs->rxs_mbuf); 2600 rxs->rxs_mbuf = NULL; 2601 } 2602 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2603 } 2604 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2605 txs = &sc->sc_txsoft[i]; 2606 if (txs->txs_mbuf != NULL) { 2607 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2608 m_freem(txs->txs_mbuf); 2609 txs->txs_mbuf = NULL; 2610 } 2611 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2612 } 2613 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2614 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2615 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2616 sizeof(struct atw_control_data)); 2617 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2618 2619 shutdownhook_disestablish(sc->sc_sdhook); 2620 powerhook_disestablish(sc->sc_powerhook); 2621 2622 if (sc->sc_srom) 2623 free(sc->sc_srom, M_DEVBUF); 2624 2625 return (0); 2626 } 2627 2628 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2629 void 2630 atw_shutdown(void *arg) 2631 { 2632 struct atw_softc *sc = arg; 2633 2634 atw_stop(&sc->sc_ic.ic_if, 1); 2635 } 2636 2637 int 2638 atw_intr(void *arg) 2639 { 2640 struct atw_softc *sc = arg; 2641 struct ifnet *ifp = &sc->sc_ic.ic_if; 2642 u_int32_t status, rxstatus, txstatus, linkstatus; 2643 int handled = 0, txthresh; 2644 2645 #ifdef DEBUG 2646 if (ATW_IS_ENABLED(sc) == 0) 2647 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2648 #endif 2649 2650 /* 2651 * If the interface isn't running, the interrupt couldn't 2652 * possibly have come from us. 2653 */ 2654 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2655 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2656 return (0); 2657 2658 for (;;) { 2659 status = ATW_READ(sc, ATW_STSR); 2660 2661 if (status) 2662 ATW_WRITE(sc, ATW_STSR, status); 2663 2664 #ifdef ATW_DEBUG 2665 #define PRINTINTR(flag) do { \ 2666 if ((status & flag) != 0) { \ 2667 printf("%s" #flag, delim); \ 2668 delim = ","; \ 2669 } \ 2670 } while (0) 2671 2672 if (atw_debug > 1 && status) { 2673 const char *delim = "<"; 2674 2675 printf("%s: reg[STSR] = %x", 2676 sc->sc_dev.dv_xname, status); 2677 2678 PRINTINTR(ATW_INTR_FBE); 2679 PRINTINTR(ATW_INTR_LINKOFF); 2680 PRINTINTR(ATW_INTR_LINKON); 2681 PRINTINTR(ATW_INTR_RCI); 2682 PRINTINTR(ATW_INTR_RDU); 2683 PRINTINTR(ATW_INTR_REIS); 2684 PRINTINTR(ATW_INTR_RPS); 2685 PRINTINTR(ATW_INTR_TCI); 2686 PRINTINTR(ATW_INTR_TDU); 2687 PRINTINTR(ATW_INTR_TLT); 2688 PRINTINTR(ATW_INTR_TPS); 2689 PRINTINTR(ATW_INTR_TRT); 2690 PRINTINTR(ATW_INTR_TUF); 2691 PRINTINTR(ATW_INTR_BCNTC); 2692 PRINTINTR(ATW_INTR_ATIME); 2693 PRINTINTR(ATW_INTR_TBTT); 2694 PRINTINTR(ATW_INTR_TSCZ); 2695 PRINTINTR(ATW_INTR_TSFTF); 2696 printf(">\n"); 2697 } 2698 #undef PRINTINTR 2699 #endif /* ATW_DEBUG */ 2700 2701 if ((status & sc->sc_inten) == 0) 2702 break; 2703 2704 handled = 1; 2705 2706 rxstatus = status & sc->sc_rxint_mask; 2707 txstatus = status & sc->sc_txint_mask; 2708 linkstatus = status & sc->sc_linkint_mask; 2709 2710 if (linkstatus) { 2711 atw_linkintr(sc, linkstatus); 2712 } 2713 2714 if (rxstatus) { 2715 /* Grab any new packets. */ 2716 atw_rxintr(sc); 2717 2718 if (rxstatus & ATW_INTR_RDU) { 2719 printf("%s: receive ring overrun\n", 2720 sc->sc_dev.dv_xname); 2721 /* Get the receive process going again. */ 2722 ATW_WRITE(sc, ATW_RDR, 0x1); 2723 break; 2724 } 2725 } 2726 2727 if (txstatus) { 2728 /* Sweep up transmit descriptors. */ 2729 atw_txintr(sc); 2730 2731 if (txstatus & ATW_INTR_TLT) 2732 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2733 sc->sc_dev.dv_xname)); 2734 2735 if (txstatus & ATW_INTR_TRT) 2736 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2737 sc->sc_dev.dv_xname)); 2738 2739 /* If Tx under-run, increase our transmit threshold 2740 * if another is available. 2741 */ 2742 txthresh = sc->sc_txthresh + 1; 2743 if ((txstatus & ATW_INTR_TUF) && 2744 sc->sc_txth[txthresh].txth_name != NULL) { 2745 /* Idle the transmit process. */ 2746 atw_idle(sc, ATW_NAR_ST); 2747 2748 sc->sc_txthresh = txthresh; 2749 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2750 sc->sc_opmode |= 2751 sc->sc_txth[txthresh].txth_opmode; 2752 printf("%s: transmit underrun; new " 2753 "threshold: %s\n", sc->sc_dev.dv_xname, 2754 sc->sc_txth[txthresh].txth_name); 2755 2756 /* Set the new threshold and restart 2757 * the transmit process. 2758 */ 2759 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2760 DELAY(20 * 1000); 2761 ATW_WRITE(sc, ATW_RDR, 0x1); 2762 /* XXX Log every Nth underrun from 2763 * XXX now on? 2764 */ 2765 } 2766 } 2767 2768 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2769 if (status & ATW_INTR_TPS) 2770 printf("%s: transmit process stopped\n", 2771 sc->sc_dev.dv_xname); 2772 if (status & ATW_INTR_RPS) 2773 printf("%s: receive process stopped\n", 2774 sc->sc_dev.dv_xname); 2775 (void)atw_init(ifp); 2776 break; 2777 } 2778 2779 if (status & ATW_INTR_FBE) { 2780 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2781 (void)atw_init(ifp); 2782 break; 2783 } 2784 2785 /* 2786 * Not handled: 2787 * 2788 * Transmit buffer unavailable -- normal 2789 * condition, nothing to do, really. 2790 * 2791 * Early receive interrupt -- not available on 2792 * all chips, we just use RI. We also only 2793 * use single-segment receive DMA, so this 2794 * is mostly useless. 2795 * 2796 * TBD others 2797 */ 2798 } 2799 2800 /* Try to get more packets going. */ 2801 atw_start(ifp); 2802 2803 return (handled); 2804 } 2805 2806 /* 2807 * atw_idle: 2808 * 2809 * Cause the transmit and/or receive processes to go idle. 2810 * 2811 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2812 * process in STSR if I clear SR or ST after the process has already 2813 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2814 * do not seem to be too reliable. Perhaps I have the sense of the 2815 * Rx bits switched with the Tx bits? 2816 */ 2817 void 2818 atw_idle(struct atw_softc *sc, u_int32_t bits) 2819 { 2820 u_int32_t ackmask = 0, opmode, stsr, test0; 2821 int i, s; 2822 2823 s = splnet(); 2824 2825 opmode = sc->sc_opmode & ~bits; 2826 2827 if (bits & ATW_NAR_SR) 2828 ackmask |= ATW_INTR_RPS; 2829 2830 if (bits & ATW_NAR_ST) { 2831 ackmask |= ATW_INTR_TPS; 2832 /* set ATW_NAR_HF to flush TX FIFO. */ 2833 opmode |= ATW_NAR_HF; 2834 } 2835 2836 ATW_WRITE(sc, ATW_NAR, opmode); 2837 DELAY(20 * 1000); 2838 2839 for (i = 0; i < 10; i++) { 2840 stsr = ATW_READ(sc, ATW_STSR); 2841 if ((stsr & ackmask) == ackmask) 2842 break; 2843 DELAY(1000); 2844 } 2845 2846 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2847 2848 if ((stsr & ackmask) == ackmask) 2849 goto out; 2850 2851 test0 = ATW_READ(sc, ATW_TEST0); 2852 2853 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2854 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2855 printf("%s: transmit process not idle [%s]\n", 2856 sc->sc_dev.dv_xname, 2857 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2858 printf("%s: bits %08x test0 %08x stsr %08x\n", 2859 sc->sc_dev.dv_xname, bits, test0, stsr); 2860 } 2861 2862 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2863 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2864 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2865 sc->sc_dev.dv_xname, 2866 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2867 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2868 sc->sc_dev.dv_xname, bits, test0, stsr)); 2869 } 2870 out: 2871 if ((bits & ATW_NAR_ST) != 0) 2872 atw_txdrain(sc); 2873 splx(s); 2874 return; 2875 } 2876 2877 /* 2878 * atw_linkintr: 2879 * 2880 * Helper; handle link-status interrupts. 2881 */ 2882 void 2883 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2884 { 2885 struct ieee80211com *ic = &sc->sc_ic; 2886 2887 if (ic->ic_state != IEEE80211_S_RUN) 2888 return; 2889 2890 if (linkstatus & ATW_INTR_LINKON) { 2891 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2892 sc->sc_rescan_timer = 0; 2893 } else if (linkstatus & ATW_INTR_LINKOFF) { 2894 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2895 if (ic->ic_opmode != IEEE80211_M_STA) 2896 return; 2897 sc->sc_rescan_timer = 3; 2898 ic->ic_if.if_timer = 1; 2899 } 2900 } 2901 2902 /* 2903 * atw_rxintr: 2904 * 2905 * Helper; handle receive interrupts. 2906 */ 2907 void 2908 atw_rxintr(struct atw_softc *sc) 2909 { 2910 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2911 struct ieee80211com *ic = &sc->sc_ic; 2912 struct ieee80211_node *ni; 2913 struct ieee80211_frame *wh; 2914 struct ifnet *ifp = &ic->ic_if; 2915 struct atw_rxsoft *rxs; 2916 struct mbuf *m; 2917 u_int32_t rxstat; 2918 int i, len, rate, rate0; 2919 u_int32_t rssi; 2920 2921 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2922 rxs = &sc->sc_rxsoft[i]; 2923 2924 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2925 2926 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2927 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2928 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2929 2930 if (rxstat & ATW_RXSTAT_OWN) 2931 break; /* We have processed all receive buffers. */ 2932 2933 DPRINTF3(sc, 2934 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2935 sc->sc_dev.dv_xname, 2936 le32toh(sc->sc_rxdescs[i].ar_stat), 2937 le32toh(sc->sc_rxdescs[i].ar_rssi), 2938 le32toh(sc->sc_rxdescs[i].ar_buf1), 2939 le32toh(sc->sc_rxdescs[i].ar_buf2))); 2940 2941 /* 2942 * Make sure the packet fits in one buffer. This should 2943 * always be the case. 2944 */ 2945 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2946 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2947 printf("%s: incoming packet spilled, resetting\n", 2948 sc->sc_dev.dv_xname); 2949 (void)atw_init(ifp); 2950 return; 2951 } 2952 2953 /* 2954 * If an error occurred, update stats, clear the status 2955 * word, and leave the packet buffer in place. It will 2956 * simply be reused the next time the ring comes around. 2957 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2958 * error. 2959 */ 2960 2961 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2962 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2963 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2964 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2965 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2966 ATW_RXSTAT_ICVE)) != 0)) { 2967 #define PRINTERR(bit, str) \ 2968 if (rxstat & (bit)) \ 2969 printf("%s: receive error: %s\n", \ 2970 sc->sc_dev.dv_xname, str) 2971 ifp->if_ierrors++; 2972 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2973 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2974 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2975 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2976 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2977 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2978 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2979 #undef PRINTERR 2980 ATW_INIT_RXDESC(sc, i); 2981 continue; 2982 } 2983 2984 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2985 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2986 2987 /* 2988 * No errors; receive the packet. Note the ADM8211 2989 * includes the CRC in promiscuous mode. 2990 */ 2991 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2992 2993 /* 2994 * Allocate a new mbuf cluster. If that fails, we are 2995 * out of memory, and must drop the packet and recycle 2996 * the buffer that's already attached to this descriptor. 2997 */ 2998 m = rxs->rxs_mbuf; 2999 if (atw_add_rxbuf(sc, i) != 0) { 3000 ifp->if_ierrors++; 3001 ATW_INIT_RXDESC(sc, i); 3002 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3003 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3004 continue; 3005 } 3006 3007 ifp->if_ipackets++; 3008 if (sc->sc_opmode & ATW_NAR_PR) 3009 m->m_flags |= M_HASFCS; 3010 m->m_pkthdr.rcvif = ifp; 3011 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3012 3013 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3014 rate = 0; 3015 else 3016 rate = rate_tbl[rate0]; 3017 3018 #if NBPFILTER > 0 3019 /* Pass this up to any BPF listeners. */ 3020 if (sc->sc_radiobpf != NULL) { 3021 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3022 3023 tap->ar_rate = rate; 3024 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3025 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3026 3027 /* TBD verify units are dB */ 3028 tap->ar_antsignal = (int)rssi; 3029 /* TBD tap->ar_flags */ 3030 3031 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3032 tap->ar_ihdr.it_len, m); 3033 } 3034 #endif /* NPBFILTER > 0 */ 3035 3036 wh = mtod(m, struct ieee80211_frame *); 3037 ni = ieee80211_find_rxnode(ic, wh); 3038 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3039 /* 3040 * The frame may have caused the node to be marked for 3041 * reclamation (e.g. in response to a DEAUTH message) 3042 * so use free_node here instead of unref_node. 3043 */ 3044 if (ni == ic->ic_bss) 3045 ieee80211_unref_node(&ni); 3046 else 3047 ieee80211_free_node(ic, ni); 3048 } 3049 3050 /* Update the receive pointer. */ 3051 sc->sc_rxptr = i; 3052 } 3053 3054 /* 3055 * atw_txintr: 3056 * 3057 * Helper; handle transmit interrupts. 3058 */ 3059 void 3060 atw_txintr(struct atw_softc *sc) 3061 { 3062 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3063 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3064 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3065 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3066 3067 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3068 struct ifnet *ifp = &sc->sc_ic.ic_if; 3069 struct atw_txsoft *txs; 3070 u_int32_t txstat; 3071 3072 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3073 sc->sc_dev.dv_xname, sc->sc_flags)); 3074 3075 ifp->if_flags &= ~IFF_OACTIVE; 3076 3077 /* 3078 * Go through our Tx list and free mbufs for those 3079 * frames that have been transmitted. 3080 */ 3081 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3082 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3083 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3084 3085 #ifdef ATW_DEBUG 3086 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3087 int i; 3088 printf(" txsoft %p transmit chain:\n", txs); 3089 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3090 txs->txs_ndescs - 1, 3091 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3092 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3093 printf(" descriptor %d:\n", i); 3094 printf(" at_status: 0x%08x\n", 3095 le32toh(sc->sc_txdescs[i].at_stat)); 3096 printf(" at_flags: 0x%08x\n", 3097 le32toh(sc->sc_txdescs[i].at_flags)); 3098 printf(" at_buf1: 0x%08x\n", 3099 le32toh(sc->sc_txdescs[i].at_buf1)); 3100 printf(" at_buf2: 0x%08x\n", 3101 le32toh(sc->sc_txdescs[i].at_buf2)); 3102 if (i == txs->txs_lastdesc) 3103 break; 3104 } 3105 } 3106 #endif 3107 3108 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3109 if (txstat & ATW_TXSTAT_OWN) 3110 break; 3111 3112 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3113 3114 sc->sc_txfree += txs->txs_ndescs; 3115 3116 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3117 0, txs->txs_dmamap->dm_mapsize, 3118 BUS_DMASYNC_POSTWRITE); 3119 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3120 m_freem(txs->txs_mbuf); 3121 txs->txs_mbuf = NULL; 3122 3123 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3124 3125 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3126 (txstat & TXSTAT_ERRMASK) != 0) { 3127 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3128 txstat_buf, sizeof(txstat_buf)); 3129 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3130 txstat_buf, 3131 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3132 } 3133 3134 /* 3135 * Check for errors and collisions. 3136 */ 3137 if (txstat & ATW_TXSTAT_TUF) 3138 sc->sc_stats.ts_tx_tuf++; 3139 if (txstat & ATW_TXSTAT_TLT) 3140 sc->sc_stats.ts_tx_tlt++; 3141 if (txstat & ATW_TXSTAT_TRT) 3142 sc->sc_stats.ts_tx_trt++; 3143 if (txstat & ATW_TXSTAT_TRO) 3144 sc->sc_stats.ts_tx_tro++; 3145 if (txstat & ATW_TXSTAT_SOFBR) { 3146 sc->sc_stats.ts_tx_sofbr++; 3147 } 3148 3149 if ((txstat & ATW_TXSTAT_ES) == 0) 3150 ifp->if_collisions += 3151 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3152 else 3153 ifp->if_oerrors++; 3154 3155 ifp->if_opackets++; 3156 } 3157 3158 /* 3159 * If there are no more pending transmissions, cancel the watchdog 3160 * timer. 3161 */ 3162 if (txs == NULL) 3163 sc->sc_tx_timer = 0; 3164 #undef TXSTAT_ERRMASK 3165 #undef TXSTAT_FMT 3166 } 3167 3168 /* 3169 * atw_watchdog: [ifnet interface function] 3170 * 3171 * Watchdog timer handler. 3172 */ 3173 void 3174 atw_watchdog(struct ifnet *ifp) 3175 { 3176 struct atw_softc *sc = ifp->if_softc; 3177 struct ieee80211com *ic = &sc->sc_ic; 3178 3179 ifp->if_timer = 0; 3180 if (ATW_IS_ENABLED(sc) == 0) 3181 return; 3182 3183 if (sc->sc_rescan_timer) { 3184 if (--sc->sc_rescan_timer == 0) 3185 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3186 } 3187 if (sc->sc_tx_timer) { 3188 if (--sc->sc_tx_timer == 0 && 3189 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3190 printf("%s: transmit timeout\n", ifp->if_xname); 3191 ifp->if_oerrors++; 3192 (void)atw_init(ifp); 3193 atw_start(ifp); 3194 } 3195 } 3196 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3197 ifp->if_timer = 1; 3198 ieee80211_watchdog(ifp); 3199 } 3200 3201 /* Compute the 802.11 Duration field and the PLCP Length fields for 3202 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3203 * Write the fields to the ADM8211 Tx header, frm. 3204 * 3205 * TBD use the fragmentation threshold to find the right duration for 3206 * the first & last fragments. 3207 * 3208 * TBD make certain of the duration fields applied by the ADM8211 to each 3209 * fragment. I think that the ADM8211 knows how to subtract the CTS 3210 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3211 * I also think that the ADM8211 does *some* arithmetic for us, because 3212 * otherwise I think we would have to set a first duration for CTS/first 3213 * fragment, a second duration for fragments between the first and the 3214 * last, and a third duration for the last fragment. 3215 * 3216 * TBD make certain that duration fields reflect addition of FCS/WEP 3217 * and correct duration arithmetic as necessary. 3218 */ 3219 static void 3220 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3221 int len) 3222 { 3223 int remainder; 3224 3225 /* deal also with encrypted fragments */ 3226 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3227 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3228 sc->sc_dev.dv_xname)); 3229 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3230 IEEE80211_WEP_CRCLEN; 3231 } 3232 3233 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3234 * duration (XXX added by MAC?). 3235 */ 3236 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3237 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3238 3239 if (rate <= 4) 3240 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3241 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3242 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3243 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3244 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3245 else 3246 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3247 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3248 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3249 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3250 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3251 3252 /* lengthen duration if long preamble */ 3253 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3254 frm->atw_head_dur += 3255 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3256 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3257 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3258 IEEE80211_DUR_DS_FAST_PLCPHDR); 3259 3260 if (remainder != 0) 3261 frm->atw_head_dur++; 3262 3263 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3264 (rate == 2 || rate == 4)) { 3265 /* derived from Linux: how could this be right? */ 3266 frm->atw_head_plcplen = frm->atw_head_dur; 3267 } else { 3268 frm->atw_head_plcplen = (16 * len) / rate; 3269 remainder = (80 * len) % (rate * 5); 3270 3271 if (remainder != 0) { 3272 frm->atw_head_plcplen++; 3273 3274 /* XXX magic */ 3275 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3276 rate == 22 && remainder <= 30) 3277 frm->atw_head_plcplen |= 0x8000; 3278 } 3279 } 3280 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3281 htole16(frm->atw_head_plcplen); 3282 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3283 } 3284 3285 #ifdef ATW_DEBUG 3286 static void 3287 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3288 { 3289 struct atw_softc *sc = ifp->if_softc; 3290 struct mbuf *m; 3291 int i, noctets = 0; 3292 3293 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3294 m0->m_pkthdr.len); 3295 3296 for (m = m0; m; m = m->m_next) { 3297 if (m->m_len == 0) 3298 continue; 3299 for (i = 0; i < m->m_len; i++) { 3300 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3301 if (++noctets % 24 == 0) 3302 printf("\n"); 3303 } 3304 } 3305 printf("%s%s: %d bytes emitted\n", 3306 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3307 } 3308 #endif /* ATW_DEBUG */ 3309 3310 /* 3311 * atw_start: [ifnet interface function] 3312 * 3313 * Start packet transmission on the interface. 3314 */ 3315 void 3316 atw_start(struct ifnet *ifp) 3317 { 3318 struct atw_softc *sc = ifp->if_softc; 3319 struct ieee80211com *ic = &sc->sc_ic; 3320 struct ieee80211_node *ni; 3321 struct ieee80211_frame *wh; 3322 struct atw_frame *hh; 3323 struct mbuf *m0, *m; 3324 struct atw_txsoft *txs, *last_txs; 3325 struct atw_txdesc *txd; 3326 int do_encrypt, rate; 3327 bus_dmamap_t dmamap; 3328 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3329 3330 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3331 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3332 3333 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3334 return; 3335 3336 /* 3337 * Remember the previous number of free descriptors and 3338 * the first descriptor we'll use. 3339 */ 3340 ofree = sc->sc_txfree; 3341 firsttx = sc->sc_txnext; 3342 3343 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3344 sc->sc_dev.dv_xname, ofree, firsttx)); 3345 3346 /* 3347 * Loop through the send queue, setting up transmit descriptors 3348 * until we drain the queue, or use up all available transmit 3349 * descriptors. 3350 */ 3351 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3352 sc->sc_txfree != 0) { 3353 3354 /* 3355 * Grab a packet off the management queue, if it 3356 * is not empty. Otherwise, from the data queue. 3357 */ 3358 IF_DEQUEUE(&ic->ic_mgtq, m0); 3359 if (m0 != NULL) { 3360 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3361 m0->m_pkthdr.rcvif = NULL; 3362 } else { 3363 /* send no data packets until we are associated */ 3364 if (ic->ic_state != IEEE80211_S_RUN) 3365 break; 3366 IFQ_DEQUEUE(&ifp->if_snd, m0); 3367 if (m0 == NULL) 3368 break; 3369 #if NBPFILTER > 0 3370 if (ifp->if_bpf != NULL) 3371 bpf_mtap(ifp->if_bpf, m0); 3372 #endif /* NBPFILTER > 0 */ 3373 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3374 ifp->if_oerrors++; 3375 break; 3376 } 3377 } 3378 3379 rate = MAX(ieee80211_get_rate(ic), 2); 3380 3381 #if NBPFILTER > 0 3382 /* 3383 * Pass the packet to any BPF listeners. 3384 */ 3385 if (ic->ic_rawbpf != NULL) 3386 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3387 3388 if (sc->sc_radiobpf != NULL) { 3389 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3390 3391 tap->at_rate = rate; 3392 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3393 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3394 3395 /* TBD tap->at_flags */ 3396 3397 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3398 tap->at_ihdr.it_len, m0); 3399 } 3400 #endif /* NBPFILTER > 0 */ 3401 3402 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3403 3404 if (ni != NULL && ni != ic->ic_bss) 3405 ieee80211_free_node(ic, ni); 3406 3407 if (m0 == NULL) { 3408 ifp->if_oerrors++; 3409 break; 3410 } 3411 3412 /* just to make sure. */ 3413 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3414 3415 if (m0 == NULL) { 3416 ifp->if_oerrors++; 3417 break; 3418 } 3419 3420 hh = mtod(m0, struct atw_frame *); 3421 wh = &hh->atw_ihdr; 3422 3423 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3424 3425 /* Copy everything we need from the 802.11 header: 3426 * Frame Control; address 1, address 3, or addresses 3427 * 3 and 4. NIC fills in BSSID, SA. 3428 */ 3429 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3430 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3431 panic("%s: illegal WDS frame", 3432 sc->sc_dev.dv_xname); 3433 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3434 } else 3435 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3436 3437 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3438 3439 /* initialize remaining Tx parameters */ 3440 memset(&hh->u, 0, sizeof(hh->u)); 3441 3442 hh->atw_rate = rate * 5; 3443 /* XXX this could be incorrect if M_FCS. _encap should 3444 * probably strip FCS just in case it sticks around in 3445 * bridged packets. 3446 */ 3447 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3448 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3449 sizeof(struct atw_frame)); 3450 3451 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3452 hh->atw_rtylmt = 3; 3453 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3454 if (do_encrypt) { 3455 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3456 hh->atw_keyid = ic->ic_wep_txkey; 3457 } 3458 3459 /* TBD 4-addr frames */ 3460 atw_frame_setdurs(sc, hh, rate, 3461 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3462 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3463 3464 /* never fragment multicast frames */ 3465 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3466 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3467 } else if (sc->sc_flags & ATWF_RTSCTS) { 3468 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3469 } 3470 3471 #ifdef ATW_DEBUG 3472 hh->atw_fragnum = 0; 3473 3474 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3475 printf("%s: dst = %s, rate = 0x%02x, " 3476 "service = 0x%02x, paylen = 0x%04x\n", 3477 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3478 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3479 3480 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3481 "dur1 = 0x%04x, dur2 = 0x%04x, " 3482 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3483 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3484 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3485 hh->atw_tail_dur, hh->atw_head_dur); 3486 3487 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3488 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3489 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3490 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3491 3492 printf("%s: keyid = %d\n", 3493 sc->sc_dev.dv_xname, hh->atw_keyid); 3494 3495 atw_dump_pkt(ifp, m0); 3496 } 3497 #endif /* ATW_DEBUG */ 3498 3499 dmamap = txs->txs_dmamap; 3500 3501 /* 3502 * Load the DMA map. Copy and try (once) again if the packet 3503 * didn't fit in the alloted number of segments. 3504 */ 3505 for (first = 1; 3506 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3507 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3508 first = 0) { 3509 MGETHDR(m, M_DONTWAIT, MT_DATA); 3510 if (m == NULL) { 3511 printf("%s: unable to allocate Tx mbuf\n", 3512 sc->sc_dev.dv_xname); 3513 break; 3514 } 3515 if (m0->m_pkthdr.len > MHLEN) { 3516 MCLGET(m, M_DONTWAIT); 3517 if ((m->m_flags & M_EXT) == 0) { 3518 printf("%s: unable to allocate Tx " 3519 "cluster\n", sc->sc_dev.dv_xname); 3520 m_freem(m); 3521 break; 3522 } 3523 } 3524 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3525 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3526 m_freem(m0); 3527 m0 = m; 3528 m = NULL; 3529 } 3530 if (error != 0) { 3531 printf("%s: unable to load Tx buffer, " 3532 "error = %d\n", sc->sc_dev.dv_xname, error); 3533 m_freem(m0); 3534 break; 3535 } 3536 3537 /* 3538 * Ensure we have enough descriptors free to describe 3539 * the packet. 3540 */ 3541 if (dmamap->dm_nsegs > sc->sc_txfree) { 3542 /* 3543 * Not enough free descriptors to transmit 3544 * this packet. Unload the DMA map and 3545 * drop the packet. Notify the upper layer 3546 * that there are no more slots left. 3547 * 3548 * XXX We could allocate an mbuf and copy, but 3549 * XXX it is worth it? 3550 */ 3551 ifp->if_flags |= IFF_OACTIVE; 3552 bus_dmamap_unload(sc->sc_dmat, dmamap); 3553 m_freem(m0); 3554 break; 3555 } 3556 3557 /* 3558 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3559 */ 3560 3561 /* Sync the DMA map. */ 3562 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3563 BUS_DMASYNC_PREWRITE); 3564 3565 /* XXX arbitrary retry limit; 8 because I have seen it in 3566 * use already and maybe 0 means "no tries" ! 3567 */ 3568 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3569 3570 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3571 sc->sc_dev.dv_xname, rate * 5)); 3572 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3573 3574 /* 3575 * Initialize the transmit descriptors. 3576 */ 3577 for (nexttx = sc->sc_txnext, seg = 0; 3578 seg < dmamap->dm_nsegs; 3579 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3580 /* 3581 * If this is the first descriptor we're 3582 * enqueueing, don't set the OWN bit just 3583 * yet. That could cause a race condition. 3584 * We'll do it below. 3585 */ 3586 txd = &sc->sc_txdescs[nexttx]; 3587 txd->at_ctl = ctl | 3588 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3589 3590 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3591 txd->at_flags = 3592 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3593 ATW_TXFLAG_TBS1_MASK)) | 3594 ((nexttx == (ATW_NTXDESC - 1)) 3595 ? htole32(ATW_TXFLAG_TER) : 0); 3596 lasttx = nexttx; 3597 } 3598 3599 IASSERT(lasttx != -1, ("bad lastx")); 3600 /* Set `first segment' and `last segment' appropriately. */ 3601 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3602 htole32(ATW_TXFLAG_FS); 3603 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3604 3605 #ifdef ATW_DEBUG 3606 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3607 printf(" txsoft %p transmit chain:\n", txs); 3608 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3609 printf(" descriptor %d:\n", seg); 3610 printf(" at_ctl: 0x%08x\n", 3611 le32toh(sc->sc_txdescs[seg].at_ctl)); 3612 printf(" at_flags: 0x%08x\n", 3613 le32toh(sc->sc_txdescs[seg].at_flags)); 3614 printf(" at_buf1: 0x%08x\n", 3615 le32toh(sc->sc_txdescs[seg].at_buf1)); 3616 printf(" at_buf2: 0x%08x\n", 3617 le32toh(sc->sc_txdescs[seg].at_buf2)); 3618 if (seg == lasttx) 3619 break; 3620 } 3621 } 3622 #endif 3623 3624 /* Sync the descriptors we're using. */ 3625 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3627 3628 /* 3629 * Store a pointer to the packet so we can free it later, 3630 * and remember what txdirty will be once the packet is 3631 * done. 3632 */ 3633 txs->txs_mbuf = m0; 3634 txs->txs_firstdesc = sc->sc_txnext; 3635 txs->txs_lastdesc = lasttx; 3636 txs->txs_ndescs = dmamap->dm_nsegs; 3637 3638 /* Advance the tx pointer. */ 3639 sc->sc_txfree -= dmamap->dm_nsegs; 3640 sc->sc_txnext = nexttx; 3641 3642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3643 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3644 3645 last_txs = txs; 3646 } 3647 3648 if (txs == NULL || sc->sc_txfree == 0) { 3649 /* No more slots left; notify upper layer. */ 3650 ifp->if_flags |= IFF_OACTIVE; 3651 } 3652 3653 if (sc->sc_txfree != ofree) { 3654 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3655 sc->sc_dev.dv_xname, lasttx, firsttx)); 3656 /* 3657 * Cause a transmit interrupt to happen on the 3658 * last packet we enqueued. 3659 */ 3660 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3661 ATW_CDTXSYNC(sc, lasttx, 1, 3662 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3663 3664 /* 3665 * The entire packet chain is set up. Give the 3666 * first descriptor to the chip now. 3667 */ 3668 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3669 ATW_CDTXSYNC(sc, firsttx, 1, 3670 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3671 3672 /* Wake up the transmitter. */ 3673 ATW_WRITE(sc, ATW_TDR, 0x1); 3674 3675 /* Set a watchdog timer in case the chip flakes out. */ 3676 sc->sc_tx_timer = 5; 3677 ifp->if_timer = 1; 3678 } 3679 } 3680 3681 /* 3682 * atw_power: 3683 * 3684 * Power management (suspend/resume) hook. 3685 */ 3686 void 3687 atw_power(int why, void *arg) 3688 { 3689 struct atw_softc *sc = arg; 3690 struct ifnet *ifp = &sc->sc_ic.ic_if; 3691 int s; 3692 3693 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3694 3695 s = splnet(); 3696 switch (why) { 3697 case PWR_STANDBY: 3698 /* XXX do nothing. */ 3699 break; 3700 case PWR_SUSPEND: 3701 atw_stop(ifp, 0); 3702 if (sc->sc_power != NULL) 3703 (*sc->sc_power)(sc, why); 3704 break; 3705 case PWR_RESUME: 3706 if (ifp->if_flags & IFF_UP) { 3707 if (sc->sc_power != NULL) 3708 (*sc->sc_power)(sc, why); 3709 atw_init(ifp); 3710 } 3711 break; 3712 case PWR_SOFTSUSPEND: 3713 case PWR_SOFTSTANDBY: 3714 case PWR_SOFTRESUME: 3715 break; 3716 } 3717 splx(s); 3718 } 3719 3720 /* 3721 * atw_ioctl: [ifnet interface function] 3722 * 3723 * Handle control requests from the operator. 3724 */ 3725 int 3726 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3727 { 3728 struct atw_softc *sc = ifp->if_softc; 3729 struct ifreq *ifr = (struct ifreq *)data; 3730 int s, error = 0; 3731 3732 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3733 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3734 return ENXIO; 3735 3736 s = splnet(); 3737 3738 switch (cmd) { 3739 case SIOCSIFFLAGS: 3740 if (ifp->if_flags & IFF_UP) { 3741 if (ATW_IS_ENABLED(sc)) { 3742 /* 3743 * To avoid rescanning another access point, 3744 * do not call atw_init() here. Instead, 3745 * only reflect media settings. 3746 */ 3747 atw_filter_setup(sc); 3748 } else 3749 error = atw_init(ifp); 3750 } else if (ATW_IS_ENABLED(sc)) 3751 atw_stop(ifp, 1); 3752 break; 3753 case SIOCADDMULTI: 3754 case SIOCDELMULTI: 3755 error = (cmd == SIOCADDMULTI) ? 3756 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3757 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3758 if (error == ENETRESET) { 3759 if (ATW_IS_ENABLED(sc)) 3760 atw_filter_setup(sc); /* do not rescan */ 3761 error = 0; 3762 } 3763 break; 3764 default: 3765 error = ieee80211_ioctl(ifp, cmd, data); 3766 if (error == ENETRESET) { 3767 if (ATW_IS_ENABLED(sc)) 3768 error = atw_init(ifp); 3769 else 3770 error = 0; 3771 } 3772 break; 3773 } 3774 3775 /* Try to get more packets going. */ 3776 if (ATW_IS_ENABLED(sc)) 3777 atw_start(ifp); 3778 3779 splx(s); 3780 return (error); 3781 } 3782 3783 static int 3784 atw_media_change(struct ifnet *ifp) 3785 { 3786 int error; 3787 3788 error = ieee80211_media_change(ifp); 3789 if (error == ENETRESET) { 3790 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3791 (IFF_RUNNING|IFF_UP)) 3792 atw_init(ifp); /* XXX lose error */ 3793 error = 0; 3794 } 3795 return error; 3796 } 3797 3798 static void 3799 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3800 { 3801 struct atw_softc *sc = ifp->if_softc; 3802 3803 if (ATW_IS_ENABLED(sc) == 0) { 3804 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3805 imr->ifm_status = 0; 3806 return; 3807 } 3808 ieee80211_media_status(ifp, imr); 3809 } 3810
Indexes created Thu Sep 25 16:09:42 GMT 2025