atw.c revision 1.69
1 /* $NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_compat.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_bbp_io_enable_delay = 20 * 1000; 145 int atw_bbp_io_disable_delay = 2 * 1000; 146 int atw_writewep_delay = 1000; 147 int atw_beacon_len_adjust = 4; 148 int atw_dwelltime = 200; 149 int atw_xindiv2 = 0; 150 151 #ifdef ATW_DEBUG 152 int atw_debug = 0; 153 154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 157 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 158 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 159 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 160 161 static void atw_print_regs(struct atw_softc *, const char *); 162 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 163 164 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 165 # ifdef ATW_BBPDEBUG 166 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 167 static void atw_rf3000_print(struct atw_softc *); 168 # endif /* ATW_BBPDEBUG */ 169 170 # ifdef ATW_SYNDEBUG 171 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 172 static void atw_si4126_print(struct atw_softc *); 173 # endif /* ATW_SYNDEBUG */ 174 175 #else 176 #define ATW_DPRINTF(x) 177 #define ATW_DPRINTF2(x) 178 #define ATW_DPRINTF3(x) 179 #define DPRINTF(sc, x) /* nothing */ 180 #define DPRINTF2(sc, x) /* nothing */ 181 #define DPRINTF3(sc, x) /* nothing */ 182 #endif 183 184 /* ifnet methods */ 185 void atw_start(struct ifnet *); 186 void atw_watchdog(struct ifnet *); 187 int atw_ioctl(struct ifnet *, u_long, caddr_t); 188 int atw_init(struct ifnet *); 189 void atw_stop(struct ifnet *, int); 190 191 /* Device attachment */ 192 void atw_attach(struct atw_softc *); 193 int atw_detach(struct atw_softc *); 194 195 /* Rx/Tx process */ 196 void atw_rxdrain(struct atw_softc *); 197 void atw_txdrain(struct atw_softc *); 198 int atw_add_rxbuf(struct atw_softc *, int); 199 void atw_idle(struct atw_softc *, u_int32_t); 200 201 /* Device (de)activation and power state */ 202 int atw_enable(struct atw_softc *); 203 void atw_disable(struct atw_softc *); 204 void atw_power(int, void *); 205 void atw_shutdown(void *); 206 void atw_reset(struct atw_softc *); 207 208 /* Interrupt handlers */ 209 void atw_rxintr(struct atw_softc *); 210 void atw_txintr(struct atw_softc *); 211 void atw_linkintr(struct atw_softc *, u_int32_t); 212 213 /* 802.11 state machine */ 214 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 215 static int atw_tune(struct atw_softc *); 216 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 217 struct ieee80211_node *, int, int, u_int32_t); 218 219 /* Device initialization */ 220 static void atw_wcsr_init(struct atw_softc *); 221 static void atw_cmdr_init(struct atw_softc *); 222 static void atw_tofs2_init(struct atw_softc *); 223 static void atw_txlmt_init(struct atw_softc *); 224 static void atw_test1_init(struct atw_softc *); 225 static void atw_rf_reset(struct atw_softc *); 226 static void atw_cfp_init(struct atw_softc *); 227 static void atw_tofs0_init(struct atw_softc *); 228 static void atw_ifs_init(struct atw_softc *); 229 static void atw_response_times_init(struct atw_softc *); 230 static void atw_bbp_io_init(struct atw_softc *); 231 232 /* RAM/ROM utilities */ 233 static void atw_clear_sram(struct atw_softc *); 234 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 235 static int atw_read_srom(struct atw_softc *); 236 237 /* BSS setup */ 238 static void atw_tsf(struct atw_softc *); 239 static void atw_start_beacon(struct atw_softc *, int); 240 static void atw_write_bssid(struct atw_softc *); 241 static void atw_write_ssid(struct atw_softc *); 242 static void atw_write_sup_rates(struct atw_softc *); 243 static void atw_write_wep(struct atw_softc *); 244 245 /* Media */ 246 static int atw_media_change(struct ifnet *); 247 static void atw_media_status(struct ifnet *, struct ifmediareq *); 248 249 static void atw_filter_setup(struct atw_softc *); 250 251 /* 802.11 utilities */ 252 static void atw_frame_setdurs(struct atw_softc *, 253 struct atw_frame *, int, int); 254 static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 255 static void atw_node_free(struct ieee80211com *, 256 struct ieee80211_node *); 257 static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 258 struct ieee80211_node *, int, int, 259 u_int32_t); 260 static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 261 uint32_t); 262 static __inline void atw_tsft(struct atw_softc *, uint32_t *, 263 uint32_t *); 264 265 /* 266 * Tuner/transceiver/modem 267 */ 268 static void atw_bbp_io_enable(struct atw_softc *, int); 269 270 /* RFMD RF3000 Baseband Processor */ 271 static int atw_rf3000_init(struct atw_softc *); 272 static int atw_rf3000_tune(struct atw_softc *, u_int); 273 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 274 275 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 276 static void atw_si4126_tune(struct atw_softc *, u_int); 277 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 278 279 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 280 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 281 282 const char *atw_tx_state[] = { 283 "STOPPED", 284 "RUNNING - read descriptor", 285 "RUNNING - transmitting", 286 "RUNNING - filling fifo", /* XXX */ 287 "SUSPENDED", 288 "RUNNING -- write descriptor", 289 "RUNNING -- write last descriptor", 290 "RUNNING - fifo full" 291 }; 292 293 const char *atw_rx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - check this packet, pre-fetch next", 297 "RUNNING - wait for reception", 298 "SUSPENDED", 299 "RUNNING - write descriptor", 300 "RUNNING - flush fifo", 301 "RUNNING - fifo drain" 302 }; 303 304 int 305 atw_activate(struct device *self, enum devact act) 306 { 307 struct atw_softc *sc = (struct atw_softc *)self; 308 int rv = 0, s; 309 310 s = splnet(); 311 switch (act) { 312 case DVACT_ACTIVATE: 313 rv = EOPNOTSUPP; 314 break; 315 316 case DVACT_DEACTIVATE: 317 if_deactivate(&sc->sc_ic.ic_if); 318 break; 319 } 320 splx(s); 321 return rv; 322 } 323 324 /* 325 * atw_enable: 326 * 327 * Enable the ADM8211 chip. 328 */ 329 int 330 atw_enable(struct atw_softc *sc) 331 { 332 333 if (ATW_IS_ENABLED(sc) == 0) { 334 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 335 printf("%s: device enable failed\n", 336 sc->sc_dev.dv_xname); 337 return (EIO); 338 } 339 sc->sc_flags |= ATWF_ENABLED; 340 } 341 return (0); 342 } 343 344 /* 345 * atw_disable: 346 * 347 * Disable the ADM8211 chip. 348 */ 349 void 350 atw_disable(struct atw_softc *sc) 351 { 352 if (!ATW_IS_ENABLED(sc)) 353 return; 354 if (sc->sc_disable != NULL) 355 (*sc->sc_disable)(sc); 356 sc->sc_flags &= ~ATWF_ENABLED; 357 } 358 359 /* Returns -1 on failure. */ 360 static int 361 atw_read_srom(struct atw_softc *sc) 362 { 363 struct seeprom_descriptor sd; 364 uint32_t test0, fail_bits; 365 366 (void)memset(&sd, 0, sizeof(sd)); 367 368 test0 = ATW_READ(sc, ATW_TEST0); 369 370 switch (sc->sc_rev) { 371 case ATW_REVISION_BA: 372 case ATW_REVISION_CA: 373 fail_bits = ATW_TEST0_EPNE; 374 break; 375 default: 376 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 377 break; 378 } 379 if ((test0 & fail_bits) != 0) { 380 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 381 return -1; 382 } 383 384 switch (test0 & ATW_TEST0_EPTYP_MASK) { 385 case ATW_TEST0_EPTYP_93c66: 386 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 387 sc->sc_sromsz = 512; 388 sd.sd_chip = C56_66; 389 break; 390 case ATW_TEST0_EPTYP_93c46: 391 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 392 sc->sc_sromsz = 128; 393 sd.sd_chip = C46; 394 break; 395 default: 396 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 397 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 398 return -1; 399 } 400 401 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 402 403 if (sc->sc_srom == NULL) { 404 printf("%s: unable to allocate SROM buffer\n", 405 sc->sc_dev.dv_xname); 406 return -1; 407 } 408 409 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 410 411 /* ADM8211 has a single 32-bit register for controlling the 412 * 93cx6 SROM. Bit SRS enables the serial port. There is no 413 * "ready" bit. The ADM8211 input/output sense is the reverse 414 * of read_seeprom's. 415 */ 416 sd.sd_tag = sc->sc_st; 417 sd.sd_bsh = sc->sc_sh; 418 sd.sd_regsize = 4; 419 sd.sd_control_offset = ATW_SPR; 420 sd.sd_status_offset = ATW_SPR; 421 sd.sd_dataout_offset = ATW_SPR; 422 sd.sd_CK = ATW_SPR_SCLK; 423 sd.sd_CS = ATW_SPR_SCS; 424 sd.sd_DI = ATW_SPR_SDO; 425 sd.sd_DO = ATW_SPR_SDI; 426 sd.sd_MS = ATW_SPR_SRS; 427 sd.sd_RDY = 0; 428 429 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 430 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 431 free(sc->sc_srom, M_DEVBUF); 432 return -1; 433 } 434 #ifdef ATW_DEBUG 435 { 436 int i; 437 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 438 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 439 if (((i % 8) == 0) && (i != 0)) { 440 ATW_DPRINTF(("\n\t")); 441 } 442 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 443 } 444 ATW_DPRINTF(("\n")); 445 } 446 #endif /* ATW_DEBUG */ 447 return 0; 448 } 449 450 #ifdef ATW_DEBUG 451 static void 452 atw_print_regs(struct atw_softc *sc, const char *where) 453 { 454 #define PRINTREG(sc, reg) \ 455 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 456 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 457 458 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 459 460 PRINTREG(sc, ATW_PAR); 461 PRINTREG(sc, ATW_FRCTL); 462 PRINTREG(sc, ATW_TDR); 463 PRINTREG(sc, ATW_WTDP); 464 PRINTREG(sc, ATW_RDR); 465 PRINTREG(sc, ATW_WRDP); 466 PRINTREG(sc, ATW_RDB); 467 PRINTREG(sc, ATW_CSR3A); 468 PRINTREG(sc, ATW_TDBD); 469 PRINTREG(sc, ATW_TDBP); 470 PRINTREG(sc, ATW_STSR); 471 PRINTREG(sc, ATW_CSR5A); 472 PRINTREG(sc, ATW_NAR); 473 PRINTREG(sc, ATW_CSR6A); 474 PRINTREG(sc, ATW_IER); 475 PRINTREG(sc, ATW_CSR7A); 476 PRINTREG(sc, ATW_LPC); 477 PRINTREG(sc, ATW_TEST1); 478 PRINTREG(sc, ATW_SPR); 479 PRINTREG(sc, ATW_TEST0); 480 PRINTREG(sc, ATW_WCSR); 481 PRINTREG(sc, ATW_WPDR); 482 PRINTREG(sc, ATW_GPTMR); 483 PRINTREG(sc, ATW_GPIO); 484 PRINTREG(sc, ATW_BBPCTL); 485 PRINTREG(sc, ATW_SYNCTL); 486 PRINTREG(sc, ATW_PLCPHD); 487 PRINTREG(sc, ATW_MMIWADDR); 488 PRINTREG(sc, ATW_MMIRADDR1); 489 PRINTREG(sc, ATW_MMIRADDR2); 490 PRINTREG(sc, ATW_TXBR); 491 PRINTREG(sc, ATW_CSR15A); 492 PRINTREG(sc, ATW_ALCSTAT); 493 PRINTREG(sc, ATW_TOFS2); 494 PRINTREG(sc, ATW_CMDR); 495 PRINTREG(sc, ATW_PCIC); 496 PRINTREG(sc, ATW_PMCSR); 497 PRINTREG(sc, ATW_PAR0); 498 PRINTREG(sc, ATW_PAR1); 499 PRINTREG(sc, ATW_MAR0); 500 PRINTREG(sc, ATW_MAR1); 501 PRINTREG(sc, ATW_ATIMDA0); 502 PRINTREG(sc, ATW_ABDA1); 503 PRINTREG(sc, ATW_BSSID0); 504 PRINTREG(sc, ATW_TXLMT); 505 PRINTREG(sc, ATW_MIBCNT); 506 PRINTREG(sc, ATW_BCNT); 507 PRINTREG(sc, ATW_TSFTH); 508 PRINTREG(sc, ATW_TSC); 509 PRINTREG(sc, ATW_SYNRF); 510 PRINTREG(sc, ATW_BPLI); 511 PRINTREG(sc, ATW_CAP0); 512 PRINTREG(sc, ATW_CAP1); 513 PRINTREG(sc, ATW_RMD); 514 PRINTREG(sc, ATW_CFPP); 515 PRINTREG(sc, ATW_TOFS0); 516 PRINTREG(sc, ATW_TOFS1); 517 PRINTREG(sc, ATW_IFST); 518 PRINTREG(sc, ATW_RSPT); 519 PRINTREG(sc, ATW_TSFTL); 520 PRINTREG(sc, ATW_WEPCTL); 521 PRINTREG(sc, ATW_WESK); 522 PRINTREG(sc, ATW_WEPCNT); 523 PRINTREG(sc, ATW_MACTEST); 524 PRINTREG(sc, ATW_FER); 525 PRINTREG(sc, ATW_FEMR); 526 PRINTREG(sc, ATW_FPSR); 527 PRINTREG(sc, ATW_FFER); 528 #undef PRINTREG 529 } 530 #endif /* ATW_DEBUG */ 531 532 /* 533 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 534 */ 535 void 536 atw_attach(struct atw_softc *sc) 537 { 538 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 539 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 540 }; 541 struct ieee80211com *ic = &sc->sc_ic; 542 struct ifnet *ifp = &ic->ic_if; 543 int country_code, error, i, nrate, srom_major; 544 u_int32_t reg; 545 static const char *type_strings[] = {"Intersil (not supported)", 546 "RFMD", "Marvel (not supported)"}; 547 548 sc->sc_txth = atw_txthresh_tab_lo; 549 550 SIMPLEQ_INIT(&sc->sc_txfreeq); 551 SIMPLEQ_INIT(&sc->sc_txdirtyq); 552 553 #ifdef ATW_DEBUG 554 atw_print_regs(sc, "atw_attach"); 555 #endif /* ATW_DEBUG */ 556 557 /* 558 * Allocate the control data structures, and create and load the 559 * DMA map for it. 560 */ 561 if ((error = bus_dmamem_alloc(sc->sc_dmat, 562 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 563 1, &sc->sc_cdnseg, 0)) != 0) { 564 printf("%s: unable to allocate control data, error = %d\n", 565 sc->sc_dev.dv_xname, error); 566 goto fail_0; 567 } 568 569 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 570 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 571 BUS_DMA_COHERENT)) != 0) { 572 printf("%s: unable to map control data, error = %d\n", 573 sc->sc_dev.dv_xname, error); 574 goto fail_1; 575 } 576 577 if ((error = bus_dmamap_create(sc->sc_dmat, 578 sizeof(struct atw_control_data), 1, 579 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 580 printf("%s: unable to create control data DMA map, " 581 "error = %d\n", sc->sc_dev.dv_xname, error); 582 goto fail_2; 583 } 584 585 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 586 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 587 0)) != 0) { 588 printf("%s: unable to load control data DMA map, error = %d\n", 589 sc->sc_dev.dv_xname, error); 590 goto fail_3; 591 } 592 593 /* 594 * Create the transmit buffer DMA maps. 595 */ 596 sc->sc_ntxsegs = ATW_NTXSEGS; 597 for (i = 0; i < ATW_TXQUEUELEN; i++) { 598 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 599 sc->sc_ntxsegs, MCLBYTES, 0, 0, 600 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 601 printf("%s: unable to create tx DMA map %d, " 602 "error = %d\n", sc->sc_dev.dv_xname, i, error); 603 goto fail_4; 604 } 605 } 606 607 /* 608 * Create the receive buffer DMA maps. 609 */ 610 for (i = 0; i < ATW_NRXDESC; i++) { 611 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 612 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 613 printf("%s: unable to create rx DMA map %d, " 614 "error = %d\n", sc->sc_dev.dv_xname, i, error); 615 goto fail_5; 616 } 617 } 618 for (i = 0; i < ATW_NRXDESC; i++) { 619 sc->sc_rxsoft[i].rxs_mbuf = NULL; 620 } 621 622 switch (sc->sc_rev) { 623 case ATW_REVISION_AB: 624 case ATW_REVISION_AF: 625 sc->sc_sramlen = ATW_SRAM_A_SIZE; 626 break; 627 case ATW_REVISION_BA: 628 case ATW_REVISION_CA: 629 sc->sc_sramlen = ATW_SRAM_B_SIZE; 630 break; 631 } 632 633 /* Reset the chip to a known state. */ 634 atw_reset(sc); 635 636 if (atw_read_srom(sc) == -1) 637 return; 638 639 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 640 ATW_SR_RFTYPE_MASK); 641 642 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 643 ATW_SR_BBPTYPE_MASK); 644 645 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 646 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 647 return; 648 } 649 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 650 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 651 return; 652 } 653 654 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 655 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 656 657 /* XXX There exists a Linux driver which seems to use RFType = 0 for 658 * MARVEL. My bug, or theirs? 659 */ 660 661 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 662 663 switch (sc->sc_rftype) { 664 case ATW_RFTYPE_INTERSIL: 665 reg |= ATW_SYNCTL_CS1; 666 break; 667 case ATW_RFTYPE_RFMD: 668 reg |= ATW_SYNCTL_CS0; 669 break; 670 case ATW_RFTYPE_MARVEL: 671 break; 672 } 673 674 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 675 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 676 677 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 678 679 switch (sc->sc_bbptype) { 680 case ATW_BBPTYPE_INTERSIL: 681 reg |= ATW_BBPCTL_TWI; 682 break; 683 case ATW_BBPTYPE_RFMD: 684 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 685 ATW_BBPCTL_CCA_ACTLO; 686 break; 687 case ATW_BBPTYPE_MARVEL: 688 break; 689 case ATW_C_BBPTYPE_RFMD: 690 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 691 sc->sc_dev.dv_xname); 692 break; 693 } 694 695 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 696 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 697 698 /* 699 * From this point forward, the attachment cannot fail. A failure 700 * before this point releases all resources that may have been 701 * allocated. 702 */ 703 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 704 705 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 706 htole16(sc->sc_srom[ATW_SR_MAC00]), 707 htole16(sc->sc_srom[ATW_SR_MAC01]), 708 htole16(sc->sc_srom[ATW_SR_MAC10]))); 709 710 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 711 ATW_SR_MAJOR_MASK); 712 713 if (srom_major < 2) 714 sc->sc_rf3000_options1 = 0; 715 else if (sc->sc_rev == ATW_REVISION_BA) { 716 sc->sc_rf3000_options1 = 717 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 718 ATW_SR_CR28_MASK); 719 } else 720 sc->sc_rf3000_options1 = 0; 721 722 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 723 ATW_SR_CR29_MASK); 724 725 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 726 ATW_SR_CTRY_MASK); 727 728 #define ADD_CHANNEL(_ic, _chan) do { \ 729 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 730 _ic->ic_channels[_chan].ic_freq = \ 731 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 732 } while (0) 733 734 /* Find available channels */ 735 switch (country_code) { 736 case COUNTRY_MMK2: /* 1-14 */ 737 ADD_CHANNEL(ic, 14); 738 /*FALLTHROUGH*/ 739 case COUNTRY_ETSI: /* 1-13 */ 740 for (i = 1; i <= 13; i++) 741 ADD_CHANNEL(ic, i); 742 break; 743 case COUNTRY_FCC: /* 1-11 */ 744 case COUNTRY_IC: /* 1-11 */ 745 for (i = 1; i <= 11; i++) 746 ADD_CHANNEL(ic, i); 747 break; 748 case COUNTRY_MMK: /* 14 */ 749 ADD_CHANNEL(ic, 14); 750 break; 751 case COUNTRY_FRANCE: /* 10-13 */ 752 for (i = 10; i <= 13; i++) 753 ADD_CHANNEL(ic, i); 754 break; 755 default: /* assume channels 10-11 */ 756 case COUNTRY_SPAIN: /* 10-11 */ 757 for (i = 10; i <= 11; i++) 758 ADD_CHANNEL(ic, i); 759 break; 760 } 761 762 /* Read the MAC address. */ 763 reg = ATW_READ(sc, ATW_PAR0); 764 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 765 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 766 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 767 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 768 reg = ATW_READ(sc, ATW_PAR1); 769 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 770 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 771 772 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 773 printf(" could not get mac address, attach failed\n"); 774 return; 775 } 776 777 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 778 779 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 780 ifp->if_softc = sc; 781 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 782 IFF_NOTRAILERS; 783 ifp->if_ioctl = atw_ioctl; 784 ifp->if_start = atw_start; 785 ifp->if_watchdog = atw_watchdog; 786 ifp->if_init = atw_init; 787 ifp->if_stop = atw_stop; 788 IFQ_SET_READY(&ifp->if_snd); 789 790 ic->ic_phytype = IEEE80211_T_DS; 791 ic->ic_opmode = IEEE80211_M_STA; 792 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 793 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 794 795 nrate = 0; 796 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 797 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 798 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 799 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 800 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 801 802 /* 803 * Call MI attach routines. 804 */ 805 806 if_attach(ifp); 807 ieee80211_ifattach(ifp); 808 809 sc->sc_newstate = ic->ic_newstate; 810 ic->ic_newstate = atw_newstate; 811 812 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 813 ic->ic_recv_mgmt = atw_recv_mgmt; 814 815 sc->sc_node_free = ic->ic_node_free; 816 ic->ic_node_free = atw_node_free; 817 818 sc->sc_node_alloc = ic->ic_node_alloc; 819 ic->ic_node_alloc = atw_node_alloc; 820 821 /* possibly we should fill in our own sc_send_prresp, since 822 * the ADM8211 is probably sending probe responses in ad hoc 823 * mode. 824 */ 825 826 /* complete initialization */ 827 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 828 callout_init(&sc->sc_scan_ch); 829 830 #if NBPFILTER > 0 831 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 832 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 833 #endif 834 835 /* 836 * Make sure the interface is shutdown during reboot. 837 */ 838 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 839 if (sc->sc_sdhook == NULL) 840 printf("%s: WARNING: unable to establish shutdown hook\n", 841 sc->sc_dev.dv_xname); 842 843 /* 844 * Add a suspend hook to make sure we come back up after a 845 * resume. 846 */ 847 sc->sc_powerhook = powerhook_establish(atw_power, sc); 848 if (sc->sc_powerhook == NULL) 849 printf("%s: WARNING: unable to establish power hook\n", 850 sc->sc_dev.dv_xname); 851 852 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 853 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 854 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 855 856 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 857 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 858 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 859 860 return; 861 862 /* 863 * Free any resources we've allocated during the failed attach 864 * attempt. Do this in reverse order and fall through. 865 */ 866 fail_5: 867 for (i = 0; i < ATW_NRXDESC; i++) { 868 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 869 continue; 870 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 871 } 872 fail_4: 873 for (i = 0; i < ATW_TXQUEUELEN; i++) { 874 if (sc->sc_txsoft[i].txs_dmamap == NULL) 875 continue; 876 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 877 } 878 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 879 fail_3: 880 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 881 fail_2: 882 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 883 sizeof(struct atw_control_data)); 884 fail_1: 885 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 886 fail_0: 887 return; 888 } 889 890 static struct ieee80211_node * 891 atw_node_alloc(struct ieee80211com *ic) 892 { 893 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 894 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 895 896 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 897 return ni; 898 } 899 900 static void 901 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 902 { 903 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 904 905 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 906 ether_sprintf(ni->ni_bssid))); 907 (*sc->sc_node_free)(ic, ni); 908 } 909 910 911 static void 912 atw_test1_reset(struct atw_softc *sc) 913 { 914 switch (sc->sc_rev) { 915 case ATW_REVISION_BA: 916 if (1 /* XXX condition on transceiver type */) { 917 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 918 } 919 break; 920 case ATW_REVISION_CA: 921 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 922 break; 923 default: 924 break; 925 } 926 } 927 928 /* 929 * atw_reset: 930 * 931 * Perform a soft reset on the ADM8211. 932 */ 933 void 934 atw_reset(struct atw_softc *sc) 935 { 936 int i; 937 uint32_t lpc; 938 939 ATW_WRITE(sc, ATW_NAR, 0x0); 940 DELAY(20 * 1000); 941 942 /* Reference driver has a cryptic remark indicating that this might 943 * power-on the chip. I know that it turns off power-saving.... 944 */ 945 ATW_WRITE(sc, ATW_FRCTL, 0x0); 946 947 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 948 949 for (i = 0; i < 50; i++) { 950 if (ATW_READ(sc, ATW_PAR) == 0) 951 break; 952 DELAY(1000); 953 } 954 955 /* ... and then pause 100ms longer for good measure. */ 956 DELAY(100 * 1000); 957 958 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 959 960 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 961 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 962 963 atw_test1_reset(sc); 964 /* 965 * Initialize the PCI Access Register. 966 */ 967 sc->sc_busmode = ATW_PAR_PBL_8DW; 968 969 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 970 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 971 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 972 973 /* Turn off maximum power saving, etc. 974 * 975 * XXX Following example of reference driver, should I set 976 * an AID of 1? It didn't seem to help.... 977 */ 978 ATW_WRITE(sc, ATW_FRCTL, 0x0); 979 980 DELAY(100 * 1000); 981 982 /* Recall EEPROM. */ 983 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 984 985 DELAY(10 * 1000); 986 987 lpc = ATW_READ(sc, ATW_LPC); 988 989 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 990 991 /* A reset seems to affect the SRAM contents, so put them into 992 * a known state. 993 */ 994 atw_clear_sram(sc); 995 996 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 997 } 998 999 static void 1000 atw_clear_sram(struct atw_softc *sc) 1001 { 1002 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1003 /* XXX not for revision 0x20. */ 1004 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1005 } 1006 1007 /* TBD atw_init 1008 * 1009 * set MAC based on ic->ic_bss->myaddr 1010 * write WEP keys 1011 * set TX rate 1012 */ 1013 1014 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1015 * without receiving a beacon with the preferred BSSID & SSID. 1016 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1017 */ 1018 static void 1019 atw_wcsr_init(struct atw_softc *sc) 1020 { 1021 uint32_t wcsr; 1022 1023 wcsr = ATW_READ(sc, ATW_WCSR); 1024 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1025 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1026 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1027 1028 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1029 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1030 } 1031 1032 /* Turn off power management. Set Rx store-and-forward mode. */ 1033 static void 1034 atw_cmdr_init(struct atw_softc *sc) 1035 { 1036 uint32_t cmdr; 1037 cmdr = ATW_READ(sc, ATW_CMDR); 1038 cmdr &= ~ATW_CMDR_APM; 1039 cmdr |= ATW_CMDR_RTE; 1040 cmdr &= ~ATW_CMDR_DRT_MASK; 1041 cmdr |= ATW_CMDR_DRT_SF; 1042 1043 ATW_WRITE(sc, ATW_CMDR, cmdr); 1044 } 1045 1046 static void 1047 atw_tofs2_init(struct atw_softc *sc) 1048 { 1049 uint32_t tofs2; 1050 /* XXX this magic can probably be figured out from the RFMD docs */ 1051 #ifndef ATW_REFSLAVE 1052 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1053 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1054 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1055 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1056 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1057 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1058 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1059 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1060 #else 1061 /* XXX new magic from reference driver source */ 1062 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1063 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1064 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1065 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1066 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1067 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1068 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1069 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1070 #endif 1071 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1072 } 1073 1074 static void 1075 atw_nar_init(struct atw_softc *sc) 1076 { 1077 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1078 } 1079 1080 static void 1081 atw_txlmt_init(struct atw_softc *sc) 1082 { 1083 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1084 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1085 } 1086 1087 static void 1088 atw_test1_init(struct atw_softc *sc) 1089 { 1090 uint32_t test1; 1091 1092 test1 = ATW_READ(sc, ATW_TEST1); 1093 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1094 /* XXX magic 0x1 */ 1095 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1096 ATW_WRITE(sc, ATW_TEST1, test1); 1097 } 1098 1099 static void 1100 atw_rf_reset(struct atw_softc *sc) 1101 { 1102 /* XXX this resets an Intersil RF front-end? */ 1103 /* TBD condition on Intersil RFType? */ 1104 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1105 DELAY(10 * 1000); 1106 ATW_WRITE(sc, ATW_SYNRF, 0); 1107 DELAY(5 * 1000); 1108 } 1109 1110 /* Set 16 TU max duration for the contention-free period (CFP). */ 1111 static void 1112 atw_cfp_init(struct atw_softc *sc) 1113 { 1114 uint32_t cfpp; 1115 1116 cfpp = ATW_READ(sc, ATW_CFPP); 1117 cfpp &= ~ATW_CFPP_CFPMD; 1118 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1119 ATW_WRITE(sc, ATW_CFPP, cfpp); 1120 } 1121 1122 static void 1123 atw_tofs0_init(struct atw_softc *sc) 1124 { 1125 /* XXX I guess that the Cardbus clock is 22MHz? 1126 * I am assuming that the role of ATW_TOFS0_USCNT is 1127 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1128 * very clear on this point. It says in the datasheet that it is 1129 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1130 * and 33MHz; maybe this is the way? I see a binary-only driver write 1131 * these values. These values are also the power-on default. 1132 */ 1133 ATW_WRITE(sc, ATW_TOFS0, 1134 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1135 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1136 } 1137 1138 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1139 static void 1140 atw_ifs_init(struct atw_softc *sc) 1141 { 1142 uint32_t ifst; 1143 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1144 * Go figure. 1145 */ 1146 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1147 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1148 ATW_IFST_SIFS_MASK) | 1149 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1150 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1151 1152 ATW_WRITE(sc, ATW_IFST, ifst); 1153 } 1154 1155 static void 1156 atw_response_times_init(struct atw_softc *sc) 1157 { 1158 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1159 * indicate that the MAC expects at least SIFS + MIRT microseconds 1160 * to pass after it transmits a frame that requires a response; 1161 * it waits at most SIFS + MART microseconds for the response. 1162 * Surely this is not the ACK timeout? 1163 */ 1164 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1165 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1166 } 1167 1168 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1169 * engines read and write baseband registers after Rx and before 1170 * Tx, respectively. 1171 */ 1172 static void 1173 atw_bbp_io_init(struct atw_softc *sc) 1174 { 1175 uint32_t mmiraddr2; 1176 1177 /* XXX The reference driver does this, but is it *really* 1178 * necessary? 1179 */ 1180 switch (sc->sc_rev) { 1181 case ATW_REVISION_AB: 1182 case ATW_REVISION_AF: 1183 mmiraddr2 = 0x0; 1184 break; 1185 default: 1186 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1187 mmiraddr2 &= 1188 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1189 break; 1190 } 1191 1192 switch (sc->sc_bbptype) { 1193 case ATW_BBPTYPE_INTERSIL: 1194 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1195 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1196 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1197 break; 1198 case ATW_BBPTYPE_MARVEL: 1199 /* TBD find out the Marvel settings. */ 1200 break; 1201 case ATW_BBPTYPE_RFMD: 1202 default: 1203 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1204 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1205 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1206 break; 1207 } 1208 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1209 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1210 } 1211 1212 /* 1213 * atw_init: [ ifnet interface function ] 1214 * 1215 * Initialize the interface. Must be called at splnet(). 1216 */ 1217 int 1218 atw_init(struct ifnet *ifp) 1219 { 1220 struct atw_softc *sc = ifp->if_softc; 1221 struct ieee80211com *ic = &sc->sc_ic; 1222 struct atw_txsoft *txs; 1223 struct atw_rxsoft *rxs; 1224 int i, error = 0; 1225 1226 if ((error = atw_enable(sc)) != 0) 1227 goto out; 1228 1229 /* 1230 * Cancel any pending I/O. This also resets. 1231 */ 1232 atw_stop(ifp, 0); 1233 1234 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1235 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1236 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1237 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1238 1239 atw_wcsr_init(sc); 1240 1241 atw_cmdr_init(sc); 1242 1243 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1244 * 1245 * XXX Set transmit power for ATIM, RTS, Beacon. 1246 */ 1247 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1248 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1249 1250 atw_tofs2_init(sc); 1251 1252 atw_nar_init(sc); 1253 1254 atw_txlmt_init(sc); 1255 1256 atw_test1_init(sc); 1257 1258 atw_rf_reset(sc); 1259 1260 atw_cfp_init(sc); 1261 1262 atw_tofs0_init(sc); 1263 1264 atw_ifs_init(sc); 1265 1266 /* XXX Fall asleep after one second of inactivity. 1267 * XXX A frame may only dribble in for 65536us. 1268 */ 1269 ATW_WRITE(sc, ATW_RMD, 1270 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1271 1272 atw_response_times_init(sc); 1273 1274 atw_bbp_io_init(sc); 1275 1276 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1277 1278 if ((error = atw_rf3000_init(sc)) != 0) 1279 goto out; 1280 1281 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1282 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1283 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1284 1285 /* 1286 * Initialize the transmit descriptor ring. 1287 */ 1288 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1289 for (i = 0; i < ATW_NTXDESC; i++) { 1290 sc->sc_txdescs[i].at_ctl = 0; 1291 /* no transmit chaining */ 1292 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1293 sc->sc_txdescs[i].at_buf2 = 1294 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1295 } 1296 /* use ring mode */ 1297 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1298 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1299 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1300 sc->sc_txfree = ATW_NTXDESC; 1301 sc->sc_txnext = 0; 1302 1303 /* 1304 * Initialize the transmit job descriptors. 1305 */ 1306 SIMPLEQ_INIT(&sc->sc_txfreeq); 1307 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1308 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1309 txs = &sc->sc_txsoft[i]; 1310 txs->txs_mbuf = NULL; 1311 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1312 } 1313 1314 /* 1315 * Initialize the receive descriptor and receive job 1316 * descriptor rings. 1317 */ 1318 for (i = 0; i < ATW_NRXDESC; i++) { 1319 rxs = &sc->sc_rxsoft[i]; 1320 if (rxs->rxs_mbuf == NULL) { 1321 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1322 printf("%s: unable to allocate or map rx " 1323 "buffer %d, error = %d\n", 1324 sc->sc_dev.dv_xname, i, error); 1325 /* 1326 * XXX Should attempt to run with fewer receive 1327 * XXX buffers instead of just failing. 1328 */ 1329 atw_rxdrain(sc); 1330 goto out; 1331 } 1332 } else 1333 ATW_INIT_RXDESC(sc, i); 1334 } 1335 sc->sc_rxptr = 0; 1336 1337 /* 1338 * Initialize the interrupt mask and enable interrupts. 1339 */ 1340 /* normal interrupts */ 1341 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1342 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1343 1344 /* abnormal interrupts */ 1345 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1346 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1347 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1348 1349 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1350 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1351 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1352 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1353 ATW_INTR_TRT; 1354 1355 sc->sc_linkint_mask &= sc->sc_inten; 1356 sc->sc_rxint_mask &= sc->sc_inten; 1357 sc->sc_txint_mask &= sc->sc_inten; 1358 1359 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1360 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1361 1362 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1363 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1364 1365 /* 1366 * Give the transmit and receive rings to the ADM8211. 1367 */ 1368 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1369 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1370 1371 sc->sc_txthresh = 0; 1372 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1373 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1374 1375 /* common 802.11 configuration */ 1376 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1377 switch (ic->ic_opmode) { 1378 case IEEE80211_M_STA: 1379 break; 1380 case IEEE80211_M_AHDEMO: /* XXX */ 1381 case IEEE80211_M_IBSS: 1382 ic->ic_flags |= IEEE80211_F_IBSSON; 1383 /*FALLTHROUGH*/ 1384 case IEEE80211_M_HOSTAP: /* XXX */ 1385 break; 1386 case IEEE80211_M_MONITOR: /* XXX */ 1387 break; 1388 } 1389 1390 switch (ic->ic_opmode) { 1391 case IEEE80211_M_AHDEMO: 1392 case IEEE80211_M_HOSTAP: 1393 ic->ic_bss->ni_intval = ic->ic_lintval; 1394 ic->ic_bss->ni_rssi = 0; 1395 ic->ic_bss->ni_rstamp = 0; 1396 break; 1397 default: /* XXX */ 1398 break; 1399 } 1400 1401 sc->sc_wepctl = 0; 1402 1403 atw_write_ssid(sc); 1404 atw_write_sup_rates(sc); 1405 if (ic->ic_caps & IEEE80211_C_WEP) 1406 atw_write_wep(sc); 1407 1408 ic->ic_state = IEEE80211_S_INIT; 1409 1410 /* 1411 * Set the receive filter. This will start the transmit and 1412 * receive processes. 1413 */ 1414 atw_filter_setup(sc); 1415 1416 /* 1417 * Start the receive process. 1418 */ 1419 ATW_WRITE(sc, ATW_RDR, 0x1); 1420 1421 /* 1422 * Note that the interface is now running. 1423 */ 1424 ifp->if_flags |= IFF_RUNNING; 1425 ifp->if_flags &= ~IFF_OACTIVE; 1426 1427 /* send no beacons, yet. */ 1428 atw_start_beacon(sc, 0); 1429 1430 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1431 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1432 else 1433 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1434 out: 1435 if (error) { 1436 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1437 ifp->if_timer = 0; 1438 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1439 } 1440 #ifdef ATW_DEBUG 1441 atw_print_regs(sc, "end of init"); 1442 #endif /* ATW_DEBUG */ 1443 1444 return (error); 1445 } 1446 1447 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1448 * 0: MAC control of RF3000/Si4126. 1449 * 1450 * Applies power, or selects RF front-end? Sets reset condition. 1451 * 1452 * TBD support non-RFMD BBP, non-SiLabs synth. 1453 */ 1454 static void 1455 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1456 { 1457 if (enable) { 1458 ATW_WRITE(sc, ATW_SYNRF, 1459 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1460 DELAY(atw_bbp_io_enable_delay); 1461 } else { 1462 ATW_WRITE(sc, ATW_SYNRF, 0); 1463 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1464 } 1465 } 1466 1467 static int 1468 atw_tune(struct atw_softc *sc) 1469 { 1470 int rc; 1471 u_int chan; 1472 struct ieee80211com *ic = &sc->sc_ic; 1473 1474 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1475 if (chan == IEEE80211_CHAN_ANY) 1476 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1477 1478 if (chan == sc->sc_cur_chan) 1479 return 0; 1480 1481 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1482 sc->sc_cur_chan, chan)); 1483 1484 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1485 1486 atw_si4126_tune(sc, chan); 1487 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1488 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1489 chan); 1490 1491 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1492 DELAY(20 * 1000); 1493 ATW_WRITE(sc, ATW_RDR, 0x1); 1494 1495 if (rc == 0) 1496 sc->sc_cur_chan = chan; 1497 1498 return rc; 1499 } 1500 1501 #ifdef ATW_SYNDEBUG 1502 static void 1503 atw_si4126_print(struct atw_softc *sc) 1504 { 1505 struct ifnet *ifp = &sc->sc_ic.ic_if; 1506 u_int addr, val; 1507 1508 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1509 return; 1510 1511 for (addr = 0; addr <= 8; addr++) { 1512 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1513 if (atw_si4126_read(sc, addr, &val) == 0) { 1514 printf("<unknown> (quitting print-out)\n"); 1515 break; 1516 } 1517 printf("%05x\n", val); 1518 } 1519 } 1520 #endif /* ATW_SYNDEBUG */ 1521 1522 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1523 * 1524 * The RF/IF synthesizer produces two reference frequencies for 1525 * the RF2948B transceiver. The first frequency the RF2948B requires 1526 * is two times the so-called "intermediate frequency" (IF). Since 1527 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1528 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1529 * frequency required by the transceiver is the radio frequency 1530 * (RF). This is a superheterodyne transceiver; for f(chan) the 1531 * center frequency of the channel we are tuning, RF = f(chan) - 1532 * IF. 1533 * 1534 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1535 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1536 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1537 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1538 */ 1539 static void 1540 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1541 { 1542 u_int mhz; 1543 u_int R; 1544 u_int32_t gpio; 1545 u_int16_t gain; 1546 1547 #ifdef ATW_SYNDEBUG 1548 atw_si4126_print(sc); 1549 #endif /* ATW_SYNDEBUG */ 1550 1551 if (chan == 14) 1552 mhz = 2484; 1553 else 1554 mhz = 2412 + 5 * (chan - 1); 1555 1556 /* Tune IF to 748MHz to suit the IF LO input of the 1557 * RF2494B, which is 2 x IF. No need to set an IF divider 1558 * because an IF in 526MHz - 952MHz is allowed. 1559 * 1560 * XIN is 44.000MHz, so divide it by two to get allowable 1561 * range of 2-25MHz. SiLabs tells me that this is not 1562 * strictly necessary. 1563 */ 1564 1565 if (atw_xindiv2) 1566 R = 44; 1567 else 1568 R = 88; 1569 1570 /* Power-up RF, IF synthesizers. */ 1571 atw_si4126_write(sc, SI4126_POWER, 1572 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1573 1574 /* set LPWR, too? */ 1575 atw_si4126_write(sc, SI4126_MAIN, 1576 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1577 1578 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1579 * set KP2 to 1. 1580 * 1581 * REFDIF This is different from the reference driver, which 1582 * always sets SI4126_GAIN to 0. 1583 */ 1584 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1585 1586 atw_si4126_write(sc, SI4126_GAIN, gain); 1587 1588 /* XIN = 44MHz. 1589 * 1590 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1591 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1592 * 1593 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1594 * so that 1496/88 * 44MHz = 748MHz. 1595 */ 1596 atw_si4126_write(sc, SI4126_IFN, 1496); 1597 1598 atw_si4126_write(sc, SI4126_IFR, R); 1599 1600 #ifndef ATW_REFSLAVE 1601 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1602 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1603 * which has no RF1! 1604 */ 1605 atw_si4126_write(sc, SI4126_RF1R, R); 1606 1607 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1608 #endif 1609 1610 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1611 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1612 * Now let's multiply it to mhz. So mhz - IF = N. 1613 */ 1614 atw_si4126_write(sc, SI4126_RF2R, R); 1615 1616 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1617 1618 /* wait 100us from power-up for RF, IF to settle */ 1619 DELAY(100); 1620 1621 gpio = ATW_READ(sc, ATW_GPIO); 1622 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1623 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1624 1625 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1626 /* Set a Prism RF front-end to a special mode for channel 14? 1627 * 1628 * Apparently the SMC2635W needs this, although I don't think 1629 * it has a Prism RF. 1630 */ 1631 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1632 } 1633 ATW_WRITE(sc, ATW_GPIO, gpio); 1634 1635 #ifdef ATW_SYNDEBUG 1636 atw_si4126_print(sc); 1637 #endif /* ATW_SYNDEBUG */ 1638 } 1639 1640 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1641 * diversity. 1642 * 1643 * !!! 1644 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1645 * !!! 1646 */ 1647 static int 1648 atw_rf3000_init(struct atw_softc *sc) 1649 { 1650 int rc = 0; 1651 1652 atw_bbp_io_enable(sc, 1); 1653 1654 /* CCA is acquisition sensitive */ 1655 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1656 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1657 1658 if (rc != 0) 1659 goto out; 1660 1661 /* enable diversity */ 1662 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1663 1664 if (rc != 0) 1665 goto out; 1666 1667 /* sensible setting from a binary-only driver */ 1668 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1669 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1670 1671 if (rc != 0) 1672 goto out; 1673 1674 /* magic from a binary-only driver */ 1675 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1676 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1677 1678 if (rc != 0) 1679 goto out; 1680 1681 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1682 1683 if (rc != 0) 1684 goto out; 1685 1686 /* XXX Reference driver remarks that Abocom sets this to 50. 1687 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1688 * in the "reserved" area of register RF3000_OPTIONS1. 1689 */ 1690 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1691 1692 if (rc != 0) 1693 goto out; 1694 1695 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1696 1697 if (rc != 0) 1698 goto out; 1699 1700 out: 1701 atw_bbp_io_enable(sc, 0); 1702 return rc; 1703 } 1704 1705 #ifdef ATW_BBPDEBUG 1706 static void 1707 atw_rf3000_print(struct atw_softc *sc) 1708 { 1709 struct ifnet *ifp = &sc->sc_ic.ic_if; 1710 u_int addr, val; 1711 1712 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1713 return; 1714 1715 for (addr = 0x01; addr <= 0x15; addr++) { 1716 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1717 if (atw_rf3000_read(sc, addr, &val) != 0) { 1718 printf("<unknown> (quitting print-out)\n"); 1719 break; 1720 } 1721 printf("%08x\n", val); 1722 } 1723 } 1724 #endif /* ATW_BBPDEBUG */ 1725 1726 /* Set the power settings on the BBP for channel `chan'. */ 1727 static int 1728 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1729 { 1730 int rc = 0; 1731 u_int32_t reg; 1732 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1733 1734 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1735 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1736 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1737 1738 /* odd channels: LSB, even channels: MSB */ 1739 if (chan % 2 == 1) { 1740 txpower &= 0xFF; 1741 lpf_cutoff &= 0xFF; 1742 lna_gs_thresh &= 0xFF; 1743 } else { 1744 txpower >>= 8; 1745 lpf_cutoff >>= 8; 1746 lna_gs_thresh >>= 8; 1747 } 1748 1749 #ifdef ATW_BBPDEBUG 1750 atw_rf3000_print(sc); 1751 #endif /* ATW_BBPDEBUG */ 1752 1753 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1754 "lna_gs_thresh %02x\n", 1755 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1756 1757 atw_bbp_io_enable(sc, 1); 1758 1759 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1760 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1761 goto out; 1762 1763 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1764 goto out; 1765 1766 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1767 goto out; 1768 1769 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1770 1771 if (rc != 0) 1772 goto out; 1773 1774 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1775 1776 if (rc != 0) 1777 goto out; 1778 1779 #ifdef ATW_BBPDEBUG 1780 atw_rf3000_print(sc); 1781 #endif /* ATW_BBPDEBUG */ 1782 1783 out: 1784 atw_bbp_io_enable(sc, 0); 1785 1786 /* set beacon, rts, atim transmit power */ 1787 reg = ATW_READ(sc, ATW_PLCPHD); 1788 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1789 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1790 ATW_PLCPHD_SERVICE_MASK); 1791 ATW_WRITE(sc, ATW_PLCPHD, reg); 1792 DELAY(2 * 1000); 1793 1794 return rc; 1795 } 1796 1797 /* Write a register on the RF3000 baseband processor using the 1798 * registers provided by the ADM8211 for this purpose. 1799 * 1800 * Return 0 on success. 1801 */ 1802 static int 1803 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1804 { 1805 u_int32_t reg; 1806 int i; 1807 1808 reg = sc->sc_bbpctl_wr | 1809 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1810 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1811 1812 for (i = 10; --i >= 0; ) { 1813 ATW_WRITE(sc, ATW_BBPCTL, reg); 1814 DELAY(2000); 1815 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1816 break; 1817 } 1818 1819 if (i < 0) { 1820 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1821 return ETIMEDOUT; 1822 } 1823 return 0; 1824 } 1825 1826 /* Read a register on the RF3000 baseband processor using the registers 1827 * the ADM8211 provides for this purpose. 1828 * 1829 * The 7-bit register address is addr. Record the 8-bit data in the register 1830 * in *val. 1831 * 1832 * Return 0 on success. 1833 * 1834 * XXX This does not seem to work. The ADM8211 must require more or 1835 * different magic to read the chip than to write it. Possibly some 1836 * of the magic I have derived from a binary-only driver concerns 1837 * the "chip address" (see the RF3000 manual). 1838 */ 1839 #ifdef ATW_BBPDEBUG 1840 static int 1841 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1842 { 1843 u_int32_t reg; 1844 int i; 1845 1846 for (i = 1000; --i >= 0; ) { 1847 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1848 break; 1849 DELAY(100); 1850 } 1851 1852 if (i < 0) { 1853 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1854 sc->sc_dev.dv_xname); 1855 return ETIMEDOUT; 1856 } 1857 1858 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1859 1860 ATW_WRITE(sc, ATW_BBPCTL, reg); 1861 1862 for (i = 1000; --i >= 0; ) { 1863 DELAY(100); 1864 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1865 break; 1866 } 1867 1868 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1869 1870 if (i < 0) { 1871 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1872 sc->sc_dev.dv_xname, reg); 1873 return ETIMEDOUT; 1874 } 1875 if (val != NULL) 1876 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1877 return 0; 1878 } 1879 #endif /* ATW_BBPDEBUG */ 1880 1881 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1882 * provided by the ADM8211 for that purpose. 1883 * 1884 * val is 18 bits of data, and val is the 4-bit address of the register. 1885 * 1886 * Return 0 on success. 1887 */ 1888 static void 1889 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1890 { 1891 uint32_t bits, mask, reg; 1892 const int nbits = 22; 1893 1894 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1895 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1896 1897 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1898 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1899 1900 reg = ATW_SYNRF_SELSYN; 1901 /* reference driver: reset Si4126 serial bus to initial 1902 * conditions? 1903 */ 1904 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1905 ATW_WRITE(sc, ATW_SYNRF, reg); 1906 1907 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1908 if ((bits & mask) != 0) 1909 reg |= ATW_SYNRF_SYNDATA; 1910 else 1911 reg &= ~ATW_SYNRF_SYNDATA; 1912 ATW_WRITE(sc, ATW_SYNRF, reg); 1913 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1914 ATW_WRITE(sc, ATW_SYNRF, reg); 1915 } 1916 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1917 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1918 } 1919 1920 /* Read 18-bit data from the 4-bit address addr in Si4126 1921 * RF synthesizer and write the data to *val. Return 0 on success. 1922 * 1923 * XXX This does not seem to work. The ADM8211 must require more or 1924 * different magic to read the chip than to write it. 1925 */ 1926 #ifdef ATW_SYNDEBUG 1927 static int 1928 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1929 { 1930 u_int32_t reg; 1931 int i; 1932 1933 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1934 1935 for (i = 1000; --i >= 0; ) { 1936 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1937 break; 1938 DELAY(100); 1939 } 1940 1941 if (i < 0) { 1942 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1943 sc->sc_dev.dv_xname); 1944 return ETIMEDOUT; 1945 } 1946 1947 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1948 1949 ATW_WRITE(sc, ATW_SYNCTL, reg); 1950 1951 for (i = 1000; --i >= 0; ) { 1952 DELAY(100); 1953 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1954 break; 1955 } 1956 1957 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1958 1959 if (i < 0) { 1960 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1961 sc->sc_dev.dv_xname, reg); 1962 return ETIMEDOUT; 1963 } 1964 if (val != NULL) 1965 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1966 ATW_SYNCTL_DATA_MASK); 1967 return 0; 1968 } 1969 #endif /* ATW_SYNDEBUG */ 1970 1971 /* XXX is the endianness correct? test. */ 1972 #define atw_calchash(addr) \ 1973 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1974 1975 /* 1976 * atw_filter_setup: 1977 * 1978 * Set the ADM8211's receive filter. 1979 */ 1980 static void 1981 atw_filter_setup(struct atw_softc *sc) 1982 { 1983 struct ieee80211com *ic = &sc->sc_ic; 1984 struct ethercom *ec = &ic->ic_ec; 1985 struct ifnet *ifp = &sc->sc_ic.ic_if; 1986 int hash; 1987 u_int32_t hashes[2]; 1988 struct ether_multi *enm; 1989 struct ether_multistep step; 1990 1991 /* According to comments in tlp_al981_filter_setup 1992 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1993 * multicast filter to be set while it is running. Hopefully 1994 * the ADM8211 is not the same! 1995 */ 1996 if ((ifp->if_flags & IFF_RUNNING) != 0) 1997 atw_idle(sc, ATW_NAR_SR); 1998 1999 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2000 2001 /* XXX in scan mode, do not filter packets. Maybe this is 2002 * unnecessary. 2003 */ 2004 if (ic->ic_state == IEEE80211_S_SCAN || 2005 (ifp->if_flags & IFF_PROMISC) != 0) { 2006 sc->sc_opmode |= ATW_NAR_PR; 2007 goto allmulti; 2008 } 2009 2010 hashes[0] = hashes[1] = 0x0; 2011 2012 /* 2013 * Program the 64-bit multicast hash filter. 2014 */ 2015 ETHER_FIRST_MULTI(step, ec, enm); 2016 while (enm != NULL) { 2017 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2018 ETHER_ADDR_LEN) != 0) 2019 goto allmulti; 2020 2021 hash = atw_calchash(enm->enm_addrlo); 2022 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2023 ETHER_NEXT_MULTI(step, enm); 2024 } 2025 ifp->if_flags &= ~IFF_ALLMULTI; 2026 goto setit; 2027 2028 allmulti: 2029 ifp->if_flags |= IFF_ALLMULTI; 2030 hashes[0] = hashes[1] = 0xffffffff; 2031 2032 setit: 2033 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2034 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2035 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2036 DELAY(20 * 1000); 2037 2038 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2039 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2040 } 2041 2042 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2043 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2044 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2045 * no beacon with the preferred BSSID and SSID in the number of 2046 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2047 */ 2048 static void 2049 atw_write_bssid(struct atw_softc *sc) 2050 { 2051 struct ieee80211com *ic = &sc->sc_ic; 2052 u_int8_t *bssid; 2053 2054 bssid = ic->ic_bss->ni_bssid; 2055 2056 ATW_WRITE(sc, ATW_BSSID0, 2057 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2058 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2059 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2060 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2061 2062 ATW_WRITE(sc, ATW_ABDA1, 2063 (ATW_READ(sc, ATW_ABDA1) & 2064 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2065 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2066 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2067 2068 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2069 ether_sprintf(sc->sc_bssid))); 2070 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2071 2072 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2073 } 2074 2075 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2076 * 16-bit word. 2077 */ 2078 static void 2079 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2080 { 2081 u_int i; 2082 u_int8_t *ptr; 2083 2084 memcpy(&sc->sc_sram[ofs], buf, buflen); 2085 2086 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2087 2088 KASSERT(buflen + ofs <= sc->sc_sramlen); 2089 2090 ptr = &sc->sc_sram[ofs]; 2091 2092 for (i = 0; i < buflen; i += 2) { 2093 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2094 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2095 DELAY(atw_writewep_delay); 2096 2097 ATW_WRITE(sc, ATW_WESK, 2098 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2099 DELAY(atw_writewep_delay); 2100 } 2101 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2102 2103 if (sc->sc_if.if_flags & IFF_DEBUG) { 2104 int n_octets = 0; 2105 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2106 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2107 for (i = 0; i < buflen; i++) { 2108 printf(" %02x", ptr[i]); 2109 if (++n_octets % 24 == 0) 2110 printf("\n"); 2111 } 2112 if (n_octets % 24 != 0) 2113 printf("\n"); 2114 } 2115 } 2116 2117 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2118 static void 2119 atw_write_wep(struct atw_softc *sc) 2120 { 2121 struct ieee80211com *ic = &sc->sc_ic; 2122 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2123 u_int8_t buf[IEEE80211_WEP_NKID] 2124 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2125 u_int32_t reg; 2126 int i; 2127 2128 sc->sc_wepctl = 0; 2129 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2130 2131 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2132 return; 2133 2134 memset(&buf[0][0], 0, sizeof(buf)); 2135 2136 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2137 if (ic->ic_nw_keys[i].wk_len > 5) { 2138 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2139 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2140 buf[i][1] = ATW_WEP_ENABLED; 2141 } else { 2142 buf[i][1] = 0; 2143 continue; 2144 } 2145 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2146 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2147 ic->ic_nw_keys[i].wk_len - 1); 2148 } 2149 2150 reg = ATW_READ(sc, ATW_MACTEST); 2151 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2152 reg &= ~ATW_MACTEST_KEYID_MASK; 2153 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2154 ATW_WRITE(sc, ATW_MACTEST, reg); 2155 2156 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE; 2157 2158 switch (sc->sc_rev) { 2159 case ATW_REVISION_AB: 2160 case ATW_REVISION_AF: 2161 /* Bypass WEP on Rx. */ 2162 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2163 break; 2164 default: 2165 break; 2166 } 2167 2168 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2169 sizeof(buf)); 2170 } 2171 2172 const struct timeval atw_beacon_mininterval = {.tv_sec = 1, .tv_usec = 0}; 2173 2174 static void 2175 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2176 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2177 { 2178 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2179 2180 switch (subtype) { 2181 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2182 /* do nothing: hardware answers probe request */ 2183 break; 2184 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2185 case IEEE80211_FC0_SUBTYPE_BEACON: 2186 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2187 break; 2188 default: 2189 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2190 break; 2191 } 2192 return; 2193 } 2194 2195 static int 2196 do_slow_print(struct atw_softc *sc, int *did_print) 2197 { 2198 if ((sc->sc_if.if_flags & IFF_LINK0) == 0) 2199 return 0; 2200 if (!*did_print && (sc->sc_if.if_flags & IFF_DEBUG) == 0 && 2201 !ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval)) 2202 return 0; 2203 2204 *did_print = 1; 2205 return 1; 2206 } 2207 2208 /* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2209 * of IBSSs with like SSID/channel but different BSSID. It joins the 2210 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2211 * convention. Possibly the ADMtek chip does this for us; I will have 2212 * to test to find out. 2213 * 2214 * XXX we should add the duration field of the received beacon to 2215 * the TSF time it contains before comparing it with the ADM8211's 2216 * TSF. 2217 */ 2218 static void 2219 atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2220 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2221 { 2222 struct atw_softc *sc; 2223 struct ieee80211_frame *wh; 2224 uint32_t tsftl, tsfth; 2225 uint32_t bcn_tsftl, bcn_tsfth; 2226 int did_print = 0, sign; 2227 union { 2228 uint32_t words[2]; 2229 uint8_t tstamp[8]; 2230 } u; 2231 2232 sc = (struct atw_softc*)ic->ic_if.if_softc; 2233 2234 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2235 2236 if (ic->ic_state != IEEE80211_S_RUN) 2237 return; 2238 2239 atw_tsft(sc, &tsfth, &tsftl); 2240 2241 (void)memcpy(&u, &ni->ni_tstamp[0], sizeof(u)); 2242 bcn_tsftl = le32toh(u.words[0]); 2243 bcn_tsfth = le32toh(u.words[1]); 2244 2245 /* we are faster, let the other guy catch up */ 2246 if (bcn_tsfth < tsfth) 2247 sign = -1; 2248 else if (bcn_tsfth == tsfth && bcn_tsftl < tsftl) 2249 sign = -1; 2250 else 2251 sign = 1; 2252 2253 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, 2254 IEEE80211_ADDR_LEN) == 0) { 2255 if (!do_slow_print(sc, &did_print)) 2256 return; 2257 printf("%s: tsft offset %s%" PRIu64 "\n", sc->sc_dev.dv_xname, 2258 (sign < 0) ? "-" : "", 2259 (sign < 0) 2260 ? ((((uint64_t)tsfth << 32) | tsftl) - 2261 (((uint64_t)bcn_tsfth << 32) | bcn_tsftl)) 2262 : ((((uint64_t)bcn_tsfth << 32) | bcn_tsftl) - 2263 (((uint64_t)tsfth << 32) | tsftl))); 2264 return; 2265 } 2266 2267 if (sign < 0) 2268 return; 2269 2270 if (ieee80211_match_bss(ic, ni) != 0) 2271 return; 2272 2273 if (do_slow_print(sc, &did_print)) { 2274 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2275 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2276 } 2277 2278 if (ic->ic_opmode != IEEE80211_M_IBSS) 2279 return; 2280 2281 if (do_slow_print(sc, &did_print)) { 2282 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2283 sc->sc_dev.dv_xname, ((uint64_t)tsfth << 32) | tsftl, 2284 ((uint64_t)bcn_tsfth << 32) | bcn_tsftl); 2285 } 2286 2287 wh = mtod(m0, struct ieee80211_frame *); 2288 2289 if (do_slow_print(sc, &did_print)) { 2290 printf("%s: sync TSF with %s\n", 2291 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2292 } 2293 2294 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2295 2296 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u, sizeof(u)); 2297 2298 atw_tsf(sc); 2299 2300 /* negotiate rates with new IBSS */ 2301 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2302 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2303 if (ni->ni_rates.rs_nrates == 0) { 2304 if (do_slow_print(sc, &did_print)) { 2305 printf("%s: rates mismatch, BSSID %s\n", 2306 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2307 } 2308 return; 2309 } 2310 2311 if (do_slow_print(sc, &did_print)) { 2312 printf("%s: sync BSSID %s -> ", 2313 sc->sc_dev.dv_xname, ether_sprintf(ic->ic_bss->ni_bssid)); 2314 printf("%s ", ether_sprintf(ni->ni_bssid)); 2315 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2316 } 2317 2318 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2319 2320 atw_write_bssid(sc); 2321 atw_start_beacon(sc, 1); 2322 } 2323 2324 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2325 * In ad hoc mode, the SSID is written to the beacons sent by the 2326 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2327 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2328 * indications. 2329 */ 2330 static void 2331 atw_write_ssid(struct atw_softc *sc) 2332 { 2333 struct ieee80211com *ic = &sc->sc_ic; 2334 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2335 * it only expects the element length, not its ID. 2336 */ 2337 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2338 2339 memset(buf, 0, sizeof(buf)); 2340 buf[0] = ic->ic_bss->ni_esslen; 2341 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2342 2343 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2344 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2345 } 2346 2347 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2348 * In ad hoc mode, the supported rates are written to beacons sent by the 2349 * ADM8211. 2350 */ 2351 static void 2352 atw_write_sup_rates(struct atw_softc *sc) 2353 { 2354 struct ieee80211com *ic = &sc->sc_ic; 2355 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2356 * supported rates 2357 */ 2358 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2359 2360 memset(buf, 0, sizeof(buf)); 2361 2362 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2363 2364 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2365 ic->ic_bss->ni_rates.rs_nrates); 2366 2367 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2368 } 2369 2370 /* Start/stop sending beacons. */ 2371 void 2372 atw_start_beacon(struct atw_softc *sc, int start) 2373 { 2374 struct ieee80211com *ic = &sc->sc_ic; 2375 uint16_t chan; 2376 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2377 size_t len; 2378 2379 if (ATW_IS_ENABLED(sc) == 0) 2380 return; 2381 2382 /* start beacons */ 2383 len = sizeof(struct ieee80211_frame) + 2384 8 /* timestamp */ + 2 /* beacon interval */ + 2385 2 /* capability info */ + 2386 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2387 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2388 3 /* DS parameters */ + 2389 IEEE80211_CRC_LEN; 2390 2391 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2392 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2393 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2394 2395 ATW_WRITE(sc, ATW_BCNT, bcnt); 2396 ATW_WRITE(sc, ATW_CAP1, cap1); 2397 2398 if (!start) 2399 return; 2400 2401 /* TBD use ni_capinfo */ 2402 2403 capinfo = 0; 2404 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2405 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2406 if (ic->ic_flags & IEEE80211_F_WEPON) 2407 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2408 2409 switch (ic->ic_opmode) { 2410 case IEEE80211_M_IBSS: 2411 len += 4; /* IBSS parameters */ 2412 capinfo |= IEEE80211_CAPINFO_IBSS; 2413 break; 2414 case IEEE80211_M_HOSTAP: 2415 /* XXX 6-byte minimum TIM */ 2416 len += atw_beacon_len_adjust; 2417 capinfo |= IEEE80211_CAPINFO_ESS; 2418 break; 2419 default: 2420 return; 2421 } 2422 2423 /* set listen interval 2424 * XXX do software units agree w/ hardware? 2425 */ 2426 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2427 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2428 2429 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2430 2431 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2432 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2433 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2434 2435 ATW_WRITE(sc, ATW_BCNT, bcnt); 2436 ATW_WRITE(sc, ATW_BPLI, bpli); 2437 ATW_WRITE(sc, ATW_CAP0, cap0); 2438 ATW_WRITE(sc, ATW_CAP1, cap1); 2439 2440 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2441 sc->sc_dev.dv_xname, bcnt)); 2442 2443 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2444 sc->sc_dev.dv_xname, cap1)); 2445 } 2446 2447 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2448 static __inline uint32_t 2449 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2450 { 2451 /* Following the reference driver's lead, I compute 2452 * 2453 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2454 * 2455 * without using 64-bit arithmetic, using the following 2456 * relationship: 2457 * 2458 * (0x100000000 * H + L) % m 2459 * = ((0x100000000 % m) * H + L) % m 2460 * = (((0xffffffff + 1) % m) * H + L) % m 2461 * = ((0xffffffff % m + 1 % m) * H + L) % m 2462 * = ((0xffffffff % m + 1) * H + L) % m 2463 */ 2464 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2465 } 2466 2467 static __inline void 2468 atw_tsft(struct atw_softc *sc, uint32_t *tsfth, uint32_t *tsftl) 2469 { 2470 int i; 2471 for (i = 0; i < 2; i++) { 2472 *tsfth = ATW_READ(sc, ATW_TSFTH); 2473 *tsftl = ATW_READ(sc, ATW_TSFTL); 2474 if (ATW_READ(sc, ATW_TSFTH) == *tsfth) 2475 break; 2476 } 2477 } 2478 2479 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2480 * the ieee80211com. 2481 * 2482 * Predict the next target beacon transmission time (TBTT) and 2483 * write it to the ADM8211. 2484 */ 2485 static void 2486 atw_tsf(struct atw_softc *sc) 2487 { 2488 #define TBTTOFS 20 /* TU */ 2489 2490 struct ieee80211com *ic = &sc->sc_ic; 2491 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2492 union { 2493 uint32_t words[2]; 2494 uint8_t tstamp[8]; 2495 } u; 2496 2497 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2498 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2499 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2500 atw_tsft(sc, &tsfth, &tsftl); 2501 u.words[0] = htole32(tsftl); 2502 u.words[1] = htole32(tsfth); 2503 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u, 2504 sizeof(ic->ic_bss->ni_tstamp)); 2505 } else { 2506 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2507 tsftl = le32toh(u.words[0]); 2508 tsfth = le32toh(u.words[1]); 2509 } 2510 2511 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2512 2513 /* We sent/received the last beacon `past' microseconds 2514 * after the interval divided the TSF timer. 2515 */ 2516 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2517 2518 /* Skip ten beacons so that the TBTT cannot pass before 2519 * we've programmed it. Ten is an arbitrary number. 2520 */ 2521 tbtt = past_even + ival * 10; 2522 2523 ATW_WRITE(sc, ATW_TOFS1, 2524 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2525 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2526 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2527 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2528 #undef TBTTOFS 2529 } 2530 2531 static void 2532 atw_next_scan(void *arg) 2533 { 2534 struct atw_softc *sc = arg; 2535 struct ieee80211com *ic = &sc->sc_ic; 2536 struct ifnet *ifp = &ic->ic_if; 2537 int s; 2538 2539 /* don't call atw_start w/o network interrupts blocked */ 2540 s = splnet(); 2541 if (ic->ic_state == IEEE80211_S_SCAN) 2542 ieee80211_next_scan(ifp); 2543 splx(s); 2544 } 2545 2546 /* Synchronize the hardware state with the software state. */ 2547 static int 2548 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2549 { 2550 struct ifnet *ifp = &ic->ic_if; 2551 struct atw_softc *sc = ifp->if_softc; 2552 enum ieee80211_state ostate; 2553 int error; 2554 2555 ostate = ic->ic_state; 2556 2557 if (nstate == IEEE80211_S_INIT) { 2558 callout_stop(&sc->sc_scan_ch); 2559 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2560 atw_start_beacon(sc, 0); 2561 return (*sc->sc_newstate)(ic, nstate, arg); 2562 } 2563 2564 if ((error = atw_tune(sc)) != 0) 2565 return error; 2566 2567 switch (nstate) { 2568 case IEEE80211_S_ASSOC: 2569 break; 2570 case IEEE80211_S_INIT: 2571 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2572 break; 2573 case IEEE80211_S_SCAN: 2574 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2575 atw_next_scan, sc); 2576 2577 break; 2578 case IEEE80211_S_RUN: 2579 if (ic->ic_opmode == IEEE80211_M_STA) 2580 break; 2581 /*FALLTHROUGH*/ 2582 case IEEE80211_S_AUTH: 2583 atw_write_bssid(sc); 2584 atw_write_ssid(sc); 2585 atw_write_sup_rates(sc); 2586 2587 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2588 ic->ic_opmode == IEEE80211_M_MONITOR) 2589 break; 2590 2591 /* set listen interval 2592 * XXX do software units agree w/ hardware? 2593 */ 2594 ATW_WRITE(sc, ATW_BPLI, 2595 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2596 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2597 ATW_BPLI_LI_MASK)); 2598 2599 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2600 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2601 2602 atw_tsf(sc); 2603 break; 2604 } 2605 2606 if (nstate != IEEE80211_S_SCAN) 2607 callout_stop(&sc->sc_scan_ch); 2608 2609 if (nstate == IEEE80211_S_RUN && 2610 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2611 ic->ic_opmode == IEEE80211_M_IBSS)) 2612 atw_start_beacon(sc, 1); 2613 else 2614 atw_start_beacon(sc, 0); 2615 2616 error = (*sc->sc_newstate)(ic, nstate, arg); 2617 2618 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2619 atw_write_bssid(sc); 2620 2621 return error; 2622 } 2623 2624 /* 2625 * atw_add_rxbuf: 2626 * 2627 * Add a receive buffer to the indicated descriptor. 2628 */ 2629 int 2630 atw_add_rxbuf(struct atw_softc *sc, int idx) 2631 { 2632 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2633 struct mbuf *m; 2634 int error; 2635 2636 MGETHDR(m, M_DONTWAIT, MT_DATA); 2637 if (m == NULL) 2638 return (ENOBUFS); 2639 2640 MCLGET(m, M_DONTWAIT); 2641 if ((m->m_flags & M_EXT) == 0) { 2642 m_freem(m); 2643 return (ENOBUFS); 2644 } 2645 2646 if (rxs->rxs_mbuf != NULL) 2647 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2648 2649 rxs->rxs_mbuf = m; 2650 2651 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2652 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2653 BUS_DMA_READ|BUS_DMA_NOWAIT); 2654 if (error) { 2655 printf("%s: can't load rx DMA map %d, error = %d\n", 2656 sc->sc_dev.dv_xname, idx, error); 2657 panic("atw_add_rxbuf"); /* XXX */ 2658 } 2659 2660 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2661 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2662 2663 ATW_INIT_RXDESC(sc, idx); 2664 2665 return (0); 2666 } 2667 2668 /* 2669 * Release any queued transmit buffers. 2670 */ 2671 void 2672 atw_txdrain(struct atw_softc *sc) 2673 { 2674 struct atw_txsoft *txs; 2675 2676 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2677 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2678 if (txs->txs_mbuf != NULL) { 2679 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2680 m_freem(txs->txs_mbuf); 2681 txs->txs_mbuf = NULL; 2682 } 2683 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2684 } 2685 sc->sc_tx_timer = 0; 2686 } 2687 2688 /* 2689 * atw_stop: [ ifnet interface function ] 2690 * 2691 * Stop transmission on the interface. 2692 */ 2693 void 2694 atw_stop(struct ifnet *ifp, int disable) 2695 { 2696 struct atw_softc *sc = ifp->if_softc; 2697 struct ieee80211com *ic = &sc->sc_ic; 2698 2699 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2700 2701 /* Disable interrupts. */ 2702 ATW_WRITE(sc, ATW_IER, 0); 2703 2704 /* Stop the transmit and receive processes. */ 2705 sc->sc_opmode = 0; 2706 ATW_WRITE(sc, ATW_NAR, 0); 2707 DELAY(20 * 1000); 2708 ATW_WRITE(sc, ATW_TDBD, 0); 2709 ATW_WRITE(sc, ATW_TDBP, 0); 2710 ATW_WRITE(sc, ATW_RDB, 0); 2711 2712 atw_txdrain(sc); 2713 2714 if (disable) { 2715 atw_rxdrain(sc); 2716 atw_disable(sc); 2717 } 2718 2719 /* 2720 * Mark the interface down and cancel the watchdog timer. 2721 */ 2722 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2723 ifp->if_timer = 0; 2724 2725 if (!disable) 2726 atw_reset(sc); 2727 } 2728 2729 /* 2730 * atw_rxdrain: 2731 * 2732 * Drain the receive queue. 2733 */ 2734 void 2735 atw_rxdrain(struct atw_softc *sc) 2736 { 2737 struct atw_rxsoft *rxs; 2738 int i; 2739 2740 for (i = 0; i < ATW_NRXDESC; i++) { 2741 rxs = &sc->sc_rxsoft[i]; 2742 if (rxs->rxs_mbuf == NULL) 2743 continue; 2744 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2745 m_freem(rxs->rxs_mbuf); 2746 rxs->rxs_mbuf = NULL; 2747 } 2748 } 2749 2750 /* 2751 * atw_detach: 2752 * 2753 * Detach an ADM8211 interface. 2754 */ 2755 int 2756 atw_detach(struct atw_softc *sc) 2757 { 2758 struct ifnet *ifp = &sc->sc_ic.ic_if; 2759 struct atw_rxsoft *rxs; 2760 struct atw_txsoft *txs; 2761 int i; 2762 2763 /* 2764 * Succeed now if there isn't any work to do. 2765 */ 2766 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2767 return (0); 2768 2769 ieee80211_ifdetach(ifp); 2770 if_detach(ifp); 2771 2772 for (i = 0; i < ATW_NRXDESC; i++) { 2773 rxs = &sc->sc_rxsoft[i]; 2774 if (rxs->rxs_mbuf != NULL) { 2775 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2776 m_freem(rxs->rxs_mbuf); 2777 rxs->rxs_mbuf = NULL; 2778 } 2779 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2780 } 2781 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2782 txs = &sc->sc_txsoft[i]; 2783 if (txs->txs_mbuf != NULL) { 2784 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2785 m_freem(txs->txs_mbuf); 2786 txs->txs_mbuf = NULL; 2787 } 2788 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2789 } 2790 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2791 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2792 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2793 sizeof(struct atw_control_data)); 2794 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2795 2796 shutdownhook_disestablish(sc->sc_sdhook); 2797 powerhook_disestablish(sc->sc_powerhook); 2798 2799 if (sc->sc_srom) 2800 free(sc->sc_srom, M_DEVBUF); 2801 2802 return (0); 2803 } 2804 2805 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2806 void 2807 atw_shutdown(void *arg) 2808 { 2809 struct atw_softc *sc = arg; 2810 2811 atw_stop(&sc->sc_ic.ic_if, 1); 2812 } 2813 2814 int 2815 atw_intr(void *arg) 2816 { 2817 struct atw_softc *sc = arg; 2818 struct ifnet *ifp = &sc->sc_ic.ic_if; 2819 u_int32_t status, rxstatus, txstatus, linkstatus; 2820 int handled = 0, txthresh; 2821 2822 #ifdef DEBUG 2823 if (ATW_IS_ENABLED(sc) == 0) 2824 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2825 #endif 2826 2827 /* 2828 * If the interface isn't running, the interrupt couldn't 2829 * possibly have come from us. 2830 */ 2831 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2832 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2833 return (0); 2834 2835 for (;;) { 2836 status = ATW_READ(sc, ATW_STSR); 2837 2838 if (status) 2839 ATW_WRITE(sc, ATW_STSR, status); 2840 2841 #ifdef ATW_DEBUG 2842 #define PRINTINTR(flag) do { \ 2843 if ((status & flag) != 0) { \ 2844 printf("%s" #flag, delim); \ 2845 delim = ","; \ 2846 } \ 2847 } while (0) 2848 2849 if (atw_debug > 1 && status) { 2850 const char *delim = "<"; 2851 2852 printf("%s: reg[STSR] = %x", 2853 sc->sc_dev.dv_xname, status); 2854 2855 PRINTINTR(ATW_INTR_FBE); 2856 PRINTINTR(ATW_INTR_LINKOFF); 2857 PRINTINTR(ATW_INTR_LINKON); 2858 PRINTINTR(ATW_INTR_RCI); 2859 PRINTINTR(ATW_INTR_RDU); 2860 PRINTINTR(ATW_INTR_REIS); 2861 PRINTINTR(ATW_INTR_RPS); 2862 PRINTINTR(ATW_INTR_TCI); 2863 PRINTINTR(ATW_INTR_TDU); 2864 PRINTINTR(ATW_INTR_TLT); 2865 PRINTINTR(ATW_INTR_TPS); 2866 PRINTINTR(ATW_INTR_TRT); 2867 PRINTINTR(ATW_INTR_TUF); 2868 PRINTINTR(ATW_INTR_BCNTC); 2869 PRINTINTR(ATW_INTR_ATIME); 2870 PRINTINTR(ATW_INTR_TBTT); 2871 PRINTINTR(ATW_INTR_TSCZ); 2872 PRINTINTR(ATW_INTR_TSFTF); 2873 printf(">\n"); 2874 } 2875 #undef PRINTINTR 2876 #endif /* ATW_DEBUG */ 2877 2878 if ((status & sc->sc_inten) == 0) 2879 break; 2880 2881 handled = 1; 2882 2883 rxstatus = status & sc->sc_rxint_mask; 2884 txstatus = status & sc->sc_txint_mask; 2885 linkstatus = status & sc->sc_linkint_mask; 2886 2887 if (linkstatus) { 2888 atw_linkintr(sc, linkstatus); 2889 } 2890 2891 if (rxstatus) { 2892 /* Grab any new packets. */ 2893 atw_rxintr(sc); 2894 2895 if (rxstatus & ATW_INTR_RDU) { 2896 printf("%s: receive ring overrun\n", 2897 sc->sc_dev.dv_xname); 2898 /* Get the receive process going again. */ 2899 ATW_WRITE(sc, ATW_RDR, 0x1); 2900 break; 2901 } 2902 } 2903 2904 if (txstatus) { 2905 /* Sweep up transmit descriptors. */ 2906 atw_txintr(sc); 2907 2908 if (txstatus & ATW_INTR_TLT) 2909 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2910 sc->sc_dev.dv_xname)); 2911 2912 if (txstatus & ATW_INTR_TRT) 2913 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2914 sc->sc_dev.dv_xname)); 2915 2916 /* If Tx under-run, increase our transmit threshold 2917 * if another is available. 2918 */ 2919 txthresh = sc->sc_txthresh + 1; 2920 if ((txstatus & ATW_INTR_TUF) && 2921 sc->sc_txth[txthresh].txth_name != NULL) { 2922 /* Idle the transmit process. */ 2923 atw_idle(sc, ATW_NAR_ST); 2924 2925 sc->sc_txthresh = txthresh; 2926 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2927 sc->sc_opmode |= 2928 sc->sc_txth[txthresh].txth_opmode; 2929 printf("%s: transmit underrun; new " 2930 "threshold: %s\n", sc->sc_dev.dv_xname, 2931 sc->sc_txth[txthresh].txth_name); 2932 2933 /* Set the new threshold and restart 2934 * the transmit process. 2935 */ 2936 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2937 DELAY(20 * 1000); 2938 ATW_WRITE(sc, ATW_RDR, 0x1); 2939 /* XXX Log every Nth underrun from 2940 * XXX now on? 2941 */ 2942 } 2943 } 2944 2945 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2946 if (status & ATW_INTR_TPS) 2947 printf("%s: transmit process stopped\n", 2948 sc->sc_dev.dv_xname); 2949 if (status & ATW_INTR_RPS) 2950 printf("%s: receive process stopped\n", 2951 sc->sc_dev.dv_xname); 2952 (void)atw_init(ifp); 2953 break; 2954 } 2955 2956 if (status & ATW_INTR_FBE) { 2957 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2958 (void)atw_init(ifp); 2959 break; 2960 } 2961 2962 /* 2963 * Not handled: 2964 * 2965 * Transmit buffer unavailable -- normal 2966 * condition, nothing to do, really. 2967 * 2968 * Early receive interrupt -- not available on 2969 * all chips, we just use RI. We also only 2970 * use single-segment receive DMA, so this 2971 * is mostly useless. 2972 * 2973 * TBD others 2974 */ 2975 } 2976 2977 /* Try to get more packets going. */ 2978 atw_start(ifp); 2979 2980 return (handled); 2981 } 2982 2983 /* 2984 * atw_idle: 2985 * 2986 * Cause the transmit and/or receive processes to go idle. 2987 * 2988 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2989 * process in STSR if I clear SR or ST after the process has already 2990 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2991 * do not seem to be too reliable. Perhaps I have the sense of the 2992 * Rx bits switched with the Tx bits? 2993 */ 2994 void 2995 atw_idle(struct atw_softc *sc, u_int32_t bits) 2996 { 2997 u_int32_t ackmask = 0, opmode, stsr, test0; 2998 int i, s; 2999 3000 s = splnet(); 3001 3002 opmode = sc->sc_opmode & ~bits; 3003 3004 if (bits & ATW_NAR_SR) 3005 ackmask |= ATW_INTR_RPS; 3006 3007 if (bits & ATW_NAR_ST) { 3008 ackmask |= ATW_INTR_TPS; 3009 /* set ATW_NAR_HF to flush TX FIFO. */ 3010 opmode |= ATW_NAR_HF; 3011 } 3012 3013 ATW_WRITE(sc, ATW_NAR, opmode); 3014 DELAY(20 * 1000); 3015 3016 for (i = 0; i < 10; i++) { 3017 stsr = ATW_READ(sc, ATW_STSR); 3018 if ((stsr & ackmask) == ackmask) 3019 break; 3020 DELAY(1000); 3021 } 3022 3023 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3024 3025 if ((stsr & ackmask) == ackmask) 3026 goto out; 3027 3028 test0 = ATW_READ(sc, ATW_TEST0); 3029 3030 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3031 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3032 printf("%s: transmit process not idle [%s]\n", 3033 sc->sc_dev.dv_xname, 3034 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 3035 printf("%s: bits %08x test0 %08x stsr %08x\n", 3036 sc->sc_dev.dv_xname, bits, test0, stsr); 3037 } 3038 3039 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3040 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3041 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3042 sc->sc_dev.dv_xname, 3043 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3044 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3045 sc->sc_dev.dv_xname, bits, test0, stsr)); 3046 } 3047 out: 3048 if ((bits & ATW_NAR_ST) != 0) 3049 atw_txdrain(sc); 3050 splx(s); 3051 return; 3052 } 3053 3054 /* 3055 * atw_linkintr: 3056 * 3057 * Helper; handle link-status interrupts. 3058 */ 3059 void 3060 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3061 { 3062 struct ieee80211com *ic = &sc->sc_ic; 3063 3064 if (ic->ic_state != IEEE80211_S_RUN) 3065 return; 3066 3067 if (linkstatus & ATW_INTR_LINKON) { 3068 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3069 sc->sc_rescan_timer = 0; 3070 } else if (linkstatus & ATW_INTR_LINKOFF) { 3071 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3072 if (ic->ic_opmode != IEEE80211_M_STA) 3073 return; 3074 sc->sc_rescan_timer = 3; 3075 ic->ic_if.if_timer = 1; 3076 } 3077 } 3078 3079 static __inline int 3080 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame *wh) 3081 { 3082 if ((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) == 0) 3083 return 0; 3084 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3085 return 0; 3086 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3087 } 3088 3089 /* 3090 * atw_rxintr: 3091 * 3092 * Helper; handle receive interrupts. 3093 */ 3094 void 3095 atw_rxintr(struct atw_softc *sc) 3096 { 3097 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3098 struct ieee80211com *ic = &sc->sc_ic; 3099 struct ieee80211_node *ni; 3100 struct ieee80211_frame *wh; 3101 struct ifnet *ifp = &ic->ic_if; 3102 struct atw_rxsoft *rxs; 3103 struct mbuf *m; 3104 u_int32_t rxstat; 3105 int i, len, rate, rate0; 3106 u_int32_t rssi, rssi0; 3107 3108 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3109 rxs = &sc->sc_rxsoft[i]; 3110 3111 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3112 3113 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3114 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3115 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3116 3117 if (rxstat & ATW_RXSTAT_OWN) 3118 break; /* We have processed all receive buffers. */ 3119 3120 DPRINTF3(sc, 3121 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3122 sc->sc_dev.dv_xname, 3123 rxstat, rssi0, 3124 le32toh(sc->sc_rxdescs[i].ar_buf1), 3125 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3126 3127 /* 3128 * Make sure the packet fits in one buffer. This should 3129 * always be the case. 3130 */ 3131 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3132 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3133 printf("%s: incoming packet spilled, resetting\n", 3134 sc->sc_dev.dv_xname); 3135 (void)atw_init(ifp); 3136 return; 3137 } 3138 3139 /* 3140 * If an error occurred, update stats, clear the status 3141 * word, and leave the packet buffer in place. It will 3142 * simply be reused the next time the ring comes around. 3143 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3144 * error. 3145 */ 3146 3147 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3148 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3149 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3150 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3151 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3152 ATW_RXSTAT_ICVE)) != 0)) { 3153 #define PRINTERR(bit, str) \ 3154 if (rxstat & (bit)) \ 3155 printf("%s: receive error: %s\n", \ 3156 sc->sc_dev.dv_xname, str) 3157 ifp->if_ierrors++; 3158 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3159 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3160 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3161 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3162 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3163 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3164 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3165 #undef PRINTERR 3166 ATW_INIT_RXDESC(sc, i); 3167 continue; 3168 } 3169 3170 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3171 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3172 3173 /* 3174 * No errors; receive the packet. Note the ADM8211 3175 * includes the CRC in promiscuous mode. 3176 */ 3177 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3178 3179 /* 3180 * Allocate a new mbuf cluster. If that fails, we are 3181 * out of memory, and must drop the packet and recycle 3182 * the buffer that's already attached to this descriptor. 3183 */ 3184 m = rxs->rxs_mbuf; 3185 if (atw_add_rxbuf(sc, i) != 0) { 3186 ifp->if_ierrors++; 3187 ATW_INIT_RXDESC(sc, i); 3188 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3189 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3190 continue; 3191 } 3192 3193 ifp->if_ipackets++; 3194 if (sc->sc_opmode & ATW_NAR_PR) 3195 m->m_flags |= M_HASFCS; 3196 m->m_pkthdr.rcvif = ifp; 3197 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3198 3199 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3200 rate = 0; 3201 else 3202 rate = rate_tbl[rate0]; 3203 3204 /* The RSSI comes straight from a register in the 3205 * baseband processor. I know that for the RF3000, 3206 * the RSSI register also contains the antenna-selection 3207 * bits. Mask those off. 3208 * 3209 * TBD Treat other basebands. 3210 */ 3211 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3212 rssi = rssi0 & RF3000_RSSI_MASK; 3213 else 3214 rssi = rssi0; 3215 3216 #if NBPFILTER > 0 3217 /* Pass this up to any BPF listeners. */ 3218 if (sc->sc_radiobpf != NULL) { 3219 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3220 3221 tap->ar_rate = rate; 3222 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3223 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3224 3225 /* TBD verify units are dB */ 3226 tap->ar_antsignal = (int)rssi; 3227 /* TBD tap->ar_flags */ 3228 3229 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3230 tap->ar_ihdr.it_len, m); 3231 } 3232 #endif /* NPBFILTER > 0 */ 3233 3234 wh = mtod(m, struct ieee80211_frame *); 3235 ni = ieee80211_find_rxnode(ic, wh); 3236 if (atw_hw_decrypted(sc, wh)) 3237 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3238 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3239 /* 3240 * The frame may have caused the node to be marked for 3241 * reclamation (e.g. in response to a DEAUTH message) 3242 * so use free_node here instead of unref_node. 3243 */ 3244 if (ni == ic->ic_bss) 3245 ieee80211_unref_node(&ni); 3246 else 3247 ieee80211_free_node(ic, ni); 3248 } 3249 3250 /* Update the receive pointer. */ 3251 sc->sc_rxptr = i; 3252 } 3253 3254 /* 3255 * atw_txintr: 3256 * 3257 * Helper; handle transmit interrupts. 3258 */ 3259 void 3260 atw_txintr(struct atw_softc *sc) 3261 { 3262 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3263 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3264 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3265 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3266 3267 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3268 struct ifnet *ifp = &sc->sc_ic.ic_if; 3269 struct atw_txsoft *txs; 3270 u_int32_t txstat; 3271 3272 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3273 sc->sc_dev.dv_xname, sc->sc_flags)); 3274 3275 ifp->if_flags &= ~IFF_OACTIVE; 3276 3277 /* 3278 * Go through our Tx list and free mbufs for those 3279 * frames that have been transmitted. 3280 */ 3281 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3282 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3283 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3284 3285 #ifdef ATW_DEBUG 3286 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3287 int i; 3288 printf(" txsoft %p transmit chain:\n", txs); 3289 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3290 txs->txs_ndescs - 1, 3291 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3292 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3293 printf(" descriptor %d:\n", i); 3294 printf(" at_status: 0x%08x\n", 3295 le32toh(sc->sc_txdescs[i].at_stat)); 3296 printf(" at_flags: 0x%08x\n", 3297 le32toh(sc->sc_txdescs[i].at_flags)); 3298 printf(" at_buf1: 0x%08x\n", 3299 le32toh(sc->sc_txdescs[i].at_buf1)); 3300 printf(" at_buf2: 0x%08x\n", 3301 le32toh(sc->sc_txdescs[i].at_buf2)); 3302 if (i == txs->txs_lastdesc) 3303 break; 3304 } 3305 } 3306 #endif 3307 3308 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3309 if (txstat & ATW_TXSTAT_OWN) 3310 break; 3311 3312 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3313 3314 sc->sc_txfree += txs->txs_ndescs; 3315 3316 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3317 0, txs->txs_dmamap->dm_mapsize, 3318 BUS_DMASYNC_POSTWRITE); 3319 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3320 m_freem(txs->txs_mbuf); 3321 txs->txs_mbuf = NULL; 3322 3323 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3324 3325 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3326 (txstat & TXSTAT_ERRMASK) != 0) { 3327 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3328 txstat_buf, sizeof(txstat_buf)); 3329 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3330 txstat_buf, 3331 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3332 } 3333 3334 /* 3335 * Check for errors and collisions. 3336 */ 3337 if (txstat & ATW_TXSTAT_TUF) 3338 sc->sc_stats.ts_tx_tuf++; 3339 if (txstat & ATW_TXSTAT_TLT) 3340 sc->sc_stats.ts_tx_tlt++; 3341 if (txstat & ATW_TXSTAT_TRT) 3342 sc->sc_stats.ts_tx_trt++; 3343 if (txstat & ATW_TXSTAT_TRO) 3344 sc->sc_stats.ts_tx_tro++; 3345 if (txstat & ATW_TXSTAT_SOFBR) { 3346 sc->sc_stats.ts_tx_sofbr++; 3347 } 3348 3349 if ((txstat & ATW_TXSTAT_ES) == 0) 3350 ifp->if_collisions += 3351 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3352 else 3353 ifp->if_oerrors++; 3354 3355 ifp->if_opackets++; 3356 } 3357 3358 /* 3359 * If there are no more pending transmissions, cancel the watchdog 3360 * timer. 3361 */ 3362 if (txs == NULL) 3363 sc->sc_tx_timer = 0; 3364 #undef TXSTAT_ERRMASK 3365 #undef TXSTAT_FMT 3366 } 3367 3368 /* 3369 * atw_watchdog: [ifnet interface function] 3370 * 3371 * Watchdog timer handler. 3372 */ 3373 void 3374 atw_watchdog(struct ifnet *ifp) 3375 { 3376 struct atw_softc *sc = ifp->if_softc; 3377 struct ieee80211com *ic = &sc->sc_ic; 3378 3379 ifp->if_timer = 0; 3380 if (ATW_IS_ENABLED(sc) == 0) 3381 return; 3382 3383 if (sc->sc_rescan_timer) { 3384 if (--sc->sc_rescan_timer == 0) 3385 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3386 } 3387 if (sc->sc_tx_timer) { 3388 if (--sc->sc_tx_timer == 0 && 3389 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3390 printf("%s: transmit timeout\n", ifp->if_xname); 3391 ifp->if_oerrors++; 3392 (void)atw_init(ifp); 3393 atw_start(ifp); 3394 } 3395 } 3396 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3397 ifp->if_timer = 1; 3398 ieee80211_watchdog(ifp); 3399 } 3400 3401 /* Compute the 802.11 Duration field and the PLCP Length fields for 3402 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3403 * Write the fields to the ADM8211 Tx header, frm. 3404 * 3405 * TBD use the fragmentation threshold to find the right duration for 3406 * the first & last fragments. 3407 * 3408 * TBD make certain of the duration fields applied by the ADM8211 to each 3409 * fragment. I think that the ADM8211 knows how to subtract the CTS 3410 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3411 * I also think that the ADM8211 does *some* arithmetic for us, because 3412 * otherwise I think we would have to set a first duration for CTS/first 3413 * fragment, a second duration for fragments between the first and the 3414 * last, and a third duration for the last fragment. 3415 * 3416 * TBD make certain that duration fields reflect addition of FCS/WEP 3417 * and correct duration arithmetic as necessary. 3418 */ 3419 static void 3420 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3421 int len) 3422 { 3423 int remainder; 3424 3425 /* deal also with encrypted fragments */ 3426 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3427 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3428 sc->sc_dev.dv_xname)); 3429 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3430 IEEE80211_WEP_CRCLEN; 3431 } 3432 3433 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3434 * duration (XXX added by MAC?). 3435 */ 3436 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3437 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3438 3439 if (rate <= 4) 3440 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3441 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3442 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3443 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3444 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3445 else 3446 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3447 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3448 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3449 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3450 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3451 3452 /* lengthen duration if long preamble */ 3453 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3454 frm->atw_head_dur += 3455 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3456 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3457 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3458 IEEE80211_DUR_DS_FAST_PLCPHDR); 3459 3460 if (remainder != 0) 3461 frm->atw_head_dur++; 3462 3463 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3464 (rate == 2 || rate == 4)) { 3465 /* derived from Linux: how could this be right? */ 3466 frm->atw_head_plcplen = frm->atw_head_dur; 3467 } else { 3468 frm->atw_head_plcplen = (16 * len) / rate; 3469 remainder = (80 * len) % (rate * 5); 3470 3471 if (remainder != 0) { 3472 frm->atw_head_plcplen++; 3473 3474 /* XXX magic */ 3475 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3476 rate == 22 && remainder <= 30) 3477 frm->atw_head_plcplen |= 0x8000; 3478 } 3479 } 3480 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3481 htole16(frm->atw_head_plcplen); 3482 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3483 } 3484 3485 #ifdef ATW_DEBUG 3486 static void 3487 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3488 { 3489 struct atw_softc *sc = ifp->if_softc; 3490 struct mbuf *m; 3491 int i, noctets = 0; 3492 3493 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3494 m0->m_pkthdr.len); 3495 3496 for (m = m0; m; m = m->m_next) { 3497 if (m->m_len == 0) 3498 continue; 3499 for (i = 0; i < m->m_len; i++) { 3500 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3501 if (++noctets % 24 == 0) 3502 printf("\n"); 3503 } 3504 } 3505 printf("%s%s: %d bytes emitted\n", 3506 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3507 } 3508 #endif /* ATW_DEBUG */ 3509 3510 /* 3511 * atw_start: [ifnet interface function] 3512 * 3513 * Start packet transmission on the interface. 3514 */ 3515 void 3516 atw_start(struct ifnet *ifp) 3517 { 3518 struct atw_softc *sc = ifp->if_softc; 3519 struct ieee80211com *ic = &sc->sc_ic; 3520 struct ieee80211_node *ni; 3521 struct ieee80211_frame *wh; 3522 struct atw_frame *hh; 3523 struct mbuf *m0, *m; 3524 struct atw_txsoft *txs, *last_txs; 3525 struct atw_txdesc *txd; 3526 int do_encrypt, rate; 3527 bus_dmamap_t dmamap; 3528 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3529 3530 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3531 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3532 3533 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3534 return; 3535 3536 /* 3537 * Remember the previous number of free descriptors and 3538 * the first descriptor we'll use. 3539 */ 3540 ofree = sc->sc_txfree; 3541 firsttx = sc->sc_txnext; 3542 3543 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3544 sc->sc_dev.dv_xname, ofree, firsttx)); 3545 3546 /* 3547 * Loop through the send queue, setting up transmit descriptors 3548 * until we drain the queue, or use up all available transmit 3549 * descriptors. 3550 */ 3551 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3552 sc->sc_txfree != 0) { 3553 3554 /* 3555 * Grab a packet off the management queue, if it 3556 * is not empty. Otherwise, from the data queue. 3557 */ 3558 IF_DEQUEUE(&ic->ic_mgtq, m0); 3559 if (m0 != NULL) { 3560 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3561 m0->m_pkthdr.rcvif = NULL; 3562 } else { 3563 /* send no data packets until we are associated */ 3564 if (ic->ic_state != IEEE80211_S_RUN) 3565 break; 3566 IFQ_DEQUEUE(&ifp->if_snd, m0); 3567 if (m0 == NULL) 3568 break; 3569 #if NBPFILTER > 0 3570 if (ifp->if_bpf != NULL) 3571 bpf_mtap(ifp->if_bpf, m0); 3572 #endif /* NBPFILTER > 0 */ 3573 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3574 ifp->if_oerrors++; 3575 break; 3576 } 3577 } 3578 3579 rate = MAX(ieee80211_get_rate(ic), 2); 3580 3581 #if NBPFILTER > 0 3582 /* 3583 * Pass the packet to any BPF listeners. 3584 */ 3585 if (ic->ic_rawbpf != NULL) 3586 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3587 3588 if (sc->sc_radiobpf != NULL) { 3589 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3590 3591 tap->at_rate = rate; 3592 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3593 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3594 3595 /* TBD tap->at_flags */ 3596 3597 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3598 tap->at_ihdr.it_len, m0); 3599 } 3600 #endif /* NBPFILTER > 0 */ 3601 3602 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3603 3604 if (ni != NULL && ni != ic->ic_bss) 3605 ieee80211_free_node(ic, ni); 3606 3607 if (m0 == NULL) { 3608 ifp->if_oerrors++; 3609 break; 3610 } 3611 3612 /* just to make sure. */ 3613 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3614 3615 if (m0 == NULL) { 3616 ifp->if_oerrors++; 3617 break; 3618 } 3619 3620 hh = mtod(m0, struct atw_frame *); 3621 wh = &hh->atw_ihdr; 3622 3623 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3624 3625 /* Copy everything we need from the 802.11 header: 3626 * Frame Control; address 1, address 3, or addresses 3627 * 3 and 4. NIC fills in BSSID, SA. 3628 */ 3629 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3630 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3631 panic("%s: illegal WDS frame", 3632 sc->sc_dev.dv_xname); 3633 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3634 } else 3635 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3636 3637 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3638 3639 /* initialize remaining Tx parameters */ 3640 memset(&hh->u, 0, sizeof(hh->u)); 3641 3642 hh->atw_rate = rate * 5; 3643 /* XXX this could be incorrect if M_FCS. _encap should 3644 * probably strip FCS just in case it sticks around in 3645 * bridged packets. 3646 */ 3647 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3648 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3649 sizeof(struct atw_frame)); 3650 3651 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3652 hh->atw_rtylmt = 3; 3653 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3654 if (do_encrypt) { 3655 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3656 hh->atw_keyid = ic->ic_wep_txkey; 3657 } 3658 3659 /* TBD 4-addr frames */ 3660 atw_frame_setdurs(sc, hh, rate, 3661 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3662 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3663 3664 /* never fragment multicast frames */ 3665 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3666 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3667 } else if (sc->sc_flags & ATWF_RTSCTS) { 3668 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3669 } 3670 3671 #ifdef ATW_DEBUG 3672 hh->atw_fragnum = 0; 3673 3674 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3675 printf("%s: dst = %s, rate = 0x%02x, " 3676 "service = 0x%02x, paylen = 0x%04x\n", 3677 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3678 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3679 3680 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3681 "dur1 = 0x%04x, dur2 = 0x%04x, " 3682 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3683 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3684 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3685 hh->atw_tail_dur, hh->atw_head_dur); 3686 3687 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3688 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3689 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3690 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3691 3692 printf("%s: keyid = %d\n", 3693 sc->sc_dev.dv_xname, hh->atw_keyid); 3694 3695 atw_dump_pkt(ifp, m0); 3696 } 3697 #endif /* ATW_DEBUG */ 3698 3699 dmamap = txs->txs_dmamap; 3700 3701 /* 3702 * Load the DMA map. Copy and try (once) again if the packet 3703 * didn't fit in the alloted number of segments. 3704 */ 3705 for (first = 1; 3706 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3707 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3708 first = 0) { 3709 MGETHDR(m, M_DONTWAIT, MT_DATA); 3710 if (m == NULL) { 3711 printf("%s: unable to allocate Tx mbuf\n", 3712 sc->sc_dev.dv_xname); 3713 break; 3714 } 3715 if (m0->m_pkthdr.len > MHLEN) { 3716 MCLGET(m, M_DONTWAIT); 3717 if ((m->m_flags & M_EXT) == 0) { 3718 printf("%s: unable to allocate Tx " 3719 "cluster\n", sc->sc_dev.dv_xname); 3720 m_freem(m); 3721 break; 3722 } 3723 } 3724 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3725 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3726 m_freem(m0); 3727 m0 = m; 3728 m = NULL; 3729 } 3730 if (error != 0) { 3731 printf("%s: unable to load Tx buffer, " 3732 "error = %d\n", sc->sc_dev.dv_xname, error); 3733 m_freem(m0); 3734 break; 3735 } 3736 3737 /* 3738 * Ensure we have enough descriptors free to describe 3739 * the packet. 3740 */ 3741 if (dmamap->dm_nsegs > sc->sc_txfree) { 3742 /* 3743 * Not enough free descriptors to transmit 3744 * this packet. Unload the DMA map and 3745 * drop the packet. Notify the upper layer 3746 * that there are no more slots left. 3747 * 3748 * XXX We could allocate an mbuf and copy, but 3749 * XXX it is worth it? 3750 */ 3751 ifp->if_flags |= IFF_OACTIVE; 3752 bus_dmamap_unload(sc->sc_dmat, dmamap); 3753 m_freem(m0); 3754 break; 3755 } 3756 3757 /* 3758 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3759 */ 3760 3761 /* Sync the DMA map. */ 3762 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3763 BUS_DMASYNC_PREWRITE); 3764 3765 /* XXX arbitrary retry limit; 8 because I have seen it in 3766 * use already and maybe 0 means "no tries" ! 3767 */ 3768 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3769 3770 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3771 sc->sc_dev.dv_xname, rate * 5)); 3772 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3773 3774 /* 3775 * Initialize the transmit descriptors. 3776 */ 3777 for (nexttx = sc->sc_txnext, seg = 0; 3778 seg < dmamap->dm_nsegs; 3779 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3780 /* 3781 * If this is the first descriptor we're 3782 * enqueueing, don't set the OWN bit just 3783 * yet. That could cause a race condition. 3784 * We'll do it below. 3785 */ 3786 txd = &sc->sc_txdescs[nexttx]; 3787 txd->at_ctl = ctl | 3788 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3789 3790 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3791 txd->at_flags = 3792 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3793 ATW_TXFLAG_TBS1_MASK)) | 3794 ((nexttx == (ATW_NTXDESC - 1)) 3795 ? htole32(ATW_TXFLAG_TER) : 0); 3796 lasttx = nexttx; 3797 } 3798 3799 IASSERT(lasttx != -1, ("bad lastx")); 3800 /* Set `first segment' and `last segment' appropriately. */ 3801 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3802 htole32(ATW_TXFLAG_FS); 3803 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3804 3805 #ifdef ATW_DEBUG 3806 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3807 printf(" txsoft %p transmit chain:\n", txs); 3808 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3809 printf(" descriptor %d:\n", seg); 3810 printf(" at_ctl: 0x%08x\n", 3811 le32toh(sc->sc_txdescs[seg].at_ctl)); 3812 printf(" at_flags: 0x%08x\n", 3813 le32toh(sc->sc_txdescs[seg].at_flags)); 3814 printf(" at_buf1: 0x%08x\n", 3815 le32toh(sc->sc_txdescs[seg].at_buf1)); 3816 printf(" at_buf2: 0x%08x\n", 3817 le32toh(sc->sc_txdescs[seg].at_buf2)); 3818 if (seg == lasttx) 3819 break; 3820 } 3821 } 3822 #endif 3823 3824 /* Sync the descriptors we're using. */ 3825 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3826 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3827 3828 /* 3829 * Store a pointer to the packet so we can free it later, 3830 * and remember what txdirty will be once the packet is 3831 * done. 3832 */ 3833 txs->txs_mbuf = m0; 3834 txs->txs_firstdesc = sc->sc_txnext; 3835 txs->txs_lastdesc = lasttx; 3836 txs->txs_ndescs = dmamap->dm_nsegs; 3837 3838 /* Advance the tx pointer. */ 3839 sc->sc_txfree -= dmamap->dm_nsegs; 3840 sc->sc_txnext = nexttx; 3841 3842 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3843 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3844 3845 last_txs = txs; 3846 } 3847 3848 if (txs == NULL || sc->sc_txfree == 0) { 3849 /* No more slots left; notify upper layer. */ 3850 ifp->if_flags |= IFF_OACTIVE; 3851 } 3852 3853 if (sc->sc_txfree != ofree) { 3854 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3855 sc->sc_dev.dv_xname, lasttx, firsttx)); 3856 /* 3857 * Cause a transmit interrupt to happen on the 3858 * last packet we enqueued. 3859 */ 3860 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3861 ATW_CDTXSYNC(sc, lasttx, 1, 3862 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3863 3864 /* 3865 * The entire packet chain is set up. Give the 3866 * first descriptor to the chip now. 3867 */ 3868 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3869 ATW_CDTXSYNC(sc, firsttx, 1, 3870 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3871 3872 /* Wake up the transmitter. */ 3873 ATW_WRITE(sc, ATW_TDR, 0x1); 3874 3875 /* Set a watchdog timer in case the chip flakes out. */ 3876 sc->sc_tx_timer = 5; 3877 ifp->if_timer = 1; 3878 } 3879 } 3880 3881 /* 3882 * atw_power: 3883 * 3884 * Power management (suspend/resume) hook. 3885 */ 3886 void 3887 atw_power(int why, void *arg) 3888 { 3889 struct atw_softc *sc = arg; 3890 struct ifnet *ifp = &sc->sc_ic.ic_if; 3891 int s; 3892 3893 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3894 3895 s = splnet(); 3896 switch (why) { 3897 case PWR_STANDBY: 3898 /* XXX do nothing. */ 3899 break; 3900 case PWR_SUSPEND: 3901 atw_stop(ifp, 0); 3902 if (sc->sc_power != NULL) 3903 (*sc->sc_power)(sc, why); 3904 break; 3905 case PWR_RESUME: 3906 if (ifp->if_flags & IFF_UP) { 3907 if (sc->sc_power != NULL) 3908 (*sc->sc_power)(sc, why); 3909 atw_init(ifp); 3910 } 3911 break; 3912 case PWR_SOFTSUSPEND: 3913 case PWR_SOFTSTANDBY: 3914 case PWR_SOFTRESUME: 3915 break; 3916 } 3917 splx(s); 3918 } 3919 3920 /* 3921 * atw_ioctl: [ifnet interface function] 3922 * 3923 * Handle control requests from the operator. 3924 */ 3925 int 3926 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3927 { 3928 struct atw_softc *sc = ifp->if_softc; 3929 struct ifreq *ifr = (struct ifreq *)data; 3930 int s, error = 0; 3931 3932 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3933 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3934 return ENXIO; 3935 3936 s = splnet(); 3937 3938 switch (cmd) { 3939 case SIOCSIFFLAGS: 3940 if (ifp->if_flags & IFF_UP) { 3941 if (ATW_IS_ENABLED(sc)) { 3942 /* 3943 * To avoid rescanning another access point, 3944 * do not call atw_init() here. Instead, 3945 * only reflect media settings. 3946 */ 3947 atw_filter_setup(sc); 3948 } else 3949 error = atw_init(ifp); 3950 } else if (ATW_IS_ENABLED(sc)) 3951 atw_stop(ifp, 1); 3952 break; 3953 case SIOCADDMULTI: 3954 case SIOCDELMULTI: 3955 error = (cmd == SIOCADDMULTI) ? 3956 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3957 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3958 if (error == ENETRESET) { 3959 if (ATW_IS_ENABLED(sc)) 3960 atw_filter_setup(sc); /* do not rescan */ 3961 error = 0; 3962 } 3963 break; 3964 default: 3965 error = ieee80211_ioctl(ifp, cmd, data); 3966 if (error == ENETRESET) { 3967 if (ATW_IS_ENABLED(sc)) 3968 error = atw_init(ifp); 3969 else 3970 error = 0; 3971 } 3972 break; 3973 } 3974 3975 /* Try to get more packets going. */ 3976 if (ATW_IS_ENABLED(sc)) 3977 atw_start(ifp); 3978 3979 splx(s); 3980 return (error); 3981 } 3982 3983 static int 3984 atw_media_change(struct ifnet *ifp) 3985 { 3986 int error; 3987 3988 error = ieee80211_media_change(ifp); 3989 if (error == ENETRESET) { 3990 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3991 (IFF_RUNNING|IFF_UP)) 3992 atw_init(ifp); /* XXX lose error */ 3993 error = 0; 3994 } 3995 return error; 3996 } 3997 3998 static void 3999 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 4000 { 4001 struct atw_softc *sc = ifp->if_softc; 4002 4003 if (ATW_IS_ENABLED(sc) == 0) { 4004 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 4005 imr->ifm_status = 0; 4006 return; 4007 } 4008 ieee80211_media_status(ifp, imr); 4009 } 4010
Indexes created Fri Sep 26 20:09:58 GMT 2025