atw.c revision 1.85
1 /* $NetBSD: atw.c,v 1.85 2005/06/22 06:15:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.85 2005/06/22 06:15:51 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_alloc(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 247 const u_int8_t[IEEE80211_ADDR_LEN]); 248 static void atw_key_update_begin(struct ieee80211com *); 249 static void atw_key_update_end(struct ieee80211com *); 250 251 /* RAM/ROM utilities */ 252 static void atw_clear_sram(struct atw_softc *); 253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 254 static int atw_read_srom(struct atw_softc *); 255 256 /* BSS setup */ 257 static void atw_predict_beacon(struct atw_softc *); 258 static void atw_start_beacon(struct atw_softc *, int); 259 static void atw_write_bssid(struct atw_softc *); 260 static void atw_write_ssid(struct atw_softc *); 261 static void atw_write_sup_rates(struct atw_softc *); 262 static void atw_write_wep(struct atw_softc *); 263 264 /* Media */ 265 static int atw_media_change(struct ifnet *); 266 static void atw_media_status(struct ifnet *, struct ifmediareq *); 267 268 static void atw_filter_setup(struct atw_softc *); 269 270 /* 802.11 utilities */ 271 static void atw_frame_setdurs(struct atw_softc *, 272 struct atw_frame *, int, int); 273 static uint64_t atw_get_tsft(struct atw_softc *); 274 static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 275 uint32_t); 276 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 277 static void atw_node_free(struct ieee80211_node *); 278 static void atw_change_ibss(struct atw_softc *); 279 280 /* 281 * Tuner/transceiver/modem 282 */ 283 static void atw_bbp_io_enable(struct atw_softc *, int); 284 285 /* RFMD RF3000 Baseband Processor */ 286 static int atw_rf3000_init(struct atw_softc *); 287 static int atw_rf3000_tune(struct atw_softc *, u_int); 288 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 289 290 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 291 static void atw_si4126_tune(struct atw_softc *, u_int); 292 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 293 294 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 295 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 296 297 const char *atw_tx_state[] = { 298 "STOPPED", 299 "RUNNING - read descriptor", 300 "RUNNING - transmitting", 301 "RUNNING - filling fifo", /* XXX */ 302 "SUSPENDED", 303 "RUNNING -- write descriptor", 304 "RUNNING -- write last descriptor", 305 "RUNNING - fifo full" 306 }; 307 308 const char *atw_rx_state[] = { 309 "STOPPED", 310 "RUNNING - read descriptor", 311 "RUNNING - check this packet, pre-fetch next", 312 "RUNNING - wait for reception", 313 "SUSPENDED", 314 "RUNNING - write descriptor", 315 "RUNNING - flush fifo", 316 "RUNNING - fifo drain" 317 }; 318 319 int 320 atw_activate(struct device *self, enum devact act) 321 { 322 struct atw_softc *sc = (struct atw_softc *)self; 323 int rv = 0, s; 324 325 s = splnet(); 326 switch (act) { 327 case DVACT_ACTIVATE: 328 rv = EOPNOTSUPP; 329 break; 330 331 case DVACT_DEACTIVATE: 332 if_deactivate(&sc->sc_if); 333 break; 334 } 335 splx(s); 336 return rv; 337 } 338 339 /* 340 * atw_enable: 341 * 342 * Enable the ADM8211 chip. 343 */ 344 int 345 atw_enable(struct atw_softc *sc) 346 { 347 348 if (ATW_IS_ENABLED(sc) == 0) { 349 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 350 printf("%s: device enable failed\n", 351 sc->sc_dev.dv_xname); 352 return (EIO); 353 } 354 sc->sc_flags |= ATWF_ENABLED; 355 } 356 return (0); 357 } 358 359 /* 360 * atw_disable: 361 * 362 * Disable the ADM8211 chip. 363 */ 364 void 365 atw_disable(struct atw_softc *sc) 366 { 367 if (!ATW_IS_ENABLED(sc)) 368 return; 369 if (sc->sc_disable != NULL) 370 (*sc->sc_disable)(sc); 371 sc->sc_flags &= ~ATWF_ENABLED; 372 } 373 374 /* Returns -1 on failure. */ 375 static int 376 atw_read_srom(struct atw_softc *sc) 377 { 378 struct seeprom_descriptor sd; 379 uint32_t test0, fail_bits; 380 381 (void)memset(&sd, 0, sizeof(sd)); 382 383 test0 = ATW_READ(sc, ATW_TEST0); 384 385 switch (sc->sc_rev) { 386 case ATW_REVISION_BA: 387 case ATW_REVISION_CA: 388 fail_bits = ATW_TEST0_EPNE; 389 break; 390 default: 391 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 392 break; 393 } 394 if ((test0 & fail_bits) != 0) { 395 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 396 return -1; 397 } 398 399 switch (test0 & ATW_TEST0_EPTYP_MASK) { 400 case ATW_TEST0_EPTYP_93c66: 401 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 402 sc->sc_sromsz = 512; 403 sd.sd_chip = C56_66; 404 break; 405 case ATW_TEST0_EPTYP_93c46: 406 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 407 sc->sc_sromsz = 128; 408 sd.sd_chip = C46; 409 break; 410 default: 411 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 412 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 413 return -1; 414 } 415 416 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 417 418 if (sc->sc_srom == NULL) { 419 printf("%s: unable to allocate SROM buffer\n", 420 sc->sc_dev.dv_xname); 421 return -1; 422 } 423 424 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 425 426 /* ADM8211 has a single 32-bit register for controlling the 427 * 93cx6 SROM. Bit SRS enables the serial port. There is no 428 * "ready" bit. The ADM8211 input/output sense is the reverse 429 * of read_seeprom's. 430 */ 431 sd.sd_tag = sc->sc_st; 432 sd.sd_bsh = sc->sc_sh; 433 sd.sd_regsize = 4; 434 sd.sd_control_offset = ATW_SPR; 435 sd.sd_status_offset = ATW_SPR; 436 sd.sd_dataout_offset = ATW_SPR; 437 sd.sd_CK = ATW_SPR_SCLK; 438 sd.sd_CS = ATW_SPR_SCS; 439 sd.sd_DI = ATW_SPR_SDO; 440 sd.sd_DO = ATW_SPR_SDI; 441 sd.sd_MS = ATW_SPR_SRS; 442 sd.sd_RDY = 0; 443 444 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 445 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 446 free(sc->sc_srom, M_DEVBUF); 447 return -1; 448 } 449 #ifdef ATW_DEBUG 450 { 451 int i; 452 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 453 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 454 if (((i % 8) == 0) && (i != 0)) { 455 ATW_DPRINTF(("\n\t")); 456 } 457 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 458 } 459 ATW_DPRINTF(("\n")); 460 } 461 #endif /* ATW_DEBUG */ 462 return 0; 463 } 464 465 #ifdef ATW_DEBUG 466 static void 467 atw_print_regs(struct atw_softc *sc, const char *where) 468 { 469 #define PRINTREG(sc, reg) \ 470 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 471 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 472 473 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 474 475 PRINTREG(sc, ATW_PAR); 476 PRINTREG(sc, ATW_FRCTL); 477 PRINTREG(sc, ATW_TDR); 478 PRINTREG(sc, ATW_WTDP); 479 PRINTREG(sc, ATW_RDR); 480 PRINTREG(sc, ATW_WRDP); 481 PRINTREG(sc, ATW_RDB); 482 PRINTREG(sc, ATW_CSR3A); 483 PRINTREG(sc, ATW_TDBD); 484 PRINTREG(sc, ATW_TDBP); 485 PRINTREG(sc, ATW_STSR); 486 PRINTREG(sc, ATW_CSR5A); 487 PRINTREG(sc, ATW_NAR); 488 PRINTREG(sc, ATW_CSR6A); 489 PRINTREG(sc, ATW_IER); 490 PRINTREG(sc, ATW_CSR7A); 491 PRINTREG(sc, ATW_LPC); 492 PRINTREG(sc, ATW_TEST1); 493 PRINTREG(sc, ATW_SPR); 494 PRINTREG(sc, ATW_TEST0); 495 PRINTREG(sc, ATW_WCSR); 496 PRINTREG(sc, ATW_WPDR); 497 PRINTREG(sc, ATW_GPTMR); 498 PRINTREG(sc, ATW_GPIO); 499 PRINTREG(sc, ATW_BBPCTL); 500 PRINTREG(sc, ATW_SYNCTL); 501 PRINTREG(sc, ATW_PLCPHD); 502 PRINTREG(sc, ATW_MMIWADDR); 503 PRINTREG(sc, ATW_MMIRADDR1); 504 PRINTREG(sc, ATW_MMIRADDR2); 505 PRINTREG(sc, ATW_TXBR); 506 PRINTREG(sc, ATW_CSR15A); 507 PRINTREG(sc, ATW_ALCSTAT); 508 PRINTREG(sc, ATW_TOFS2); 509 PRINTREG(sc, ATW_CMDR); 510 PRINTREG(sc, ATW_PCIC); 511 PRINTREG(sc, ATW_PMCSR); 512 PRINTREG(sc, ATW_PAR0); 513 PRINTREG(sc, ATW_PAR1); 514 PRINTREG(sc, ATW_MAR0); 515 PRINTREG(sc, ATW_MAR1); 516 PRINTREG(sc, ATW_ATIMDA0); 517 PRINTREG(sc, ATW_ABDA1); 518 PRINTREG(sc, ATW_BSSID0); 519 PRINTREG(sc, ATW_TXLMT); 520 PRINTREG(sc, ATW_MIBCNT); 521 PRINTREG(sc, ATW_BCNT); 522 PRINTREG(sc, ATW_TSFTH); 523 PRINTREG(sc, ATW_TSC); 524 PRINTREG(sc, ATW_SYNRF); 525 PRINTREG(sc, ATW_BPLI); 526 PRINTREG(sc, ATW_CAP0); 527 PRINTREG(sc, ATW_CAP1); 528 PRINTREG(sc, ATW_RMD); 529 PRINTREG(sc, ATW_CFPP); 530 PRINTREG(sc, ATW_TOFS0); 531 PRINTREG(sc, ATW_TOFS1); 532 PRINTREG(sc, ATW_IFST); 533 PRINTREG(sc, ATW_RSPT); 534 PRINTREG(sc, ATW_TSFTL); 535 PRINTREG(sc, ATW_WEPCTL); 536 PRINTREG(sc, ATW_WESK); 537 PRINTREG(sc, ATW_WEPCNT); 538 PRINTREG(sc, ATW_MACTEST); 539 PRINTREG(sc, ATW_FER); 540 PRINTREG(sc, ATW_FEMR); 541 PRINTREG(sc, ATW_FPSR); 542 PRINTREG(sc, ATW_FFER); 543 #undef PRINTREG 544 } 545 #endif /* ATW_DEBUG */ 546 547 /* 548 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 549 */ 550 void 551 atw_attach(struct atw_softc *sc) 552 { 553 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 554 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 555 }; 556 struct ieee80211com *ic = &sc->sc_ic; 557 struct ifnet *ifp = &sc->sc_if; 558 int country_code, error, i, nrate, srom_major; 559 u_int32_t reg; 560 static const char *type_strings[] = {"Intersil (not supported)", 561 "RFMD", "Marvel (not supported)"}; 562 563 sc->sc_txth = atw_txthresh_tab_lo; 564 565 SIMPLEQ_INIT(&sc->sc_txfreeq); 566 SIMPLEQ_INIT(&sc->sc_txdirtyq); 567 568 #ifdef ATW_DEBUG 569 atw_print_regs(sc, "atw_attach"); 570 #endif /* ATW_DEBUG */ 571 572 /* 573 * Allocate the control data structures, and create and load the 574 * DMA map for it. 575 */ 576 if ((error = bus_dmamem_alloc(sc->sc_dmat, 577 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 578 1, &sc->sc_cdnseg, 0)) != 0) { 579 printf("%s: unable to allocate control data, error = %d\n", 580 sc->sc_dev.dv_xname, error); 581 goto fail_0; 582 } 583 584 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 585 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 586 BUS_DMA_COHERENT)) != 0) { 587 printf("%s: unable to map control data, error = %d\n", 588 sc->sc_dev.dv_xname, error); 589 goto fail_1; 590 } 591 592 if ((error = bus_dmamap_create(sc->sc_dmat, 593 sizeof(struct atw_control_data), 1, 594 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 595 printf("%s: unable to create control data DMA map, " 596 "error = %d\n", sc->sc_dev.dv_xname, error); 597 goto fail_2; 598 } 599 600 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 601 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 602 0)) != 0) { 603 printf("%s: unable to load control data DMA map, error = %d\n", 604 sc->sc_dev.dv_xname, error); 605 goto fail_3; 606 } 607 608 /* 609 * Create the transmit buffer DMA maps. 610 */ 611 sc->sc_ntxsegs = ATW_NTXSEGS; 612 for (i = 0; i < ATW_TXQUEUELEN; i++) { 613 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 614 sc->sc_ntxsegs, MCLBYTES, 0, 0, 615 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 616 printf("%s: unable to create tx DMA map %d, " 617 "error = %d\n", sc->sc_dev.dv_xname, i, error); 618 goto fail_4; 619 } 620 } 621 622 /* 623 * Create the receive buffer DMA maps. 624 */ 625 for (i = 0; i < ATW_NRXDESC; i++) { 626 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 627 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 628 printf("%s: unable to create rx DMA map %d, " 629 "error = %d\n", sc->sc_dev.dv_xname, i, error); 630 goto fail_5; 631 } 632 } 633 for (i = 0; i < ATW_NRXDESC; i++) { 634 sc->sc_rxsoft[i].rxs_mbuf = NULL; 635 } 636 637 switch (sc->sc_rev) { 638 case ATW_REVISION_AB: 639 case ATW_REVISION_AF: 640 sc->sc_sramlen = ATW_SRAM_A_SIZE; 641 break; 642 case ATW_REVISION_BA: 643 case ATW_REVISION_CA: 644 sc->sc_sramlen = ATW_SRAM_B_SIZE; 645 break; 646 } 647 648 /* Reset the chip to a known state. */ 649 atw_reset(sc); 650 651 if (atw_read_srom(sc) == -1) 652 return; 653 654 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 655 ATW_SR_RFTYPE_MASK); 656 657 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 658 ATW_SR_BBPTYPE_MASK); 659 660 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 661 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 662 return; 663 } 664 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 665 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 666 return; 667 } 668 669 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 670 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 671 672 /* XXX There exists a Linux driver which seems to use RFType = 0 for 673 * MARVEL. My bug, or theirs? 674 */ 675 676 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 677 678 switch (sc->sc_rftype) { 679 case ATW_RFTYPE_INTERSIL: 680 reg |= ATW_SYNCTL_CS1; 681 break; 682 case ATW_RFTYPE_RFMD: 683 reg |= ATW_SYNCTL_CS0; 684 break; 685 case ATW_RFTYPE_MARVEL: 686 break; 687 } 688 689 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 690 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 691 692 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 693 694 switch (sc->sc_bbptype) { 695 case ATW_BBPTYPE_INTERSIL: 696 reg |= ATW_BBPCTL_TWI; 697 break; 698 case ATW_BBPTYPE_RFMD: 699 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 700 ATW_BBPCTL_CCA_ACTLO; 701 break; 702 case ATW_BBPTYPE_MARVEL: 703 break; 704 case ATW_C_BBPTYPE_RFMD: 705 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 706 sc->sc_dev.dv_xname); 707 break; 708 } 709 710 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 711 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 712 713 /* 714 * From this point forward, the attachment cannot fail. A failure 715 * before this point releases all resources that may have been 716 * allocated. 717 */ 718 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 719 720 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 721 htole16(sc->sc_srom[ATW_SR_MAC00]), 722 htole16(sc->sc_srom[ATW_SR_MAC01]), 723 htole16(sc->sc_srom[ATW_SR_MAC10]))); 724 725 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 726 ATW_SR_MAJOR_MASK); 727 728 if (srom_major < 2) 729 sc->sc_rf3000_options1 = 0; 730 else if (sc->sc_rev == ATW_REVISION_BA) { 731 sc->sc_rf3000_options1 = 732 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 733 ATW_SR_CR28_MASK); 734 } else 735 sc->sc_rf3000_options1 = 0; 736 737 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 738 ATW_SR_CR29_MASK); 739 740 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 741 ATW_SR_CTRY_MASK); 742 743 #define ADD_CHANNEL(_ic, _chan) do { \ 744 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 745 _ic->ic_channels[_chan].ic_freq = \ 746 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 747 } while (0) 748 749 /* Find available channels */ 750 switch (country_code) { 751 case COUNTRY_MMK2: /* 1-14 */ 752 ADD_CHANNEL(ic, 14); 753 /*FALLTHROUGH*/ 754 case COUNTRY_ETSI: /* 1-13 */ 755 for (i = 1; i <= 13; i++) 756 ADD_CHANNEL(ic, i); 757 break; 758 case COUNTRY_FCC: /* 1-11 */ 759 case COUNTRY_IC: /* 1-11 */ 760 for (i = 1; i <= 11; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 case COUNTRY_MMK: /* 14 */ 764 ADD_CHANNEL(ic, 14); 765 break; 766 case COUNTRY_FRANCE: /* 10-13 */ 767 for (i = 10; i <= 13; i++) 768 ADD_CHANNEL(ic, i); 769 break; 770 default: /* assume channels 10-11 */ 771 case COUNTRY_SPAIN: /* 10-11 */ 772 for (i = 10; i <= 11; i++) 773 ADD_CHANNEL(ic, i); 774 break; 775 } 776 777 /* Read the MAC address. */ 778 reg = ATW_READ(sc, ATW_PAR0); 779 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 780 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 781 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 782 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 783 reg = ATW_READ(sc, ATW_PAR1); 784 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 785 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 786 787 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 788 printf(" could not get mac address, attach failed\n"); 789 return; 790 } 791 792 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 793 794 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 795 ifp->if_softc = sc; 796 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 797 IFF_NOTRAILERS; 798 ifp->if_ioctl = atw_ioctl; 799 ifp->if_start = atw_start; 800 ifp->if_watchdog = atw_watchdog; 801 ifp->if_init = atw_init; 802 ifp->if_stop = atw_stop; 803 IFQ_SET_READY(&ifp->if_snd); 804 805 ic->ic_ifp = ifp; 806 ic->ic_phytype = IEEE80211_T_DS; 807 ic->ic_opmode = IEEE80211_M_STA; 808 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 809 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 810 811 nrate = 0; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 813 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 814 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 815 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 816 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 817 818 /* 819 * Call MI attach routines. 820 */ 821 822 if_attach(ifp); 823 ieee80211_ifattach(ic); 824 825 sc->sc_newstate = ic->ic_newstate; 826 ic->ic_newstate = atw_newstate; 827 828 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 829 ic->ic_recv_mgmt = atw_recv_mgmt; 830 831 sc->sc_node_free = ic->ic_node_free; 832 ic->ic_node_free = atw_node_free; 833 834 sc->sc_node_alloc = ic->ic_node_alloc; 835 ic->ic_node_alloc = atw_node_alloc; 836 837 ic->ic_crypto.cs_key_alloc = atw_key_alloc; 838 ic->ic_crypto.cs_key_delete = atw_key_delete; 839 ic->ic_crypto.cs_key_set = atw_key_set; 840 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 841 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 842 843 /* possibly we should fill in our own sc_send_prresp, since 844 * the ADM8211 is probably sending probe responses in ad hoc 845 * mode. 846 */ 847 848 /* complete initialization */ 849 ieee80211_media_init(ic, atw_media_change, atw_media_status); 850 callout_init(&sc->sc_scan_ch); 851 852 #if NBPFILTER > 0 853 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 854 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 855 #endif 856 857 /* 858 * Make sure the interface is shutdown during reboot. 859 */ 860 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 861 if (sc->sc_sdhook == NULL) 862 printf("%s: WARNING: unable to establish shutdown hook\n", 863 sc->sc_dev.dv_xname); 864 865 /* 866 * Add a suspend hook to make sure we come back up after a 867 * resume. 868 */ 869 sc->sc_powerhook = powerhook_establish(atw_power, sc); 870 if (sc->sc_powerhook == NULL) 871 printf("%s: WARNING: unable to establish power hook\n", 872 sc->sc_dev.dv_xname); 873 874 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 875 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 876 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 877 878 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 879 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 880 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 881 882 return; 883 884 /* 885 * Free any resources we've allocated during the failed attach 886 * attempt. Do this in reverse order and fall through. 887 */ 888 fail_5: 889 for (i = 0; i < ATW_NRXDESC; i++) { 890 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 891 continue; 892 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 893 } 894 fail_4: 895 for (i = 0; i < ATW_TXQUEUELEN; i++) { 896 if (sc->sc_txsoft[i].txs_dmamap == NULL) 897 continue; 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 899 } 900 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 901 fail_3: 902 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 903 fail_2: 904 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 905 sizeof(struct atw_control_data)); 906 fail_1: 907 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 908 fail_0: 909 return; 910 } 911 912 static struct ieee80211_node * 913 atw_node_alloc(struct ieee80211_node_table *nt) 914 { 915 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 916 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 917 918 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 919 return ni; 920 } 921 922 static void 923 atw_node_free(struct ieee80211_node *ni) 924 { 925 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 926 927 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 928 ether_sprintf(ni->ni_bssid))); 929 (*sc->sc_node_free)(ni); 930 } 931 932 933 static void 934 atw_test1_reset(struct atw_softc *sc) 935 { 936 switch (sc->sc_rev) { 937 case ATW_REVISION_BA: 938 if (1 /* XXX condition on transceiver type */) { 939 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 940 } 941 break; 942 case ATW_REVISION_CA: 943 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 944 break; 945 default: 946 break; 947 } 948 } 949 950 /* 951 * atw_reset: 952 * 953 * Perform a soft reset on the ADM8211. 954 */ 955 void 956 atw_reset(struct atw_softc *sc) 957 { 958 int i; 959 uint32_t lpc; 960 961 ATW_WRITE(sc, ATW_NAR, 0x0); 962 DELAY(atw_nar_delay); 963 964 /* Reference driver has a cryptic remark indicating that this might 965 * power-on the chip. I know that it turns off power-saving.... 966 */ 967 ATW_WRITE(sc, ATW_FRCTL, 0x0); 968 969 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 970 971 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 972 if (ATW_READ(sc, ATW_PAR) == 0) 973 break; 974 DELAY(atw_pseudo_milli); 975 } 976 977 /* ... and then pause 100ms longer for good measure. */ 978 DELAY(atw_magic_delay1); 979 980 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 981 982 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 983 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 984 985 atw_test1_reset(sc); 986 /* 987 * Initialize the PCI Access Register. 988 */ 989 sc->sc_busmode = ATW_PAR_PBL_8DW; 990 991 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 992 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 993 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 994 995 /* Turn off maximum power saving, etc. 996 * 997 * XXX Following example of reference driver, should I set 998 * an AID of 1? It didn't seem to help.... 999 */ 1000 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1001 1002 DELAY(atw_magic_delay2); 1003 1004 /* Recall EEPROM. */ 1005 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1006 1007 DELAY(atw_magic_delay4); 1008 1009 lpc = ATW_READ(sc, ATW_LPC); 1010 1011 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1012 1013 /* A reset seems to affect the SRAM contents, so put them into 1014 * a known state. 1015 */ 1016 atw_clear_sram(sc); 1017 1018 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1019 } 1020 1021 static void 1022 atw_clear_sram(struct atw_softc *sc) 1023 { 1024 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1025 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1026 /* XXX not for revision 0x20. */ 1027 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1028 } 1029 1030 /* TBD atw_init 1031 * 1032 * set MAC based on ic->ic_bss->myaddr 1033 * write WEP keys 1034 * set TX rate 1035 */ 1036 1037 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1038 * without receiving a beacon with the preferred BSSID & SSID. 1039 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1040 */ 1041 static void 1042 atw_wcsr_init(struct atw_softc *sc) 1043 { 1044 uint32_t wcsr; 1045 1046 wcsr = ATW_READ(sc, ATW_WCSR); 1047 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1048 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1049 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1050 1051 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1052 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1053 } 1054 1055 /* Turn off power management. Set Rx store-and-forward mode. */ 1056 static void 1057 atw_cmdr_init(struct atw_softc *sc) 1058 { 1059 uint32_t cmdr; 1060 cmdr = ATW_READ(sc, ATW_CMDR); 1061 cmdr &= ~ATW_CMDR_APM; 1062 cmdr |= ATW_CMDR_RTE; 1063 cmdr &= ~ATW_CMDR_DRT_MASK; 1064 cmdr |= ATW_CMDR_DRT_SF; 1065 1066 ATW_WRITE(sc, ATW_CMDR, cmdr); 1067 } 1068 1069 static void 1070 atw_tofs2_init(struct atw_softc *sc) 1071 { 1072 uint32_t tofs2; 1073 /* XXX this magic can probably be figured out from the RFMD docs */ 1074 #ifndef ATW_REFSLAVE 1075 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1076 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1077 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1078 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1079 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1080 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1081 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1082 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1083 #else 1084 /* XXX new magic from reference driver source */ 1085 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1086 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1087 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1088 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1089 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1090 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1091 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1092 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1093 #endif 1094 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1095 } 1096 1097 static void 1098 atw_nar_init(struct atw_softc *sc) 1099 { 1100 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1101 } 1102 1103 static void 1104 atw_txlmt_init(struct atw_softc *sc) 1105 { 1106 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1107 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1108 } 1109 1110 static void 1111 atw_test1_init(struct atw_softc *sc) 1112 { 1113 uint32_t test1; 1114 1115 test1 = ATW_READ(sc, ATW_TEST1); 1116 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1117 /* XXX magic 0x1 */ 1118 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1119 ATW_WRITE(sc, ATW_TEST1, test1); 1120 } 1121 1122 static void 1123 atw_rf_reset(struct atw_softc *sc) 1124 { 1125 /* XXX this resets an Intersil RF front-end? */ 1126 /* TBD condition on Intersil RFType? */ 1127 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1128 DELAY(atw_rf_delay1); 1129 ATW_WRITE(sc, ATW_SYNRF, 0); 1130 DELAY(atw_rf_delay2); 1131 } 1132 1133 /* Set 16 TU max duration for the contention-free period (CFP). */ 1134 static void 1135 atw_cfp_init(struct atw_softc *sc) 1136 { 1137 uint32_t cfpp; 1138 1139 cfpp = ATW_READ(sc, ATW_CFPP); 1140 cfpp &= ~ATW_CFPP_CFPMD; 1141 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1142 ATW_WRITE(sc, ATW_CFPP, cfpp); 1143 } 1144 1145 static void 1146 atw_tofs0_init(struct atw_softc *sc) 1147 { 1148 /* XXX I guess that the Cardbus clock is 22MHz? 1149 * I am assuming that the role of ATW_TOFS0_USCNT is 1150 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1151 * very clear on this point. It says in the datasheet that it is 1152 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1153 * and 33MHz; maybe this is the way? I see a binary-only driver write 1154 * these values. These values are also the power-on default. 1155 */ 1156 ATW_WRITE(sc, ATW_TOFS0, 1157 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1158 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1159 } 1160 1161 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1162 static void 1163 atw_ifs_init(struct atw_softc *sc) 1164 { 1165 uint32_t ifst; 1166 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1167 * Go figure. 1168 */ 1169 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1170 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1171 ATW_IFST_SIFS_MASK) | 1172 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1173 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1174 1175 ATW_WRITE(sc, ATW_IFST, ifst); 1176 } 1177 1178 static void 1179 atw_response_times_init(struct atw_softc *sc) 1180 { 1181 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1182 * indicate that the MAC expects at least SIFS + MIRT microseconds 1183 * to pass after it transmits a frame that requires a response; 1184 * it waits at most SIFS + MART microseconds for the response. 1185 * Surely this is not the ACK timeout? 1186 */ 1187 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1188 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1189 } 1190 1191 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1192 * engines read and write baseband registers after Rx and before 1193 * Tx, respectively. 1194 */ 1195 static void 1196 atw_bbp_io_init(struct atw_softc *sc) 1197 { 1198 uint32_t mmiraddr2; 1199 1200 /* XXX The reference driver does this, but is it *really* 1201 * necessary? 1202 */ 1203 switch (sc->sc_rev) { 1204 case ATW_REVISION_AB: 1205 case ATW_REVISION_AF: 1206 mmiraddr2 = 0x0; 1207 break; 1208 default: 1209 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1210 mmiraddr2 &= 1211 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1212 break; 1213 } 1214 1215 switch (sc->sc_bbptype) { 1216 case ATW_BBPTYPE_INTERSIL: 1217 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1218 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1219 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1220 break; 1221 case ATW_BBPTYPE_MARVEL: 1222 /* TBD find out the Marvel settings. */ 1223 break; 1224 case ATW_BBPTYPE_RFMD: 1225 default: 1226 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1227 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1228 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1229 break; 1230 } 1231 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1232 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1233 } 1234 1235 /* 1236 * atw_init: [ ifnet interface function ] 1237 * 1238 * Initialize the interface. Must be called at splnet(). 1239 */ 1240 int 1241 atw_init(struct ifnet *ifp) 1242 { 1243 struct atw_softc *sc = ifp->if_softc; 1244 struct ieee80211com *ic = &sc->sc_ic; 1245 struct atw_txsoft *txs; 1246 struct atw_rxsoft *rxs; 1247 int i, error = 0; 1248 1249 if ((error = atw_enable(sc)) != 0) 1250 goto out; 1251 1252 /* 1253 * Cancel any pending I/O. This also resets. 1254 */ 1255 atw_stop(ifp, 0); 1256 1257 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1258 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1259 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1260 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1261 1262 atw_wcsr_init(sc); 1263 1264 atw_cmdr_init(sc); 1265 1266 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1267 * 1268 * XXX Set transmit power for ATIM, RTS, Beacon. 1269 */ 1270 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1271 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1272 1273 atw_tofs2_init(sc); 1274 1275 atw_nar_init(sc); 1276 1277 atw_txlmt_init(sc); 1278 1279 atw_test1_init(sc); 1280 1281 atw_rf_reset(sc); 1282 1283 atw_cfp_init(sc); 1284 1285 atw_tofs0_init(sc); 1286 1287 atw_ifs_init(sc); 1288 1289 /* XXX Fall asleep after one second of inactivity. 1290 * XXX A frame may only dribble in for 65536us. 1291 */ 1292 ATW_WRITE(sc, ATW_RMD, 1293 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1294 1295 atw_response_times_init(sc); 1296 1297 atw_bbp_io_init(sc); 1298 1299 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1300 1301 if ((error = atw_rf3000_init(sc)) != 0) 1302 goto out; 1303 1304 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1305 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1306 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1307 1308 /* 1309 * Initialize the transmit descriptor ring. 1310 */ 1311 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1312 for (i = 0; i < ATW_NTXDESC; i++) { 1313 sc->sc_txdescs[i].at_ctl = 0; 1314 /* no transmit chaining */ 1315 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1316 sc->sc_txdescs[i].at_buf2 = 1317 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1318 } 1319 /* use ring mode */ 1320 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1321 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1322 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1323 sc->sc_txfree = ATW_NTXDESC; 1324 sc->sc_txnext = 0; 1325 1326 /* 1327 * Initialize the transmit job descriptors. 1328 */ 1329 SIMPLEQ_INIT(&sc->sc_txfreeq); 1330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1331 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1332 txs = &sc->sc_txsoft[i]; 1333 txs->txs_mbuf = NULL; 1334 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1335 } 1336 1337 /* 1338 * Initialize the receive descriptor and receive job 1339 * descriptor rings. 1340 */ 1341 for (i = 0; i < ATW_NRXDESC; i++) { 1342 rxs = &sc->sc_rxsoft[i]; 1343 if (rxs->rxs_mbuf == NULL) { 1344 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1345 printf("%s: unable to allocate or map rx " 1346 "buffer %d, error = %d\n", 1347 sc->sc_dev.dv_xname, i, error); 1348 /* 1349 * XXX Should attempt to run with fewer receive 1350 * XXX buffers instead of just failing. 1351 */ 1352 atw_rxdrain(sc); 1353 goto out; 1354 } 1355 } else 1356 ATW_INIT_RXDESC(sc, i); 1357 } 1358 sc->sc_rxptr = 0; 1359 1360 /* 1361 * Initialize the interrupt mask and enable interrupts. 1362 */ 1363 /* normal interrupts */ 1364 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1365 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1366 1367 /* abnormal interrupts */ 1368 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1369 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1370 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1371 1372 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1373 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1374 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1375 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1376 ATW_INTR_TRT; 1377 1378 sc->sc_linkint_mask &= sc->sc_inten; 1379 sc->sc_rxint_mask &= sc->sc_inten; 1380 sc->sc_txint_mask &= sc->sc_inten; 1381 1382 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1383 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1384 1385 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1386 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1387 1388 /* 1389 * Give the transmit and receive rings to the ADM8211. 1390 */ 1391 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1392 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1393 1394 sc->sc_txthresh = 0; 1395 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1396 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1397 1398 /* common 802.11 configuration */ 1399 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1400 switch (ic->ic_opmode) { 1401 case IEEE80211_M_STA: 1402 break; 1403 case IEEE80211_M_AHDEMO: /* XXX */ 1404 case IEEE80211_M_IBSS: 1405 ic->ic_flags |= IEEE80211_F_IBSSON; 1406 /*FALLTHROUGH*/ 1407 case IEEE80211_M_HOSTAP: /* XXX */ 1408 break; 1409 case IEEE80211_M_MONITOR: /* XXX */ 1410 break; 1411 } 1412 1413 switch (ic->ic_opmode) { 1414 case IEEE80211_M_AHDEMO: 1415 case IEEE80211_M_HOSTAP: 1416 ic->ic_bss->ni_intval = ic->ic_lintval; 1417 ic->ic_bss->ni_rssi = 0; 1418 ic->ic_bss->ni_rstamp = 0; 1419 break; 1420 default: /* XXX */ 1421 break; 1422 } 1423 1424 sc->sc_wepctl = 0; 1425 1426 atw_write_ssid(sc); 1427 atw_write_sup_rates(sc); 1428 if (ic->ic_caps & IEEE80211_C_WEP) 1429 atw_write_wep(sc); 1430 1431 ic->ic_state = IEEE80211_S_INIT; 1432 1433 /* 1434 * Set the receive filter. This will start the transmit and 1435 * receive processes. 1436 */ 1437 atw_filter_setup(sc); 1438 1439 /* 1440 * Start the receive process. 1441 */ 1442 ATW_WRITE(sc, ATW_RDR, 0x1); 1443 1444 /* 1445 * Note that the interface is now running. 1446 */ 1447 ifp->if_flags |= IFF_RUNNING; 1448 ifp->if_flags &= ~IFF_OACTIVE; 1449 1450 /* send no beacons, yet. */ 1451 atw_start_beacon(sc, 0); 1452 1453 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1454 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1455 else 1456 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1457 out: 1458 if (error) { 1459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1460 ifp->if_timer = 0; 1461 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1462 } 1463 #ifdef ATW_DEBUG 1464 atw_print_regs(sc, "end of init"); 1465 #endif /* ATW_DEBUG */ 1466 1467 return (error); 1468 } 1469 1470 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1471 * 0: MAC control of RF3000/Si4126. 1472 * 1473 * Applies power, or selects RF front-end? Sets reset condition. 1474 * 1475 * TBD support non-RFMD BBP, non-SiLabs synth. 1476 */ 1477 static void 1478 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1479 { 1480 if (enable) { 1481 ATW_WRITE(sc, ATW_SYNRF, 1482 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1483 DELAY(atw_bbp_io_enable_delay); 1484 } else { 1485 ATW_WRITE(sc, ATW_SYNRF, 0); 1486 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1487 } 1488 } 1489 1490 static int 1491 atw_tune(struct atw_softc *sc) 1492 { 1493 int rc; 1494 u_int chan; 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 1497 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1498 if (chan == IEEE80211_CHAN_ANY) 1499 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1500 1501 if (chan == sc->sc_cur_chan) 1502 return 0; 1503 1504 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1505 sc->sc_cur_chan, chan)); 1506 1507 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1508 1509 atw_si4126_tune(sc, chan); 1510 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1511 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1512 chan); 1513 1514 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1515 DELAY(atw_nar_delay); 1516 ATW_WRITE(sc, ATW_RDR, 0x1); 1517 1518 if (rc == 0) 1519 sc->sc_cur_chan = chan; 1520 1521 return rc; 1522 } 1523 1524 #ifdef ATW_SYNDEBUG 1525 static void 1526 atw_si4126_print(struct atw_softc *sc) 1527 { 1528 struct ifnet *ifp = &sc->sc_if; 1529 u_int addr, val; 1530 1531 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1532 return; 1533 1534 for (addr = 0; addr <= 8; addr++) { 1535 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1536 if (atw_si4126_read(sc, addr, &val) == 0) { 1537 printf("<unknown> (quitting print-out)\n"); 1538 break; 1539 } 1540 printf("%05x\n", val); 1541 } 1542 } 1543 #endif /* ATW_SYNDEBUG */ 1544 1545 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1546 * 1547 * The RF/IF synthesizer produces two reference frequencies for 1548 * the RF2948B transceiver. The first frequency the RF2948B requires 1549 * is two times the so-called "intermediate frequency" (IF). Since 1550 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1551 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1552 * frequency required by the transceiver is the radio frequency 1553 * (RF). This is a superheterodyne transceiver; for f(chan) the 1554 * center frequency of the channel we are tuning, RF = f(chan) - 1555 * IF. 1556 * 1557 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1558 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1559 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1560 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1561 */ 1562 static void 1563 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1564 { 1565 u_int mhz; 1566 u_int R; 1567 u_int32_t gpio; 1568 u_int16_t gain; 1569 1570 #ifdef ATW_SYNDEBUG 1571 atw_si4126_print(sc); 1572 #endif /* ATW_SYNDEBUG */ 1573 1574 if (chan == 14) 1575 mhz = 2484; 1576 else 1577 mhz = 2412 + 5 * (chan - 1); 1578 1579 /* Tune IF to 748MHz to suit the IF LO input of the 1580 * RF2494B, which is 2 x IF. No need to set an IF divider 1581 * because an IF in 526MHz - 952MHz is allowed. 1582 * 1583 * XIN is 44.000MHz, so divide it by two to get allowable 1584 * range of 2-25MHz. SiLabs tells me that this is not 1585 * strictly necessary. 1586 */ 1587 1588 if (atw_xindiv2) 1589 R = 44; 1590 else 1591 R = 88; 1592 1593 /* Power-up RF, IF synthesizers. */ 1594 atw_si4126_write(sc, SI4126_POWER, 1595 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1596 1597 /* set LPWR, too? */ 1598 atw_si4126_write(sc, SI4126_MAIN, 1599 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1600 1601 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1602 * set KP2 to 1. 1603 * 1604 * REFDIF This is different from the reference driver, which 1605 * always sets SI4126_GAIN to 0. 1606 */ 1607 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1608 1609 atw_si4126_write(sc, SI4126_GAIN, gain); 1610 1611 /* XIN = 44MHz. 1612 * 1613 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1614 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1615 * 1616 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1617 * so that 1496/88 * 44MHz = 748MHz. 1618 */ 1619 atw_si4126_write(sc, SI4126_IFN, 1496); 1620 1621 atw_si4126_write(sc, SI4126_IFR, R); 1622 1623 #ifndef ATW_REFSLAVE 1624 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1625 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1626 * which has no RF1! 1627 */ 1628 atw_si4126_write(sc, SI4126_RF1R, R); 1629 1630 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1631 #endif 1632 1633 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1634 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1635 * Now let's multiply it to mhz. So mhz - IF = N. 1636 */ 1637 atw_si4126_write(sc, SI4126_RF2R, R); 1638 1639 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1640 1641 /* wait 100us from power-up for RF, IF to settle */ 1642 DELAY(100); 1643 1644 gpio = ATW_READ(sc, ATW_GPIO); 1645 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1646 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1647 1648 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1649 /* Set a Prism RF front-end to a special mode for channel 14? 1650 * 1651 * Apparently the SMC2635W needs this, although I don't think 1652 * it has a Prism RF. 1653 */ 1654 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1655 } 1656 ATW_WRITE(sc, ATW_GPIO, gpio); 1657 1658 #ifdef ATW_SYNDEBUG 1659 atw_si4126_print(sc); 1660 #endif /* ATW_SYNDEBUG */ 1661 } 1662 1663 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1664 * diversity. 1665 * 1666 * !!! 1667 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1668 * !!! 1669 */ 1670 static int 1671 atw_rf3000_init(struct atw_softc *sc) 1672 { 1673 int rc = 0; 1674 1675 atw_bbp_io_enable(sc, 1); 1676 1677 /* CCA is acquisition sensitive */ 1678 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1679 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1680 1681 if (rc != 0) 1682 goto out; 1683 1684 /* enable diversity */ 1685 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1686 1687 if (rc != 0) 1688 goto out; 1689 1690 /* sensible setting from a binary-only driver */ 1691 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1692 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1693 1694 if (rc != 0) 1695 goto out; 1696 1697 /* magic from a binary-only driver */ 1698 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1699 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1700 1701 if (rc != 0) 1702 goto out; 1703 1704 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1705 1706 if (rc != 0) 1707 goto out; 1708 1709 /* XXX Reference driver remarks that Abocom sets this to 50. 1710 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1711 * in the "reserved" area of register RF3000_OPTIONS1. 1712 */ 1713 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1714 1715 if (rc != 0) 1716 goto out; 1717 1718 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1719 1720 if (rc != 0) 1721 goto out; 1722 1723 out: 1724 atw_bbp_io_enable(sc, 0); 1725 return rc; 1726 } 1727 1728 #ifdef ATW_BBPDEBUG 1729 static void 1730 atw_rf3000_print(struct atw_softc *sc) 1731 { 1732 struct ifnet *ifp = &sc->sc_if; 1733 u_int addr, val; 1734 1735 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1736 return; 1737 1738 for (addr = 0x01; addr <= 0x15; addr++) { 1739 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1740 if (atw_rf3000_read(sc, addr, &val) != 0) { 1741 printf("<unknown> (quitting print-out)\n"); 1742 break; 1743 } 1744 printf("%08x\n", val); 1745 } 1746 } 1747 #endif /* ATW_BBPDEBUG */ 1748 1749 /* Set the power settings on the BBP for channel `chan'. */ 1750 static int 1751 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1752 { 1753 int rc = 0; 1754 u_int32_t reg; 1755 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1756 1757 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1758 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1759 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1760 1761 /* odd channels: LSB, even channels: MSB */ 1762 if (chan % 2 == 1) { 1763 txpower &= 0xFF; 1764 lpf_cutoff &= 0xFF; 1765 lna_gs_thresh &= 0xFF; 1766 } else { 1767 txpower >>= 8; 1768 lpf_cutoff >>= 8; 1769 lna_gs_thresh >>= 8; 1770 } 1771 1772 #ifdef ATW_BBPDEBUG 1773 atw_rf3000_print(sc); 1774 #endif /* ATW_BBPDEBUG */ 1775 1776 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1777 "lna_gs_thresh %02x\n", 1778 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1779 1780 atw_bbp_io_enable(sc, 1); 1781 1782 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1783 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1784 goto out; 1785 1786 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1787 goto out; 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1790 goto out; 1791 1792 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1793 1794 if (rc != 0) 1795 goto out; 1796 1797 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1798 1799 if (rc != 0) 1800 goto out; 1801 1802 #ifdef ATW_BBPDEBUG 1803 atw_rf3000_print(sc); 1804 #endif /* ATW_BBPDEBUG */ 1805 1806 out: 1807 atw_bbp_io_enable(sc, 0); 1808 1809 /* set beacon, rts, atim transmit power */ 1810 reg = ATW_READ(sc, ATW_PLCPHD); 1811 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1812 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1813 ATW_PLCPHD_SERVICE_MASK); 1814 ATW_WRITE(sc, ATW_PLCPHD, reg); 1815 DELAY(atw_plcphd_delay); 1816 1817 return rc; 1818 } 1819 1820 /* Write a register on the RF3000 baseband processor using the 1821 * registers provided by the ADM8211 for this purpose. 1822 * 1823 * Return 0 on success. 1824 */ 1825 static int 1826 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1827 { 1828 u_int32_t reg; 1829 int i; 1830 1831 reg = sc->sc_bbpctl_wr | 1832 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1833 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1834 1835 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1836 ATW_WRITE(sc, ATW_BBPCTL, reg); 1837 DELAY(2 * atw_pseudo_milli); 1838 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1839 break; 1840 } 1841 1842 if (i < 0) { 1843 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1844 return ETIMEDOUT; 1845 } 1846 return 0; 1847 } 1848 1849 /* Read a register on the RF3000 baseband processor using the registers 1850 * the ADM8211 provides for this purpose. 1851 * 1852 * The 7-bit register address is addr. Record the 8-bit data in the register 1853 * in *val. 1854 * 1855 * Return 0 on success. 1856 * 1857 * XXX This does not seem to work. The ADM8211 must require more or 1858 * different magic to read the chip than to write it. Possibly some 1859 * of the magic I have derived from a binary-only driver concerns 1860 * the "chip address" (see the RF3000 manual). 1861 */ 1862 #ifdef ATW_BBPDEBUG 1863 static int 1864 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1865 { 1866 u_int32_t reg; 1867 int i; 1868 1869 for (i = 1000; --i >= 0; ) { 1870 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1871 break; 1872 DELAY(100); 1873 } 1874 1875 if (i < 0) { 1876 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1877 sc->sc_dev.dv_xname); 1878 return ETIMEDOUT; 1879 } 1880 1881 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1882 1883 ATW_WRITE(sc, ATW_BBPCTL, reg); 1884 1885 for (i = 1000; --i >= 0; ) { 1886 DELAY(100); 1887 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1888 break; 1889 } 1890 1891 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1892 1893 if (i < 0) { 1894 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1895 sc->sc_dev.dv_xname, reg); 1896 return ETIMEDOUT; 1897 } 1898 if (val != NULL) 1899 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1900 return 0; 1901 } 1902 #endif /* ATW_BBPDEBUG */ 1903 1904 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1905 * provided by the ADM8211 for that purpose. 1906 * 1907 * val is 18 bits of data, and val is the 4-bit address of the register. 1908 * 1909 * Return 0 on success. 1910 */ 1911 static void 1912 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1913 { 1914 uint32_t bits, mask, reg; 1915 const int nbits = 22; 1916 1917 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1918 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1919 1920 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1921 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1922 1923 reg = ATW_SYNRF_SELSYN; 1924 /* reference driver: reset Si4126 serial bus to initial 1925 * conditions? 1926 */ 1927 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1928 ATW_WRITE(sc, ATW_SYNRF, reg); 1929 1930 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1931 if ((bits & mask) != 0) 1932 reg |= ATW_SYNRF_SYNDATA; 1933 else 1934 reg &= ~ATW_SYNRF_SYNDATA; 1935 ATW_WRITE(sc, ATW_SYNRF, reg); 1936 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1937 ATW_WRITE(sc, ATW_SYNRF, reg); 1938 } 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1940 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1941 } 1942 1943 /* Read 18-bit data from the 4-bit address addr in Si4126 1944 * RF synthesizer and write the data to *val. Return 0 on success. 1945 * 1946 * XXX This does not seem to work. The ADM8211 must require more or 1947 * different magic to read the chip than to write it. 1948 */ 1949 #ifdef ATW_SYNDEBUG 1950 static int 1951 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1952 { 1953 u_int32_t reg; 1954 int i; 1955 1956 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1957 1958 for (i = 1000; --i >= 0; ) { 1959 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1960 break; 1961 DELAY(100); 1962 } 1963 1964 if (i < 0) { 1965 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1966 sc->sc_dev.dv_xname); 1967 return ETIMEDOUT; 1968 } 1969 1970 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1971 1972 ATW_WRITE(sc, ATW_SYNCTL, reg); 1973 1974 for (i = 1000; --i >= 0; ) { 1975 DELAY(100); 1976 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1977 break; 1978 } 1979 1980 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1981 1982 if (i < 0) { 1983 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1984 sc->sc_dev.dv_xname, reg); 1985 return ETIMEDOUT; 1986 } 1987 if (val != NULL) 1988 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1989 ATW_SYNCTL_DATA_MASK); 1990 return 0; 1991 } 1992 #endif /* ATW_SYNDEBUG */ 1993 1994 /* XXX is the endianness correct? test. */ 1995 #define atw_calchash(addr) \ 1996 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1997 1998 /* 1999 * atw_filter_setup: 2000 * 2001 * Set the ADM8211's receive filter. 2002 */ 2003 static void 2004 atw_filter_setup(struct atw_softc *sc) 2005 { 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 struct ethercom *ec = &sc->sc_ec; 2008 struct ifnet *ifp = &sc->sc_if; 2009 int hash; 2010 u_int32_t hashes[2]; 2011 struct ether_multi *enm; 2012 struct ether_multistep step; 2013 2014 /* According to comments in tlp_al981_filter_setup 2015 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2016 * multicast filter to be set while it is running. Hopefully 2017 * the ADM8211 is not the same! 2018 */ 2019 if ((ifp->if_flags & IFF_RUNNING) != 0) 2020 atw_idle(sc, ATW_NAR_SR); 2021 2022 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2023 2024 /* XXX in scan mode, do not filter packets. Maybe this is 2025 * unnecessary. 2026 */ 2027 if (ic->ic_state == IEEE80211_S_SCAN || 2028 (ifp->if_flags & IFF_PROMISC) != 0) { 2029 sc->sc_opmode |= ATW_NAR_PR; 2030 goto allmulti; 2031 } 2032 2033 hashes[0] = hashes[1] = 0x0; 2034 2035 /* 2036 * Program the 64-bit multicast hash filter. 2037 */ 2038 ETHER_FIRST_MULTI(step, ec, enm); 2039 while (enm != NULL) { 2040 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2041 ETHER_ADDR_LEN) != 0) 2042 goto allmulti; 2043 2044 hash = atw_calchash(enm->enm_addrlo); 2045 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2046 ETHER_NEXT_MULTI(step, enm); 2047 sc->sc_opmode |= ATW_NAR_MM; 2048 } 2049 ifp->if_flags &= ~IFF_ALLMULTI; 2050 goto setit; 2051 2052 allmulti: 2053 sc->sc_opmode |= ATW_NAR_MM; 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = 0xffffffff; 2056 2057 setit: 2058 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2059 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2060 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2061 DELAY(atw_nar_delay); 2062 2063 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2064 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2065 } 2066 2067 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2068 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2069 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2070 * no beacon with the preferred BSSID and SSID in the number of 2071 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2072 */ 2073 static void 2074 atw_write_bssid(struct atw_softc *sc) 2075 { 2076 struct ieee80211com *ic = &sc->sc_ic; 2077 u_int8_t *bssid; 2078 2079 bssid = ic->ic_bss->ni_bssid; 2080 2081 ATW_WRITE(sc, ATW_BSSID0, 2082 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2083 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2084 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2085 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2086 2087 ATW_WRITE(sc, ATW_ABDA1, 2088 (ATW_READ(sc, ATW_ABDA1) & 2089 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2090 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2091 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2092 2093 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2094 ether_sprintf(sc->sc_bssid))); 2095 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2096 2097 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2098 } 2099 2100 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2101 * 16-bit word. 2102 */ 2103 static void 2104 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2105 { 2106 u_int i; 2107 u_int8_t *ptr; 2108 2109 memcpy(&sc->sc_sram[ofs], buf, buflen); 2110 2111 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2112 2113 KASSERT(buflen + ofs <= sc->sc_sramlen); 2114 2115 ptr = &sc->sc_sram[ofs]; 2116 2117 for (i = 0; i < buflen; i += 2) { 2118 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2119 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2120 DELAY(atw_writewep_delay); 2121 2122 ATW_WRITE(sc, ATW_WESK, 2123 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2124 DELAY(atw_writewep_delay); 2125 } 2126 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2127 2128 if (sc->sc_if.if_flags & IFF_DEBUG) { 2129 int n_octets = 0; 2130 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2131 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2132 for (i = 0; i < buflen; i++) { 2133 printf(" %02x", ptr[i]); 2134 if (++n_octets % 24 == 0) 2135 printf("\n"); 2136 } 2137 if (n_octets % 24 != 0) 2138 printf("\n"); 2139 } 2140 } 2141 2142 static int 2143 atw_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k) 2144 { 2145 int keyix; 2146 #ifdef ATW_DEBUG 2147 struct atw_softc *sc = ic->ic_ifp->if_softc; 2148 #endif 2149 2150 if (&ic->ic_nw_keys[0] <= k && 2151 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID]) 2152 keyix = k - ic->ic_nw_keys; 2153 else 2154 keyix = IEEE80211_KEYIX_NONE; 2155 2156 DPRINTF(sc, ("%s: alloc key %u\n", __func__, keyix)); 2157 2158 return keyix; 2159 } 2160 2161 static int 2162 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2163 { 2164 struct atw_softc *sc = ic->ic_ifp->if_softc; 2165 u_int keyix = k->wk_keyix; 2166 2167 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2168 2169 if (keyix >= IEEE80211_WEP_NKID) 2170 return 0; 2171 if (k->wk_keylen != 0) 2172 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2173 2174 return 1; 2175 } 2176 2177 static int 2178 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2179 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2180 { 2181 struct atw_softc *sc = ic->ic_ifp->if_softc; 2182 2183 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2184 2185 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2186 return 0; 2187 2188 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2189 2190 return 1; 2191 } 2192 2193 static void 2194 atw_key_update_begin(struct ieee80211com *ic) 2195 { 2196 #ifdef ATW_DEBUG 2197 struct ifnet *ifp = ic->ic_ifp; 2198 struct atw_softc *sc = ifp->if_softc; 2199 #endif 2200 2201 DPRINTF(sc, ("%s:\n", __func__)); 2202 } 2203 2204 static void 2205 atw_key_update_end(struct ieee80211com *ic) 2206 { 2207 struct ifnet *ifp = ic->ic_ifp; 2208 struct atw_softc *sc = ifp->if_softc; 2209 2210 DPRINTF(sc, ("%s:\n", __func__)); 2211 2212 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2213 return; 2214 atw_write_wep(sc); 2215 } 2216 2217 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2218 static void 2219 atw_write_wep(struct atw_softc *sc) 2220 { 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2223 u_int8_t buf[IEEE80211_WEP_NKID] 2224 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2225 u_int32_t reg; 2226 int i; 2227 2228 sc->sc_wepctl = 0; 2229 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2230 2231 memset(&buf[0][0], 0, sizeof(buf)); 2232 2233 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2234 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2235 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2236 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2237 buf[i][1] = ATW_WEP_ENABLED; 2238 } else { 2239 buf[i][1] = 0; 2240 continue; 2241 } 2242 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2243 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2244 ic->ic_nw_keys[i].wk_keylen - 1); 2245 } 2246 2247 reg = ATW_READ(sc, ATW_MACTEST); 2248 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2249 reg &= ~ATW_MACTEST_KEYID_MASK; 2250 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2251 ATW_WRITE(sc, ATW_MACTEST, reg); 2252 2253 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2254 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2255 2256 switch (sc->sc_rev) { 2257 case ATW_REVISION_AB: 2258 case ATW_REVISION_AF: 2259 /* Bypass WEP on Rx. */ 2260 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2261 break; 2262 default: 2263 break; 2264 } 2265 2266 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2267 sizeof(buf)); 2268 2269 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2270 } 2271 2272 static void 2273 atw_change_ibss(struct atw_softc *sc) 2274 { 2275 atw_predict_beacon(sc); 2276 atw_write_bssid(sc); 2277 atw_start_beacon(sc, 1); 2278 } 2279 2280 static void 2281 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2282 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2283 { 2284 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2285 2286 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2287 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2288 return; 2289 2290 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2291 2292 switch (subtype) { 2293 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2294 case IEEE80211_FC0_SUBTYPE_BEACON: 2295 if (ic->ic_opmode != IEEE80211_M_IBSS || 2296 ic->ic_state != IEEE80211_S_RUN) 2297 break; 2298 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc) && 2299 ieee80211_ibss_merge(ic, ni) == ENETRESET) 2300 atw_change_ibss(sc); 2301 break; 2302 default: 2303 break; 2304 } 2305 return; 2306 } 2307 2308 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2309 * In ad hoc mode, the SSID is written to the beacons sent by the 2310 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2311 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2312 * indications. 2313 */ 2314 static void 2315 atw_write_ssid(struct atw_softc *sc) 2316 { 2317 struct ieee80211com *ic = &sc->sc_ic; 2318 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2319 * it only expects the element length, not its ID. 2320 */ 2321 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2322 2323 memset(buf, 0, sizeof(buf)); 2324 buf[0] = ic->ic_bss->ni_esslen; 2325 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2326 2327 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2328 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2329 } 2330 2331 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2332 * In ad hoc mode, the supported rates are written to beacons sent by the 2333 * ADM8211. 2334 */ 2335 static void 2336 atw_write_sup_rates(struct atw_softc *sc) 2337 { 2338 struct ieee80211com *ic = &sc->sc_ic; 2339 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2340 * supported rates 2341 */ 2342 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2343 2344 memset(buf, 0, sizeof(buf)); 2345 2346 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2347 2348 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2349 ic->ic_bss->ni_rates.rs_nrates); 2350 2351 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2352 } 2353 2354 /* Start/stop sending beacons. */ 2355 void 2356 atw_start_beacon(struct atw_softc *sc, int start) 2357 { 2358 struct ieee80211com *ic = &sc->sc_ic; 2359 uint16_t chan; 2360 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2361 size_t len; 2362 2363 if (ATW_IS_ENABLED(sc) == 0) 2364 return; 2365 2366 /* start beacons */ 2367 len = sizeof(struct ieee80211_frame) + 2368 8 /* timestamp */ + 2 /* beacon interval */ + 2369 2 /* capability info */ + 2370 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2371 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2372 3 /* DS parameters */ + 2373 IEEE80211_CRC_LEN; 2374 2375 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2376 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2377 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2378 2379 ATW_WRITE(sc, ATW_BCNT, bcnt); 2380 ATW_WRITE(sc, ATW_CAP1, cap1); 2381 2382 if (!start) 2383 return; 2384 2385 /* TBD use ni_capinfo */ 2386 2387 capinfo = 0; 2388 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2389 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2390 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2391 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2392 2393 switch (ic->ic_opmode) { 2394 case IEEE80211_M_IBSS: 2395 len += 4; /* IBSS parameters */ 2396 capinfo |= IEEE80211_CAPINFO_IBSS; 2397 break; 2398 case IEEE80211_M_HOSTAP: 2399 /* XXX 6-byte minimum TIM */ 2400 len += atw_beacon_len_adjust; 2401 capinfo |= IEEE80211_CAPINFO_ESS; 2402 break; 2403 default: 2404 return; 2405 } 2406 2407 /* set listen interval 2408 * XXX do software units agree w/ hardware? 2409 */ 2410 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2411 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2412 2413 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2414 2415 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2416 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2417 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2418 2419 ATW_WRITE(sc, ATW_BCNT, bcnt); 2420 ATW_WRITE(sc, ATW_BPLI, bpli); 2421 ATW_WRITE(sc, ATW_CAP0, cap0); 2422 ATW_WRITE(sc, ATW_CAP1, cap1); 2423 2424 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2425 sc->sc_dev.dv_xname, bcnt)); 2426 2427 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2428 sc->sc_dev.dv_xname, cap1)); 2429 } 2430 2431 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2432 static __inline uint32_t 2433 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2434 { 2435 /* Following the reference driver's lead, I compute 2436 * 2437 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2438 * 2439 * without using 64-bit arithmetic, using the following 2440 * relationship: 2441 * 2442 * (0x100000000 * H + L) % m 2443 * = ((0x100000000 % m) * H + L) % m 2444 * = (((0xffffffff + 1) % m) * H + L) % m 2445 * = ((0xffffffff % m + 1 % m) * H + L) % m 2446 * = ((0xffffffff % m + 1) * H + L) % m 2447 */ 2448 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2449 } 2450 2451 static uint64_t 2452 atw_get_tsft(struct atw_softc *sc) 2453 { 2454 int i; 2455 uint32_t tsfth, tsftl; 2456 for (i = 0; i < 2; i++) { 2457 tsfth = ATW_READ(sc, ATW_TSFTH); 2458 tsftl = ATW_READ(sc, ATW_TSFTL); 2459 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2460 break; 2461 } 2462 return ((uint64_t)tsfth << 32) | tsftl; 2463 } 2464 2465 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2466 * the ieee80211com. 2467 * 2468 * Predict the next target beacon transmission time (TBTT) and 2469 * write it to the ADM8211. 2470 */ 2471 static void 2472 atw_predict_beacon(struct atw_softc *sc) 2473 { 2474 #define TBTTOFS 20 /* TU */ 2475 2476 struct ieee80211com *ic = &sc->sc_ic; 2477 uint64_t tsft; 2478 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2479 union { 2480 uint64_t word; 2481 uint8_t tstamp[8]; 2482 } u; 2483 2484 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2485 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2486 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2487 tsft = atw_get_tsft(sc); 2488 u.word = htole64(tsft); 2489 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2490 sizeof(ic->ic_bss->ni_tstamp)); 2491 } else 2492 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2493 2494 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2495 2496 tsftl = tsft & 0xFFFFFFFF; 2497 tsfth = tsft >> 32; 2498 2499 /* We sent/received the last beacon `past' microseconds 2500 * after the interval divided the TSF timer. 2501 */ 2502 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2503 2504 /* Skip ten beacons so that the TBTT cannot pass before 2505 * we've programmed it. Ten is an arbitrary number. 2506 */ 2507 tbtt = past_even + ival * 10; 2508 2509 ATW_WRITE(sc, ATW_TOFS1, 2510 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2511 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2512 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2513 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2514 #undef TBTTOFS 2515 } 2516 2517 static void 2518 atw_next_scan(void *arg) 2519 { 2520 struct atw_softc *sc = arg; 2521 struct ieee80211com *ic = &sc->sc_ic; 2522 int s; 2523 2524 /* don't call atw_start w/o network interrupts blocked */ 2525 s = splnet(); 2526 if (ic->ic_state == IEEE80211_S_SCAN) 2527 ieee80211_next_scan(ic); 2528 splx(s); 2529 } 2530 2531 /* Synchronize the hardware state with the software state. */ 2532 static int 2533 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2534 { 2535 struct ifnet *ifp = ic->ic_ifp; 2536 struct atw_softc *sc = ifp->if_softc; 2537 enum ieee80211_state ostate; 2538 int error; 2539 2540 ostate = ic->ic_state; 2541 2542 if (nstate == IEEE80211_S_INIT) { 2543 callout_stop(&sc->sc_scan_ch); 2544 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2545 atw_start_beacon(sc, 0); 2546 return (*sc->sc_newstate)(ic, nstate, arg); 2547 } 2548 2549 if ((error = atw_tune(sc)) != 0) 2550 return error; 2551 2552 switch (nstate) { 2553 case IEEE80211_S_ASSOC: 2554 break; 2555 case IEEE80211_S_INIT: 2556 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2557 break; 2558 case IEEE80211_S_SCAN: 2559 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2560 atw_next_scan, sc); 2561 2562 break; 2563 case IEEE80211_S_RUN: 2564 if (ic->ic_opmode == IEEE80211_M_STA) 2565 break; 2566 /*FALLTHROUGH*/ 2567 case IEEE80211_S_AUTH: 2568 atw_write_bssid(sc); 2569 atw_write_ssid(sc); 2570 atw_write_sup_rates(sc); 2571 2572 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2573 ic->ic_opmode == IEEE80211_M_MONITOR) 2574 break; 2575 2576 /* set listen interval 2577 * XXX do software units agree w/ hardware? 2578 */ 2579 ATW_WRITE(sc, ATW_BPLI, 2580 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2581 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2582 ATW_BPLI_LI_MASK)); 2583 2584 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2585 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2586 2587 atw_predict_beacon(sc); 2588 break; 2589 } 2590 2591 if (nstate != IEEE80211_S_SCAN) 2592 callout_stop(&sc->sc_scan_ch); 2593 2594 if (nstate == IEEE80211_S_RUN && 2595 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2596 ic->ic_opmode == IEEE80211_M_IBSS)) 2597 atw_start_beacon(sc, 1); 2598 else 2599 atw_start_beacon(sc, 0); 2600 2601 error = (*sc->sc_newstate)(ic, nstate, arg); 2602 2603 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2604 atw_write_bssid(sc); 2605 2606 return error; 2607 } 2608 2609 /* 2610 * atw_add_rxbuf: 2611 * 2612 * Add a receive buffer to the indicated descriptor. 2613 */ 2614 int 2615 atw_add_rxbuf(struct atw_softc *sc, int idx) 2616 { 2617 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2618 struct mbuf *m; 2619 int error; 2620 2621 MGETHDR(m, M_DONTWAIT, MT_DATA); 2622 if (m == NULL) 2623 return (ENOBUFS); 2624 2625 MCLGET(m, M_DONTWAIT); 2626 if ((m->m_flags & M_EXT) == 0) { 2627 m_freem(m); 2628 return (ENOBUFS); 2629 } 2630 2631 if (rxs->rxs_mbuf != NULL) 2632 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2633 2634 rxs->rxs_mbuf = m; 2635 2636 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2637 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2638 BUS_DMA_READ|BUS_DMA_NOWAIT); 2639 if (error) { 2640 printf("%s: can't load rx DMA map %d, error = %d\n", 2641 sc->sc_dev.dv_xname, idx, error); 2642 panic("atw_add_rxbuf"); /* XXX */ 2643 } 2644 2645 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2646 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2647 2648 ATW_INIT_RXDESC(sc, idx); 2649 2650 return (0); 2651 } 2652 2653 /* 2654 * Release any queued transmit buffers. 2655 */ 2656 void 2657 atw_txdrain(struct atw_softc *sc) 2658 { 2659 struct atw_txsoft *txs; 2660 2661 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2662 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2663 if (txs->txs_mbuf != NULL) { 2664 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2665 m_freem(txs->txs_mbuf); 2666 txs->txs_mbuf = NULL; 2667 } 2668 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2669 } 2670 sc->sc_tx_timer = 0; 2671 } 2672 2673 /* 2674 * atw_stop: [ ifnet interface function ] 2675 * 2676 * Stop transmission on the interface. 2677 */ 2678 void 2679 atw_stop(struct ifnet *ifp, int disable) 2680 { 2681 struct atw_softc *sc = ifp->if_softc; 2682 struct ieee80211com *ic = &sc->sc_ic; 2683 2684 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2685 2686 /* Disable interrupts. */ 2687 ATW_WRITE(sc, ATW_IER, 0); 2688 2689 /* Stop the transmit and receive processes. */ 2690 sc->sc_opmode = 0; 2691 ATW_WRITE(sc, ATW_NAR, 0); 2692 DELAY(atw_nar_delay); 2693 ATW_WRITE(sc, ATW_TDBD, 0); 2694 ATW_WRITE(sc, ATW_TDBP, 0); 2695 ATW_WRITE(sc, ATW_RDB, 0); 2696 2697 atw_txdrain(sc); 2698 2699 if (disable) { 2700 atw_rxdrain(sc); 2701 atw_disable(sc); 2702 } 2703 2704 /* 2705 * Mark the interface down and cancel the watchdog timer. 2706 */ 2707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2708 ifp->if_timer = 0; 2709 2710 if (!disable) 2711 atw_reset(sc); 2712 } 2713 2714 /* 2715 * atw_rxdrain: 2716 * 2717 * Drain the receive queue. 2718 */ 2719 void 2720 atw_rxdrain(struct atw_softc *sc) 2721 { 2722 struct atw_rxsoft *rxs; 2723 int i; 2724 2725 for (i = 0; i < ATW_NRXDESC; i++) { 2726 rxs = &sc->sc_rxsoft[i]; 2727 if (rxs->rxs_mbuf == NULL) 2728 continue; 2729 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2730 m_freem(rxs->rxs_mbuf); 2731 rxs->rxs_mbuf = NULL; 2732 } 2733 } 2734 2735 /* 2736 * atw_detach: 2737 * 2738 * Detach an ADM8211 interface. 2739 */ 2740 int 2741 atw_detach(struct atw_softc *sc) 2742 { 2743 struct ifnet *ifp = &sc->sc_if; 2744 struct atw_rxsoft *rxs; 2745 struct atw_txsoft *txs; 2746 int i; 2747 2748 /* 2749 * Succeed now if there isn't any work to do. 2750 */ 2751 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2752 return (0); 2753 2754 callout_stop(&sc->sc_scan_ch); 2755 2756 ieee80211_ifdetach(&sc->sc_ic); 2757 if_detach(ifp); 2758 2759 for (i = 0; i < ATW_NRXDESC; i++) { 2760 rxs = &sc->sc_rxsoft[i]; 2761 if (rxs->rxs_mbuf != NULL) { 2762 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2763 m_freem(rxs->rxs_mbuf); 2764 rxs->rxs_mbuf = NULL; 2765 } 2766 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2767 } 2768 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2769 txs = &sc->sc_txsoft[i]; 2770 if (txs->txs_mbuf != NULL) { 2771 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2772 m_freem(txs->txs_mbuf); 2773 txs->txs_mbuf = NULL; 2774 } 2775 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2776 } 2777 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2778 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2779 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2780 sizeof(struct atw_control_data)); 2781 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2782 2783 shutdownhook_disestablish(sc->sc_sdhook); 2784 powerhook_disestablish(sc->sc_powerhook); 2785 2786 if (sc->sc_srom) 2787 free(sc->sc_srom, M_DEVBUF); 2788 2789 return (0); 2790 } 2791 2792 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2793 void 2794 atw_shutdown(void *arg) 2795 { 2796 struct atw_softc *sc = arg; 2797 2798 atw_stop(&sc->sc_if, 1); 2799 } 2800 2801 int 2802 atw_intr(void *arg) 2803 { 2804 struct atw_softc *sc = arg; 2805 struct ifnet *ifp = &sc->sc_if; 2806 u_int32_t status, rxstatus, txstatus, linkstatus; 2807 int handled = 0, txthresh; 2808 2809 #ifdef DEBUG 2810 if (ATW_IS_ENABLED(sc) == 0) 2811 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2812 #endif 2813 2814 /* 2815 * If the interface isn't running, the interrupt couldn't 2816 * possibly have come from us. 2817 */ 2818 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2819 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2820 return (0); 2821 2822 for (;;) { 2823 status = ATW_READ(sc, ATW_STSR); 2824 2825 if (status) 2826 ATW_WRITE(sc, ATW_STSR, status); 2827 2828 #ifdef ATW_DEBUG 2829 #define PRINTINTR(flag) do { \ 2830 if ((status & flag) != 0) { \ 2831 printf("%s" #flag, delim); \ 2832 delim = ","; \ 2833 } \ 2834 } while (0) 2835 2836 if (atw_debug > 1 && status) { 2837 const char *delim = "<"; 2838 2839 printf("%s: reg[STSR] = %x", 2840 sc->sc_dev.dv_xname, status); 2841 2842 PRINTINTR(ATW_INTR_FBE); 2843 PRINTINTR(ATW_INTR_LINKOFF); 2844 PRINTINTR(ATW_INTR_LINKON); 2845 PRINTINTR(ATW_INTR_RCI); 2846 PRINTINTR(ATW_INTR_RDU); 2847 PRINTINTR(ATW_INTR_REIS); 2848 PRINTINTR(ATW_INTR_RPS); 2849 PRINTINTR(ATW_INTR_TCI); 2850 PRINTINTR(ATW_INTR_TDU); 2851 PRINTINTR(ATW_INTR_TLT); 2852 PRINTINTR(ATW_INTR_TPS); 2853 PRINTINTR(ATW_INTR_TRT); 2854 PRINTINTR(ATW_INTR_TUF); 2855 PRINTINTR(ATW_INTR_BCNTC); 2856 PRINTINTR(ATW_INTR_ATIME); 2857 PRINTINTR(ATW_INTR_TBTT); 2858 PRINTINTR(ATW_INTR_TSCZ); 2859 PRINTINTR(ATW_INTR_TSFTF); 2860 printf(">\n"); 2861 } 2862 #undef PRINTINTR 2863 #endif /* ATW_DEBUG */ 2864 2865 if ((status & sc->sc_inten) == 0) 2866 break; 2867 2868 handled = 1; 2869 2870 rxstatus = status & sc->sc_rxint_mask; 2871 txstatus = status & sc->sc_txint_mask; 2872 linkstatus = status & sc->sc_linkint_mask; 2873 2874 if (linkstatus) { 2875 atw_linkintr(sc, linkstatus); 2876 } 2877 2878 if (rxstatus) { 2879 /* Grab any new packets. */ 2880 atw_rxintr(sc); 2881 2882 if (rxstatus & ATW_INTR_RDU) { 2883 printf("%s: receive ring overrun\n", 2884 sc->sc_dev.dv_xname); 2885 /* Get the receive process going again. */ 2886 ATW_WRITE(sc, ATW_RDR, 0x1); 2887 break; 2888 } 2889 } 2890 2891 if (txstatus) { 2892 /* Sweep up transmit descriptors. */ 2893 atw_txintr(sc); 2894 2895 if (txstatus & ATW_INTR_TLT) 2896 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2897 sc->sc_dev.dv_xname)); 2898 2899 if (txstatus & ATW_INTR_TRT) 2900 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2901 sc->sc_dev.dv_xname)); 2902 2903 /* If Tx under-run, increase our transmit threshold 2904 * if another is available. 2905 */ 2906 txthresh = sc->sc_txthresh + 1; 2907 if ((txstatus & ATW_INTR_TUF) && 2908 sc->sc_txth[txthresh].txth_name != NULL) { 2909 /* Idle the transmit process. */ 2910 atw_idle(sc, ATW_NAR_ST); 2911 2912 sc->sc_txthresh = txthresh; 2913 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2914 sc->sc_opmode |= 2915 sc->sc_txth[txthresh].txth_opmode; 2916 printf("%s: transmit underrun; new " 2917 "threshold: %s\n", sc->sc_dev.dv_xname, 2918 sc->sc_txth[txthresh].txth_name); 2919 2920 /* Set the new threshold and restart 2921 * the transmit process. 2922 */ 2923 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2924 DELAY(atw_nar_delay); 2925 ATW_WRITE(sc, ATW_RDR, 0x1); 2926 /* XXX Log every Nth underrun from 2927 * XXX now on? 2928 */ 2929 } 2930 } 2931 2932 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2933 if (status & ATW_INTR_TPS) 2934 printf("%s: transmit process stopped\n", 2935 sc->sc_dev.dv_xname); 2936 if (status & ATW_INTR_RPS) 2937 printf("%s: receive process stopped\n", 2938 sc->sc_dev.dv_xname); 2939 (void)atw_init(ifp); 2940 break; 2941 } 2942 2943 if (status & ATW_INTR_FBE) { 2944 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2945 (void)atw_init(ifp); 2946 break; 2947 } 2948 2949 /* 2950 * Not handled: 2951 * 2952 * Transmit buffer unavailable -- normal 2953 * condition, nothing to do, really. 2954 * 2955 * Early receive interrupt -- not available on 2956 * all chips, we just use RI. We also only 2957 * use single-segment receive DMA, so this 2958 * is mostly useless. 2959 * 2960 * TBD others 2961 */ 2962 } 2963 2964 /* Try to get more packets going. */ 2965 atw_start(ifp); 2966 2967 return (handled); 2968 } 2969 2970 /* 2971 * atw_idle: 2972 * 2973 * Cause the transmit and/or receive processes to go idle. 2974 * 2975 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2976 * process in STSR if I clear SR or ST after the process has already 2977 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2978 * do not seem to be too reliable. Perhaps I have the sense of the 2979 * Rx bits switched with the Tx bits? 2980 */ 2981 void 2982 atw_idle(struct atw_softc *sc, u_int32_t bits) 2983 { 2984 u_int32_t ackmask = 0, opmode, stsr, test0; 2985 int i, s; 2986 2987 s = splnet(); 2988 2989 opmode = sc->sc_opmode & ~bits; 2990 2991 if (bits & ATW_NAR_SR) 2992 ackmask |= ATW_INTR_RPS; 2993 2994 if (bits & ATW_NAR_ST) { 2995 ackmask |= ATW_INTR_TPS; 2996 /* set ATW_NAR_HF to flush TX FIFO. */ 2997 opmode |= ATW_NAR_HF; 2998 } 2999 3000 ATW_WRITE(sc, ATW_NAR, opmode); 3001 DELAY(atw_nar_delay); 3002 3003 for (i = 0; i < 1000; i++) { 3004 stsr = ATW_READ(sc, ATW_STSR); 3005 if ((stsr & ackmask) == ackmask) 3006 break; 3007 DELAY(10); 3008 } 3009 3010 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3011 3012 if ((stsr & ackmask) == ackmask) 3013 goto out; 3014 3015 test0 = ATW_READ(sc, ATW_TEST0); 3016 3017 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3018 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3019 printf("%s: transmit process not idle [%s]\n", 3020 sc->sc_dev.dv_xname, 3021 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 3022 printf("%s: bits %08x test0 %08x stsr %08x\n", 3023 sc->sc_dev.dv_xname, bits, test0, stsr); 3024 } 3025 3026 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3027 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3028 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3029 sc->sc_dev.dv_xname, 3030 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3031 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3032 sc->sc_dev.dv_xname, bits, test0, stsr)); 3033 } 3034 out: 3035 if ((bits & ATW_NAR_ST) != 0) 3036 atw_txdrain(sc); 3037 splx(s); 3038 return; 3039 } 3040 3041 /* 3042 * atw_linkintr: 3043 * 3044 * Helper; handle link-status interrupts. 3045 */ 3046 void 3047 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3048 { 3049 struct ieee80211com *ic = &sc->sc_ic; 3050 3051 if (ic->ic_state != IEEE80211_S_RUN) 3052 return; 3053 3054 if (linkstatus & ATW_INTR_LINKON) { 3055 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3056 sc->sc_rescan_timer = 0; 3057 } else if (linkstatus & ATW_INTR_LINKOFF) { 3058 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3059 if (ic->ic_opmode != IEEE80211_M_STA) 3060 return; 3061 sc->sc_rescan_timer = 3; 3062 sc->sc_if.if_timer = 1; 3063 } 3064 } 3065 3066 static __inline int 3067 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3068 { 3069 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3070 return 0; 3071 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3072 return 0; 3073 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3074 } 3075 3076 /* 3077 * atw_rxintr: 3078 * 3079 * Helper; handle receive interrupts. 3080 */ 3081 void 3082 atw_rxintr(struct atw_softc *sc) 3083 { 3084 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3085 struct ieee80211com *ic = &sc->sc_ic; 3086 struct ieee80211_node *ni; 3087 struct ieee80211_frame_min *wh; 3088 struct ifnet *ifp = &sc->sc_if; 3089 struct atw_rxsoft *rxs; 3090 struct mbuf *m; 3091 u_int32_t rxstat; 3092 int i, len, rate, rate0; 3093 u_int32_t rssi, rssi0; 3094 3095 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3096 rxs = &sc->sc_rxsoft[i]; 3097 3098 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3099 3100 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3101 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3102 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3103 3104 if (rxstat & ATW_RXSTAT_OWN) 3105 break; /* We have processed all receive buffers. */ 3106 3107 DPRINTF3(sc, 3108 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3109 sc->sc_dev.dv_xname, 3110 rxstat, rssi0, 3111 le32toh(sc->sc_rxdescs[i].ar_buf1), 3112 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3113 3114 /* 3115 * Make sure the packet fits in one buffer. This should 3116 * always be the case. 3117 */ 3118 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3119 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3120 printf("%s: incoming packet spilled, resetting\n", 3121 sc->sc_dev.dv_xname); 3122 (void)atw_init(ifp); 3123 return; 3124 } 3125 3126 /* 3127 * If an error occurred, update stats, clear the status 3128 * word, and leave the packet buffer in place. It will 3129 * simply be reused the next time the ring comes around. 3130 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3131 * error. 3132 */ 3133 3134 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3135 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3136 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3137 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3138 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3139 ATW_RXSTAT_ICVE)) != 0)) { 3140 #define PRINTERR(bit, str) \ 3141 if (rxstat & (bit)) \ 3142 printf("%s: receive error: %s\n", \ 3143 sc->sc_dev.dv_xname, str) 3144 ifp->if_ierrors++; 3145 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3146 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3147 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3148 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3149 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3150 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3151 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3152 #undef PRINTERR 3153 ATW_INIT_RXDESC(sc, i); 3154 continue; 3155 } 3156 3157 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3158 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3159 3160 /* 3161 * No errors; receive the packet. Note the ADM8211 3162 * includes the CRC in promiscuous mode. 3163 */ 3164 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3165 3166 /* 3167 * Allocate a new mbuf cluster. If that fails, we are 3168 * out of memory, and must drop the packet and recycle 3169 * the buffer that's already attached to this descriptor. 3170 */ 3171 m = rxs->rxs_mbuf; 3172 if (atw_add_rxbuf(sc, i) != 0) { 3173 ifp->if_ierrors++; 3174 ATW_INIT_RXDESC(sc, i); 3175 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3176 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3177 continue; 3178 } 3179 3180 ifp->if_ipackets++; 3181 if (sc->sc_opmode & ATW_NAR_PR) 3182 len -= IEEE80211_CRC_LEN; 3183 m->m_pkthdr.rcvif = ifp; 3184 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3185 3186 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3187 rate = 0; 3188 else 3189 rate = rate_tbl[rate0]; 3190 3191 /* The RSSI comes straight from a register in the 3192 * baseband processor. I know that for the RF3000, 3193 * the RSSI register also contains the antenna-selection 3194 * bits. Mask those off. 3195 * 3196 * TBD Treat other basebands. 3197 */ 3198 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3199 rssi = rssi0 & RF3000_RSSI_MASK; 3200 else 3201 rssi = rssi0; 3202 3203 #if NBPFILTER > 0 3204 /* Pass this up to any BPF listeners. */ 3205 if (sc->sc_radiobpf != NULL) { 3206 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3207 3208 tap->ar_rate = rate; 3209 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3210 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3211 3212 /* TBD verify units are dB */ 3213 tap->ar_antsignal = (int)rssi; 3214 /* TBD tap->ar_flags */ 3215 3216 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3217 tap->ar_ihdr.it_len, m); 3218 } 3219 #endif /* NPBFILTER > 0 */ 3220 3221 wh = mtod(m, struct ieee80211_frame_min *); 3222 ni = ieee80211_find_rxnode(ic, wh); 3223 if (atw_hw_decrypted(sc, wh)) { 3224 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3225 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3226 } 3227 ieee80211_input(ic, m, ni, (int)rssi, 0); 3228 ieee80211_free_node(ni); 3229 } 3230 3231 /* Update the receive pointer. */ 3232 sc->sc_rxptr = i; 3233 } 3234 3235 /* 3236 * atw_txintr: 3237 * 3238 * Helper; handle transmit interrupts. 3239 */ 3240 void 3241 atw_txintr(struct atw_softc *sc) 3242 { 3243 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3244 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3245 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3246 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3247 3248 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3249 struct ifnet *ifp = &sc->sc_if; 3250 struct atw_txsoft *txs; 3251 u_int32_t txstat; 3252 3253 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3254 sc->sc_dev.dv_xname, sc->sc_flags)); 3255 3256 ifp->if_flags &= ~IFF_OACTIVE; 3257 3258 /* 3259 * Go through our Tx list and free mbufs for those 3260 * frames that have been transmitted. 3261 */ 3262 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3263 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3264 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3265 3266 #ifdef ATW_DEBUG 3267 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3268 int i; 3269 printf(" txsoft %p transmit chain:\n", txs); 3270 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3271 txs->txs_ndescs - 1, 3272 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3273 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3274 printf(" descriptor %d:\n", i); 3275 printf(" at_status: 0x%08x\n", 3276 le32toh(sc->sc_txdescs[i].at_stat)); 3277 printf(" at_flags: 0x%08x\n", 3278 le32toh(sc->sc_txdescs[i].at_flags)); 3279 printf(" at_buf1: 0x%08x\n", 3280 le32toh(sc->sc_txdescs[i].at_buf1)); 3281 printf(" at_buf2: 0x%08x\n", 3282 le32toh(sc->sc_txdescs[i].at_buf2)); 3283 if (i == txs->txs_lastdesc) 3284 break; 3285 } 3286 } 3287 #endif 3288 3289 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3290 if (txstat & ATW_TXSTAT_OWN) 3291 break; 3292 3293 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3294 3295 sc->sc_txfree += txs->txs_ndescs; 3296 3297 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3298 0, txs->txs_dmamap->dm_mapsize, 3299 BUS_DMASYNC_POSTWRITE); 3300 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3301 m_freem(txs->txs_mbuf); 3302 txs->txs_mbuf = NULL; 3303 3304 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3305 3306 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3307 (txstat & TXSTAT_ERRMASK) != 0) { 3308 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3309 txstat_buf, sizeof(txstat_buf)); 3310 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3311 txstat_buf, 3312 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3313 } 3314 3315 /* 3316 * Check for errors and collisions. 3317 */ 3318 if (txstat & ATW_TXSTAT_TUF) 3319 sc->sc_stats.ts_tx_tuf++; 3320 if (txstat & ATW_TXSTAT_TLT) 3321 sc->sc_stats.ts_tx_tlt++; 3322 if (txstat & ATW_TXSTAT_TRT) 3323 sc->sc_stats.ts_tx_trt++; 3324 if (txstat & ATW_TXSTAT_TRO) 3325 sc->sc_stats.ts_tx_tro++; 3326 if (txstat & ATW_TXSTAT_SOFBR) { 3327 sc->sc_stats.ts_tx_sofbr++; 3328 } 3329 3330 if ((txstat & ATW_TXSTAT_ES) == 0) 3331 ifp->if_collisions += 3332 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3333 else 3334 ifp->if_oerrors++; 3335 3336 ifp->if_opackets++; 3337 } 3338 3339 /* 3340 * If there are no more pending transmissions, cancel the watchdog 3341 * timer. 3342 */ 3343 if (txs == NULL) 3344 sc->sc_tx_timer = 0; 3345 #undef TXSTAT_ERRMASK 3346 #undef TXSTAT_FMT 3347 } 3348 3349 /* 3350 * atw_watchdog: [ifnet interface function] 3351 * 3352 * Watchdog timer handler. 3353 */ 3354 void 3355 atw_watchdog(struct ifnet *ifp) 3356 { 3357 struct atw_softc *sc = ifp->if_softc; 3358 struct ieee80211com *ic = &sc->sc_ic; 3359 3360 ifp->if_timer = 0; 3361 if (ATW_IS_ENABLED(sc) == 0) 3362 return; 3363 3364 if (sc->sc_rescan_timer) { 3365 if (--sc->sc_rescan_timer == 0) 3366 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3367 } 3368 if (sc->sc_tx_timer) { 3369 if (--sc->sc_tx_timer == 0 && 3370 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3371 printf("%s: transmit timeout\n", ifp->if_xname); 3372 ifp->if_oerrors++; 3373 (void)atw_init(ifp); 3374 atw_start(ifp); 3375 } 3376 } 3377 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3378 ifp->if_timer = 1; 3379 ieee80211_watchdog(ic); 3380 } 3381 3382 /* Compute the 802.11 Duration field and the PLCP Length fields for 3383 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3384 * Write the fields to the ADM8211 Tx header, frm. 3385 * 3386 * TBD use the fragmentation threshold to find the right duration for 3387 * the first & last fragments. 3388 * 3389 * TBD make certain of the duration fields applied by the ADM8211 to each 3390 * fragment. I think that the ADM8211 knows how to subtract the CTS 3391 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3392 * I also think that the ADM8211 does *some* arithmetic for us, because 3393 * otherwise I think we would have to set a first duration for CTS/first 3394 * fragment, a second duration for fragments between the first and the 3395 * last, and a third duration for the last fragment. 3396 * 3397 * TBD make certain that duration fields reflect addition of FCS/WEP 3398 * and correct duration arithmetic as necessary. 3399 */ 3400 static void 3401 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3402 int len) 3403 { 3404 int remainder; 3405 3406 /* deal also with encrypted fragments */ 3407 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3408 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3409 sc->sc_dev.dv_xname)); 3410 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3411 IEEE80211_WEP_CRCLEN; 3412 } 3413 3414 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3415 * duration (XXX added by MAC?). 3416 */ 3417 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3418 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3419 3420 if (rate <= 4) 3421 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3422 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3423 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3424 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3425 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3426 else 3427 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3428 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3429 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3430 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3431 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3432 3433 /* lengthen duration if long preamble */ 3434 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3435 frm->atw_head_dur += 3436 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3437 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3438 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3439 IEEE80211_DUR_DS_FAST_PLCPHDR); 3440 3441 if (remainder != 0) 3442 frm->atw_head_dur++; 3443 3444 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3445 (rate == 2 || rate == 4)) { 3446 /* derived from Linux: how could this be right? */ 3447 frm->atw_head_plcplen = frm->atw_head_dur; 3448 } else { 3449 frm->atw_head_plcplen = (16 * len) / rate; 3450 remainder = (80 * len) % (rate * 5); 3451 3452 if (remainder != 0) { 3453 frm->atw_head_plcplen++; 3454 3455 /* XXX magic */ 3456 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3457 rate == 22 && remainder <= 30) 3458 frm->atw_head_plcplen |= 0x8000; 3459 } 3460 } 3461 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3462 htole16(frm->atw_head_plcplen); 3463 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3464 } 3465 3466 #ifdef ATW_DEBUG 3467 static void 3468 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3469 { 3470 struct atw_softc *sc = ifp->if_softc; 3471 struct mbuf *m; 3472 int i, noctets = 0; 3473 3474 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3475 m0->m_pkthdr.len); 3476 3477 for (m = m0; m; m = m->m_next) { 3478 if (m->m_len == 0) 3479 continue; 3480 for (i = 0; i < m->m_len; i++) { 3481 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3482 if (++noctets % 24 == 0) 3483 printf("\n"); 3484 } 3485 } 3486 printf("%s%s: %d bytes emitted\n", 3487 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3488 } 3489 #endif /* ATW_DEBUG */ 3490 3491 /* 3492 * atw_start: [ifnet interface function] 3493 * 3494 * Start packet transmission on the interface. 3495 */ 3496 void 3497 atw_start(struct ifnet *ifp) 3498 { 3499 struct atw_softc *sc = ifp->if_softc; 3500 struct ieee80211com *ic = &sc->sc_ic; 3501 struct ieee80211_node *ni; 3502 struct ieee80211_frame *wh; 3503 struct atw_frame *hh; 3504 struct mbuf *m0, *m; 3505 struct atw_txsoft *txs, *last_txs; 3506 struct atw_txdesc *txd; 3507 int do_encrypt, rate; 3508 bus_dmamap_t dmamap; 3509 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3510 3511 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3512 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3513 3514 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3515 return; 3516 3517 /* 3518 * Remember the previous number of free descriptors and 3519 * the first descriptor we'll use. 3520 */ 3521 ofree = sc->sc_txfree; 3522 firsttx = sc->sc_txnext; 3523 3524 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3525 sc->sc_dev.dv_xname, ofree, firsttx)); 3526 3527 /* 3528 * Loop through the send queue, setting up transmit descriptors 3529 * until we drain the queue, or use up all available transmit 3530 * descriptors. 3531 */ 3532 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3533 sc->sc_txfree != 0) { 3534 3535 /* 3536 * Grab a packet off the management queue, if it 3537 * is not empty. Otherwise, from the data queue. 3538 */ 3539 IF_DEQUEUE(&ic->ic_mgtq, m0); 3540 if (m0 != NULL) { 3541 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3542 m0->m_pkthdr.rcvif = NULL; 3543 } else { 3544 /* send no data packets until we are associated */ 3545 if (ic->ic_state != IEEE80211_S_RUN) 3546 break; 3547 IFQ_DEQUEUE(&ifp->if_snd, m0); 3548 if (m0 == NULL) 3549 break; 3550 #if NBPFILTER > 0 3551 if (ifp->if_bpf != NULL) 3552 bpf_mtap(ifp->if_bpf, m0); 3553 #endif /* NBPFILTER > 0 */ 3554 ni = ieee80211_find_txnode(ic, 3555 mtod(m0, struct ether_header *)->ether_dhost); 3556 if (ni == NULL) { 3557 ifp->if_oerrors++; 3558 break; 3559 } 3560 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3561 ieee80211_free_node(ni); 3562 ifp->if_oerrors++; 3563 break; 3564 } 3565 } 3566 3567 rate = MAX(ieee80211_get_rate(ic), 2); 3568 3569 #if NBPFILTER > 0 3570 /* 3571 * Pass the packet to any BPF listeners. 3572 */ 3573 if (ic->ic_rawbpf != NULL) 3574 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3575 3576 if (sc->sc_radiobpf != NULL) { 3577 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3578 3579 tap->at_rate = rate; 3580 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3581 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3582 3583 /* TBD tap->at_flags */ 3584 3585 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3586 tap->at_ihdr.it_len, m0); 3587 } 3588 #endif /* NBPFILTER > 0 */ 3589 3590 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3591 3592 if (ni != NULL) 3593 ieee80211_free_node(ni); 3594 3595 if (m0 == NULL) { 3596 ifp->if_oerrors++; 3597 break; 3598 } 3599 3600 /* just to make sure. */ 3601 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3602 3603 if (m0 == NULL) { 3604 ifp->if_oerrors++; 3605 break; 3606 } 3607 3608 hh = mtod(m0, struct atw_frame *); 3609 wh = &hh->atw_ihdr; 3610 3611 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3612 3613 /* Copy everything we need from the 802.11 header: 3614 * Frame Control; address 1, address 3, or addresses 3615 * 3 and 4. NIC fills in BSSID, SA. 3616 */ 3617 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3618 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3619 panic("%s: illegal WDS frame", 3620 sc->sc_dev.dv_xname); 3621 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3622 } else 3623 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3624 3625 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3626 3627 /* initialize remaining Tx parameters */ 3628 memset(&hh->u, 0, sizeof(hh->u)); 3629 3630 hh->atw_rate = rate * 5; 3631 /* XXX this could be incorrect if M_FCS. _encap should 3632 * probably strip FCS just in case it sticks around in 3633 * bridged packets. 3634 */ 3635 hh->atw_service = 0x00; /* XXX guess */ 3636 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3637 sizeof(struct atw_frame)); 3638 3639 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3640 hh->atw_rtylmt = 3; 3641 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3642 if (do_encrypt) { 3643 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3644 hh->atw_keyid = ic->ic_def_txkey; 3645 } 3646 3647 /* TBD 4-addr frames */ 3648 atw_frame_setdurs(sc, hh, rate, 3649 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3650 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3651 3652 /* never fragment multicast frames */ 3653 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3654 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3655 } else if (sc->sc_flags & ATWF_RTSCTS) { 3656 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3657 } 3658 3659 #ifdef ATW_DEBUG 3660 hh->atw_fragnum = 0; 3661 3662 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3663 printf("%s: dst = %s, rate = 0x%02x, " 3664 "service = 0x%02x, paylen = 0x%04x\n", 3665 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3666 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3667 3668 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3669 "dur1 = 0x%04x, dur2 = 0x%04x, " 3670 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3671 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3672 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3673 hh->atw_tail_dur, hh->atw_head_dur); 3674 3675 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3676 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3677 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3678 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3679 3680 printf("%s: keyid = %d\n", 3681 sc->sc_dev.dv_xname, hh->atw_keyid); 3682 3683 atw_dump_pkt(ifp, m0); 3684 } 3685 #endif /* ATW_DEBUG */ 3686 3687 dmamap = txs->txs_dmamap; 3688 3689 /* 3690 * Load the DMA map. Copy and try (once) again if the packet 3691 * didn't fit in the alloted number of segments. 3692 */ 3693 for (first = 1; 3694 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3695 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3696 first = 0) { 3697 MGETHDR(m, M_DONTWAIT, MT_DATA); 3698 if (m == NULL) { 3699 printf("%s: unable to allocate Tx mbuf\n", 3700 sc->sc_dev.dv_xname); 3701 break; 3702 } 3703 if (m0->m_pkthdr.len > MHLEN) { 3704 MCLGET(m, M_DONTWAIT); 3705 if ((m->m_flags & M_EXT) == 0) { 3706 printf("%s: unable to allocate Tx " 3707 "cluster\n", sc->sc_dev.dv_xname); 3708 m_freem(m); 3709 break; 3710 } 3711 } 3712 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3713 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3714 m_freem(m0); 3715 m0 = m; 3716 m = NULL; 3717 } 3718 if (error != 0) { 3719 printf("%s: unable to load Tx buffer, " 3720 "error = %d\n", sc->sc_dev.dv_xname, error); 3721 m_freem(m0); 3722 break; 3723 } 3724 3725 /* 3726 * Ensure we have enough descriptors free to describe 3727 * the packet. 3728 */ 3729 if (dmamap->dm_nsegs > sc->sc_txfree) { 3730 /* 3731 * Not enough free descriptors to transmit 3732 * this packet. Unload the DMA map and 3733 * drop the packet. Notify the upper layer 3734 * that there are no more slots left. 3735 * 3736 * XXX We could allocate an mbuf and copy, but 3737 * XXX it is worth it? 3738 */ 3739 ifp->if_flags |= IFF_OACTIVE; 3740 bus_dmamap_unload(sc->sc_dmat, dmamap); 3741 m_freem(m0); 3742 break; 3743 } 3744 3745 /* 3746 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3747 */ 3748 3749 /* Sync the DMA map. */ 3750 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3751 BUS_DMASYNC_PREWRITE); 3752 3753 /* XXX arbitrary retry limit; 8 because I have seen it in 3754 * use already and maybe 0 means "no tries" ! 3755 */ 3756 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3757 3758 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3759 sc->sc_dev.dv_xname, rate * 5)); 3760 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3761 3762 /* 3763 * Initialize the transmit descriptors. 3764 */ 3765 for (nexttx = sc->sc_txnext, seg = 0; 3766 seg < dmamap->dm_nsegs; 3767 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3768 /* 3769 * If this is the first descriptor we're 3770 * enqueueing, don't set the OWN bit just 3771 * yet. That could cause a race condition. 3772 * We'll do it below. 3773 */ 3774 txd = &sc->sc_txdescs[nexttx]; 3775 txd->at_ctl = ctl | 3776 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3777 3778 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3779 txd->at_flags = 3780 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3781 ATW_TXFLAG_TBS1_MASK)) | 3782 ((nexttx == (ATW_NTXDESC - 1)) 3783 ? htole32(ATW_TXFLAG_TER) : 0); 3784 lasttx = nexttx; 3785 } 3786 3787 IASSERT(lasttx != -1, ("bad lastx")); 3788 /* Set `first segment' and `last segment' appropriately. */ 3789 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3790 htole32(ATW_TXFLAG_FS); 3791 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3792 3793 #ifdef ATW_DEBUG 3794 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3795 printf(" txsoft %p transmit chain:\n", txs); 3796 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3797 printf(" descriptor %d:\n", seg); 3798 printf(" at_ctl: 0x%08x\n", 3799 le32toh(sc->sc_txdescs[seg].at_ctl)); 3800 printf(" at_flags: 0x%08x\n", 3801 le32toh(sc->sc_txdescs[seg].at_flags)); 3802 printf(" at_buf1: 0x%08x\n", 3803 le32toh(sc->sc_txdescs[seg].at_buf1)); 3804 printf(" at_buf2: 0x%08x\n", 3805 le32toh(sc->sc_txdescs[seg].at_buf2)); 3806 if (seg == lasttx) 3807 break; 3808 } 3809 } 3810 #endif 3811 3812 /* Sync the descriptors we're using. */ 3813 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3814 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3815 3816 /* 3817 * Store a pointer to the packet so we can free it later, 3818 * and remember what txdirty will be once the packet is 3819 * done. 3820 */ 3821 txs->txs_mbuf = m0; 3822 txs->txs_firstdesc = sc->sc_txnext; 3823 txs->txs_lastdesc = lasttx; 3824 txs->txs_ndescs = dmamap->dm_nsegs; 3825 3826 /* Advance the tx pointer. */ 3827 sc->sc_txfree -= dmamap->dm_nsegs; 3828 sc->sc_txnext = nexttx; 3829 3830 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3831 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3832 3833 last_txs = txs; 3834 } 3835 3836 if (txs == NULL || sc->sc_txfree == 0) { 3837 /* No more slots left; notify upper layer. */ 3838 ifp->if_flags |= IFF_OACTIVE; 3839 } 3840 3841 if (sc->sc_txfree != ofree) { 3842 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3843 sc->sc_dev.dv_xname, lasttx, firsttx)); 3844 /* 3845 * Cause a transmit interrupt to happen on the 3846 * last packet we enqueued. 3847 */ 3848 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3849 ATW_CDTXSYNC(sc, lasttx, 1, 3850 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3851 3852 /* 3853 * The entire packet chain is set up. Give the 3854 * first descriptor to the chip now. 3855 */ 3856 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3857 ATW_CDTXSYNC(sc, firsttx, 1, 3858 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3859 3860 /* Wake up the transmitter. */ 3861 ATW_WRITE(sc, ATW_TDR, 0x1); 3862 3863 /* Set a watchdog timer in case the chip flakes out. */ 3864 sc->sc_tx_timer = 5; 3865 ifp->if_timer = 1; 3866 } 3867 } 3868 3869 /* 3870 * atw_power: 3871 * 3872 * Power management (suspend/resume) hook. 3873 */ 3874 void 3875 atw_power(int why, void *arg) 3876 { 3877 struct atw_softc *sc = arg; 3878 struct ifnet *ifp = &sc->sc_if; 3879 int s; 3880 3881 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3882 3883 s = splnet(); 3884 switch (why) { 3885 case PWR_STANDBY: 3886 /* XXX do nothing. */ 3887 break; 3888 case PWR_SUSPEND: 3889 atw_stop(ifp, 0); 3890 if (sc->sc_power != NULL) 3891 (*sc->sc_power)(sc, why); 3892 break; 3893 case PWR_RESUME: 3894 if (ifp->if_flags & IFF_UP) { 3895 if (sc->sc_power != NULL) 3896 (*sc->sc_power)(sc, why); 3897 atw_init(ifp); 3898 } 3899 break; 3900 case PWR_SOFTSUSPEND: 3901 case PWR_SOFTSTANDBY: 3902 case PWR_SOFTRESUME: 3903 break; 3904 } 3905 splx(s); 3906 } 3907 3908 /* 3909 * atw_ioctl: [ifnet interface function] 3910 * 3911 * Handle control requests from the operator. 3912 */ 3913 int 3914 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3915 { 3916 struct atw_softc *sc = ifp->if_softc; 3917 struct ifreq *ifr = (struct ifreq *)data; 3918 int s, error = 0; 3919 3920 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3921 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3922 return ENXIO; 3923 3924 s = splnet(); 3925 3926 switch (cmd) { 3927 case SIOCSIFFLAGS: 3928 if (ifp->if_flags & IFF_UP) { 3929 if (ATW_IS_ENABLED(sc)) { 3930 /* 3931 * To avoid rescanning another access point, 3932 * do not call atw_init() here. Instead, 3933 * only reflect media settings. 3934 */ 3935 atw_filter_setup(sc); 3936 } else 3937 error = atw_init(ifp); 3938 } else if (ATW_IS_ENABLED(sc)) 3939 atw_stop(ifp, 1); 3940 break; 3941 case SIOCADDMULTI: 3942 case SIOCDELMULTI: 3943 error = (cmd == SIOCADDMULTI) ? 3944 ether_addmulti(ifr, &sc->sc_ec) : 3945 ether_delmulti(ifr, &sc->sc_ec); 3946 if (error == ENETRESET) { 3947 if (ifp->if_flags & IFF_RUNNING) 3948 atw_filter_setup(sc); /* do not rescan */ 3949 error = 0; 3950 } 3951 break; 3952 default: 3953 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3954 if (error == ENETRESET) { 3955 if (ATW_IS_ENABLED(sc)) 3956 error = atw_init(ifp); 3957 else 3958 error = 0; 3959 } 3960 break; 3961 } 3962 3963 /* Try to get more packets going. */ 3964 if (ATW_IS_ENABLED(sc)) 3965 atw_start(ifp); 3966 3967 splx(s); 3968 return (error); 3969 } 3970 3971 static int 3972 atw_media_change(struct ifnet *ifp) 3973 { 3974 int error; 3975 3976 error = ieee80211_media_change(ifp); 3977 if (error == ENETRESET) { 3978 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3979 (IFF_RUNNING|IFF_UP)) 3980 atw_init(ifp); /* XXX lose error */ 3981 error = 0; 3982 } 3983 return error; 3984 } 3985 3986 static void 3987 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3988 { 3989 struct atw_softc *sc = ifp->if_softc; 3990 3991 if (ATW_IS_ENABLED(sc) == 0) { 3992 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3993 imr->ifm_status = 0; 3994 return; 3995 } 3996 ieee80211_media_status(ifp, imr); 3997 } 3998
Indexes created Fri Sep 26 20:09:58 GMT 2025