atw.c revision 1.92
1 /* $NetBSD: atw.c,v 1.92 2005/12/24 20:27:29 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.92 2005/12/24 20:27:29 perry Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 static void atw_media_status(struct ifnet *, struct ifmediareq *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static void atw_frame_setdurs(struct atw_softc *, 271 struct atw_frame *, int, int); 272 static uint64_t atw_get_tsft(struct atw_softc *); 273 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 274 uint32_t); 275 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 276 static void atw_node_free(struct ieee80211_node *); 277 static void atw_change_ibss(struct atw_softc *); 278 279 /* 280 * Tuner/transceiver/modem 281 */ 282 static void atw_bbp_io_enable(struct atw_softc *, int); 283 284 /* RFMD RF3000 Baseband Processor */ 285 static int atw_rf3000_init(struct atw_softc *); 286 static int atw_rf3000_tune(struct atw_softc *, u_int); 287 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 288 289 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 290 static void atw_si4126_tune(struct atw_softc *, u_int); 291 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 292 293 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 294 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 295 296 const char *atw_tx_state[] = { 297 "STOPPED", 298 "RUNNING - read descriptor", 299 "RUNNING - transmitting", 300 "RUNNING - filling fifo", /* XXX */ 301 "SUSPENDED", 302 "RUNNING -- write descriptor", 303 "RUNNING -- write last descriptor", 304 "RUNNING - fifo full" 305 }; 306 307 const char *atw_rx_state[] = { 308 "STOPPED", 309 "RUNNING - read descriptor", 310 "RUNNING - check this packet, pre-fetch next", 311 "RUNNING - wait for reception", 312 "SUSPENDED", 313 "RUNNING - write descriptor", 314 "RUNNING - flush fifo", 315 "RUNNING - fifo drain" 316 }; 317 318 int 319 atw_activate(struct device *self, enum devact act) 320 { 321 struct atw_softc *sc = (struct atw_softc *)self; 322 int rv = 0, s; 323 324 s = splnet(); 325 switch (act) { 326 case DVACT_ACTIVATE: 327 rv = EOPNOTSUPP; 328 break; 329 330 case DVACT_DEACTIVATE: 331 if_deactivate(&sc->sc_if); 332 break; 333 } 334 splx(s); 335 return rv; 336 } 337 338 /* 339 * atw_enable: 340 * 341 * Enable the ADM8211 chip. 342 */ 343 int 344 atw_enable(struct atw_softc *sc) 345 { 346 347 if (ATW_IS_ENABLED(sc) == 0) { 348 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 349 printf("%s: device enable failed\n", 350 sc->sc_dev.dv_xname); 351 return (EIO); 352 } 353 sc->sc_flags |= ATWF_ENABLED; 354 } 355 return (0); 356 } 357 358 /* 359 * atw_disable: 360 * 361 * Disable the ADM8211 chip. 362 */ 363 void 364 atw_disable(struct atw_softc *sc) 365 { 366 if (!ATW_IS_ENABLED(sc)) 367 return; 368 if (sc->sc_disable != NULL) 369 (*sc->sc_disable)(sc); 370 sc->sc_flags &= ~ATWF_ENABLED; 371 } 372 373 /* Returns -1 on failure. */ 374 static int 375 atw_read_srom(struct atw_softc *sc) 376 { 377 struct seeprom_descriptor sd; 378 uint32_t test0, fail_bits; 379 380 (void)memset(&sd, 0, sizeof(sd)); 381 382 test0 = ATW_READ(sc, ATW_TEST0); 383 384 switch (sc->sc_rev) { 385 case ATW_REVISION_BA: 386 case ATW_REVISION_CA: 387 fail_bits = ATW_TEST0_EPNE; 388 break; 389 default: 390 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 391 break; 392 } 393 if ((test0 & fail_bits) != 0) { 394 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 395 return -1; 396 } 397 398 switch (test0 & ATW_TEST0_EPTYP_MASK) { 399 case ATW_TEST0_EPTYP_93c66: 400 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 401 sc->sc_sromsz = 512; 402 sd.sd_chip = C56_66; 403 break; 404 case ATW_TEST0_EPTYP_93c46: 405 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 406 sc->sc_sromsz = 128; 407 sd.sd_chip = C46; 408 break; 409 default: 410 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 411 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 412 return -1; 413 } 414 415 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 416 417 if (sc->sc_srom == NULL) { 418 printf("%s: unable to allocate SROM buffer\n", 419 sc->sc_dev.dv_xname); 420 return -1; 421 } 422 423 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 424 425 /* ADM8211 has a single 32-bit register for controlling the 426 * 93cx6 SROM. Bit SRS enables the serial port. There is no 427 * "ready" bit. The ADM8211 input/output sense is the reverse 428 * of read_seeprom's. 429 */ 430 sd.sd_tag = sc->sc_st; 431 sd.sd_bsh = sc->sc_sh; 432 sd.sd_regsize = 4; 433 sd.sd_control_offset = ATW_SPR; 434 sd.sd_status_offset = ATW_SPR; 435 sd.sd_dataout_offset = ATW_SPR; 436 sd.sd_CK = ATW_SPR_SCLK; 437 sd.sd_CS = ATW_SPR_SCS; 438 sd.sd_DI = ATW_SPR_SDO; 439 sd.sd_DO = ATW_SPR_SDI; 440 sd.sd_MS = ATW_SPR_SRS; 441 sd.sd_RDY = 0; 442 443 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 444 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 445 free(sc->sc_srom, M_DEVBUF); 446 return -1; 447 } 448 #ifdef ATW_DEBUG 449 { 450 int i; 451 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 452 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 453 if (((i % 8) == 0) && (i != 0)) { 454 ATW_DPRINTF(("\n\t")); 455 } 456 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 457 } 458 ATW_DPRINTF(("\n")); 459 } 460 #endif /* ATW_DEBUG */ 461 return 0; 462 } 463 464 #ifdef ATW_DEBUG 465 static void 466 atw_print_regs(struct atw_softc *sc, const char *where) 467 { 468 #define PRINTREG(sc, reg) \ 469 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 470 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 471 472 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 473 474 PRINTREG(sc, ATW_PAR); 475 PRINTREG(sc, ATW_FRCTL); 476 PRINTREG(sc, ATW_TDR); 477 PRINTREG(sc, ATW_WTDP); 478 PRINTREG(sc, ATW_RDR); 479 PRINTREG(sc, ATW_WRDP); 480 PRINTREG(sc, ATW_RDB); 481 PRINTREG(sc, ATW_CSR3A); 482 PRINTREG(sc, ATW_TDBD); 483 PRINTREG(sc, ATW_TDBP); 484 PRINTREG(sc, ATW_STSR); 485 PRINTREG(sc, ATW_CSR5A); 486 PRINTREG(sc, ATW_NAR); 487 PRINTREG(sc, ATW_CSR6A); 488 PRINTREG(sc, ATW_IER); 489 PRINTREG(sc, ATW_CSR7A); 490 PRINTREG(sc, ATW_LPC); 491 PRINTREG(sc, ATW_TEST1); 492 PRINTREG(sc, ATW_SPR); 493 PRINTREG(sc, ATW_TEST0); 494 PRINTREG(sc, ATW_WCSR); 495 PRINTREG(sc, ATW_WPDR); 496 PRINTREG(sc, ATW_GPTMR); 497 PRINTREG(sc, ATW_GPIO); 498 PRINTREG(sc, ATW_BBPCTL); 499 PRINTREG(sc, ATW_SYNCTL); 500 PRINTREG(sc, ATW_PLCPHD); 501 PRINTREG(sc, ATW_MMIWADDR); 502 PRINTREG(sc, ATW_MMIRADDR1); 503 PRINTREG(sc, ATW_MMIRADDR2); 504 PRINTREG(sc, ATW_TXBR); 505 PRINTREG(sc, ATW_CSR15A); 506 PRINTREG(sc, ATW_ALCSTAT); 507 PRINTREG(sc, ATW_TOFS2); 508 PRINTREG(sc, ATW_CMDR); 509 PRINTREG(sc, ATW_PCIC); 510 PRINTREG(sc, ATW_PMCSR); 511 PRINTREG(sc, ATW_PAR0); 512 PRINTREG(sc, ATW_PAR1); 513 PRINTREG(sc, ATW_MAR0); 514 PRINTREG(sc, ATW_MAR1); 515 PRINTREG(sc, ATW_ATIMDA0); 516 PRINTREG(sc, ATW_ABDA1); 517 PRINTREG(sc, ATW_BSSID0); 518 PRINTREG(sc, ATW_TXLMT); 519 PRINTREG(sc, ATW_MIBCNT); 520 PRINTREG(sc, ATW_BCNT); 521 PRINTREG(sc, ATW_TSFTH); 522 PRINTREG(sc, ATW_TSC); 523 PRINTREG(sc, ATW_SYNRF); 524 PRINTREG(sc, ATW_BPLI); 525 PRINTREG(sc, ATW_CAP0); 526 PRINTREG(sc, ATW_CAP1); 527 PRINTREG(sc, ATW_RMD); 528 PRINTREG(sc, ATW_CFPP); 529 PRINTREG(sc, ATW_TOFS0); 530 PRINTREG(sc, ATW_TOFS1); 531 PRINTREG(sc, ATW_IFST); 532 PRINTREG(sc, ATW_RSPT); 533 PRINTREG(sc, ATW_TSFTL); 534 PRINTREG(sc, ATW_WEPCTL); 535 PRINTREG(sc, ATW_WESK); 536 PRINTREG(sc, ATW_WEPCNT); 537 PRINTREG(sc, ATW_MACTEST); 538 PRINTREG(sc, ATW_FER); 539 PRINTREG(sc, ATW_FEMR); 540 PRINTREG(sc, ATW_FPSR); 541 PRINTREG(sc, ATW_FFER); 542 #undef PRINTREG 543 } 544 #endif /* ATW_DEBUG */ 545 546 /* 547 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 548 */ 549 void 550 atw_attach(struct atw_softc *sc) 551 { 552 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 553 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 554 }; 555 struct ieee80211com *ic = &sc->sc_ic; 556 struct ifnet *ifp = &sc->sc_if; 557 int country_code, error, i, nrate, srom_major; 558 u_int32_t reg; 559 static const char *type_strings[] = {"Intersil (not supported)", 560 "RFMD", "Marvel (not supported)"}; 561 562 sc->sc_txth = atw_txthresh_tab_lo; 563 564 SIMPLEQ_INIT(&sc->sc_txfreeq); 565 SIMPLEQ_INIT(&sc->sc_txdirtyq); 566 567 #ifdef ATW_DEBUG 568 atw_print_regs(sc, "atw_attach"); 569 #endif /* ATW_DEBUG */ 570 571 /* 572 * Allocate the control data structures, and create and load the 573 * DMA map for it. 574 */ 575 if ((error = bus_dmamem_alloc(sc->sc_dmat, 576 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 577 1, &sc->sc_cdnseg, 0)) != 0) { 578 printf("%s: unable to allocate control data, error = %d\n", 579 sc->sc_dev.dv_xname, error); 580 goto fail_0; 581 } 582 583 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 584 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 585 BUS_DMA_COHERENT)) != 0) { 586 printf("%s: unable to map control data, error = %d\n", 587 sc->sc_dev.dv_xname, error); 588 goto fail_1; 589 } 590 591 if ((error = bus_dmamap_create(sc->sc_dmat, 592 sizeof(struct atw_control_data), 1, 593 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 594 printf("%s: unable to create control data DMA map, " 595 "error = %d\n", sc->sc_dev.dv_xname, error); 596 goto fail_2; 597 } 598 599 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 600 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 601 0)) != 0) { 602 printf("%s: unable to load control data DMA map, error = %d\n", 603 sc->sc_dev.dv_xname, error); 604 goto fail_3; 605 } 606 607 /* 608 * Create the transmit buffer DMA maps. 609 */ 610 sc->sc_ntxsegs = ATW_NTXSEGS; 611 for (i = 0; i < ATW_TXQUEUELEN; i++) { 612 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 613 sc->sc_ntxsegs, MCLBYTES, 0, 0, 614 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 615 printf("%s: unable to create tx DMA map %d, " 616 "error = %d\n", sc->sc_dev.dv_xname, i, error); 617 goto fail_4; 618 } 619 } 620 621 /* 622 * Create the receive buffer DMA maps. 623 */ 624 for (i = 0; i < ATW_NRXDESC; i++) { 625 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 626 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 627 printf("%s: unable to create rx DMA map %d, " 628 "error = %d\n", sc->sc_dev.dv_xname, i, error); 629 goto fail_5; 630 } 631 } 632 for (i = 0; i < ATW_NRXDESC; i++) { 633 sc->sc_rxsoft[i].rxs_mbuf = NULL; 634 } 635 636 switch (sc->sc_rev) { 637 case ATW_REVISION_AB: 638 case ATW_REVISION_AF: 639 sc->sc_sramlen = ATW_SRAM_A_SIZE; 640 break; 641 case ATW_REVISION_BA: 642 case ATW_REVISION_CA: 643 sc->sc_sramlen = ATW_SRAM_B_SIZE; 644 break; 645 } 646 647 /* Reset the chip to a known state. */ 648 atw_reset(sc); 649 650 if (atw_read_srom(sc) == -1) 651 return; 652 653 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 654 ATW_SR_RFTYPE_MASK); 655 656 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 657 ATW_SR_BBPTYPE_MASK); 658 659 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 660 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 661 return; 662 } 663 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 664 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 665 return; 666 } 667 668 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 669 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 670 671 /* XXX There exists a Linux driver which seems to use RFType = 0 for 672 * MARVEL. My bug, or theirs? 673 */ 674 675 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 676 677 switch (sc->sc_rftype) { 678 case ATW_RFTYPE_INTERSIL: 679 reg |= ATW_SYNCTL_CS1; 680 break; 681 case ATW_RFTYPE_RFMD: 682 reg |= ATW_SYNCTL_CS0; 683 break; 684 case ATW_RFTYPE_MARVEL: 685 break; 686 } 687 688 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 689 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 690 691 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 692 693 switch (sc->sc_bbptype) { 694 case ATW_BBPTYPE_INTERSIL: 695 reg |= ATW_BBPCTL_TWI; 696 break; 697 case ATW_BBPTYPE_RFMD: 698 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 699 ATW_BBPCTL_CCA_ACTLO; 700 break; 701 case ATW_BBPTYPE_MARVEL: 702 break; 703 case ATW_C_BBPTYPE_RFMD: 704 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 705 sc->sc_dev.dv_xname); 706 break; 707 } 708 709 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 710 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 711 712 /* 713 * From this point forward, the attachment cannot fail. A failure 714 * before this point releases all resources that may have been 715 * allocated. 716 */ 717 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 718 719 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 720 htole16(sc->sc_srom[ATW_SR_MAC00]), 721 htole16(sc->sc_srom[ATW_SR_MAC01]), 722 htole16(sc->sc_srom[ATW_SR_MAC10]))); 723 724 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 725 ATW_SR_MAJOR_MASK); 726 727 if (srom_major < 2) 728 sc->sc_rf3000_options1 = 0; 729 else if (sc->sc_rev == ATW_REVISION_BA) { 730 sc->sc_rf3000_options1 = 731 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 732 ATW_SR_CR28_MASK); 733 } else 734 sc->sc_rf3000_options1 = 0; 735 736 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 737 ATW_SR_CR29_MASK); 738 739 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 740 ATW_SR_CTRY_MASK); 741 742 #define ADD_CHANNEL(_ic, _chan) do { \ 743 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 744 _ic->ic_channels[_chan].ic_freq = \ 745 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 746 } while (0) 747 748 /* Find available channels */ 749 switch (country_code) { 750 case COUNTRY_MMK2: /* 1-14 */ 751 ADD_CHANNEL(ic, 14); 752 /*FALLTHROUGH*/ 753 case COUNTRY_ETSI: /* 1-13 */ 754 for (i = 1; i <= 13; i++) 755 ADD_CHANNEL(ic, i); 756 break; 757 case COUNTRY_FCC: /* 1-11 */ 758 case COUNTRY_IC: /* 1-11 */ 759 for (i = 1; i <= 11; i++) 760 ADD_CHANNEL(ic, i); 761 break; 762 case COUNTRY_MMK: /* 14 */ 763 ADD_CHANNEL(ic, 14); 764 break; 765 case COUNTRY_FRANCE: /* 10-13 */ 766 for (i = 10; i <= 13; i++) 767 ADD_CHANNEL(ic, i); 768 break; 769 default: /* assume channels 10-11 */ 770 case COUNTRY_SPAIN: /* 10-11 */ 771 for (i = 10; i <= 11; i++) 772 ADD_CHANNEL(ic, i); 773 break; 774 } 775 776 /* Read the MAC address. */ 777 reg = ATW_READ(sc, ATW_PAR0); 778 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 779 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 780 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 781 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 782 reg = ATW_READ(sc, ATW_PAR1); 783 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 784 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 785 786 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 787 printf(" could not get mac address, attach failed\n"); 788 return; 789 } 790 791 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 792 793 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 794 ifp->if_softc = sc; 795 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 796 IFF_NOTRAILERS; 797 ifp->if_ioctl = atw_ioctl; 798 ifp->if_start = atw_start; 799 ifp->if_watchdog = atw_watchdog; 800 ifp->if_init = atw_init; 801 ifp->if_stop = atw_stop; 802 IFQ_SET_READY(&ifp->if_snd); 803 804 ic->ic_ifp = ifp; 805 ic->ic_phytype = IEEE80211_T_DS; 806 ic->ic_opmode = IEEE80211_M_STA; 807 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 808 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 809 810 nrate = 0; 811 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 813 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 814 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 815 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 816 817 /* 818 * Call MI attach routines. 819 */ 820 821 if_attach(ifp); 822 ieee80211_ifattach(ic); 823 824 sc->sc_newstate = ic->ic_newstate; 825 ic->ic_newstate = atw_newstate; 826 827 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 828 ic->ic_recv_mgmt = atw_recv_mgmt; 829 830 sc->sc_node_free = ic->ic_node_free; 831 ic->ic_node_free = atw_node_free; 832 833 sc->sc_node_alloc = ic->ic_node_alloc; 834 ic->ic_node_alloc = atw_node_alloc; 835 836 ic->ic_crypto.cs_key_delete = atw_key_delete; 837 ic->ic_crypto.cs_key_set = atw_key_set; 838 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 839 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 840 841 /* possibly we should fill in our own sc_send_prresp, since 842 * the ADM8211 is probably sending probe responses in ad hoc 843 * mode. 844 */ 845 846 /* complete initialization */ 847 ieee80211_media_init(ic, atw_media_change, atw_media_status); 848 callout_init(&sc->sc_scan_ch); 849 850 #if NBPFILTER > 0 851 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 852 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 853 #endif 854 855 /* 856 * Make sure the interface is shutdown during reboot. 857 */ 858 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 859 if (sc->sc_sdhook == NULL) 860 printf("%s: WARNING: unable to establish shutdown hook\n", 861 sc->sc_dev.dv_xname); 862 863 /* 864 * Add a suspend hook to make sure we come back up after a 865 * resume. 866 */ 867 sc->sc_powerhook = powerhook_establish(atw_power, sc); 868 if (sc->sc_powerhook == NULL) 869 printf("%s: WARNING: unable to establish power hook\n", 870 sc->sc_dev.dv_xname); 871 872 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 873 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 874 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 875 876 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 877 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 878 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 879 880 ieee80211_announce(ic); 881 return; 882 883 /* 884 * Free any resources we've allocated during the failed attach 885 * attempt. Do this in reverse order and fall through. 886 */ 887 fail_5: 888 for (i = 0; i < ATW_NRXDESC; i++) { 889 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 890 continue; 891 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 892 } 893 fail_4: 894 for (i = 0; i < ATW_TXQUEUELEN; i++) { 895 if (sc->sc_txsoft[i].txs_dmamap == NULL) 896 continue; 897 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 898 } 899 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 900 fail_3: 901 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 902 fail_2: 903 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 904 sizeof(struct atw_control_data)); 905 fail_1: 906 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 907 fail_0: 908 return; 909 } 910 911 static struct ieee80211_node * 912 atw_node_alloc(struct ieee80211_node_table *nt) 913 { 914 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 915 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 916 917 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 918 return ni; 919 } 920 921 static void 922 atw_node_free(struct ieee80211_node *ni) 923 { 924 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 925 926 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 927 ether_sprintf(ni->ni_bssid))); 928 (*sc->sc_node_free)(ni); 929 } 930 931 932 static void 933 atw_test1_reset(struct atw_softc *sc) 934 { 935 switch (sc->sc_rev) { 936 case ATW_REVISION_BA: 937 if (1 /* XXX condition on transceiver type */) { 938 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 939 } 940 break; 941 case ATW_REVISION_CA: 942 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 943 break; 944 default: 945 break; 946 } 947 } 948 949 /* 950 * atw_reset: 951 * 952 * Perform a soft reset on the ADM8211. 953 */ 954 void 955 atw_reset(struct atw_softc *sc) 956 { 957 int i; 958 uint32_t lpc; 959 960 ATW_WRITE(sc, ATW_NAR, 0x0); 961 DELAY(atw_nar_delay); 962 963 /* Reference driver has a cryptic remark indicating that this might 964 * power-on the chip. I know that it turns off power-saving.... 965 */ 966 ATW_WRITE(sc, ATW_FRCTL, 0x0); 967 968 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 969 970 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 971 if (ATW_READ(sc, ATW_PAR) == 0) 972 break; 973 DELAY(atw_pseudo_milli); 974 } 975 976 /* ... and then pause 100ms longer for good measure. */ 977 DELAY(atw_magic_delay1); 978 979 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 980 981 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 982 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 983 984 atw_test1_reset(sc); 985 /* 986 * Initialize the PCI Access Register. 987 */ 988 sc->sc_busmode = ATW_PAR_PBL_8DW; 989 990 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 991 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 992 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 993 994 /* Turn off maximum power saving, etc. 995 * 996 * XXX Following example of reference driver, should I set 997 * an AID of 1? It didn't seem to help.... 998 */ 999 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1000 1001 DELAY(atw_magic_delay2); 1002 1003 /* Recall EEPROM. */ 1004 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1005 1006 DELAY(atw_magic_delay4); 1007 1008 lpc = ATW_READ(sc, ATW_LPC); 1009 1010 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1011 1012 /* A reset seems to affect the SRAM contents, so put them into 1013 * a known state. 1014 */ 1015 atw_clear_sram(sc); 1016 1017 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1018 } 1019 1020 static void 1021 atw_clear_sram(struct atw_softc *sc) 1022 { 1023 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1024 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1025 /* XXX not for revision 0x20. */ 1026 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1027 } 1028 1029 /* TBD atw_init 1030 * 1031 * set MAC based on ic->ic_bss->myaddr 1032 * write WEP keys 1033 * set TX rate 1034 */ 1035 1036 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1037 * without receiving a beacon with the preferred BSSID & SSID. 1038 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1039 */ 1040 static void 1041 atw_wcsr_init(struct atw_softc *sc) 1042 { 1043 uint32_t wcsr; 1044 1045 wcsr = ATW_READ(sc, ATW_WCSR); 1046 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1047 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1048 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1049 1050 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1051 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1052 } 1053 1054 /* Turn off power management. Set Rx store-and-forward mode. */ 1055 static void 1056 atw_cmdr_init(struct atw_softc *sc) 1057 { 1058 uint32_t cmdr; 1059 cmdr = ATW_READ(sc, ATW_CMDR); 1060 cmdr &= ~ATW_CMDR_APM; 1061 cmdr |= ATW_CMDR_RTE; 1062 cmdr &= ~ATW_CMDR_DRT_MASK; 1063 cmdr |= ATW_CMDR_DRT_SF; 1064 1065 ATW_WRITE(sc, ATW_CMDR, cmdr); 1066 } 1067 1068 static void 1069 atw_tofs2_init(struct atw_softc *sc) 1070 { 1071 uint32_t tofs2; 1072 /* XXX this magic can probably be figured out from the RFMD docs */ 1073 #ifndef ATW_REFSLAVE 1074 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1075 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1076 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1077 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1078 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1079 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1080 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1081 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1082 #else 1083 /* XXX new magic from reference driver source */ 1084 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1085 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1086 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1087 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1088 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1089 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1090 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1091 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1092 #endif 1093 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1094 } 1095 1096 static void 1097 atw_nar_init(struct atw_softc *sc) 1098 { 1099 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1100 } 1101 1102 static void 1103 atw_txlmt_init(struct atw_softc *sc) 1104 { 1105 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1106 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1107 } 1108 1109 static void 1110 atw_test1_init(struct atw_softc *sc) 1111 { 1112 uint32_t test1; 1113 1114 test1 = ATW_READ(sc, ATW_TEST1); 1115 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1116 /* XXX magic 0x1 */ 1117 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1118 ATW_WRITE(sc, ATW_TEST1, test1); 1119 } 1120 1121 static void 1122 atw_rf_reset(struct atw_softc *sc) 1123 { 1124 /* XXX this resets an Intersil RF front-end? */ 1125 /* TBD condition on Intersil RFType? */ 1126 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1127 DELAY(atw_rf_delay1); 1128 ATW_WRITE(sc, ATW_SYNRF, 0); 1129 DELAY(atw_rf_delay2); 1130 } 1131 1132 /* Set 16 TU max duration for the contention-free period (CFP). */ 1133 static void 1134 atw_cfp_init(struct atw_softc *sc) 1135 { 1136 uint32_t cfpp; 1137 1138 cfpp = ATW_READ(sc, ATW_CFPP); 1139 cfpp &= ~ATW_CFPP_CFPMD; 1140 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1141 ATW_WRITE(sc, ATW_CFPP, cfpp); 1142 } 1143 1144 static void 1145 atw_tofs0_init(struct atw_softc *sc) 1146 { 1147 /* XXX I guess that the Cardbus clock is 22MHz? 1148 * I am assuming that the role of ATW_TOFS0_USCNT is 1149 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1150 * very clear on this point. It says in the datasheet that it is 1151 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1152 * and 33MHz; maybe this is the way? I see a binary-only driver write 1153 * these values. These values are also the power-on default. 1154 */ 1155 ATW_WRITE(sc, ATW_TOFS0, 1156 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1157 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1158 } 1159 1160 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1161 static void 1162 atw_ifs_init(struct atw_softc *sc) 1163 { 1164 uint32_t ifst; 1165 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1166 * Go figure. 1167 */ 1168 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1169 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1170 ATW_IFST_SIFS_MASK) | 1171 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1172 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1173 1174 ATW_WRITE(sc, ATW_IFST, ifst); 1175 } 1176 1177 static void 1178 atw_response_times_init(struct atw_softc *sc) 1179 { 1180 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1181 * indicate that the MAC expects at least SIFS + MIRT microseconds 1182 * to pass after it transmits a frame that requires a response; 1183 * it waits at most SIFS + MART microseconds for the response. 1184 * Surely this is not the ACK timeout? 1185 */ 1186 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1187 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1188 } 1189 1190 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1191 * engines read and write baseband registers after Rx and before 1192 * Tx, respectively. 1193 */ 1194 static void 1195 atw_bbp_io_init(struct atw_softc *sc) 1196 { 1197 uint32_t mmiraddr2; 1198 1199 /* XXX The reference driver does this, but is it *really* 1200 * necessary? 1201 */ 1202 switch (sc->sc_rev) { 1203 case ATW_REVISION_AB: 1204 case ATW_REVISION_AF: 1205 mmiraddr2 = 0x0; 1206 break; 1207 default: 1208 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1209 mmiraddr2 &= 1210 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1211 break; 1212 } 1213 1214 switch (sc->sc_bbptype) { 1215 case ATW_BBPTYPE_INTERSIL: 1216 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1217 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1218 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1219 break; 1220 case ATW_BBPTYPE_MARVEL: 1221 /* TBD find out the Marvel settings. */ 1222 break; 1223 case ATW_BBPTYPE_RFMD: 1224 default: 1225 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1226 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1227 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1228 break; 1229 } 1230 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1231 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1232 } 1233 1234 /* 1235 * atw_init: [ ifnet interface function ] 1236 * 1237 * Initialize the interface. Must be called at splnet(). 1238 */ 1239 int 1240 atw_init(struct ifnet *ifp) 1241 { 1242 struct atw_softc *sc = ifp->if_softc; 1243 struct ieee80211com *ic = &sc->sc_ic; 1244 struct atw_txsoft *txs; 1245 struct atw_rxsoft *rxs; 1246 int i, error = 0; 1247 1248 if ((error = atw_enable(sc)) != 0) 1249 goto out; 1250 1251 /* 1252 * Cancel any pending I/O. This also resets. 1253 */ 1254 atw_stop(ifp, 0); 1255 1256 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1257 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1258 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1259 1260 atw_wcsr_init(sc); 1261 1262 atw_cmdr_init(sc); 1263 1264 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1265 * 1266 * XXX Set transmit power for ATIM, RTS, Beacon. 1267 */ 1268 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1269 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1270 1271 atw_tofs2_init(sc); 1272 1273 atw_nar_init(sc); 1274 1275 atw_txlmt_init(sc); 1276 1277 atw_test1_init(sc); 1278 1279 atw_rf_reset(sc); 1280 1281 atw_cfp_init(sc); 1282 1283 atw_tofs0_init(sc); 1284 1285 atw_ifs_init(sc); 1286 1287 /* XXX Fall asleep after one second of inactivity. 1288 * XXX A frame may only dribble in for 65536us. 1289 */ 1290 ATW_WRITE(sc, ATW_RMD, 1291 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1292 1293 atw_response_times_init(sc); 1294 1295 atw_bbp_io_init(sc); 1296 1297 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1298 1299 if ((error = atw_rf3000_init(sc)) != 0) 1300 goto out; 1301 1302 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1303 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1304 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1305 1306 /* 1307 * Initialize the transmit descriptor ring. 1308 */ 1309 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1310 for (i = 0; i < ATW_NTXDESC; i++) { 1311 sc->sc_txdescs[i].at_ctl = 0; 1312 /* no transmit chaining */ 1313 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1314 sc->sc_txdescs[i].at_buf2 = 1315 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1316 } 1317 /* use ring mode */ 1318 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1319 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1320 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1321 sc->sc_txfree = ATW_NTXDESC; 1322 sc->sc_txnext = 0; 1323 1324 /* 1325 * Initialize the transmit job descriptors. 1326 */ 1327 SIMPLEQ_INIT(&sc->sc_txfreeq); 1328 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1329 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1330 txs = &sc->sc_txsoft[i]; 1331 txs->txs_mbuf = NULL; 1332 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1333 } 1334 1335 /* 1336 * Initialize the receive descriptor and receive job 1337 * descriptor rings. 1338 */ 1339 for (i = 0; i < ATW_NRXDESC; i++) { 1340 rxs = &sc->sc_rxsoft[i]; 1341 if (rxs->rxs_mbuf == NULL) { 1342 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1343 printf("%s: unable to allocate or map rx " 1344 "buffer %d, error = %d\n", 1345 sc->sc_dev.dv_xname, i, error); 1346 /* 1347 * XXX Should attempt to run with fewer receive 1348 * XXX buffers instead of just failing. 1349 */ 1350 atw_rxdrain(sc); 1351 goto out; 1352 } 1353 } else 1354 ATW_INIT_RXDESC(sc, i); 1355 } 1356 sc->sc_rxptr = 0; 1357 1358 /* 1359 * Initialize the interrupt mask and enable interrupts. 1360 */ 1361 /* normal interrupts */ 1362 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1363 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1364 1365 /* abnormal interrupts */ 1366 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1367 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1368 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1369 1370 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1371 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1372 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1373 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1374 ATW_INTR_TRT; 1375 1376 sc->sc_linkint_mask &= sc->sc_inten; 1377 sc->sc_rxint_mask &= sc->sc_inten; 1378 sc->sc_txint_mask &= sc->sc_inten; 1379 1380 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1381 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1382 1383 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1384 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1385 1386 /* 1387 * Give the transmit and receive rings to the ADM8211. 1388 */ 1389 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1390 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1391 1392 sc->sc_txthresh = 0; 1393 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1394 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1395 1396 /* common 802.11 configuration */ 1397 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1398 switch (ic->ic_opmode) { 1399 case IEEE80211_M_STA: 1400 break; 1401 case IEEE80211_M_AHDEMO: /* XXX */ 1402 case IEEE80211_M_IBSS: 1403 ic->ic_flags |= IEEE80211_F_IBSSON; 1404 /*FALLTHROUGH*/ 1405 case IEEE80211_M_HOSTAP: /* XXX */ 1406 break; 1407 case IEEE80211_M_MONITOR: /* XXX */ 1408 break; 1409 } 1410 1411 switch (ic->ic_opmode) { 1412 case IEEE80211_M_AHDEMO: 1413 case IEEE80211_M_HOSTAP: 1414 #ifndef IEEE80211_NO_HOSTAP 1415 ic->ic_bss->ni_intval = ic->ic_lintval; 1416 ic->ic_bss->ni_rssi = 0; 1417 ic->ic_bss->ni_rstamp = 0; 1418 #endif /* !IEEE80211_NO_HOSTAP */ 1419 break; 1420 default: /* XXX */ 1421 break; 1422 } 1423 1424 sc->sc_wepctl = 0; 1425 1426 atw_write_ssid(sc); 1427 atw_write_sup_rates(sc); 1428 if (ic->ic_caps & IEEE80211_C_WEP) 1429 atw_write_wep(sc); 1430 1431 ic->ic_state = IEEE80211_S_INIT; 1432 1433 /* 1434 * Set the receive filter. This will start the transmit and 1435 * receive processes. 1436 */ 1437 atw_filter_setup(sc); 1438 1439 /* 1440 * Start the receive process. 1441 */ 1442 ATW_WRITE(sc, ATW_RDR, 0x1); 1443 1444 /* 1445 * Note that the interface is now running. 1446 */ 1447 ifp->if_flags |= IFF_RUNNING; 1448 ifp->if_flags &= ~IFF_OACTIVE; 1449 1450 /* send no beacons, yet. */ 1451 atw_start_beacon(sc, 0); 1452 1453 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1454 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1455 else 1456 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1457 out: 1458 if (error) { 1459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1460 sc->sc_tx_timer = 0; 1461 ifp->if_timer = 0; 1462 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1463 } 1464 #ifdef ATW_DEBUG 1465 atw_print_regs(sc, "end of init"); 1466 #endif /* ATW_DEBUG */ 1467 1468 return (error); 1469 } 1470 1471 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1472 * 0: MAC control of RF3000/Si4126. 1473 * 1474 * Applies power, or selects RF front-end? Sets reset condition. 1475 * 1476 * TBD support non-RFMD BBP, non-SiLabs synth. 1477 */ 1478 static void 1479 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1480 { 1481 if (enable) { 1482 ATW_WRITE(sc, ATW_SYNRF, 1483 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1484 DELAY(atw_bbp_io_enable_delay); 1485 } else { 1486 ATW_WRITE(sc, ATW_SYNRF, 0); 1487 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1488 } 1489 } 1490 1491 static int 1492 atw_tune(struct atw_softc *sc) 1493 { 1494 int rc; 1495 u_int chan; 1496 struct ieee80211com *ic = &sc->sc_ic; 1497 1498 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1499 if (chan == IEEE80211_CHAN_ANY) 1500 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1501 1502 if (chan == sc->sc_cur_chan) 1503 return 0; 1504 1505 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1506 sc->sc_cur_chan, chan)); 1507 1508 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1509 1510 atw_si4126_tune(sc, chan); 1511 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1512 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1513 chan); 1514 1515 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1516 DELAY(atw_nar_delay); 1517 ATW_WRITE(sc, ATW_RDR, 0x1); 1518 1519 if (rc == 0) 1520 sc->sc_cur_chan = chan; 1521 1522 return rc; 1523 } 1524 1525 #ifdef ATW_SYNDEBUG 1526 static void 1527 atw_si4126_print(struct atw_softc *sc) 1528 { 1529 struct ifnet *ifp = &sc->sc_if; 1530 u_int addr, val; 1531 1532 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1533 return; 1534 1535 for (addr = 0; addr <= 8; addr++) { 1536 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1537 if (atw_si4126_read(sc, addr, &val) == 0) { 1538 printf("<unknown> (quitting print-out)\n"); 1539 break; 1540 } 1541 printf("%05x\n", val); 1542 } 1543 } 1544 #endif /* ATW_SYNDEBUG */ 1545 1546 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1547 * 1548 * The RF/IF synthesizer produces two reference frequencies for 1549 * the RF2948B transceiver. The first frequency the RF2948B requires 1550 * is two times the so-called "intermediate frequency" (IF). Since 1551 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1552 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1553 * frequency required by the transceiver is the radio frequency 1554 * (RF). This is a superheterodyne transceiver; for f(chan) the 1555 * center frequency of the channel we are tuning, RF = f(chan) - 1556 * IF. 1557 * 1558 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1559 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1560 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1561 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1562 */ 1563 static void 1564 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1565 { 1566 u_int mhz; 1567 u_int R; 1568 u_int32_t gpio; 1569 u_int16_t gain; 1570 1571 #ifdef ATW_SYNDEBUG 1572 atw_si4126_print(sc); 1573 #endif /* ATW_SYNDEBUG */ 1574 1575 if (chan == 14) 1576 mhz = 2484; 1577 else 1578 mhz = 2412 + 5 * (chan - 1); 1579 1580 /* Tune IF to 748MHz to suit the IF LO input of the 1581 * RF2494B, which is 2 x IF. No need to set an IF divider 1582 * because an IF in 526MHz - 952MHz is allowed. 1583 * 1584 * XIN is 44.000MHz, so divide it by two to get allowable 1585 * range of 2-25MHz. SiLabs tells me that this is not 1586 * strictly necessary. 1587 */ 1588 1589 if (atw_xindiv2) 1590 R = 44; 1591 else 1592 R = 88; 1593 1594 /* Power-up RF, IF synthesizers. */ 1595 atw_si4126_write(sc, SI4126_POWER, 1596 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1597 1598 /* set LPWR, too? */ 1599 atw_si4126_write(sc, SI4126_MAIN, 1600 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1601 1602 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1603 * set KP2 to 1. 1604 * 1605 * REFDIF This is different from the reference driver, which 1606 * always sets SI4126_GAIN to 0. 1607 */ 1608 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1609 1610 atw_si4126_write(sc, SI4126_GAIN, gain); 1611 1612 /* XIN = 44MHz. 1613 * 1614 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1615 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1616 * 1617 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1618 * so that 1496/88 * 44MHz = 748MHz. 1619 */ 1620 atw_si4126_write(sc, SI4126_IFN, 1496); 1621 1622 atw_si4126_write(sc, SI4126_IFR, R); 1623 1624 #ifndef ATW_REFSLAVE 1625 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1626 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1627 * which has no RF1! 1628 */ 1629 atw_si4126_write(sc, SI4126_RF1R, R); 1630 1631 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1632 #endif 1633 1634 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1635 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1636 * Now let's multiply it to mhz. So mhz - IF = N. 1637 */ 1638 atw_si4126_write(sc, SI4126_RF2R, R); 1639 1640 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1641 1642 /* wait 100us from power-up for RF, IF to settle */ 1643 DELAY(100); 1644 1645 gpio = ATW_READ(sc, ATW_GPIO); 1646 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1647 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1648 1649 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1650 /* Set a Prism RF front-end to a special mode for channel 14? 1651 * 1652 * Apparently the SMC2635W needs this, although I don't think 1653 * it has a Prism RF. 1654 */ 1655 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1656 } 1657 ATW_WRITE(sc, ATW_GPIO, gpio); 1658 1659 #ifdef ATW_SYNDEBUG 1660 atw_si4126_print(sc); 1661 #endif /* ATW_SYNDEBUG */ 1662 } 1663 1664 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1665 * diversity. 1666 * 1667 * !!! 1668 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1669 * !!! 1670 */ 1671 static int 1672 atw_rf3000_init(struct atw_softc *sc) 1673 { 1674 int rc = 0; 1675 1676 atw_bbp_io_enable(sc, 1); 1677 1678 /* CCA is acquisition sensitive */ 1679 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1680 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1681 1682 if (rc != 0) 1683 goto out; 1684 1685 /* enable diversity */ 1686 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1687 1688 if (rc != 0) 1689 goto out; 1690 1691 /* sensible setting from a binary-only driver */ 1692 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1693 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1694 1695 if (rc != 0) 1696 goto out; 1697 1698 /* magic from a binary-only driver */ 1699 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1700 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1701 1702 if (rc != 0) 1703 goto out; 1704 1705 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1706 1707 if (rc != 0) 1708 goto out; 1709 1710 /* XXX Reference driver remarks that Abocom sets this to 50. 1711 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1712 * in the "reserved" area of register RF3000_OPTIONS1. 1713 */ 1714 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1715 1716 if (rc != 0) 1717 goto out; 1718 1719 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1720 1721 if (rc != 0) 1722 goto out; 1723 1724 out: 1725 atw_bbp_io_enable(sc, 0); 1726 return rc; 1727 } 1728 1729 #ifdef ATW_BBPDEBUG 1730 static void 1731 atw_rf3000_print(struct atw_softc *sc) 1732 { 1733 struct ifnet *ifp = &sc->sc_if; 1734 u_int addr, val; 1735 1736 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1737 return; 1738 1739 for (addr = 0x01; addr <= 0x15; addr++) { 1740 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1741 if (atw_rf3000_read(sc, addr, &val) != 0) { 1742 printf("<unknown> (quitting print-out)\n"); 1743 break; 1744 } 1745 printf("%08x\n", val); 1746 } 1747 } 1748 #endif /* ATW_BBPDEBUG */ 1749 1750 /* Set the power settings on the BBP for channel `chan'. */ 1751 static int 1752 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1753 { 1754 int rc = 0; 1755 u_int32_t reg; 1756 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1757 1758 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1759 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1760 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1761 1762 /* odd channels: LSB, even channels: MSB */ 1763 if (chan % 2 == 1) { 1764 txpower &= 0xFF; 1765 lpf_cutoff &= 0xFF; 1766 lna_gs_thresh &= 0xFF; 1767 } else { 1768 txpower >>= 8; 1769 lpf_cutoff >>= 8; 1770 lna_gs_thresh >>= 8; 1771 } 1772 1773 #ifdef ATW_BBPDEBUG 1774 atw_rf3000_print(sc); 1775 #endif /* ATW_BBPDEBUG */ 1776 1777 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1778 "lna_gs_thresh %02x\n", 1779 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1780 1781 atw_bbp_io_enable(sc, 1); 1782 1783 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1784 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1785 goto out; 1786 1787 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1788 goto out; 1789 1790 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1791 goto out; 1792 1793 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1794 1795 if (rc != 0) 1796 goto out; 1797 1798 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1799 1800 if (rc != 0) 1801 goto out; 1802 1803 #ifdef ATW_BBPDEBUG 1804 atw_rf3000_print(sc); 1805 #endif /* ATW_BBPDEBUG */ 1806 1807 out: 1808 atw_bbp_io_enable(sc, 0); 1809 1810 /* set beacon, rts, atim transmit power */ 1811 reg = ATW_READ(sc, ATW_PLCPHD); 1812 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1813 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1814 ATW_PLCPHD_SERVICE_MASK); 1815 ATW_WRITE(sc, ATW_PLCPHD, reg); 1816 DELAY(atw_plcphd_delay); 1817 1818 return rc; 1819 } 1820 1821 /* Write a register on the RF3000 baseband processor using the 1822 * registers provided by the ADM8211 for this purpose. 1823 * 1824 * Return 0 on success. 1825 */ 1826 static int 1827 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1828 { 1829 u_int32_t reg; 1830 int i; 1831 1832 reg = sc->sc_bbpctl_wr | 1833 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1834 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1835 1836 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1837 ATW_WRITE(sc, ATW_BBPCTL, reg); 1838 DELAY(2 * atw_pseudo_milli); 1839 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1840 break; 1841 } 1842 1843 if (i < 0) { 1844 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1845 return ETIMEDOUT; 1846 } 1847 return 0; 1848 } 1849 1850 /* Read a register on the RF3000 baseband processor using the registers 1851 * the ADM8211 provides for this purpose. 1852 * 1853 * The 7-bit register address is addr. Record the 8-bit data in the register 1854 * in *val. 1855 * 1856 * Return 0 on success. 1857 * 1858 * XXX This does not seem to work. The ADM8211 must require more or 1859 * different magic to read the chip than to write it. Possibly some 1860 * of the magic I have derived from a binary-only driver concerns 1861 * the "chip address" (see the RF3000 manual). 1862 */ 1863 #ifdef ATW_BBPDEBUG 1864 static int 1865 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1866 { 1867 u_int32_t reg; 1868 int i; 1869 1870 for (i = 1000; --i >= 0; ) { 1871 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1872 break; 1873 DELAY(100); 1874 } 1875 1876 if (i < 0) { 1877 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1878 sc->sc_dev.dv_xname); 1879 return ETIMEDOUT; 1880 } 1881 1882 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1883 1884 ATW_WRITE(sc, ATW_BBPCTL, reg); 1885 1886 for (i = 1000; --i >= 0; ) { 1887 DELAY(100); 1888 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1889 break; 1890 } 1891 1892 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1893 1894 if (i < 0) { 1895 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1896 sc->sc_dev.dv_xname, reg); 1897 return ETIMEDOUT; 1898 } 1899 if (val != NULL) 1900 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1901 return 0; 1902 } 1903 #endif /* ATW_BBPDEBUG */ 1904 1905 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1906 * provided by the ADM8211 for that purpose. 1907 * 1908 * val is 18 bits of data, and val is the 4-bit address of the register. 1909 * 1910 * Return 0 on success. 1911 */ 1912 static void 1913 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1914 { 1915 uint32_t bits, mask, reg; 1916 const int nbits = 22; 1917 1918 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1919 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1920 1921 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1922 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1923 1924 reg = ATW_SYNRF_SELSYN; 1925 /* reference driver: reset Si4126 serial bus to initial 1926 * conditions? 1927 */ 1928 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1929 ATW_WRITE(sc, ATW_SYNRF, reg); 1930 1931 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1932 if ((bits & mask) != 0) 1933 reg |= ATW_SYNRF_SYNDATA; 1934 else 1935 reg &= ~ATW_SYNRF_SYNDATA; 1936 ATW_WRITE(sc, ATW_SYNRF, reg); 1937 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1938 ATW_WRITE(sc, ATW_SYNRF, reg); 1939 } 1940 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1941 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1942 } 1943 1944 /* Read 18-bit data from the 4-bit address addr in Si4126 1945 * RF synthesizer and write the data to *val. Return 0 on success. 1946 * 1947 * XXX This does not seem to work. The ADM8211 must require more or 1948 * different magic to read the chip than to write it. 1949 */ 1950 #ifdef ATW_SYNDEBUG 1951 static int 1952 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1953 { 1954 u_int32_t reg; 1955 int i; 1956 1957 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1958 1959 for (i = 1000; --i >= 0; ) { 1960 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1961 break; 1962 DELAY(100); 1963 } 1964 1965 if (i < 0) { 1966 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1967 sc->sc_dev.dv_xname); 1968 return ETIMEDOUT; 1969 } 1970 1971 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1972 1973 ATW_WRITE(sc, ATW_SYNCTL, reg); 1974 1975 for (i = 1000; --i >= 0; ) { 1976 DELAY(100); 1977 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1978 break; 1979 } 1980 1981 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1982 1983 if (i < 0) { 1984 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1985 sc->sc_dev.dv_xname, reg); 1986 return ETIMEDOUT; 1987 } 1988 if (val != NULL) 1989 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1990 ATW_SYNCTL_DATA_MASK); 1991 return 0; 1992 } 1993 #endif /* ATW_SYNDEBUG */ 1994 1995 /* XXX is the endianness correct? test. */ 1996 #define atw_calchash(addr) \ 1997 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1998 1999 /* 2000 * atw_filter_setup: 2001 * 2002 * Set the ADM8211's receive filter. 2003 */ 2004 static void 2005 atw_filter_setup(struct atw_softc *sc) 2006 { 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 struct ethercom *ec = &sc->sc_ec; 2009 struct ifnet *ifp = &sc->sc_if; 2010 int hash; 2011 u_int32_t hashes[2]; 2012 struct ether_multi *enm; 2013 struct ether_multistep step; 2014 2015 /* According to comments in tlp_al981_filter_setup 2016 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2017 * multicast filter to be set while it is running. Hopefully 2018 * the ADM8211 is not the same! 2019 */ 2020 if ((ifp->if_flags & IFF_RUNNING) != 0) 2021 atw_idle(sc, ATW_NAR_SR); 2022 2023 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2024 ifp->if_flags &= ~IFF_ALLMULTI; 2025 2026 /* XXX in scan mode, do not filter packets. Maybe this is 2027 * unnecessary. 2028 */ 2029 if (ic->ic_state == IEEE80211_S_SCAN || 2030 (ifp->if_flags & IFF_PROMISC) != 0) { 2031 sc->sc_opmode |= ATW_NAR_PR; 2032 goto allmulti; 2033 } 2034 2035 hashes[0] = hashes[1] = 0x0; 2036 2037 /* 2038 * Program the 64-bit multicast hash filter. 2039 */ 2040 ETHER_FIRST_MULTI(step, ec, enm); 2041 while (enm != NULL) { 2042 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2043 ETHER_ADDR_LEN) != 0) 2044 goto allmulti; 2045 2046 hash = atw_calchash(enm->enm_addrlo); 2047 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2048 ETHER_NEXT_MULTI(step, enm); 2049 sc->sc_opmode |= ATW_NAR_MM; 2050 } 2051 ifp->if_flags &= ~IFF_ALLMULTI; 2052 goto setit; 2053 2054 allmulti: 2055 sc->sc_opmode |= ATW_NAR_MM; 2056 ifp->if_flags |= IFF_ALLMULTI; 2057 hashes[0] = hashes[1] = 0xffffffff; 2058 2059 setit: 2060 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2061 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2062 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2063 DELAY(atw_nar_delay); 2064 2065 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2066 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2067 } 2068 2069 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2070 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2071 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2072 * no beacon with the preferred BSSID and SSID in the number of 2073 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2074 */ 2075 static void 2076 atw_write_bssid(struct atw_softc *sc) 2077 { 2078 struct ieee80211com *ic = &sc->sc_ic; 2079 u_int8_t *bssid; 2080 2081 bssid = ic->ic_bss->ni_bssid; 2082 2083 ATW_WRITE(sc, ATW_BSSID0, 2084 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2085 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2086 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2087 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2088 2089 ATW_WRITE(sc, ATW_ABDA1, 2090 (ATW_READ(sc, ATW_ABDA1) & 2091 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2092 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2093 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2094 2095 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2096 ether_sprintf(sc->sc_bssid))); 2097 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2098 2099 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2100 } 2101 2102 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2103 * 16-bit word. 2104 */ 2105 static void 2106 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2107 { 2108 u_int i; 2109 u_int8_t *ptr; 2110 2111 memcpy(&sc->sc_sram[ofs], buf, buflen); 2112 2113 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2114 2115 KASSERT(buflen + ofs <= sc->sc_sramlen); 2116 2117 ptr = &sc->sc_sram[ofs]; 2118 2119 for (i = 0; i < buflen; i += 2) { 2120 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2121 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2122 DELAY(atw_writewep_delay); 2123 2124 ATW_WRITE(sc, ATW_WESK, 2125 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2126 DELAY(atw_writewep_delay); 2127 } 2128 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2129 2130 if (sc->sc_if.if_flags & IFF_DEBUG) { 2131 int n_octets = 0; 2132 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2133 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2134 for (i = 0; i < buflen; i++) { 2135 printf(" %02x", ptr[i]); 2136 if (++n_octets % 24 == 0) 2137 printf("\n"); 2138 } 2139 if (n_octets % 24 != 0) 2140 printf("\n"); 2141 } 2142 } 2143 2144 static int 2145 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2146 { 2147 struct atw_softc *sc = ic->ic_ifp->if_softc; 2148 u_int keyix = k->wk_keyix; 2149 2150 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2151 2152 if (keyix >= IEEE80211_WEP_NKID) 2153 return 0; 2154 if (k->wk_keylen != 0) 2155 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2156 2157 return 1; 2158 } 2159 2160 static int 2161 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2162 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2163 { 2164 struct atw_softc *sc = ic->ic_ifp->if_softc; 2165 2166 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2167 2168 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2169 return 0; 2170 2171 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2172 2173 return 1; 2174 } 2175 2176 static void 2177 atw_key_update_begin(struct ieee80211com *ic) 2178 { 2179 #ifdef ATW_DEBUG 2180 struct ifnet *ifp = ic->ic_ifp; 2181 struct atw_softc *sc = ifp->if_softc; 2182 #endif 2183 2184 DPRINTF(sc, ("%s:\n", __func__)); 2185 } 2186 2187 static void 2188 atw_key_update_end(struct ieee80211com *ic) 2189 { 2190 struct ifnet *ifp = ic->ic_ifp; 2191 struct atw_softc *sc = ifp->if_softc; 2192 2193 DPRINTF(sc, ("%s:\n", __func__)); 2194 2195 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2196 return; 2197 if (ATW_IS_ENABLED(sc) == 0) 2198 return; 2199 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2200 atw_write_wep(sc); 2201 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2202 } 2203 2204 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2205 static void 2206 atw_write_wep(struct atw_softc *sc) 2207 { 2208 struct ieee80211com *ic = &sc->sc_ic; 2209 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2210 u_int8_t buf[IEEE80211_WEP_NKID] 2211 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2212 u_int32_t reg; 2213 int i; 2214 2215 sc->sc_wepctl = 0; 2216 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2217 2218 memset(&buf[0][0], 0, sizeof(buf)); 2219 2220 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2221 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2222 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2223 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2224 buf[i][1] = ATW_WEP_ENABLED; 2225 } else { 2226 buf[i][1] = 0; 2227 continue; 2228 } 2229 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2230 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2231 ic->ic_nw_keys[i].wk_keylen - 1); 2232 } 2233 2234 reg = ATW_READ(sc, ATW_MACTEST); 2235 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2236 reg &= ~ATW_MACTEST_KEYID_MASK; 2237 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2238 ATW_WRITE(sc, ATW_MACTEST, reg); 2239 2240 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2241 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2242 2243 switch (sc->sc_rev) { 2244 case ATW_REVISION_AB: 2245 case ATW_REVISION_AF: 2246 /* Bypass WEP on Rx. */ 2247 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2248 break; 2249 default: 2250 break; 2251 } 2252 2253 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2254 sizeof(buf)); 2255 2256 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2257 } 2258 2259 static void 2260 atw_change_ibss(struct atw_softc *sc) 2261 { 2262 atw_predict_beacon(sc); 2263 atw_write_bssid(sc); 2264 atw_start_beacon(sc, 1); 2265 } 2266 2267 static void 2268 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2269 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2270 { 2271 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2272 2273 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2274 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2275 return; 2276 2277 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2278 2279 switch (subtype) { 2280 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2281 case IEEE80211_FC0_SUBTYPE_BEACON: 2282 if (ic->ic_opmode != IEEE80211_M_IBSS || 2283 ic->ic_state != IEEE80211_S_RUN) 2284 break; 2285 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc) && 2286 ieee80211_ibss_merge(ni) == ENETRESET) 2287 atw_change_ibss(sc); 2288 break; 2289 default: 2290 break; 2291 } 2292 return; 2293 } 2294 2295 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2296 * In ad hoc mode, the SSID is written to the beacons sent by the 2297 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2298 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2299 * indications. 2300 */ 2301 static void 2302 atw_write_ssid(struct atw_softc *sc) 2303 { 2304 struct ieee80211com *ic = &sc->sc_ic; 2305 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2306 * it only expects the element length, not its ID. 2307 */ 2308 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2309 2310 memset(buf, 0, sizeof(buf)); 2311 buf[0] = ic->ic_bss->ni_esslen; 2312 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2313 2314 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2315 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2316 } 2317 2318 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2319 * In ad hoc mode, the supported rates are written to beacons sent by the 2320 * ADM8211. 2321 */ 2322 static void 2323 atw_write_sup_rates(struct atw_softc *sc) 2324 { 2325 struct ieee80211com *ic = &sc->sc_ic; 2326 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2327 * supported rates 2328 */ 2329 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2330 2331 memset(buf, 0, sizeof(buf)); 2332 2333 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2334 2335 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2336 ic->ic_bss->ni_rates.rs_nrates); 2337 2338 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2339 } 2340 2341 /* Start/stop sending beacons. */ 2342 void 2343 atw_start_beacon(struct atw_softc *sc, int start) 2344 { 2345 struct ieee80211com *ic = &sc->sc_ic; 2346 uint16_t chan; 2347 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2348 size_t len; 2349 2350 if (ATW_IS_ENABLED(sc) == 0) 2351 return; 2352 2353 /* start beacons */ 2354 len = sizeof(struct ieee80211_frame) + 2355 8 /* timestamp */ + 2 /* beacon interval */ + 2356 2 /* capability info */ + 2357 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2358 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2359 3 /* DS parameters */ + 2360 IEEE80211_CRC_LEN; 2361 2362 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2363 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2364 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2365 2366 ATW_WRITE(sc, ATW_BCNT, bcnt); 2367 ATW_WRITE(sc, ATW_CAP1, cap1); 2368 2369 if (!start) 2370 return; 2371 2372 /* TBD use ni_capinfo */ 2373 2374 capinfo = 0; 2375 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2376 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2377 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2378 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2379 2380 switch (ic->ic_opmode) { 2381 case IEEE80211_M_IBSS: 2382 len += 4; /* IBSS parameters */ 2383 capinfo |= IEEE80211_CAPINFO_IBSS; 2384 break; 2385 case IEEE80211_M_HOSTAP: 2386 /* XXX 6-byte minimum TIM */ 2387 len += atw_beacon_len_adjust; 2388 capinfo |= IEEE80211_CAPINFO_ESS; 2389 break; 2390 default: 2391 return; 2392 } 2393 2394 /* set listen interval 2395 * XXX do software units agree w/ hardware? 2396 */ 2397 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2398 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2399 2400 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2401 2402 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2403 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2404 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2405 2406 ATW_WRITE(sc, ATW_BCNT, bcnt); 2407 ATW_WRITE(sc, ATW_BPLI, bpli); 2408 ATW_WRITE(sc, ATW_CAP0, cap0); 2409 ATW_WRITE(sc, ATW_CAP1, cap1); 2410 2411 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2412 sc->sc_dev.dv_xname, bcnt)); 2413 2414 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2415 sc->sc_dev.dv_xname, cap1)); 2416 } 2417 2418 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2419 static inline uint32_t 2420 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2421 { 2422 /* Following the reference driver's lead, I compute 2423 * 2424 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2425 * 2426 * without using 64-bit arithmetic, using the following 2427 * relationship: 2428 * 2429 * (0x100000000 * H + L) % m 2430 * = ((0x100000000 % m) * H + L) % m 2431 * = (((0xffffffff + 1) % m) * H + L) % m 2432 * = ((0xffffffff % m + 1 % m) * H + L) % m 2433 * = ((0xffffffff % m + 1) * H + L) % m 2434 */ 2435 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2436 } 2437 2438 static uint64_t 2439 atw_get_tsft(struct atw_softc *sc) 2440 { 2441 int i; 2442 uint32_t tsfth, tsftl; 2443 for (i = 0; i < 2; i++) { 2444 tsfth = ATW_READ(sc, ATW_TSFTH); 2445 tsftl = ATW_READ(sc, ATW_TSFTL); 2446 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2447 break; 2448 } 2449 return ((uint64_t)tsfth << 32) | tsftl; 2450 } 2451 2452 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2453 * the ieee80211com. 2454 * 2455 * Predict the next target beacon transmission time (TBTT) and 2456 * write it to the ADM8211. 2457 */ 2458 static void 2459 atw_predict_beacon(struct atw_softc *sc) 2460 { 2461 #define TBTTOFS 20 /* TU */ 2462 2463 struct ieee80211com *ic = &sc->sc_ic; 2464 uint64_t tsft; 2465 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2466 union { 2467 uint64_t word; 2468 uint8_t tstamp[8]; 2469 } u; 2470 2471 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2472 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2473 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2474 tsft = atw_get_tsft(sc); 2475 u.word = htole64(tsft); 2476 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2477 sizeof(ic->ic_bss->ni_tstamp)); 2478 } else 2479 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2480 2481 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2482 2483 tsftl = tsft & 0xFFFFFFFF; 2484 tsfth = tsft >> 32; 2485 2486 /* We sent/received the last beacon `past' microseconds 2487 * after the interval divided the TSF timer. 2488 */ 2489 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2490 2491 /* Skip ten beacons so that the TBTT cannot pass before 2492 * we've programmed it. Ten is an arbitrary number. 2493 */ 2494 tbtt = past_even + ival * 10; 2495 2496 ATW_WRITE(sc, ATW_TOFS1, 2497 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2498 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2499 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2500 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2501 #undef TBTTOFS 2502 } 2503 2504 static void 2505 atw_next_scan(void *arg) 2506 { 2507 struct atw_softc *sc = arg; 2508 struct ieee80211com *ic = &sc->sc_ic; 2509 int s; 2510 2511 /* don't call atw_start w/o network interrupts blocked */ 2512 s = splnet(); 2513 if (ic->ic_state == IEEE80211_S_SCAN) 2514 ieee80211_next_scan(ic); 2515 splx(s); 2516 } 2517 2518 /* Synchronize the hardware state with the software state. */ 2519 static int 2520 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2521 { 2522 struct ifnet *ifp = ic->ic_ifp; 2523 struct atw_softc *sc = ifp->if_softc; 2524 enum ieee80211_state ostate; 2525 int error = 0; 2526 2527 ostate = ic->ic_state; 2528 callout_stop(&sc->sc_scan_ch); 2529 atw_start_beacon(sc, 0); 2530 2531 switch (nstate) { 2532 case IEEE80211_S_ASSOC: 2533 error = atw_tune(sc); 2534 break; 2535 case IEEE80211_S_INIT: 2536 callout_stop(&sc->sc_scan_ch); 2537 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2538 break; 2539 case IEEE80211_S_SCAN: 2540 error = atw_tune(sc); 2541 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2542 atw_next_scan, sc); 2543 break; 2544 case IEEE80211_S_AUTH: 2545 error = atw_tune(sc); 2546 break; 2547 case IEEE80211_S_RUN: 2548 error = atw_tune(sc); 2549 atw_write_bssid(sc); 2550 atw_write_ssid(sc); 2551 atw_write_sup_rates(sc); 2552 2553 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2554 ic->ic_opmode == IEEE80211_M_MONITOR) 2555 break; 2556 2557 /* set listen interval 2558 * XXX do software units agree w/ hardware? 2559 */ 2560 ATW_WRITE(sc, ATW_BPLI, 2561 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2562 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2563 ATW_BPLI_LI_MASK)); 2564 2565 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2566 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2567 2568 atw_predict_beacon(sc); 2569 atw_start_beacon(sc, 2570 ic->ic_opmode == IEEE80211_M_HOSTAP || 2571 ic->ic_opmode == IEEE80211_M_IBSS); 2572 break; 2573 } 2574 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2575 } 2576 2577 /* 2578 * atw_add_rxbuf: 2579 * 2580 * Add a receive buffer to the indicated descriptor. 2581 */ 2582 int 2583 atw_add_rxbuf(struct atw_softc *sc, int idx) 2584 { 2585 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2586 struct mbuf *m; 2587 int error; 2588 2589 MGETHDR(m, M_DONTWAIT, MT_DATA); 2590 if (m == NULL) 2591 return (ENOBUFS); 2592 2593 MCLGET(m, M_DONTWAIT); 2594 if ((m->m_flags & M_EXT) == 0) { 2595 m_freem(m); 2596 return (ENOBUFS); 2597 } 2598 2599 if (rxs->rxs_mbuf != NULL) 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 2602 rxs->rxs_mbuf = m; 2603 2604 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2606 BUS_DMA_READ|BUS_DMA_NOWAIT); 2607 if (error) { 2608 printf("%s: can't load rx DMA map %d, error = %d\n", 2609 sc->sc_dev.dv_xname, idx, error); 2610 panic("atw_add_rxbuf"); /* XXX */ 2611 } 2612 2613 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2614 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2615 2616 ATW_INIT_RXDESC(sc, idx); 2617 2618 return (0); 2619 } 2620 2621 /* 2622 * Release any queued transmit buffers. 2623 */ 2624 void 2625 atw_txdrain(struct atw_softc *sc) 2626 { 2627 struct atw_txsoft *txs; 2628 2629 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2630 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2631 if (txs->txs_mbuf != NULL) { 2632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2633 m_freem(txs->txs_mbuf); 2634 txs->txs_mbuf = NULL; 2635 } 2636 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2637 sc->sc_txfree += txs->txs_ndescs; 2638 } 2639 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2640 sc->sc_tx_timer = 0; 2641 } 2642 2643 /* 2644 * atw_stop: [ ifnet interface function ] 2645 * 2646 * Stop transmission on the interface. 2647 */ 2648 void 2649 atw_stop(struct ifnet *ifp, int disable) 2650 { 2651 struct atw_softc *sc = ifp->if_softc; 2652 struct ieee80211com *ic = &sc->sc_ic; 2653 2654 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2655 2656 /* Disable interrupts. */ 2657 ATW_WRITE(sc, ATW_IER, 0); 2658 2659 /* Stop the transmit and receive processes. */ 2660 sc->sc_opmode = 0; 2661 ATW_WRITE(sc, ATW_NAR, 0); 2662 DELAY(atw_nar_delay); 2663 ATW_WRITE(sc, ATW_TDBD, 0); 2664 ATW_WRITE(sc, ATW_TDBP, 0); 2665 ATW_WRITE(sc, ATW_RDB, 0); 2666 2667 atw_txdrain(sc); 2668 2669 if (disable) { 2670 atw_rxdrain(sc); 2671 atw_disable(sc); 2672 } 2673 2674 /* 2675 * Mark the interface down and cancel the watchdog timer. 2676 */ 2677 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2678 sc->sc_tx_timer = 0; 2679 ifp->if_timer = 0; 2680 2681 if (!disable) 2682 atw_reset(sc); 2683 } 2684 2685 /* 2686 * atw_rxdrain: 2687 * 2688 * Drain the receive queue. 2689 */ 2690 void 2691 atw_rxdrain(struct atw_softc *sc) 2692 { 2693 struct atw_rxsoft *rxs; 2694 int i; 2695 2696 for (i = 0; i < ATW_NRXDESC; i++) { 2697 rxs = &sc->sc_rxsoft[i]; 2698 if (rxs->rxs_mbuf == NULL) 2699 continue; 2700 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2701 m_freem(rxs->rxs_mbuf); 2702 rxs->rxs_mbuf = NULL; 2703 } 2704 } 2705 2706 /* 2707 * atw_detach: 2708 * 2709 * Detach an ADM8211 interface. 2710 */ 2711 int 2712 atw_detach(struct atw_softc *sc) 2713 { 2714 struct ifnet *ifp = &sc->sc_if; 2715 struct atw_rxsoft *rxs; 2716 struct atw_txsoft *txs; 2717 int i; 2718 2719 /* 2720 * Succeed now if there isn't any work to do. 2721 */ 2722 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2723 return (0); 2724 2725 callout_stop(&sc->sc_scan_ch); 2726 2727 ieee80211_ifdetach(&sc->sc_ic); 2728 if_detach(ifp); 2729 2730 for (i = 0; i < ATW_NRXDESC; i++) { 2731 rxs = &sc->sc_rxsoft[i]; 2732 if (rxs->rxs_mbuf != NULL) { 2733 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2734 m_freem(rxs->rxs_mbuf); 2735 rxs->rxs_mbuf = NULL; 2736 } 2737 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2738 } 2739 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2740 txs = &sc->sc_txsoft[i]; 2741 if (txs->txs_mbuf != NULL) { 2742 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2743 m_freem(txs->txs_mbuf); 2744 txs->txs_mbuf = NULL; 2745 } 2746 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2747 } 2748 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2749 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2750 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2751 sizeof(struct atw_control_data)); 2752 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2753 2754 shutdownhook_disestablish(sc->sc_sdhook); 2755 powerhook_disestablish(sc->sc_powerhook); 2756 2757 if (sc->sc_srom) 2758 free(sc->sc_srom, M_DEVBUF); 2759 2760 return (0); 2761 } 2762 2763 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2764 void 2765 atw_shutdown(void *arg) 2766 { 2767 struct atw_softc *sc = arg; 2768 2769 atw_stop(&sc->sc_if, 1); 2770 } 2771 2772 int 2773 atw_intr(void *arg) 2774 { 2775 struct atw_softc *sc = arg; 2776 struct ifnet *ifp = &sc->sc_if; 2777 u_int32_t status, rxstatus, txstatus, linkstatus; 2778 int handled = 0, txthresh; 2779 2780 #ifdef DEBUG 2781 if (ATW_IS_ENABLED(sc) == 0) 2782 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2783 #endif 2784 2785 /* 2786 * If the interface isn't running, the interrupt couldn't 2787 * possibly have come from us. 2788 */ 2789 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2790 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2791 return (0); 2792 2793 for (;;) { 2794 status = ATW_READ(sc, ATW_STSR); 2795 2796 if (status) 2797 ATW_WRITE(sc, ATW_STSR, status); 2798 2799 #ifdef ATW_DEBUG 2800 #define PRINTINTR(flag) do { \ 2801 if ((status & flag) != 0) { \ 2802 printf("%s" #flag, delim); \ 2803 delim = ","; \ 2804 } \ 2805 } while (0) 2806 2807 if (atw_debug > 1 && status) { 2808 const char *delim = "<"; 2809 2810 printf("%s: reg[STSR] = %x", 2811 sc->sc_dev.dv_xname, status); 2812 2813 PRINTINTR(ATW_INTR_FBE); 2814 PRINTINTR(ATW_INTR_LINKOFF); 2815 PRINTINTR(ATW_INTR_LINKON); 2816 PRINTINTR(ATW_INTR_RCI); 2817 PRINTINTR(ATW_INTR_RDU); 2818 PRINTINTR(ATW_INTR_REIS); 2819 PRINTINTR(ATW_INTR_RPS); 2820 PRINTINTR(ATW_INTR_TCI); 2821 PRINTINTR(ATW_INTR_TDU); 2822 PRINTINTR(ATW_INTR_TLT); 2823 PRINTINTR(ATW_INTR_TPS); 2824 PRINTINTR(ATW_INTR_TRT); 2825 PRINTINTR(ATW_INTR_TUF); 2826 PRINTINTR(ATW_INTR_BCNTC); 2827 PRINTINTR(ATW_INTR_ATIME); 2828 PRINTINTR(ATW_INTR_TBTT); 2829 PRINTINTR(ATW_INTR_TSCZ); 2830 PRINTINTR(ATW_INTR_TSFTF); 2831 printf(">\n"); 2832 } 2833 #undef PRINTINTR 2834 #endif /* ATW_DEBUG */ 2835 2836 if ((status & sc->sc_inten) == 0) 2837 break; 2838 2839 handled = 1; 2840 2841 rxstatus = status & sc->sc_rxint_mask; 2842 txstatus = status & sc->sc_txint_mask; 2843 linkstatus = status & sc->sc_linkint_mask; 2844 2845 if (linkstatus) { 2846 atw_linkintr(sc, linkstatus); 2847 } 2848 2849 if (rxstatus) { 2850 /* Grab any new packets. */ 2851 atw_rxintr(sc); 2852 2853 if (rxstatus & ATW_INTR_RDU) { 2854 printf("%s: receive ring overrun\n", 2855 sc->sc_dev.dv_xname); 2856 /* Get the receive process going again. */ 2857 ATW_WRITE(sc, ATW_RDR, 0x1); 2858 break; 2859 } 2860 } 2861 2862 if (txstatus) { 2863 /* Sweep up transmit descriptors. */ 2864 atw_txintr(sc); 2865 2866 if (txstatus & ATW_INTR_TLT) 2867 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2868 sc->sc_dev.dv_xname)); 2869 2870 if (txstatus & ATW_INTR_TRT) 2871 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2872 sc->sc_dev.dv_xname)); 2873 2874 /* If Tx under-run, increase our transmit threshold 2875 * if another is available. 2876 */ 2877 txthresh = sc->sc_txthresh + 1; 2878 if ((txstatus & ATW_INTR_TUF) && 2879 sc->sc_txth[txthresh].txth_name != NULL) { 2880 /* Idle the transmit process. */ 2881 atw_idle(sc, ATW_NAR_ST); 2882 2883 sc->sc_txthresh = txthresh; 2884 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2885 sc->sc_opmode |= 2886 sc->sc_txth[txthresh].txth_opmode; 2887 printf("%s: transmit underrun; new " 2888 "threshold: %s\n", sc->sc_dev.dv_xname, 2889 sc->sc_txth[txthresh].txth_name); 2890 2891 /* Set the new threshold and restart 2892 * the transmit process. 2893 */ 2894 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2895 DELAY(atw_nar_delay); 2896 ATW_WRITE(sc, ATW_RDR, 0x1); 2897 /* XXX Log every Nth underrun from 2898 * XXX now on? 2899 */ 2900 } 2901 } 2902 2903 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2904 if (status & ATW_INTR_TPS) 2905 printf("%s: transmit process stopped\n", 2906 sc->sc_dev.dv_xname); 2907 if (status & ATW_INTR_RPS) 2908 printf("%s: receive process stopped\n", 2909 sc->sc_dev.dv_xname); 2910 (void)atw_init(ifp); 2911 break; 2912 } 2913 2914 if (status & ATW_INTR_FBE) { 2915 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2916 (void)atw_init(ifp); 2917 break; 2918 } 2919 2920 /* 2921 * Not handled: 2922 * 2923 * Transmit buffer unavailable -- normal 2924 * condition, nothing to do, really. 2925 * 2926 * Early receive interrupt -- not available on 2927 * all chips, we just use RI. We also only 2928 * use single-segment receive DMA, so this 2929 * is mostly useless. 2930 * 2931 * TBD others 2932 */ 2933 } 2934 2935 /* Try to get more packets going. */ 2936 atw_start(ifp); 2937 2938 return (handled); 2939 } 2940 2941 /* 2942 * atw_idle: 2943 * 2944 * Cause the transmit and/or receive processes to go idle. 2945 * 2946 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2947 * process in STSR if I clear SR or ST after the process has already 2948 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2949 * do not seem to be too reliable. Perhaps I have the sense of the 2950 * Rx bits switched with the Tx bits? 2951 */ 2952 void 2953 atw_idle(struct atw_softc *sc, u_int32_t bits) 2954 { 2955 u_int32_t ackmask = 0, opmode, stsr, test0; 2956 int i, s; 2957 2958 s = splnet(); 2959 2960 opmode = sc->sc_opmode & ~bits; 2961 2962 if (bits & ATW_NAR_SR) 2963 ackmask |= ATW_INTR_RPS; 2964 2965 if (bits & ATW_NAR_ST) { 2966 ackmask |= ATW_INTR_TPS; 2967 /* set ATW_NAR_HF to flush TX FIFO. */ 2968 opmode |= ATW_NAR_HF; 2969 } 2970 2971 ATW_WRITE(sc, ATW_NAR, opmode); 2972 DELAY(atw_nar_delay); 2973 2974 for (i = 0; i < 1000; i++) { 2975 stsr = ATW_READ(sc, ATW_STSR); 2976 if ((stsr & ackmask) == ackmask) 2977 break; 2978 DELAY(10); 2979 } 2980 2981 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2982 2983 if ((stsr & ackmask) == ackmask) 2984 goto out; 2985 2986 test0 = ATW_READ(sc, ATW_TEST0); 2987 2988 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2989 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2990 printf("%s: transmit process not idle [%s]\n", 2991 sc->sc_dev.dv_xname, 2992 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2993 printf("%s: bits %08x test0 %08x stsr %08x\n", 2994 sc->sc_dev.dv_xname, bits, test0, stsr); 2995 } 2996 2997 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2998 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2999 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3000 sc->sc_dev.dv_xname, 3001 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 3002 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3003 sc->sc_dev.dv_xname, bits, test0, stsr)); 3004 } 3005 out: 3006 if ((bits & ATW_NAR_ST) != 0) 3007 atw_txdrain(sc); 3008 splx(s); 3009 return; 3010 } 3011 3012 /* 3013 * atw_linkintr: 3014 * 3015 * Helper; handle link-status interrupts. 3016 */ 3017 void 3018 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3019 { 3020 struct ieee80211com *ic = &sc->sc_ic; 3021 3022 if (ic->ic_state != IEEE80211_S_RUN) 3023 return; 3024 3025 if (linkstatus & ATW_INTR_LINKON) { 3026 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3027 sc->sc_rescan_timer = 0; 3028 } else if (linkstatus & ATW_INTR_LINKOFF) { 3029 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3030 if (ic->ic_opmode != IEEE80211_M_STA) 3031 return; 3032 sc->sc_rescan_timer = 3; 3033 sc->sc_if.if_timer = 1; 3034 } 3035 } 3036 3037 static inline int 3038 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3039 { 3040 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3041 return 0; 3042 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3043 return 0; 3044 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3045 } 3046 3047 /* 3048 * atw_rxintr: 3049 * 3050 * Helper; handle receive interrupts. 3051 */ 3052 void 3053 atw_rxintr(struct atw_softc *sc) 3054 { 3055 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3056 struct ieee80211com *ic = &sc->sc_ic; 3057 struct ieee80211_node *ni; 3058 struct ieee80211_frame_min *wh; 3059 struct ifnet *ifp = &sc->sc_if; 3060 struct atw_rxsoft *rxs; 3061 struct mbuf *m; 3062 u_int32_t rxstat; 3063 int i, len, rate, rate0; 3064 u_int32_t rssi, rssi0; 3065 3066 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3067 rxs = &sc->sc_rxsoft[i]; 3068 3069 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3070 3071 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3072 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3073 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3074 3075 if (rxstat & ATW_RXSTAT_OWN) 3076 break; /* We have processed all receive buffers. */ 3077 3078 DPRINTF3(sc, 3079 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3080 sc->sc_dev.dv_xname, 3081 rxstat, rssi0, 3082 le32toh(sc->sc_rxdescs[i].ar_buf1), 3083 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3084 3085 /* 3086 * Make sure the packet fits in one buffer. This should 3087 * always be the case. 3088 */ 3089 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3090 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3091 printf("%s: incoming packet spilled, resetting\n", 3092 sc->sc_dev.dv_xname); 3093 (void)atw_init(ifp); 3094 return; 3095 } 3096 3097 /* 3098 * If an error occurred, update stats, clear the status 3099 * word, and leave the packet buffer in place. It will 3100 * simply be reused the next time the ring comes around. 3101 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3102 * error. 3103 */ 3104 3105 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3106 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3107 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3108 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3109 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3110 ATW_RXSTAT_ICVE)) != 0)) { 3111 #define PRINTERR(bit, str) \ 3112 if (rxstat & (bit)) \ 3113 printf("%s: receive error: %s\n", \ 3114 sc->sc_dev.dv_xname, str) 3115 ifp->if_ierrors++; 3116 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3117 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3118 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3119 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3120 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3121 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3122 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3123 #undef PRINTERR 3124 ATW_INIT_RXDESC(sc, i); 3125 continue; 3126 } 3127 3128 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3129 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3130 3131 /* 3132 * No errors; receive the packet. Note the ADM8211 3133 * includes the CRC in promiscuous mode. 3134 */ 3135 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3136 3137 /* 3138 * Allocate a new mbuf cluster. If that fails, we are 3139 * out of memory, and must drop the packet and recycle 3140 * the buffer that's already attached to this descriptor. 3141 */ 3142 m = rxs->rxs_mbuf; 3143 if (atw_add_rxbuf(sc, i) != 0) { 3144 ifp->if_ierrors++; 3145 ATW_INIT_RXDESC(sc, i); 3146 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3147 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3148 continue; 3149 } 3150 3151 ifp->if_ipackets++; 3152 if (sc->sc_opmode & ATW_NAR_PR) 3153 len -= IEEE80211_CRC_LEN; 3154 m->m_pkthdr.rcvif = ifp; 3155 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3156 3157 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3158 rate = 0; 3159 else 3160 rate = rate_tbl[rate0]; 3161 3162 /* The RSSI comes straight from a register in the 3163 * baseband processor. I know that for the RF3000, 3164 * the RSSI register also contains the antenna-selection 3165 * bits. Mask those off. 3166 * 3167 * TBD Treat other basebands. 3168 */ 3169 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3170 rssi = rssi0 & RF3000_RSSI_MASK; 3171 else 3172 rssi = rssi0; 3173 3174 #if NBPFILTER > 0 3175 /* Pass this up to any BPF listeners. */ 3176 if (sc->sc_radiobpf != NULL) { 3177 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3178 3179 tap->ar_rate = rate; 3180 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3181 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3182 3183 /* TBD verify units are dB */ 3184 tap->ar_antsignal = (int)rssi; 3185 /* TBD tap->ar_flags */ 3186 3187 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3188 tap->ar_ihdr.it_len, m); 3189 } 3190 #endif /* NPBFILTER > 0 */ 3191 3192 wh = mtod(m, struct ieee80211_frame_min *); 3193 ni = ieee80211_find_rxnode(ic, wh); 3194 if (atw_hw_decrypted(sc, wh)) { 3195 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3196 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3197 } 3198 ieee80211_input(ic, m, ni, (int)rssi, 0); 3199 ieee80211_free_node(ni); 3200 } 3201 3202 /* Update the receive pointer. */ 3203 sc->sc_rxptr = i; 3204 } 3205 3206 /* 3207 * atw_txintr: 3208 * 3209 * Helper; handle transmit interrupts. 3210 */ 3211 void 3212 atw_txintr(struct atw_softc *sc) 3213 { 3214 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3215 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3216 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3217 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3218 3219 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3220 struct ifnet *ifp = &sc->sc_if; 3221 struct atw_txsoft *txs; 3222 u_int32_t txstat; 3223 3224 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3225 sc->sc_dev.dv_xname, sc->sc_flags)); 3226 3227 /* 3228 * Go through our Tx list and free mbufs for those 3229 * frames that have been transmitted. 3230 */ 3231 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3232 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3233 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3234 3235 #ifdef ATW_DEBUG 3236 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3237 int i; 3238 printf(" txsoft %p transmit chain:\n", txs); 3239 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3240 txs->txs_ndescs - 1, 3241 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3242 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3243 printf(" descriptor %d:\n", i); 3244 printf(" at_status: 0x%08x\n", 3245 le32toh(sc->sc_txdescs[i].at_stat)); 3246 printf(" at_flags: 0x%08x\n", 3247 le32toh(sc->sc_txdescs[i].at_flags)); 3248 printf(" at_buf1: 0x%08x\n", 3249 le32toh(sc->sc_txdescs[i].at_buf1)); 3250 printf(" at_buf2: 0x%08x\n", 3251 le32toh(sc->sc_txdescs[i].at_buf2)); 3252 if (i == txs->txs_lastdesc) 3253 break; 3254 } 3255 } 3256 #endif 3257 3258 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3259 if (txstat & ATW_TXSTAT_OWN) 3260 break; 3261 3262 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3263 3264 sc->sc_txfree += txs->txs_ndescs; 3265 3266 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3267 0, txs->txs_dmamap->dm_mapsize, 3268 BUS_DMASYNC_POSTWRITE); 3269 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3270 m_freem(txs->txs_mbuf); 3271 txs->txs_mbuf = NULL; 3272 3273 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3274 3275 ifp->if_flags &= ~IFF_OACTIVE; 3276 3277 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3278 (txstat & TXSTAT_ERRMASK) != 0) { 3279 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3280 txstat_buf, sizeof(txstat_buf)); 3281 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3282 txstat_buf, 3283 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3284 } 3285 3286 /* 3287 * Check for errors and collisions. 3288 */ 3289 if (txstat & ATW_TXSTAT_TUF) 3290 sc->sc_stats.ts_tx_tuf++; 3291 if (txstat & ATW_TXSTAT_TLT) 3292 sc->sc_stats.ts_tx_tlt++; 3293 if (txstat & ATW_TXSTAT_TRT) 3294 sc->sc_stats.ts_tx_trt++; 3295 if (txstat & ATW_TXSTAT_TRO) 3296 sc->sc_stats.ts_tx_tro++; 3297 if (txstat & ATW_TXSTAT_SOFBR) { 3298 sc->sc_stats.ts_tx_sofbr++; 3299 } 3300 3301 if ((txstat & ATW_TXSTAT_ES) == 0) 3302 ifp->if_collisions += 3303 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3304 else 3305 ifp->if_oerrors++; 3306 3307 ifp->if_opackets++; 3308 } 3309 3310 /* 3311 * If there are no more pending transmissions, cancel the watchdog 3312 * timer. 3313 */ 3314 if (txs == NULL) 3315 sc->sc_tx_timer = 0; 3316 #undef TXSTAT_ERRMASK 3317 #undef TXSTAT_FMT 3318 } 3319 3320 /* 3321 * atw_watchdog: [ifnet interface function] 3322 * 3323 * Watchdog timer handler. 3324 */ 3325 void 3326 atw_watchdog(struct ifnet *ifp) 3327 { 3328 struct atw_softc *sc = ifp->if_softc; 3329 struct ieee80211com *ic = &sc->sc_ic; 3330 3331 ifp->if_timer = 0; 3332 if (ATW_IS_ENABLED(sc) == 0) 3333 return; 3334 3335 if (sc->sc_rescan_timer) { 3336 if (--sc->sc_rescan_timer == 0) 3337 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3338 } 3339 if (sc->sc_tx_timer) { 3340 if (--sc->sc_tx_timer == 0 && 3341 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3342 printf("%s: transmit timeout\n", ifp->if_xname); 3343 ifp->if_oerrors++; 3344 (void)atw_init(ifp); 3345 atw_start(ifp); 3346 } 3347 } 3348 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3349 ifp->if_timer = 1; 3350 ieee80211_watchdog(ic); 3351 } 3352 3353 /* Compute the 802.11 Duration field and the PLCP Length fields for 3354 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3355 * Write the fields to the ADM8211 Tx header, frm. 3356 * 3357 * TBD use the fragmentation threshold to find the right duration for 3358 * the first & last fragments. 3359 * 3360 * TBD make certain of the duration fields applied by the ADM8211 to each 3361 * fragment. I think that the ADM8211 knows how to subtract the CTS 3362 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3363 * I also think that the ADM8211 does *some* arithmetic for us, because 3364 * otherwise I think we would have to set a first duration for CTS/first 3365 * fragment, a second duration for fragments between the first and the 3366 * last, and a third duration for the last fragment. 3367 * 3368 * TBD make certain that duration fields reflect addition of FCS/WEP 3369 * and correct duration arithmetic as necessary. 3370 */ 3371 static void 3372 atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3373 int len) 3374 { 3375 int remainder; 3376 3377 /* deal also with encrypted fragments */ 3378 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3379 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3380 sc->sc_dev.dv_xname)); 3381 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3382 IEEE80211_WEP_CRCLEN; 3383 } 3384 3385 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3386 * duration (XXX added by MAC?). 3387 */ 3388 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3389 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3390 3391 if (rate <= 4) 3392 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3393 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3394 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3395 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3396 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3397 else 3398 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3399 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3400 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3401 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3402 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3403 3404 /* lengthen duration if long preamble */ 3405 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3406 frm->atw_head_dur += 3407 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3408 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3409 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3410 IEEE80211_DUR_DS_FAST_PLCPHDR); 3411 3412 if (remainder != 0) 3413 frm->atw_head_dur++; 3414 3415 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3416 (rate == 2 || rate == 4)) { 3417 /* derived from Linux: how could this be right? */ 3418 frm->atw_head_plcplen = frm->atw_head_dur; 3419 } else { 3420 frm->atw_head_plcplen = (16 * len) / rate; 3421 remainder = (80 * len) % (rate * 5); 3422 3423 if (remainder != 0) { 3424 frm->atw_head_plcplen++; 3425 3426 /* XXX magic */ 3427 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3428 rate == 22 && remainder <= 30) 3429 frm->atw_head_plcplen |= 0x8000; 3430 } 3431 } 3432 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3433 htole16(frm->atw_head_plcplen); 3434 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3435 } 3436 3437 #ifdef ATW_DEBUG 3438 static void 3439 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3440 { 3441 struct atw_softc *sc = ifp->if_softc; 3442 struct mbuf *m; 3443 int i, noctets = 0; 3444 3445 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3446 m0->m_pkthdr.len); 3447 3448 for (m = m0; m; m = m->m_next) { 3449 if (m->m_len == 0) 3450 continue; 3451 for (i = 0; i < m->m_len; i++) { 3452 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3453 if (++noctets % 24 == 0) 3454 printf("\n"); 3455 } 3456 } 3457 printf("%s%s: %d bytes emitted\n", 3458 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3459 } 3460 #endif /* ATW_DEBUG */ 3461 3462 /* 3463 * atw_start: [ifnet interface function] 3464 * 3465 * Start packet transmission on the interface. 3466 */ 3467 void 3468 atw_start(struct ifnet *ifp) 3469 { 3470 struct atw_softc *sc = ifp->if_softc; 3471 struct ieee80211com *ic = &sc->sc_ic; 3472 struct ieee80211_node *ni; 3473 struct ieee80211_frame *wh; 3474 struct atw_frame *hh; 3475 struct mbuf *m0, *m; 3476 struct atw_txsoft *txs, *last_txs; 3477 struct atw_txdesc *txd; 3478 int do_encrypt, rate; 3479 bus_dmamap_t dmamap; 3480 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3481 3482 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3483 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3484 3485 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3486 return; 3487 3488 /* 3489 * Remember the previous number of free descriptors and 3490 * the first descriptor we'll use. 3491 */ 3492 ofree = sc->sc_txfree; 3493 firsttx = sc->sc_txnext; 3494 3495 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3496 sc->sc_dev.dv_xname, ofree, firsttx)); 3497 3498 /* 3499 * Loop through the send queue, setting up transmit descriptors 3500 * until we drain the queue, or use up all available transmit 3501 * descriptors. 3502 */ 3503 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3504 sc->sc_txfree != 0) { 3505 3506 /* 3507 * Grab a packet off the management queue, if it 3508 * is not empty. Otherwise, from the data queue. 3509 */ 3510 IF_DEQUEUE(&ic->ic_mgtq, m0); 3511 if (m0 != NULL) { 3512 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3513 m0->m_pkthdr.rcvif = NULL; 3514 } else { 3515 /* send no data packets until we are associated */ 3516 if (ic->ic_state != IEEE80211_S_RUN) 3517 break; 3518 IFQ_DEQUEUE(&ifp->if_snd, m0); 3519 if (m0 == NULL) 3520 break; 3521 #if NBPFILTER > 0 3522 if (ifp->if_bpf != NULL) 3523 bpf_mtap(ifp->if_bpf, m0); 3524 #endif /* NBPFILTER > 0 */ 3525 ni = ieee80211_find_txnode(ic, 3526 mtod(m0, struct ether_header *)->ether_dhost); 3527 if (ni == NULL) { 3528 ifp->if_oerrors++; 3529 break; 3530 } 3531 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3532 ieee80211_free_node(ni); 3533 ifp->if_oerrors++; 3534 break; 3535 } 3536 } 3537 3538 rate = MAX(ieee80211_get_rate(ic), 2); 3539 3540 #if NBPFILTER > 0 3541 /* 3542 * Pass the packet to any BPF listeners. 3543 */ 3544 if (ic->ic_rawbpf != NULL) 3545 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3546 3547 if (sc->sc_radiobpf != NULL) { 3548 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3549 3550 tap->at_rate = rate; 3551 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3552 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3553 3554 /* TBD tap->at_flags */ 3555 3556 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3557 tap->at_ihdr.it_len, m0); 3558 } 3559 #endif /* NBPFILTER > 0 */ 3560 3561 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3562 3563 if (ni != NULL) 3564 ieee80211_free_node(ni); 3565 3566 if (m0 == NULL) { 3567 ifp->if_oerrors++; 3568 break; 3569 } 3570 3571 /* just to make sure. */ 3572 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3573 3574 if (m0 == NULL) { 3575 ifp->if_oerrors++; 3576 break; 3577 } 3578 3579 hh = mtod(m0, struct atw_frame *); 3580 wh = &hh->atw_ihdr; 3581 3582 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3583 3584 /* Copy everything we need from the 802.11 header: 3585 * Frame Control; address 1, address 3, or addresses 3586 * 3 and 4. NIC fills in BSSID, SA. 3587 */ 3588 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3589 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3590 panic("%s: illegal WDS frame", 3591 sc->sc_dev.dv_xname); 3592 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3593 } else 3594 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3595 3596 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3597 3598 /* initialize remaining Tx parameters */ 3599 memset(&hh->u, 0, sizeof(hh->u)); 3600 3601 hh->atw_rate = rate * 5; 3602 /* XXX this could be incorrect if M_FCS. _encap should 3603 * probably strip FCS just in case it sticks around in 3604 * bridged packets. 3605 */ 3606 hh->atw_service = 0x00; /* XXX guess */ 3607 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3608 sizeof(struct atw_frame)); 3609 3610 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3611 hh->atw_rtylmt = 3; 3612 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3613 if (do_encrypt) { 3614 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3615 hh->atw_keyid = ic->ic_def_txkey; 3616 } 3617 3618 /* TBD 4-addr frames */ 3619 atw_frame_setdurs(sc, hh, rate, 3620 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3621 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3622 3623 /* never fragment multicast frames */ 3624 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3625 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3626 } else if (sc->sc_flags & ATWF_RTSCTS) { 3627 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3628 } 3629 3630 #ifdef ATW_DEBUG 3631 hh->atw_fragnum = 0; 3632 3633 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3634 printf("%s: dst = %s, rate = 0x%02x, " 3635 "service = 0x%02x, paylen = 0x%04x\n", 3636 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3637 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3638 3639 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3640 "dur1 = 0x%04x, dur2 = 0x%04x, " 3641 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3642 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3643 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3644 hh->atw_tail_dur, hh->atw_head_dur); 3645 3646 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3647 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3648 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3649 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3650 3651 printf("%s: keyid = %d\n", 3652 sc->sc_dev.dv_xname, hh->atw_keyid); 3653 3654 atw_dump_pkt(ifp, m0); 3655 } 3656 #endif /* ATW_DEBUG */ 3657 3658 dmamap = txs->txs_dmamap; 3659 3660 /* 3661 * Load the DMA map. Copy and try (once) again if the packet 3662 * didn't fit in the alloted number of segments. 3663 */ 3664 for (first = 1; 3665 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3666 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3667 first = 0) { 3668 MGETHDR(m, M_DONTWAIT, MT_DATA); 3669 if (m == NULL) { 3670 printf("%s: unable to allocate Tx mbuf\n", 3671 sc->sc_dev.dv_xname); 3672 break; 3673 } 3674 if (m0->m_pkthdr.len > MHLEN) { 3675 MCLGET(m, M_DONTWAIT); 3676 if ((m->m_flags & M_EXT) == 0) { 3677 printf("%s: unable to allocate Tx " 3678 "cluster\n", sc->sc_dev.dv_xname); 3679 m_freem(m); 3680 break; 3681 } 3682 } 3683 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3684 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3685 m_freem(m0); 3686 m0 = m; 3687 m = NULL; 3688 } 3689 if (error != 0) { 3690 printf("%s: unable to load Tx buffer, " 3691 "error = %d\n", sc->sc_dev.dv_xname, error); 3692 m_freem(m0); 3693 break; 3694 } 3695 3696 /* 3697 * Ensure we have enough descriptors free to describe 3698 * the packet. 3699 */ 3700 if (dmamap->dm_nsegs > sc->sc_txfree) { 3701 /* 3702 * Not enough free descriptors to transmit 3703 * this packet. Unload the DMA map and 3704 * drop the packet. Notify the upper layer 3705 * that there are no more slots left. 3706 * 3707 * XXX We could allocate an mbuf and copy, but 3708 * XXX it is worth it? 3709 */ 3710 bus_dmamap_unload(sc->sc_dmat, dmamap); 3711 m_freem(m0); 3712 break; 3713 } 3714 3715 /* 3716 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3717 */ 3718 3719 /* Sync the DMA map. */ 3720 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3721 BUS_DMASYNC_PREWRITE); 3722 3723 /* XXX arbitrary retry limit; 8 because I have seen it in 3724 * use already and maybe 0 means "no tries" ! 3725 */ 3726 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3727 3728 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3729 sc->sc_dev.dv_xname, rate * 5)); 3730 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3731 3732 /* 3733 * Initialize the transmit descriptors. 3734 */ 3735 for (nexttx = sc->sc_txnext, seg = 0; 3736 seg < dmamap->dm_nsegs; 3737 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3738 /* 3739 * If this is the first descriptor we're 3740 * enqueueing, don't set the OWN bit just 3741 * yet. That could cause a race condition. 3742 * We'll do it below. 3743 */ 3744 txd = &sc->sc_txdescs[nexttx]; 3745 txd->at_ctl = ctl | 3746 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3747 3748 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3749 txd->at_flags = 3750 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3751 ATW_TXFLAG_TBS1_MASK)) | 3752 ((nexttx == (ATW_NTXDESC - 1)) 3753 ? htole32(ATW_TXFLAG_TER) : 0); 3754 lasttx = nexttx; 3755 } 3756 3757 IASSERT(lasttx != -1, ("bad lastx")); 3758 /* Set `first segment' and `last segment' appropriately. */ 3759 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3760 htole32(ATW_TXFLAG_FS); 3761 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3762 3763 #ifdef ATW_DEBUG 3764 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3765 printf(" txsoft %p transmit chain:\n", txs); 3766 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3767 printf(" descriptor %d:\n", seg); 3768 printf(" at_ctl: 0x%08x\n", 3769 le32toh(sc->sc_txdescs[seg].at_ctl)); 3770 printf(" at_flags: 0x%08x\n", 3771 le32toh(sc->sc_txdescs[seg].at_flags)); 3772 printf(" at_buf1: 0x%08x\n", 3773 le32toh(sc->sc_txdescs[seg].at_buf1)); 3774 printf(" at_buf2: 0x%08x\n", 3775 le32toh(sc->sc_txdescs[seg].at_buf2)); 3776 if (seg == lasttx) 3777 break; 3778 } 3779 } 3780 #endif 3781 3782 /* Sync the descriptors we're using. */ 3783 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3784 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3785 3786 /* 3787 * Store a pointer to the packet so we can free it later, 3788 * and remember what txdirty will be once the packet is 3789 * done. 3790 */ 3791 txs->txs_mbuf = m0; 3792 txs->txs_firstdesc = sc->sc_txnext; 3793 txs->txs_lastdesc = lasttx; 3794 txs->txs_ndescs = dmamap->dm_nsegs; 3795 3796 /* Advance the tx pointer. */ 3797 sc->sc_txfree -= dmamap->dm_nsegs; 3798 sc->sc_txnext = nexttx; 3799 3800 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3801 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3802 3803 last_txs = txs; 3804 } 3805 3806 if (txs == NULL || sc->sc_txfree == 0) { 3807 /* No more slots left; notify upper layer. */ 3808 ifp->if_flags |= IFF_OACTIVE; 3809 } 3810 3811 if (sc->sc_txfree != ofree) { 3812 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3813 sc->sc_dev.dv_xname, lasttx, firsttx)); 3814 /* 3815 * Cause a transmit interrupt to happen on the 3816 * last packet we enqueued. 3817 */ 3818 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3819 ATW_CDTXSYNC(sc, lasttx, 1, 3820 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3821 3822 /* 3823 * The entire packet chain is set up. Give the 3824 * first descriptor to the chip now. 3825 */ 3826 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3827 ATW_CDTXSYNC(sc, firsttx, 1, 3828 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3829 3830 /* Wake up the transmitter. */ 3831 ATW_WRITE(sc, ATW_TDR, 0x1); 3832 3833 /* Set a watchdog timer in case the chip flakes out. */ 3834 sc->sc_tx_timer = 5; 3835 ifp->if_timer = 1; 3836 } 3837 } 3838 3839 /* 3840 * atw_power: 3841 * 3842 * Power management (suspend/resume) hook. 3843 */ 3844 void 3845 atw_power(int why, void *arg) 3846 { 3847 struct atw_softc *sc = arg; 3848 struct ifnet *ifp = &sc->sc_if; 3849 int s; 3850 3851 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3852 3853 s = splnet(); 3854 switch (why) { 3855 case PWR_STANDBY: 3856 /* XXX do nothing. */ 3857 break; 3858 case PWR_SUSPEND: 3859 atw_stop(ifp, 0); 3860 if (sc->sc_power != NULL) 3861 (*sc->sc_power)(sc, why); 3862 break; 3863 case PWR_RESUME: 3864 if (ifp->if_flags & IFF_UP) { 3865 if (sc->sc_power != NULL) 3866 (*sc->sc_power)(sc, why); 3867 atw_init(ifp); 3868 } 3869 break; 3870 case PWR_SOFTSUSPEND: 3871 case PWR_SOFTSTANDBY: 3872 case PWR_SOFTRESUME: 3873 break; 3874 } 3875 splx(s); 3876 } 3877 3878 /* 3879 * atw_ioctl: [ifnet interface function] 3880 * 3881 * Handle control requests from the operator. 3882 */ 3883 int 3884 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3885 { 3886 struct atw_softc *sc = ifp->if_softc; 3887 struct ifreq *ifr = (struct ifreq *)data; 3888 int s, error = 0; 3889 3890 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3891 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3892 return ENXIO; 3893 3894 s = splnet(); 3895 3896 switch (cmd) { 3897 case SIOCSIFFLAGS: 3898 if (ifp->if_flags & IFF_UP) { 3899 if (ATW_IS_ENABLED(sc)) { 3900 /* 3901 * To avoid rescanning another access point, 3902 * do not call atw_init() here. Instead, 3903 * only reflect media settings. 3904 */ 3905 atw_filter_setup(sc); 3906 } else 3907 error = atw_init(ifp); 3908 } else if (ATW_IS_ENABLED(sc)) 3909 atw_stop(ifp, 1); 3910 break; 3911 case SIOCADDMULTI: 3912 case SIOCDELMULTI: 3913 error = (cmd == SIOCADDMULTI) ? 3914 ether_addmulti(ifr, &sc->sc_ec) : 3915 ether_delmulti(ifr, &sc->sc_ec); 3916 if (error == ENETRESET) { 3917 if (ifp->if_flags & IFF_RUNNING) 3918 atw_filter_setup(sc); /* do not rescan */ 3919 error = 0; 3920 } 3921 break; 3922 default: 3923 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3924 if (error == ENETRESET) { 3925 if (ATW_IS_ENABLED(sc)) 3926 error = atw_init(ifp); 3927 else 3928 error = 0; 3929 } 3930 break; 3931 } 3932 3933 /* Try to get more packets going. */ 3934 if (ATW_IS_ENABLED(sc)) 3935 atw_start(ifp); 3936 3937 splx(s); 3938 return (error); 3939 } 3940 3941 static int 3942 atw_media_change(struct ifnet *ifp) 3943 { 3944 int error; 3945 3946 error = ieee80211_media_change(ifp); 3947 if (error == ENETRESET) { 3948 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3949 (IFF_RUNNING|IFF_UP)) 3950 atw_init(ifp); /* XXX lose error */ 3951 error = 0; 3952 } 3953 return error; 3954 } 3955 3956 static void 3957 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3958 { 3959 struct atw_softc *sc = ifp->if_softc; 3960 3961 if (ATW_IS_ENABLED(sc) == 0) { 3962 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3963 imr->ifm_status = 0; 3964 return; 3965 } 3966 ieee80211_media_status(ifp, imr); 3967 } 3968
Indexes created Wed Sep 24 15:09:51 GMT 2025