atw.c revision 1.94
1 /* $NetBSD: atw.c,v 1.94 2005/12/29 21:32:06 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.94 2005/12/29 21:32:06 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 static void atw_media_status(struct ifnet *, struct ifmediareq *); 266 267 static void atw_filter_setup(struct atw_softc *); 268 269 /* 802.11 utilities */ 270 static uint64_t atw_get_tsft(struct atw_softc *); 271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 272 uint32_t); 273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 274 static void atw_node_free(struct ieee80211_node *); 275 static void atw_change_ibss(struct atw_softc *); 276 277 /* 278 * Tuner/transceiver/modem 279 */ 280 static void atw_bbp_io_enable(struct atw_softc *, int); 281 282 /* RFMD RF3000 Baseband Processor */ 283 static int atw_rf3000_init(struct atw_softc *); 284 static int atw_rf3000_tune(struct atw_softc *, u_int); 285 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 286 287 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 288 static void atw_si4126_tune(struct atw_softc *, u_int); 289 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 290 291 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 292 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 293 294 const char *atw_tx_state[] = { 295 "STOPPED", 296 "RUNNING - read descriptor", 297 "RUNNING - transmitting", 298 "RUNNING - filling fifo", /* XXX */ 299 "SUSPENDED", 300 "RUNNING -- write descriptor", 301 "RUNNING -- write last descriptor", 302 "RUNNING - fifo full" 303 }; 304 305 const char *atw_rx_state[] = { 306 "STOPPED", 307 "RUNNING - read descriptor", 308 "RUNNING - check this packet, pre-fetch next", 309 "RUNNING - wait for reception", 310 "SUSPENDED", 311 "RUNNING - write descriptor", 312 "RUNNING - flush fifo", 313 "RUNNING - fifo drain" 314 }; 315 316 int 317 atw_activate(struct device *self, enum devact act) 318 { 319 struct atw_softc *sc = (struct atw_softc *)self; 320 int rv = 0, s; 321 322 s = splnet(); 323 switch (act) { 324 case DVACT_ACTIVATE: 325 rv = EOPNOTSUPP; 326 break; 327 328 case DVACT_DEACTIVATE: 329 if_deactivate(&sc->sc_if); 330 break; 331 } 332 splx(s); 333 return rv; 334 } 335 336 /* 337 * atw_enable: 338 * 339 * Enable the ADM8211 chip. 340 */ 341 int 342 atw_enable(struct atw_softc *sc) 343 { 344 345 if (ATW_IS_ENABLED(sc) == 0) { 346 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 347 printf("%s: device enable failed\n", 348 sc->sc_dev.dv_xname); 349 return (EIO); 350 } 351 sc->sc_flags |= ATWF_ENABLED; 352 } 353 return (0); 354 } 355 356 /* 357 * atw_disable: 358 * 359 * Disable the ADM8211 chip. 360 */ 361 void 362 atw_disable(struct atw_softc *sc) 363 { 364 if (!ATW_IS_ENABLED(sc)) 365 return; 366 if (sc->sc_disable != NULL) 367 (*sc->sc_disable)(sc); 368 sc->sc_flags &= ~ATWF_ENABLED; 369 } 370 371 /* Returns -1 on failure. */ 372 static int 373 atw_read_srom(struct atw_softc *sc) 374 { 375 struct seeprom_descriptor sd; 376 uint32_t test0, fail_bits; 377 378 (void)memset(&sd, 0, sizeof(sd)); 379 380 test0 = ATW_READ(sc, ATW_TEST0); 381 382 switch (sc->sc_rev) { 383 case ATW_REVISION_BA: 384 case ATW_REVISION_CA: 385 fail_bits = ATW_TEST0_EPNE; 386 break; 387 default: 388 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 389 break; 390 } 391 if ((test0 & fail_bits) != 0) { 392 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 393 return -1; 394 } 395 396 switch (test0 & ATW_TEST0_EPTYP_MASK) { 397 case ATW_TEST0_EPTYP_93c66: 398 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 399 sc->sc_sromsz = 512; 400 sd.sd_chip = C56_66; 401 break; 402 case ATW_TEST0_EPTYP_93c46: 403 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 404 sc->sc_sromsz = 128; 405 sd.sd_chip = C46; 406 break; 407 default: 408 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 409 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 410 return -1; 411 } 412 413 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 414 415 if (sc->sc_srom == NULL) { 416 printf("%s: unable to allocate SROM buffer\n", 417 sc->sc_dev.dv_xname); 418 return -1; 419 } 420 421 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 422 423 /* ADM8211 has a single 32-bit register for controlling the 424 * 93cx6 SROM. Bit SRS enables the serial port. There is no 425 * "ready" bit. The ADM8211 input/output sense is the reverse 426 * of read_seeprom's. 427 */ 428 sd.sd_tag = sc->sc_st; 429 sd.sd_bsh = sc->sc_sh; 430 sd.sd_regsize = 4; 431 sd.sd_control_offset = ATW_SPR; 432 sd.sd_status_offset = ATW_SPR; 433 sd.sd_dataout_offset = ATW_SPR; 434 sd.sd_CK = ATW_SPR_SCLK; 435 sd.sd_CS = ATW_SPR_SCS; 436 sd.sd_DI = ATW_SPR_SDO; 437 sd.sd_DO = ATW_SPR_SDI; 438 sd.sd_MS = ATW_SPR_SRS; 439 sd.sd_RDY = 0; 440 441 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 442 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 443 free(sc->sc_srom, M_DEVBUF); 444 return -1; 445 } 446 #ifdef ATW_DEBUG 447 { 448 int i; 449 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 450 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 451 if (((i % 8) == 0) && (i != 0)) { 452 ATW_DPRINTF(("\n\t")); 453 } 454 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 455 } 456 ATW_DPRINTF(("\n")); 457 } 458 #endif /* ATW_DEBUG */ 459 return 0; 460 } 461 462 #ifdef ATW_DEBUG 463 static void 464 atw_print_regs(struct atw_softc *sc, const char *where) 465 { 466 #define PRINTREG(sc, reg) \ 467 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 468 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 469 470 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 471 472 PRINTREG(sc, ATW_PAR); 473 PRINTREG(sc, ATW_FRCTL); 474 PRINTREG(sc, ATW_TDR); 475 PRINTREG(sc, ATW_WTDP); 476 PRINTREG(sc, ATW_RDR); 477 PRINTREG(sc, ATW_WRDP); 478 PRINTREG(sc, ATW_RDB); 479 PRINTREG(sc, ATW_CSR3A); 480 PRINTREG(sc, ATW_TDBD); 481 PRINTREG(sc, ATW_TDBP); 482 PRINTREG(sc, ATW_STSR); 483 PRINTREG(sc, ATW_CSR5A); 484 PRINTREG(sc, ATW_NAR); 485 PRINTREG(sc, ATW_CSR6A); 486 PRINTREG(sc, ATW_IER); 487 PRINTREG(sc, ATW_CSR7A); 488 PRINTREG(sc, ATW_LPC); 489 PRINTREG(sc, ATW_TEST1); 490 PRINTREG(sc, ATW_SPR); 491 PRINTREG(sc, ATW_TEST0); 492 PRINTREG(sc, ATW_WCSR); 493 PRINTREG(sc, ATW_WPDR); 494 PRINTREG(sc, ATW_GPTMR); 495 PRINTREG(sc, ATW_GPIO); 496 PRINTREG(sc, ATW_BBPCTL); 497 PRINTREG(sc, ATW_SYNCTL); 498 PRINTREG(sc, ATW_PLCPHD); 499 PRINTREG(sc, ATW_MMIWADDR); 500 PRINTREG(sc, ATW_MMIRADDR1); 501 PRINTREG(sc, ATW_MMIRADDR2); 502 PRINTREG(sc, ATW_TXBR); 503 PRINTREG(sc, ATW_CSR15A); 504 PRINTREG(sc, ATW_ALCSTAT); 505 PRINTREG(sc, ATW_TOFS2); 506 PRINTREG(sc, ATW_CMDR); 507 PRINTREG(sc, ATW_PCIC); 508 PRINTREG(sc, ATW_PMCSR); 509 PRINTREG(sc, ATW_PAR0); 510 PRINTREG(sc, ATW_PAR1); 511 PRINTREG(sc, ATW_MAR0); 512 PRINTREG(sc, ATW_MAR1); 513 PRINTREG(sc, ATW_ATIMDA0); 514 PRINTREG(sc, ATW_ABDA1); 515 PRINTREG(sc, ATW_BSSID0); 516 PRINTREG(sc, ATW_TXLMT); 517 PRINTREG(sc, ATW_MIBCNT); 518 PRINTREG(sc, ATW_BCNT); 519 PRINTREG(sc, ATW_TSFTH); 520 PRINTREG(sc, ATW_TSC); 521 PRINTREG(sc, ATW_SYNRF); 522 PRINTREG(sc, ATW_BPLI); 523 PRINTREG(sc, ATW_CAP0); 524 PRINTREG(sc, ATW_CAP1); 525 PRINTREG(sc, ATW_RMD); 526 PRINTREG(sc, ATW_CFPP); 527 PRINTREG(sc, ATW_TOFS0); 528 PRINTREG(sc, ATW_TOFS1); 529 PRINTREG(sc, ATW_IFST); 530 PRINTREG(sc, ATW_RSPT); 531 PRINTREG(sc, ATW_TSFTL); 532 PRINTREG(sc, ATW_WEPCTL); 533 PRINTREG(sc, ATW_WESK); 534 PRINTREG(sc, ATW_WEPCNT); 535 PRINTREG(sc, ATW_MACTEST); 536 PRINTREG(sc, ATW_FER); 537 PRINTREG(sc, ATW_FEMR); 538 PRINTREG(sc, ATW_FPSR); 539 PRINTREG(sc, ATW_FFER); 540 #undef PRINTREG 541 } 542 #endif /* ATW_DEBUG */ 543 544 /* 545 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 546 */ 547 void 548 atw_attach(struct atw_softc *sc) 549 { 550 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 552 }; 553 struct ieee80211com *ic = &sc->sc_ic; 554 struct ifnet *ifp = &sc->sc_if; 555 int country_code, error, i, nrate, srom_major; 556 u_int32_t reg; 557 static const char *type_strings[] = {"Intersil (not supported)", 558 "RFMD", "Marvel (not supported)"}; 559 560 sc->sc_txth = atw_txthresh_tab_lo; 561 562 SIMPLEQ_INIT(&sc->sc_txfreeq); 563 SIMPLEQ_INIT(&sc->sc_txdirtyq); 564 565 #ifdef ATW_DEBUG 566 atw_print_regs(sc, "atw_attach"); 567 #endif /* ATW_DEBUG */ 568 569 /* 570 * Allocate the control data structures, and create and load the 571 * DMA map for it. 572 */ 573 if ((error = bus_dmamem_alloc(sc->sc_dmat, 574 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 575 1, &sc->sc_cdnseg, 0)) != 0) { 576 printf("%s: unable to allocate control data, error = %d\n", 577 sc->sc_dev.dv_xname, error); 578 goto fail_0; 579 } 580 581 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 582 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 583 BUS_DMA_COHERENT)) != 0) { 584 printf("%s: unable to map control data, error = %d\n", 585 sc->sc_dev.dv_xname, error); 586 goto fail_1; 587 } 588 589 if ((error = bus_dmamap_create(sc->sc_dmat, 590 sizeof(struct atw_control_data), 1, 591 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 592 printf("%s: unable to create control data DMA map, " 593 "error = %d\n", sc->sc_dev.dv_xname, error); 594 goto fail_2; 595 } 596 597 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 598 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 599 0)) != 0) { 600 printf("%s: unable to load control data DMA map, error = %d\n", 601 sc->sc_dev.dv_xname, error); 602 goto fail_3; 603 } 604 605 /* 606 * Create the transmit buffer DMA maps. 607 */ 608 sc->sc_ntxsegs = ATW_NTXSEGS; 609 for (i = 0; i < ATW_TXQUEUELEN; i++) { 610 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 611 sc->sc_ntxsegs, MCLBYTES, 0, 0, 612 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 613 printf("%s: unable to create tx DMA map %d, " 614 "error = %d\n", sc->sc_dev.dv_xname, i, error); 615 goto fail_4; 616 } 617 } 618 619 /* 620 * Create the receive buffer DMA maps. 621 */ 622 for (i = 0; i < ATW_NRXDESC; i++) { 623 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 624 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 625 printf("%s: unable to create rx DMA map %d, " 626 "error = %d\n", sc->sc_dev.dv_xname, i, error); 627 goto fail_5; 628 } 629 } 630 for (i = 0; i < ATW_NRXDESC; i++) { 631 sc->sc_rxsoft[i].rxs_mbuf = NULL; 632 } 633 634 switch (sc->sc_rev) { 635 case ATW_REVISION_AB: 636 case ATW_REVISION_AF: 637 sc->sc_sramlen = ATW_SRAM_A_SIZE; 638 break; 639 case ATW_REVISION_BA: 640 case ATW_REVISION_CA: 641 sc->sc_sramlen = ATW_SRAM_B_SIZE; 642 break; 643 } 644 645 /* Reset the chip to a known state. */ 646 atw_reset(sc); 647 648 if (atw_read_srom(sc) == -1) 649 return; 650 651 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 652 ATW_SR_RFTYPE_MASK); 653 654 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 655 ATW_SR_BBPTYPE_MASK); 656 657 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 658 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 659 return; 660 } 661 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 662 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 663 return; 664 } 665 666 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 667 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 668 669 /* XXX There exists a Linux driver which seems to use RFType = 0 for 670 * MARVEL. My bug, or theirs? 671 */ 672 673 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 674 675 switch (sc->sc_rftype) { 676 case ATW_RFTYPE_INTERSIL: 677 reg |= ATW_SYNCTL_CS1; 678 break; 679 case ATW_RFTYPE_RFMD: 680 reg |= ATW_SYNCTL_CS0; 681 break; 682 case ATW_RFTYPE_MARVEL: 683 break; 684 } 685 686 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 687 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 688 689 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 690 691 switch (sc->sc_bbptype) { 692 case ATW_BBPTYPE_INTERSIL: 693 reg |= ATW_BBPCTL_TWI; 694 break; 695 case ATW_BBPTYPE_RFMD: 696 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 697 ATW_BBPCTL_CCA_ACTLO; 698 break; 699 case ATW_BBPTYPE_MARVEL: 700 break; 701 case ATW_C_BBPTYPE_RFMD: 702 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 703 sc->sc_dev.dv_xname); 704 break; 705 } 706 707 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 708 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 709 710 /* 711 * From this point forward, the attachment cannot fail. A failure 712 * before this point releases all resources that may have been 713 * allocated. 714 */ 715 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 716 717 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 718 htole16(sc->sc_srom[ATW_SR_MAC00]), 719 htole16(sc->sc_srom[ATW_SR_MAC01]), 720 htole16(sc->sc_srom[ATW_SR_MAC10]))); 721 722 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 723 ATW_SR_MAJOR_MASK); 724 725 if (srom_major < 2) 726 sc->sc_rf3000_options1 = 0; 727 else if (sc->sc_rev == ATW_REVISION_BA) { 728 sc->sc_rf3000_options1 = 729 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 730 ATW_SR_CR28_MASK); 731 } else 732 sc->sc_rf3000_options1 = 0; 733 734 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 735 ATW_SR_CR29_MASK); 736 737 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 738 ATW_SR_CTRY_MASK); 739 740 #define ADD_CHANNEL(_ic, _chan) do { \ 741 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 742 _ic->ic_channels[_chan].ic_freq = \ 743 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 744 } while (0) 745 746 /* Find available channels */ 747 switch (country_code) { 748 case COUNTRY_MMK2: /* 1-14 */ 749 ADD_CHANNEL(ic, 14); 750 /*FALLTHROUGH*/ 751 case COUNTRY_ETSI: /* 1-13 */ 752 for (i = 1; i <= 13; i++) 753 ADD_CHANNEL(ic, i); 754 break; 755 case COUNTRY_FCC: /* 1-11 */ 756 case COUNTRY_IC: /* 1-11 */ 757 for (i = 1; i <= 11; i++) 758 ADD_CHANNEL(ic, i); 759 break; 760 case COUNTRY_MMK: /* 14 */ 761 ADD_CHANNEL(ic, 14); 762 break; 763 case COUNTRY_FRANCE: /* 10-13 */ 764 for (i = 10; i <= 13; i++) 765 ADD_CHANNEL(ic, i); 766 break; 767 default: /* assume channels 10-11 */ 768 case COUNTRY_SPAIN: /* 10-11 */ 769 for (i = 10; i <= 11; i++) 770 ADD_CHANNEL(ic, i); 771 break; 772 } 773 774 /* Read the MAC address. */ 775 reg = ATW_READ(sc, ATW_PAR0); 776 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 777 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 778 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 779 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 780 reg = ATW_READ(sc, ATW_PAR1); 781 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 782 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 783 784 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 785 printf(" could not get mac address, attach failed\n"); 786 return; 787 } 788 789 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 790 791 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 792 ifp->if_softc = sc; 793 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 794 IFF_NOTRAILERS; 795 ifp->if_ioctl = atw_ioctl; 796 ifp->if_start = atw_start; 797 ifp->if_watchdog = atw_watchdog; 798 ifp->if_init = atw_init; 799 ifp->if_stop = atw_stop; 800 IFQ_SET_READY(&ifp->if_snd); 801 802 ic->ic_ifp = ifp; 803 ic->ic_phytype = IEEE80211_T_DS; 804 ic->ic_opmode = IEEE80211_M_STA; 805 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 806 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 807 808 nrate = 0; 809 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 810 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 811 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 813 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 814 815 /* 816 * Call MI attach routines. 817 */ 818 819 if_attach(ifp); 820 ieee80211_ifattach(ic); 821 822 sc->sc_newstate = ic->ic_newstate; 823 ic->ic_newstate = atw_newstate; 824 825 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 826 ic->ic_recv_mgmt = atw_recv_mgmt; 827 828 sc->sc_node_free = ic->ic_node_free; 829 ic->ic_node_free = atw_node_free; 830 831 sc->sc_node_alloc = ic->ic_node_alloc; 832 ic->ic_node_alloc = atw_node_alloc; 833 834 ic->ic_crypto.cs_key_delete = atw_key_delete; 835 ic->ic_crypto.cs_key_set = atw_key_set; 836 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 837 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 838 839 /* possibly we should fill in our own sc_send_prresp, since 840 * the ADM8211 is probably sending probe responses in ad hoc 841 * mode. 842 */ 843 844 /* complete initialization */ 845 ieee80211_media_init(ic, atw_media_change, atw_media_status); 846 callout_init(&sc->sc_scan_ch); 847 848 #if NBPFILTER > 0 849 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 850 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 851 #endif 852 853 /* 854 * Make sure the interface is shutdown during reboot. 855 */ 856 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 857 if (sc->sc_sdhook == NULL) 858 printf("%s: WARNING: unable to establish shutdown hook\n", 859 sc->sc_dev.dv_xname); 860 861 /* 862 * Add a suspend hook to make sure we come back up after a 863 * resume. 864 */ 865 sc->sc_powerhook = powerhook_establish(atw_power, sc); 866 if (sc->sc_powerhook == NULL) 867 printf("%s: WARNING: unable to establish power hook\n", 868 sc->sc_dev.dv_xname); 869 870 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 871 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 872 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 873 874 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 875 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 876 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 877 878 ieee80211_announce(ic); 879 return; 880 881 /* 882 * Free any resources we've allocated during the failed attach 883 * attempt. Do this in reverse order and fall through. 884 */ 885 fail_5: 886 for (i = 0; i < ATW_NRXDESC; i++) { 887 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 888 continue; 889 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 890 } 891 fail_4: 892 for (i = 0; i < ATW_TXQUEUELEN; i++) { 893 if (sc->sc_txsoft[i].txs_dmamap == NULL) 894 continue; 895 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 896 } 897 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 898 fail_3: 899 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 900 fail_2: 901 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 902 sizeof(struct atw_control_data)); 903 fail_1: 904 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 905 fail_0: 906 return; 907 } 908 909 static struct ieee80211_node * 910 atw_node_alloc(struct ieee80211_node_table *nt) 911 { 912 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 913 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 914 915 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 916 return ni; 917 } 918 919 static void 920 atw_node_free(struct ieee80211_node *ni) 921 { 922 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 923 924 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 925 ether_sprintf(ni->ni_bssid))); 926 (*sc->sc_node_free)(ni); 927 } 928 929 930 static void 931 atw_test1_reset(struct atw_softc *sc) 932 { 933 switch (sc->sc_rev) { 934 case ATW_REVISION_BA: 935 if (1 /* XXX condition on transceiver type */) { 936 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 937 } 938 break; 939 case ATW_REVISION_CA: 940 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 941 break; 942 default: 943 break; 944 } 945 } 946 947 /* 948 * atw_reset: 949 * 950 * Perform a soft reset on the ADM8211. 951 */ 952 void 953 atw_reset(struct atw_softc *sc) 954 { 955 int i; 956 uint32_t lpc; 957 958 ATW_WRITE(sc, ATW_NAR, 0x0); 959 DELAY(atw_nar_delay); 960 961 /* Reference driver has a cryptic remark indicating that this might 962 * power-on the chip. I know that it turns off power-saving.... 963 */ 964 ATW_WRITE(sc, ATW_FRCTL, 0x0); 965 966 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 967 968 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 969 if (ATW_READ(sc, ATW_PAR) == 0) 970 break; 971 DELAY(atw_pseudo_milli); 972 } 973 974 /* ... and then pause 100ms longer for good measure. */ 975 DELAY(atw_magic_delay1); 976 977 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 978 979 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 980 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 981 982 atw_test1_reset(sc); 983 /* 984 * Initialize the PCI Access Register. 985 */ 986 sc->sc_busmode = ATW_PAR_PBL_8DW; 987 988 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 989 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 990 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 991 992 /* Turn off maximum power saving, etc. 993 * 994 * XXX Following example of reference driver, should I set 995 * an AID of 1? It didn't seem to help.... 996 */ 997 ATW_WRITE(sc, ATW_FRCTL, 0x0); 998 999 DELAY(atw_magic_delay2); 1000 1001 /* Recall EEPROM. */ 1002 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1003 1004 DELAY(atw_magic_delay4); 1005 1006 lpc = ATW_READ(sc, ATW_LPC); 1007 1008 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1009 1010 /* A reset seems to affect the SRAM contents, so put them into 1011 * a known state. 1012 */ 1013 atw_clear_sram(sc); 1014 1015 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1016 } 1017 1018 static void 1019 atw_clear_sram(struct atw_softc *sc) 1020 { 1021 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1022 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1023 /* XXX not for revision 0x20. */ 1024 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1025 } 1026 1027 /* TBD atw_init 1028 * 1029 * set MAC based on ic->ic_bss->myaddr 1030 * write WEP keys 1031 * set TX rate 1032 */ 1033 1034 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1035 * without receiving a beacon with the preferred BSSID & SSID. 1036 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1037 */ 1038 static void 1039 atw_wcsr_init(struct atw_softc *sc) 1040 { 1041 uint32_t wcsr; 1042 1043 wcsr = ATW_READ(sc, ATW_WCSR); 1044 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1045 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1046 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1047 1048 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1049 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1050 } 1051 1052 /* Turn off power management. Set Rx store-and-forward mode. */ 1053 static void 1054 atw_cmdr_init(struct atw_softc *sc) 1055 { 1056 uint32_t cmdr; 1057 cmdr = ATW_READ(sc, ATW_CMDR); 1058 cmdr &= ~ATW_CMDR_APM; 1059 cmdr |= ATW_CMDR_RTE; 1060 cmdr &= ~ATW_CMDR_DRT_MASK; 1061 cmdr |= ATW_CMDR_DRT_SF; 1062 1063 ATW_WRITE(sc, ATW_CMDR, cmdr); 1064 } 1065 1066 static void 1067 atw_tofs2_init(struct atw_softc *sc) 1068 { 1069 uint32_t tofs2; 1070 /* XXX this magic can probably be figured out from the RFMD docs */ 1071 #ifndef ATW_REFSLAVE 1072 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1073 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1074 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1075 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1076 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1077 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1078 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1079 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1080 #else 1081 /* XXX new magic from reference driver source */ 1082 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1083 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1084 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1085 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1086 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1087 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1088 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1089 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1090 #endif 1091 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1092 } 1093 1094 static void 1095 atw_nar_init(struct atw_softc *sc) 1096 { 1097 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1098 } 1099 1100 static void 1101 atw_txlmt_init(struct atw_softc *sc) 1102 { 1103 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1104 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1105 } 1106 1107 static void 1108 atw_test1_init(struct atw_softc *sc) 1109 { 1110 uint32_t test1; 1111 1112 test1 = ATW_READ(sc, ATW_TEST1); 1113 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1114 /* XXX magic 0x1 */ 1115 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1116 ATW_WRITE(sc, ATW_TEST1, test1); 1117 } 1118 1119 static void 1120 atw_rf_reset(struct atw_softc *sc) 1121 { 1122 /* XXX this resets an Intersil RF front-end? */ 1123 /* TBD condition on Intersil RFType? */ 1124 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1125 DELAY(atw_rf_delay1); 1126 ATW_WRITE(sc, ATW_SYNRF, 0); 1127 DELAY(atw_rf_delay2); 1128 } 1129 1130 /* Set 16 TU max duration for the contention-free period (CFP). */ 1131 static void 1132 atw_cfp_init(struct atw_softc *sc) 1133 { 1134 uint32_t cfpp; 1135 1136 cfpp = ATW_READ(sc, ATW_CFPP); 1137 cfpp &= ~ATW_CFPP_CFPMD; 1138 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1139 ATW_WRITE(sc, ATW_CFPP, cfpp); 1140 } 1141 1142 static void 1143 atw_tofs0_init(struct atw_softc *sc) 1144 { 1145 /* XXX I guess that the Cardbus clock is 22MHz? 1146 * I am assuming that the role of ATW_TOFS0_USCNT is 1147 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1148 * very clear on this point. It says in the datasheet that it is 1149 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1150 * and 33MHz; maybe this is the way? I see a binary-only driver write 1151 * these values. These values are also the power-on default. 1152 */ 1153 ATW_WRITE(sc, ATW_TOFS0, 1154 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1155 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1156 } 1157 1158 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1159 static void 1160 atw_ifs_init(struct atw_softc *sc) 1161 { 1162 uint32_t ifst; 1163 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1164 * Go figure. 1165 */ 1166 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1167 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1168 ATW_IFST_SIFS_MASK) | 1169 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1170 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1171 1172 ATW_WRITE(sc, ATW_IFST, ifst); 1173 } 1174 1175 static void 1176 atw_response_times_init(struct atw_softc *sc) 1177 { 1178 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1179 * indicate that the MAC expects at least SIFS + MIRT microseconds 1180 * to pass after it transmits a frame that requires a response; 1181 * it waits at most SIFS + MART microseconds for the response. 1182 * Surely this is not the ACK timeout? 1183 */ 1184 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1185 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1186 } 1187 1188 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1189 * engines read and write baseband registers after Rx and before 1190 * Tx, respectively. 1191 */ 1192 static void 1193 atw_bbp_io_init(struct atw_softc *sc) 1194 { 1195 uint32_t mmiraddr2; 1196 1197 /* XXX The reference driver does this, but is it *really* 1198 * necessary? 1199 */ 1200 switch (sc->sc_rev) { 1201 case ATW_REVISION_AB: 1202 case ATW_REVISION_AF: 1203 mmiraddr2 = 0x0; 1204 break; 1205 default: 1206 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1207 mmiraddr2 &= 1208 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1209 break; 1210 } 1211 1212 switch (sc->sc_bbptype) { 1213 case ATW_BBPTYPE_INTERSIL: 1214 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1215 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1216 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1217 break; 1218 case ATW_BBPTYPE_MARVEL: 1219 /* TBD find out the Marvel settings. */ 1220 break; 1221 case ATW_BBPTYPE_RFMD: 1222 default: 1223 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1224 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1225 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1226 break; 1227 } 1228 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1229 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1230 } 1231 1232 /* 1233 * atw_init: [ ifnet interface function ] 1234 * 1235 * Initialize the interface. Must be called at splnet(). 1236 */ 1237 int 1238 atw_init(struct ifnet *ifp) 1239 { 1240 struct atw_softc *sc = ifp->if_softc; 1241 struct ieee80211com *ic = &sc->sc_ic; 1242 struct atw_txsoft *txs; 1243 struct atw_rxsoft *rxs; 1244 int i, error = 0; 1245 1246 if ((error = atw_enable(sc)) != 0) 1247 goto out; 1248 1249 /* 1250 * Cancel any pending I/O. This also resets. 1251 */ 1252 atw_stop(ifp, 0); 1253 1254 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1255 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1256 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1257 1258 atw_wcsr_init(sc); 1259 1260 atw_cmdr_init(sc); 1261 1262 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1263 * 1264 * XXX Set transmit power for ATIM, RTS, Beacon. 1265 */ 1266 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1267 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1268 1269 atw_tofs2_init(sc); 1270 1271 atw_nar_init(sc); 1272 1273 atw_txlmt_init(sc); 1274 1275 atw_test1_init(sc); 1276 1277 atw_rf_reset(sc); 1278 1279 atw_cfp_init(sc); 1280 1281 atw_tofs0_init(sc); 1282 1283 atw_ifs_init(sc); 1284 1285 /* XXX Fall asleep after one second of inactivity. 1286 * XXX A frame may only dribble in for 65536us. 1287 */ 1288 ATW_WRITE(sc, ATW_RMD, 1289 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1290 1291 atw_response_times_init(sc); 1292 1293 atw_bbp_io_init(sc); 1294 1295 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1296 1297 if ((error = atw_rf3000_init(sc)) != 0) 1298 goto out; 1299 1300 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1301 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1302 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1303 1304 /* 1305 * Initialize the transmit descriptor ring. 1306 */ 1307 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1308 for (i = 0; i < ATW_NTXDESC; i++) { 1309 sc->sc_txdescs[i].at_ctl = 0; 1310 /* no transmit chaining */ 1311 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1312 sc->sc_txdescs[i].at_buf2 = 1313 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1314 } 1315 /* use ring mode */ 1316 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1317 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1318 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1319 sc->sc_txfree = ATW_NTXDESC; 1320 sc->sc_txnext = 0; 1321 1322 /* 1323 * Initialize the transmit job descriptors. 1324 */ 1325 SIMPLEQ_INIT(&sc->sc_txfreeq); 1326 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1327 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1328 txs = &sc->sc_txsoft[i]; 1329 txs->txs_mbuf = NULL; 1330 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1331 } 1332 1333 /* 1334 * Initialize the receive descriptor and receive job 1335 * descriptor rings. 1336 */ 1337 for (i = 0; i < ATW_NRXDESC; i++) { 1338 rxs = &sc->sc_rxsoft[i]; 1339 if (rxs->rxs_mbuf == NULL) { 1340 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1341 printf("%s: unable to allocate or map rx " 1342 "buffer %d, error = %d\n", 1343 sc->sc_dev.dv_xname, i, error); 1344 /* 1345 * XXX Should attempt to run with fewer receive 1346 * XXX buffers instead of just failing. 1347 */ 1348 atw_rxdrain(sc); 1349 goto out; 1350 } 1351 } else 1352 ATW_INIT_RXDESC(sc, i); 1353 } 1354 sc->sc_rxptr = 0; 1355 1356 /* 1357 * Initialize the interrupt mask and enable interrupts. 1358 */ 1359 /* normal interrupts */ 1360 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1361 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1362 1363 /* abnormal interrupts */ 1364 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1365 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1366 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1367 1368 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1369 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1370 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1371 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1372 ATW_INTR_TRT; 1373 1374 sc->sc_linkint_mask &= sc->sc_inten; 1375 sc->sc_rxint_mask &= sc->sc_inten; 1376 sc->sc_txint_mask &= sc->sc_inten; 1377 1378 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1379 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1380 1381 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1382 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1383 1384 /* 1385 * Give the transmit and receive rings to the ADM8211. 1386 */ 1387 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1388 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1389 1390 sc->sc_txthresh = 0; 1391 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1392 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1393 1394 /* common 802.11 configuration */ 1395 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1396 switch (ic->ic_opmode) { 1397 case IEEE80211_M_STA: 1398 break; 1399 case IEEE80211_M_AHDEMO: /* XXX */ 1400 case IEEE80211_M_IBSS: 1401 ic->ic_flags |= IEEE80211_F_IBSSON; 1402 /*FALLTHROUGH*/ 1403 case IEEE80211_M_HOSTAP: /* XXX */ 1404 break; 1405 case IEEE80211_M_MONITOR: /* XXX */ 1406 break; 1407 } 1408 1409 switch (ic->ic_opmode) { 1410 case IEEE80211_M_AHDEMO: 1411 case IEEE80211_M_HOSTAP: 1412 #ifndef IEEE80211_NO_HOSTAP 1413 ic->ic_bss->ni_intval = ic->ic_lintval; 1414 ic->ic_bss->ni_rssi = 0; 1415 ic->ic_bss->ni_rstamp = 0; 1416 #endif /* !IEEE80211_NO_HOSTAP */ 1417 break; 1418 default: /* XXX */ 1419 break; 1420 } 1421 1422 sc->sc_wepctl = 0; 1423 1424 atw_write_ssid(sc); 1425 atw_write_sup_rates(sc); 1426 atw_write_wep(sc); 1427 1428 ic->ic_state = IEEE80211_S_INIT; 1429 1430 /* 1431 * Set the receive filter. This will start the transmit and 1432 * receive processes. 1433 */ 1434 atw_filter_setup(sc); 1435 1436 /* 1437 * Start the receive process. 1438 */ 1439 ATW_WRITE(sc, ATW_RDR, 0x1); 1440 1441 /* 1442 * Note that the interface is now running. 1443 */ 1444 ifp->if_flags |= IFF_RUNNING; 1445 ifp->if_flags &= ~IFF_OACTIVE; 1446 1447 /* send no beacons, yet. */ 1448 atw_start_beacon(sc, 0); 1449 1450 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1451 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1452 else 1453 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1454 out: 1455 if (error) { 1456 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1457 sc->sc_tx_timer = 0; 1458 ifp->if_timer = 0; 1459 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1460 } 1461 #ifdef ATW_DEBUG 1462 atw_print_regs(sc, "end of init"); 1463 #endif /* ATW_DEBUG */ 1464 1465 return (error); 1466 } 1467 1468 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1469 * 0: MAC control of RF3000/Si4126. 1470 * 1471 * Applies power, or selects RF front-end? Sets reset condition. 1472 * 1473 * TBD support non-RFMD BBP, non-SiLabs synth. 1474 */ 1475 static void 1476 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1477 { 1478 if (enable) { 1479 ATW_WRITE(sc, ATW_SYNRF, 1480 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1481 DELAY(atw_bbp_io_enable_delay); 1482 } else { 1483 ATW_WRITE(sc, ATW_SYNRF, 0); 1484 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1485 } 1486 } 1487 1488 static int 1489 atw_tune(struct atw_softc *sc) 1490 { 1491 int rc; 1492 u_int chan; 1493 struct ieee80211com *ic = &sc->sc_ic; 1494 1495 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1496 if (chan == IEEE80211_CHAN_ANY) 1497 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1498 1499 if (chan == sc->sc_cur_chan) 1500 return 0; 1501 1502 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1503 sc->sc_cur_chan, chan)); 1504 1505 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1506 1507 atw_si4126_tune(sc, chan); 1508 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1509 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1510 chan); 1511 1512 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1513 DELAY(atw_nar_delay); 1514 ATW_WRITE(sc, ATW_RDR, 0x1); 1515 1516 if (rc == 0) 1517 sc->sc_cur_chan = chan; 1518 1519 return rc; 1520 } 1521 1522 #ifdef ATW_SYNDEBUG 1523 static void 1524 atw_si4126_print(struct atw_softc *sc) 1525 { 1526 struct ifnet *ifp = &sc->sc_if; 1527 u_int addr, val; 1528 1529 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1530 return; 1531 1532 for (addr = 0; addr <= 8; addr++) { 1533 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1534 if (atw_si4126_read(sc, addr, &val) == 0) { 1535 printf("<unknown> (quitting print-out)\n"); 1536 break; 1537 } 1538 printf("%05x\n", val); 1539 } 1540 } 1541 #endif /* ATW_SYNDEBUG */ 1542 1543 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1544 * 1545 * The RF/IF synthesizer produces two reference frequencies for 1546 * the RF2948B transceiver. The first frequency the RF2948B requires 1547 * is two times the so-called "intermediate frequency" (IF). Since 1548 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1549 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1550 * frequency required by the transceiver is the radio frequency 1551 * (RF). This is a superheterodyne transceiver; for f(chan) the 1552 * center frequency of the channel we are tuning, RF = f(chan) - 1553 * IF. 1554 * 1555 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1556 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1557 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1558 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1559 */ 1560 static void 1561 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1562 { 1563 u_int mhz; 1564 u_int R; 1565 u_int32_t gpio; 1566 u_int16_t gain; 1567 1568 #ifdef ATW_SYNDEBUG 1569 atw_si4126_print(sc); 1570 #endif /* ATW_SYNDEBUG */ 1571 1572 if (chan == 14) 1573 mhz = 2484; 1574 else 1575 mhz = 2412 + 5 * (chan - 1); 1576 1577 /* Tune IF to 748MHz to suit the IF LO input of the 1578 * RF2494B, which is 2 x IF. No need to set an IF divider 1579 * because an IF in 526MHz - 952MHz is allowed. 1580 * 1581 * XIN is 44.000MHz, so divide it by two to get allowable 1582 * range of 2-25MHz. SiLabs tells me that this is not 1583 * strictly necessary. 1584 */ 1585 1586 if (atw_xindiv2) 1587 R = 44; 1588 else 1589 R = 88; 1590 1591 /* Power-up RF, IF synthesizers. */ 1592 atw_si4126_write(sc, SI4126_POWER, 1593 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1594 1595 /* set LPWR, too? */ 1596 atw_si4126_write(sc, SI4126_MAIN, 1597 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1598 1599 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1600 * set KP2 to 1. 1601 * 1602 * REFDIF This is different from the reference driver, which 1603 * always sets SI4126_GAIN to 0. 1604 */ 1605 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1606 1607 atw_si4126_write(sc, SI4126_GAIN, gain); 1608 1609 /* XIN = 44MHz. 1610 * 1611 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1612 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1613 * 1614 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1615 * so that 1496/88 * 44MHz = 748MHz. 1616 */ 1617 atw_si4126_write(sc, SI4126_IFN, 1496); 1618 1619 atw_si4126_write(sc, SI4126_IFR, R); 1620 1621 #ifndef ATW_REFSLAVE 1622 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1623 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1624 * which has no RF1! 1625 */ 1626 atw_si4126_write(sc, SI4126_RF1R, R); 1627 1628 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1629 #endif 1630 1631 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1632 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1633 * Now let's multiply it to mhz. So mhz - IF = N. 1634 */ 1635 atw_si4126_write(sc, SI4126_RF2R, R); 1636 1637 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1638 1639 /* wait 100us from power-up for RF, IF to settle */ 1640 DELAY(100); 1641 1642 gpio = ATW_READ(sc, ATW_GPIO); 1643 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1644 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1645 1646 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1647 /* Set a Prism RF front-end to a special mode for channel 14? 1648 * 1649 * Apparently the SMC2635W needs this, although I don't think 1650 * it has a Prism RF. 1651 */ 1652 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1653 } 1654 ATW_WRITE(sc, ATW_GPIO, gpio); 1655 1656 #ifdef ATW_SYNDEBUG 1657 atw_si4126_print(sc); 1658 #endif /* ATW_SYNDEBUG */ 1659 } 1660 1661 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1662 * diversity. 1663 * 1664 * !!! 1665 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1666 * !!! 1667 */ 1668 static int 1669 atw_rf3000_init(struct atw_softc *sc) 1670 { 1671 int rc = 0; 1672 1673 atw_bbp_io_enable(sc, 1); 1674 1675 /* CCA is acquisition sensitive */ 1676 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1677 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1678 1679 if (rc != 0) 1680 goto out; 1681 1682 /* enable diversity */ 1683 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1684 1685 if (rc != 0) 1686 goto out; 1687 1688 /* sensible setting from a binary-only driver */ 1689 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1690 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1691 1692 if (rc != 0) 1693 goto out; 1694 1695 /* magic from a binary-only driver */ 1696 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1697 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1698 1699 if (rc != 0) 1700 goto out; 1701 1702 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1703 1704 if (rc != 0) 1705 goto out; 1706 1707 /* XXX Reference driver remarks that Abocom sets this to 50. 1708 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1709 * in the "reserved" area of register RF3000_OPTIONS1. 1710 */ 1711 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1712 1713 if (rc != 0) 1714 goto out; 1715 1716 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1717 1718 if (rc != 0) 1719 goto out; 1720 1721 out: 1722 atw_bbp_io_enable(sc, 0); 1723 return rc; 1724 } 1725 1726 #ifdef ATW_BBPDEBUG 1727 static void 1728 atw_rf3000_print(struct atw_softc *sc) 1729 { 1730 struct ifnet *ifp = &sc->sc_if; 1731 u_int addr, val; 1732 1733 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1734 return; 1735 1736 for (addr = 0x01; addr <= 0x15; addr++) { 1737 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1738 if (atw_rf3000_read(sc, addr, &val) != 0) { 1739 printf("<unknown> (quitting print-out)\n"); 1740 break; 1741 } 1742 printf("%08x\n", val); 1743 } 1744 } 1745 #endif /* ATW_BBPDEBUG */ 1746 1747 /* Set the power settings on the BBP for channel `chan'. */ 1748 static int 1749 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1750 { 1751 int rc = 0; 1752 u_int32_t reg; 1753 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1754 1755 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1756 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1757 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1758 1759 /* odd channels: LSB, even channels: MSB */ 1760 if (chan % 2 == 1) { 1761 txpower &= 0xFF; 1762 lpf_cutoff &= 0xFF; 1763 lna_gs_thresh &= 0xFF; 1764 } else { 1765 txpower >>= 8; 1766 lpf_cutoff >>= 8; 1767 lna_gs_thresh >>= 8; 1768 } 1769 1770 #ifdef ATW_BBPDEBUG 1771 atw_rf3000_print(sc); 1772 #endif /* ATW_BBPDEBUG */ 1773 1774 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1775 "lna_gs_thresh %02x\n", 1776 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1777 1778 atw_bbp_io_enable(sc, 1); 1779 1780 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1781 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1782 goto out; 1783 1784 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1785 goto out; 1786 1787 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1788 goto out; 1789 1790 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1791 1792 if (rc != 0) 1793 goto out; 1794 1795 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1796 1797 if (rc != 0) 1798 goto out; 1799 1800 #ifdef ATW_BBPDEBUG 1801 atw_rf3000_print(sc); 1802 #endif /* ATW_BBPDEBUG */ 1803 1804 out: 1805 atw_bbp_io_enable(sc, 0); 1806 1807 /* set beacon, rts, atim transmit power */ 1808 reg = ATW_READ(sc, ATW_PLCPHD); 1809 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1810 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1811 ATW_PLCPHD_SERVICE_MASK); 1812 ATW_WRITE(sc, ATW_PLCPHD, reg); 1813 DELAY(atw_plcphd_delay); 1814 1815 return rc; 1816 } 1817 1818 /* Write a register on the RF3000 baseband processor using the 1819 * registers provided by the ADM8211 for this purpose. 1820 * 1821 * Return 0 on success. 1822 */ 1823 static int 1824 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1825 { 1826 u_int32_t reg; 1827 int i; 1828 1829 reg = sc->sc_bbpctl_wr | 1830 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1831 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1832 1833 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1834 ATW_WRITE(sc, ATW_BBPCTL, reg); 1835 DELAY(2 * atw_pseudo_milli); 1836 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1837 break; 1838 } 1839 1840 if (i < 0) { 1841 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1842 return ETIMEDOUT; 1843 } 1844 return 0; 1845 } 1846 1847 /* Read a register on the RF3000 baseband processor using the registers 1848 * the ADM8211 provides for this purpose. 1849 * 1850 * The 7-bit register address is addr. Record the 8-bit data in the register 1851 * in *val. 1852 * 1853 * Return 0 on success. 1854 * 1855 * XXX This does not seem to work. The ADM8211 must require more or 1856 * different magic to read the chip than to write it. Possibly some 1857 * of the magic I have derived from a binary-only driver concerns 1858 * the "chip address" (see the RF3000 manual). 1859 */ 1860 #ifdef ATW_BBPDEBUG 1861 static int 1862 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1863 { 1864 u_int32_t reg; 1865 int i; 1866 1867 for (i = 1000; --i >= 0; ) { 1868 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1869 break; 1870 DELAY(100); 1871 } 1872 1873 if (i < 0) { 1874 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1875 sc->sc_dev.dv_xname); 1876 return ETIMEDOUT; 1877 } 1878 1879 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1880 1881 ATW_WRITE(sc, ATW_BBPCTL, reg); 1882 1883 for (i = 1000; --i >= 0; ) { 1884 DELAY(100); 1885 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1886 break; 1887 } 1888 1889 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1890 1891 if (i < 0) { 1892 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1893 sc->sc_dev.dv_xname, reg); 1894 return ETIMEDOUT; 1895 } 1896 if (val != NULL) 1897 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1898 return 0; 1899 } 1900 #endif /* ATW_BBPDEBUG */ 1901 1902 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1903 * provided by the ADM8211 for that purpose. 1904 * 1905 * val is 18 bits of data, and val is the 4-bit address of the register. 1906 * 1907 * Return 0 on success. 1908 */ 1909 static void 1910 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1911 { 1912 uint32_t bits, mask, reg; 1913 const int nbits = 22; 1914 1915 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1916 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1917 1918 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1919 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1920 1921 reg = ATW_SYNRF_SELSYN; 1922 /* reference driver: reset Si4126 serial bus to initial 1923 * conditions? 1924 */ 1925 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1926 ATW_WRITE(sc, ATW_SYNRF, reg); 1927 1928 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1929 if ((bits & mask) != 0) 1930 reg |= ATW_SYNRF_SYNDATA; 1931 else 1932 reg &= ~ATW_SYNRF_SYNDATA; 1933 ATW_WRITE(sc, ATW_SYNRF, reg); 1934 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1935 ATW_WRITE(sc, ATW_SYNRF, reg); 1936 } 1937 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1938 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1939 } 1940 1941 /* Read 18-bit data from the 4-bit address addr in Si4126 1942 * RF synthesizer and write the data to *val. Return 0 on success. 1943 * 1944 * XXX This does not seem to work. The ADM8211 must require more or 1945 * different magic to read the chip than to write it. 1946 */ 1947 #ifdef ATW_SYNDEBUG 1948 static int 1949 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1950 { 1951 u_int32_t reg; 1952 int i; 1953 1954 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1955 1956 for (i = 1000; --i >= 0; ) { 1957 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1958 break; 1959 DELAY(100); 1960 } 1961 1962 if (i < 0) { 1963 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1964 sc->sc_dev.dv_xname); 1965 return ETIMEDOUT; 1966 } 1967 1968 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1969 1970 ATW_WRITE(sc, ATW_SYNCTL, reg); 1971 1972 for (i = 1000; --i >= 0; ) { 1973 DELAY(100); 1974 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1975 break; 1976 } 1977 1978 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1979 1980 if (i < 0) { 1981 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1982 sc->sc_dev.dv_xname, reg); 1983 return ETIMEDOUT; 1984 } 1985 if (val != NULL) 1986 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1987 ATW_SYNCTL_DATA_MASK); 1988 return 0; 1989 } 1990 #endif /* ATW_SYNDEBUG */ 1991 1992 /* XXX is the endianness correct? test. */ 1993 #define atw_calchash(addr) \ 1994 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1995 1996 /* 1997 * atw_filter_setup: 1998 * 1999 * Set the ADM8211's receive filter. 2000 */ 2001 static void 2002 atw_filter_setup(struct atw_softc *sc) 2003 { 2004 struct ieee80211com *ic = &sc->sc_ic; 2005 struct ethercom *ec = &sc->sc_ec; 2006 struct ifnet *ifp = &sc->sc_if; 2007 int hash; 2008 u_int32_t hashes[2]; 2009 struct ether_multi *enm; 2010 struct ether_multistep step; 2011 2012 /* According to comments in tlp_al981_filter_setup 2013 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2014 * multicast filter to be set while it is running. Hopefully 2015 * the ADM8211 is not the same! 2016 */ 2017 if ((ifp->if_flags & IFF_RUNNING) != 0) 2018 atw_idle(sc, ATW_NAR_SR); 2019 2020 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2021 ifp->if_flags &= ~IFF_ALLMULTI; 2022 2023 /* XXX in scan mode, do not filter packets. Maybe this is 2024 * unnecessary. 2025 */ 2026 if (ic->ic_state == IEEE80211_S_SCAN || 2027 (ifp->if_flags & IFF_PROMISC) != 0) { 2028 sc->sc_opmode |= ATW_NAR_PR; 2029 goto allmulti; 2030 } 2031 2032 hashes[0] = hashes[1] = 0x0; 2033 2034 /* 2035 * Program the 64-bit multicast hash filter. 2036 */ 2037 ETHER_FIRST_MULTI(step, ec, enm); 2038 while (enm != NULL) { 2039 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2040 ETHER_ADDR_LEN) != 0) 2041 goto allmulti; 2042 2043 hash = atw_calchash(enm->enm_addrlo); 2044 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2045 ETHER_NEXT_MULTI(step, enm); 2046 sc->sc_opmode |= ATW_NAR_MM; 2047 } 2048 ifp->if_flags &= ~IFF_ALLMULTI; 2049 goto setit; 2050 2051 allmulti: 2052 sc->sc_opmode |= ATW_NAR_MM; 2053 ifp->if_flags |= IFF_ALLMULTI; 2054 hashes[0] = hashes[1] = 0xffffffff; 2055 2056 setit: 2057 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2058 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2059 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2060 DELAY(atw_nar_delay); 2061 2062 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2063 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2064 } 2065 2066 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2067 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2068 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2069 * no beacon with the preferred BSSID and SSID in the number of 2070 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2071 */ 2072 static void 2073 atw_write_bssid(struct atw_softc *sc) 2074 { 2075 struct ieee80211com *ic = &sc->sc_ic; 2076 u_int8_t *bssid; 2077 2078 bssid = ic->ic_bss->ni_bssid; 2079 2080 ATW_WRITE(sc, ATW_BSSID0, 2081 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2082 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2083 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2084 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2085 2086 ATW_WRITE(sc, ATW_ABDA1, 2087 (ATW_READ(sc, ATW_ABDA1) & 2088 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2089 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2090 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2091 2092 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2093 ether_sprintf(sc->sc_bssid))); 2094 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2095 2096 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2097 } 2098 2099 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2100 * 16-bit word. 2101 */ 2102 static void 2103 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2104 { 2105 u_int i; 2106 u_int8_t *ptr; 2107 2108 memcpy(&sc->sc_sram[ofs], buf, buflen); 2109 2110 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2111 2112 KASSERT(buflen + ofs <= sc->sc_sramlen); 2113 2114 ptr = &sc->sc_sram[ofs]; 2115 2116 for (i = 0; i < buflen; i += 2) { 2117 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2118 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2119 DELAY(atw_writewep_delay); 2120 2121 ATW_WRITE(sc, ATW_WESK, 2122 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2123 DELAY(atw_writewep_delay); 2124 } 2125 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2126 2127 if (sc->sc_if.if_flags & IFF_DEBUG) { 2128 int n_octets = 0; 2129 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2130 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2131 for (i = 0; i < buflen; i++) { 2132 printf(" %02x", ptr[i]); 2133 if (++n_octets % 24 == 0) 2134 printf("\n"); 2135 } 2136 if (n_octets % 24 != 0) 2137 printf("\n"); 2138 } 2139 } 2140 2141 static int 2142 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2143 { 2144 struct atw_softc *sc = ic->ic_ifp->if_softc; 2145 u_int keyix = k->wk_keyix; 2146 2147 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2148 2149 if (keyix >= IEEE80211_WEP_NKID) 2150 return 0; 2151 if (k->wk_keylen != 0) 2152 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2153 2154 return 1; 2155 } 2156 2157 static int 2158 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2159 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2160 { 2161 struct atw_softc *sc = ic->ic_ifp->if_softc; 2162 2163 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2164 2165 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2166 return 0; 2167 2168 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2169 2170 return 1; 2171 } 2172 2173 static void 2174 atw_key_update_begin(struct ieee80211com *ic) 2175 { 2176 #ifdef ATW_DEBUG 2177 struct ifnet *ifp = ic->ic_ifp; 2178 struct atw_softc *sc = ifp->if_softc; 2179 #endif 2180 2181 DPRINTF(sc, ("%s:\n", __func__)); 2182 } 2183 2184 static void 2185 atw_key_update_end(struct ieee80211com *ic) 2186 { 2187 struct ifnet *ifp = ic->ic_ifp; 2188 struct atw_softc *sc = ifp->if_softc; 2189 2190 DPRINTF(sc, ("%s:\n", __func__)); 2191 2192 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2193 return; 2194 if (ATW_IS_ENABLED(sc) == 0) 2195 return; 2196 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2197 atw_write_wep(sc); 2198 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2199 } 2200 2201 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2202 static void 2203 atw_write_wep(struct atw_softc *sc) 2204 { 2205 struct ieee80211com *ic = &sc->sc_ic; 2206 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2207 u_int8_t buf[IEEE80211_WEP_NKID] 2208 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2209 u_int32_t reg; 2210 int i; 2211 2212 sc->sc_wepctl = 0; 2213 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2214 2215 memset(&buf[0][0], 0, sizeof(buf)); 2216 2217 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2218 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2219 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2220 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2221 buf[i][1] = ATW_WEP_ENABLED; 2222 } else { 2223 buf[i][1] = 0; 2224 continue; 2225 } 2226 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2227 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2228 ic->ic_nw_keys[i].wk_keylen - 1); 2229 } 2230 2231 reg = ATW_READ(sc, ATW_MACTEST); 2232 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2233 reg &= ~ATW_MACTEST_KEYID_MASK; 2234 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2235 ATW_WRITE(sc, ATW_MACTEST, reg); 2236 2237 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2238 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2239 2240 switch (sc->sc_rev) { 2241 case ATW_REVISION_AB: 2242 case ATW_REVISION_AF: 2243 /* Bypass WEP on Rx. */ 2244 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2245 break; 2246 default: 2247 break; 2248 } 2249 2250 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2251 sizeof(buf)); 2252 2253 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2254 } 2255 2256 static void 2257 atw_change_ibss(struct atw_softc *sc) 2258 { 2259 atw_predict_beacon(sc); 2260 atw_write_bssid(sc); 2261 atw_start_beacon(sc, 1); 2262 } 2263 2264 static void 2265 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2266 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2267 { 2268 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2269 2270 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2271 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2272 return; 2273 2274 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2275 2276 switch (subtype) { 2277 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2278 case IEEE80211_FC0_SUBTYPE_BEACON: 2279 if (ic->ic_opmode != IEEE80211_M_IBSS || 2280 ic->ic_state != IEEE80211_S_RUN) 2281 break; 2282 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc) && 2283 ieee80211_ibss_merge(ni) == ENETRESET) 2284 atw_change_ibss(sc); 2285 break; 2286 default: 2287 break; 2288 } 2289 return; 2290 } 2291 2292 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2293 * In ad hoc mode, the SSID is written to the beacons sent by the 2294 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2295 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2296 * indications. 2297 */ 2298 static void 2299 atw_write_ssid(struct atw_softc *sc) 2300 { 2301 struct ieee80211com *ic = &sc->sc_ic; 2302 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2303 * it only expects the element length, not its ID. 2304 */ 2305 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2306 2307 memset(buf, 0, sizeof(buf)); 2308 buf[0] = ic->ic_bss->ni_esslen; 2309 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2310 2311 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2312 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2313 } 2314 2315 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2316 * In ad hoc mode, the supported rates are written to beacons sent by the 2317 * ADM8211. 2318 */ 2319 static void 2320 atw_write_sup_rates(struct atw_softc *sc) 2321 { 2322 struct ieee80211com *ic = &sc->sc_ic; 2323 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2324 * supported rates 2325 */ 2326 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2327 2328 memset(buf, 0, sizeof(buf)); 2329 2330 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2331 2332 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2333 ic->ic_bss->ni_rates.rs_nrates); 2334 2335 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2336 } 2337 2338 /* Start/stop sending beacons. */ 2339 void 2340 atw_start_beacon(struct atw_softc *sc, int start) 2341 { 2342 struct ieee80211com *ic = &sc->sc_ic; 2343 uint16_t chan; 2344 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2345 size_t len; 2346 2347 if (ATW_IS_ENABLED(sc) == 0) 2348 return; 2349 2350 /* start beacons */ 2351 len = sizeof(struct ieee80211_frame) + 2352 8 /* timestamp */ + 2 /* beacon interval */ + 2353 2 /* capability info */ + 2354 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2355 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2356 3 /* DS parameters */ + 2357 IEEE80211_CRC_LEN; 2358 2359 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2360 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2361 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2362 2363 ATW_WRITE(sc, ATW_BCNT, bcnt); 2364 ATW_WRITE(sc, ATW_CAP1, cap1); 2365 2366 if (!start) 2367 return; 2368 2369 /* TBD use ni_capinfo */ 2370 2371 capinfo = 0; 2372 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2373 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2374 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2375 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2376 2377 switch (ic->ic_opmode) { 2378 case IEEE80211_M_IBSS: 2379 len += 4; /* IBSS parameters */ 2380 capinfo |= IEEE80211_CAPINFO_IBSS; 2381 break; 2382 case IEEE80211_M_HOSTAP: 2383 /* XXX 6-byte minimum TIM */ 2384 len += atw_beacon_len_adjust; 2385 capinfo |= IEEE80211_CAPINFO_ESS; 2386 break; 2387 default: 2388 return; 2389 } 2390 2391 /* set listen interval 2392 * XXX do software units agree w/ hardware? 2393 */ 2394 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2395 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2396 2397 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2398 2399 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2400 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2401 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2402 2403 ATW_WRITE(sc, ATW_BCNT, bcnt); 2404 ATW_WRITE(sc, ATW_BPLI, bpli); 2405 ATW_WRITE(sc, ATW_CAP0, cap0); 2406 ATW_WRITE(sc, ATW_CAP1, cap1); 2407 2408 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2409 sc->sc_dev.dv_xname, bcnt)); 2410 2411 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2412 sc->sc_dev.dv_xname, cap1)); 2413 } 2414 2415 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2416 static inline uint32_t 2417 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2418 { 2419 /* Following the reference driver's lead, I compute 2420 * 2421 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2422 * 2423 * without using 64-bit arithmetic, using the following 2424 * relationship: 2425 * 2426 * (0x100000000 * H + L) % m 2427 * = ((0x100000000 % m) * H + L) % m 2428 * = (((0xffffffff + 1) % m) * H + L) % m 2429 * = ((0xffffffff % m + 1 % m) * H + L) % m 2430 * = ((0xffffffff % m + 1) * H + L) % m 2431 */ 2432 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2433 } 2434 2435 static uint64_t 2436 atw_get_tsft(struct atw_softc *sc) 2437 { 2438 int i; 2439 uint32_t tsfth, tsftl; 2440 for (i = 0; i < 2; i++) { 2441 tsfth = ATW_READ(sc, ATW_TSFTH); 2442 tsftl = ATW_READ(sc, ATW_TSFTL); 2443 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2444 break; 2445 } 2446 return ((uint64_t)tsfth << 32) | tsftl; 2447 } 2448 2449 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2450 * the ieee80211com. 2451 * 2452 * Predict the next target beacon transmission time (TBTT) and 2453 * write it to the ADM8211. 2454 */ 2455 static void 2456 atw_predict_beacon(struct atw_softc *sc) 2457 { 2458 #define TBTTOFS 20 /* TU */ 2459 2460 struct ieee80211com *ic = &sc->sc_ic; 2461 uint64_t tsft; 2462 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2463 union { 2464 uint64_t word; 2465 uint8_t tstamp[8]; 2466 } u; 2467 2468 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2469 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2470 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2471 tsft = atw_get_tsft(sc); 2472 u.word = htole64(tsft); 2473 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2474 sizeof(ic->ic_bss->ni_tstamp)); 2475 } else 2476 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2477 2478 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2479 2480 tsftl = tsft & 0xFFFFFFFF; 2481 tsfth = tsft >> 32; 2482 2483 /* We sent/received the last beacon `past' microseconds 2484 * after the interval divided the TSF timer. 2485 */ 2486 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2487 2488 /* Skip ten beacons so that the TBTT cannot pass before 2489 * we've programmed it. Ten is an arbitrary number. 2490 */ 2491 tbtt = past_even + ival * 10; 2492 2493 ATW_WRITE(sc, ATW_TOFS1, 2494 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2495 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2496 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2497 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2498 #undef TBTTOFS 2499 } 2500 2501 static void 2502 atw_next_scan(void *arg) 2503 { 2504 struct atw_softc *sc = arg; 2505 struct ieee80211com *ic = &sc->sc_ic; 2506 int s; 2507 2508 /* don't call atw_start w/o network interrupts blocked */ 2509 s = splnet(); 2510 if (ic->ic_state == IEEE80211_S_SCAN) 2511 ieee80211_next_scan(ic); 2512 splx(s); 2513 } 2514 2515 /* Synchronize the hardware state with the software state. */ 2516 static int 2517 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2518 { 2519 struct ifnet *ifp = ic->ic_ifp; 2520 struct atw_softc *sc = ifp->if_softc; 2521 enum ieee80211_state ostate; 2522 int error = 0; 2523 2524 ostate = ic->ic_state; 2525 callout_stop(&sc->sc_scan_ch); 2526 atw_start_beacon(sc, 0); 2527 2528 switch (nstate) { 2529 case IEEE80211_S_ASSOC: 2530 error = atw_tune(sc); 2531 break; 2532 case IEEE80211_S_INIT: 2533 callout_stop(&sc->sc_scan_ch); 2534 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2535 break; 2536 case IEEE80211_S_SCAN: 2537 error = atw_tune(sc); 2538 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2539 atw_next_scan, sc); 2540 break; 2541 case IEEE80211_S_AUTH: 2542 error = atw_tune(sc); 2543 break; 2544 case IEEE80211_S_RUN: 2545 error = atw_tune(sc); 2546 atw_write_bssid(sc); 2547 atw_write_ssid(sc); 2548 atw_write_sup_rates(sc); 2549 2550 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2551 ic->ic_opmode == IEEE80211_M_MONITOR) 2552 break; 2553 2554 /* set listen interval 2555 * XXX do software units agree w/ hardware? 2556 */ 2557 ATW_WRITE(sc, ATW_BPLI, 2558 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2559 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2560 ATW_BPLI_LI_MASK)); 2561 2562 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2563 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2564 2565 atw_predict_beacon(sc); 2566 atw_start_beacon(sc, 2567 ic->ic_opmode == IEEE80211_M_HOSTAP || 2568 ic->ic_opmode == IEEE80211_M_IBSS); 2569 break; 2570 } 2571 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2572 } 2573 2574 /* 2575 * atw_add_rxbuf: 2576 * 2577 * Add a receive buffer to the indicated descriptor. 2578 */ 2579 int 2580 atw_add_rxbuf(struct atw_softc *sc, int idx) 2581 { 2582 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2583 struct mbuf *m; 2584 int error; 2585 2586 MGETHDR(m, M_DONTWAIT, MT_DATA); 2587 if (m == NULL) 2588 return (ENOBUFS); 2589 2590 MCLGET(m, M_DONTWAIT); 2591 if ((m->m_flags & M_EXT) == 0) { 2592 m_freem(m); 2593 return (ENOBUFS); 2594 } 2595 2596 if (rxs->rxs_mbuf != NULL) 2597 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2598 2599 rxs->rxs_mbuf = m; 2600 2601 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2602 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2603 BUS_DMA_READ|BUS_DMA_NOWAIT); 2604 if (error) { 2605 printf("%s: can't load rx DMA map %d, error = %d\n", 2606 sc->sc_dev.dv_xname, idx, error); 2607 panic("atw_add_rxbuf"); /* XXX */ 2608 } 2609 2610 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2611 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2612 2613 ATW_INIT_RXDESC(sc, idx); 2614 2615 return (0); 2616 } 2617 2618 /* 2619 * Release any queued transmit buffers. 2620 */ 2621 void 2622 atw_txdrain(struct atw_softc *sc) 2623 { 2624 struct atw_txsoft *txs; 2625 2626 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2627 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2628 if (txs->txs_mbuf != NULL) { 2629 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2630 m_freem(txs->txs_mbuf); 2631 txs->txs_mbuf = NULL; 2632 } 2633 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2634 sc->sc_txfree += txs->txs_ndescs; 2635 } 2636 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2637 sc->sc_tx_timer = 0; 2638 } 2639 2640 /* 2641 * atw_stop: [ ifnet interface function ] 2642 * 2643 * Stop transmission on the interface. 2644 */ 2645 void 2646 atw_stop(struct ifnet *ifp, int disable) 2647 { 2648 struct atw_softc *sc = ifp->if_softc; 2649 struct ieee80211com *ic = &sc->sc_ic; 2650 2651 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2652 2653 /* Disable interrupts. */ 2654 ATW_WRITE(sc, ATW_IER, 0); 2655 2656 /* Stop the transmit and receive processes. */ 2657 sc->sc_opmode = 0; 2658 ATW_WRITE(sc, ATW_NAR, 0); 2659 DELAY(atw_nar_delay); 2660 ATW_WRITE(sc, ATW_TDBD, 0); 2661 ATW_WRITE(sc, ATW_TDBP, 0); 2662 ATW_WRITE(sc, ATW_RDB, 0); 2663 2664 atw_txdrain(sc); 2665 2666 if (disable) { 2667 atw_rxdrain(sc); 2668 atw_disable(sc); 2669 } 2670 2671 /* 2672 * Mark the interface down and cancel the watchdog timer. 2673 */ 2674 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2675 sc->sc_tx_timer = 0; 2676 ifp->if_timer = 0; 2677 2678 if (!disable) 2679 atw_reset(sc); 2680 } 2681 2682 /* 2683 * atw_rxdrain: 2684 * 2685 * Drain the receive queue. 2686 */ 2687 void 2688 atw_rxdrain(struct atw_softc *sc) 2689 { 2690 struct atw_rxsoft *rxs; 2691 int i; 2692 2693 for (i = 0; i < ATW_NRXDESC; i++) { 2694 rxs = &sc->sc_rxsoft[i]; 2695 if (rxs->rxs_mbuf == NULL) 2696 continue; 2697 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2698 m_freem(rxs->rxs_mbuf); 2699 rxs->rxs_mbuf = NULL; 2700 } 2701 } 2702 2703 /* 2704 * atw_detach: 2705 * 2706 * Detach an ADM8211 interface. 2707 */ 2708 int 2709 atw_detach(struct atw_softc *sc) 2710 { 2711 struct ifnet *ifp = &sc->sc_if; 2712 struct atw_rxsoft *rxs; 2713 struct atw_txsoft *txs; 2714 int i; 2715 2716 /* 2717 * Succeed now if there isn't any work to do. 2718 */ 2719 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2720 return (0); 2721 2722 callout_stop(&sc->sc_scan_ch); 2723 2724 ieee80211_ifdetach(&sc->sc_ic); 2725 if_detach(ifp); 2726 2727 for (i = 0; i < ATW_NRXDESC; i++) { 2728 rxs = &sc->sc_rxsoft[i]; 2729 if (rxs->rxs_mbuf != NULL) { 2730 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2731 m_freem(rxs->rxs_mbuf); 2732 rxs->rxs_mbuf = NULL; 2733 } 2734 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2735 } 2736 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2737 txs = &sc->sc_txsoft[i]; 2738 if (txs->txs_mbuf != NULL) { 2739 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2740 m_freem(txs->txs_mbuf); 2741 txs->txs_mbuf = NULL; 2742 } 2743 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2744 } 2745 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2746 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2747 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2748 sizeof(struct atw_control_data)); 2749 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2750 2751 shutdownhook_disestablish(sc->sc_sdhook); 2752 powerhook_disestablish(sc->sc_powerhook); 2753 2754 if (sc->sc_srom) 2755 free(sc->sc_srom, M_DEVBUF); 2756 2757 return (0); 2758 } 2759 2760 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2761 void 2762 atw_shutdown(void *arg) 2763 { 2764 struct atw_softc *sc = arg; 2765 2766 atw_stop(&sc->sc_if, 1); 2767 } 2768 2769 int 2770 atw_intr(void *arg) 2771 { 2772 struct atw_softc *sc = arg; 2773 struct ifnet *ifp = &sc->sc_if; 2774 u_int32_t status, rxstatus, txstatus, linkstatus; 2775 int handled = 0, txthresh; 2776 2777 #ifdef DEBUG 2778 if (ATW_IS_ENABLED(sc) == 0) 2779 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2780 #endif 2781 2782 /* 2783 * If the interface isn't running, the interrupt couldn't 2784 * possibly have come from us. 2785 */ 2786 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2787 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2788 return (0); 2789 2790 for (;;) { 2791 status = ATW_READ(sc, ATW_STSR); 2792 2793 if (status) 2794 ATW_WRITE(sc, ATW_STSR, status); 2795 2796 #ifdef ATW_DEBUG 2797 #define PRINTINTR(flag) do { \ 2798 if ((status & flag) != 0) { \ 2799 printf("%s" #flag, delim); \ 2800 delim = ","; \ 2801 } \ 2802 } while (0) 2803 2804 if (atw_debug > 1 && status) { 2805 const char *delim = "<"; 2806 2807 printf("%s: reg[STSR] = %x", 2808 sc->sc_dev.dv_xname, status); 2809 2810 PRINTINTR(ATW_INTR_FBE); 2811 PRINTINTR(ATW_INTR_LINKOFF); 2812 PRINTINTR(ATW_INTR_LINKON); 2813 PRINTINTR(ATW_INTR_RCI); 2814 PRINTINTR(ATW_INTR_RDU); 2815 PRINTINTR(ATW_INTR_REIS); 2816 PRINTINTR(ATW_INTR_RPS); 2817 PRINTINTR(ATW_INTR_TCI); 2818 PRINTINTR(ATW_INTR_TDU); 2819 PRINTINTR(ATW_INTR_TLT); 2820 PRINTINTR(ATW_INTR_TPS); 2821 PRINTINTR(ATW_INTR_TRT); 2822 PRINTINTR(ATW_INTR_TUF); 2823 PRINTINTR(ATW_INTR_BCNTC); 2824 PRINTINTR(ATW_INTR_ATIME); 2825 PRINTINTR(ATW_INTR_TBTT); 2826 PRINTINTR(ATW_INTR_TSCZ); 2827 PRINTINTR(ATW_INTR_TSFTF); 2828 printf(">\n"); 2829 } 2830 #undef PRINTINTR 2831 #endif /* ATW_DEBUG */ 2832 2833 if ((status & sc->sc_inten) == 0) 2834 break; 2835 2836 handled = 1; 2837 2838 rxstatus = status & sc->sc_rxint_mask; 2839 txstatus = status & sc->sc_txint_mask; 2840 linkstatus = status & sc->sc_linkint_mask; 2841 2842 if (linkstatus) { 2843 atw_linkintr(sc, linkstatus); 2844 } 2845 2846 if (rxstatus) { 2847 /* Grab any new packets. */ 2848 atw_rxintr(sc); 2849 2850 if (rxstatus & ATW_INTR_RDU) { 2851 printf("%s: receive ring overrun\n", 2852 sc->sc_dev.dv_xname); 2853 /* Get the receive process going again. */ 2854 ATW_WRITE(sc, ATW_RDR, 0x1); 2855 break; 2856 } 2857 } 2858 2859 if (txstatus) { 2860 /* Sweep up transmit descriptors. */ 2861 atw_txintr(sc); 2862 2863 if (txstatus & ATW_INTR_TLT) 2864 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2865 sc->sc_dev.dv_xname)); 2866 2867 if (txstatus & ATW_INTR_TRT) 2868 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2869 sc->sc_dev.dv_xname)); 2870 2871 /* If Tx under-run, increase our transmit threshold 2872 * if another is available. 2873 */ 2874 txthresh = sc->sc_txthresh + 1; 2875 if ((txstatus & ATW_INTR_TUF) && 2876 sc->sc_txth[txthresh].txth_name != NULL) { 2877 /* Idle the transmit process. */ 2878 atw_idle(sc, ATW_NAR_ST); 2879 2880 sc->sc_txthresh = txthresh; 2881 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2882 sc->sc_opmode |= 2883 sc->sc_txth[txthresh].txth_opmode; 2884 printf("%s: transmit underrun; new " 2885 "threshold: %s\n", sc->sc_dev.dv_xname, 2886 sc->sc_txth[txthresh].txth_name); 2887 2888 /* Set the new threshold and restart 2889 * the transmit process. 2890 */ 2891 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2892 DELAY(atw_nar_delay); 2893 ATW_WRITE(sc, ATW_RDR, 0x1); 2894 /* XXX Log every Nth underrun from 2895 * XXX now on? 2896 */ 2897 } 2898 } 2899 2900 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2901 if (status & ATW_INTR_TPS) 2902 printf("%s: transmit process stopped\n", 2903 sc->sc_dev.dv_xname); 2904 if (status & ATW_INTR_RPS) 2905 printf("%s: receive process stopped\n", 2906 sc->sc_dev.dv_xname); 2907 (void)atw_init(ifp); 2908 break; 2909 } 2910 2911 if (status & ATW_INTR_FBE) { 2912 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2913 (void)atw_init(ifp); 2914 break; 2915 } 2916 2917 /* 2918 * Not handled: 2919 * 2920 * Transmit buffer unavailable -- normal 2921 * condition, nothing to do, really. 2922 * 2923 * Early receive interrupt -- not available on 2924 * all chips, we just use RI. We also only 2925 * use single-segment receive DMA, so this 2926 * is mostly useless. 2927 * 2928 * TBD others 2929 */ 2930 } 2931 2932 /* Try to get more packets going. */ 2933 atw_start(ifp); 2934 2935 return (handled); 2936 } 2937 2938 /* 2939 * atw_idle: 2940 * 2941 * Cause the transmit and/or receive processes to go idle. 2942 * 2943 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2944 * process in STSR if I clear SR or ST after the process has already 2945 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2946 * do not seem to be too reliable. Perhaps I have the sense of the 2947 * Rx bits switched with the Tx bits? 2948 */ 2949 void 2950 atw_idle(struct atw_softc *sc, u_int32_t bits) 2951 { 2952 u_int32_t ackmask = 0, opmode, stsr, test0; 2953 int i, s; 2954 2955 s = splnet(); 2956 2957 opmode = sc->sc_opmode & ~bits; 2958 2959 if (bits & ATW_NAR_SR) 2960 ackmask |= ATW_INTR_RPS; 2961 2962 if (bits & ATW_NAR_ST) { 2963 ackmask |= ATW_INTR_TPS; 2964 /* set ATW_NAR_HF to flush TX FIFO. */ 2965 opmode |= ATW_NAR_HF; 2966 } 2967 2968 ATW_WRITE(sc, ATW_NAR, opmode); 2969 DELAY(atw_nar_delay); 2970 2971 for (i = 0; i < 1000; i++) { 2972 stsr = ATW_READ(sc, ATW_STSR); 2973 if ((stsr & ackmask) == ackmask) 2974 break; 2975 DELAY(10); 2976 } 2977 2978 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2979 2980 if ((stsr & ackmask) == ackmask) 2981 goto out; 2982 2983 test0 = ATW_READ(sc, ATW_TEST0); 2984 2985 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2986 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2987 printf("%s: transmit process not idle [%s]\n", 2988 sc->sc_dev.dv_xname, 2989 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2990 printf("%s: bits %08x test0 %08x stsr %08x\n", 2991 sc->sc_dev.dv_xname, bits, test0, stsr); 2992 } 2993 2994 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2995 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2996 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2997 sc->sc_dev.dv_xname, 2998 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2999 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3000 sc->sc_dev.dv_xname, bits, test0, stsr)); 3001 } 3002 out: 3003 if ((bits & ATW_NAR_ST) != 0) 3004 atw_txdrain(sc); 3005 splx(s); 3006 return; 3007 } 3008 3009 /* 3010 * atw_linkintr: 3011 * 3012 * Helper; handle link-status interrupts. 3013 */ 3014 void 3015 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3016 { 3017 struct ieee80211com *ic = &sc->sc_ic; 3018 3019 if (ic->ic_state != IEEE80211_S_RUN) 3020 return; 3021 3022 if (linkstatus & ATW_INTR_LINKON) { 3023 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3024 sc->sc_rescan_timer = 0; 3025 } else if (linkstatus & ATW_INTR_LINKOFF) { 3026 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3027 if (ic->ic_opmode != IEEE80211_M_STA) 3028 return; 3029 sc->sc_rescan_timer = 3; 3030 sc->sc_if.if_timer = 1; 3031 } 3032 } 3033 3034 static inline int 3035 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3036 { 3037 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3038 return 0; 3039 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3040 return 0; 3041 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3042 } 3043 3044 /* 3045 * atw_rxintr: 3046 * 3047 * Helper; handle receive interrupts. 3048 */ 3049 void 3050 atw_rxintr(struct atw_softc *sc) 3051 { 3052 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3053 struct ieee80211com *ic = &sc->sc_ic; 3054 struct ieee80211_node *ni; 3055 struct ieee80211_frame_min *wh; 3056 struct ifnet *ifp = &sc->sc_if; 3057 struct atw_rxsoft *rxs; 3058 struct mbuf *m; 3059 u_int32_t rxstat; 3060 int i, len, rate, rate0; 3061 u_int32_t rssi, rssi0; 3062 3063 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3064 rxs = &sc->sc_rxsoft[i]; 3065 3066 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3067 3068 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3069 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3070 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3071 3072 if (rxstat & ATW_RXSTAT_OWN) 3073 break; /* We have processed all receive buffers. */ 3074 3075 DPRINTF3(sc, 3076 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3077 sc->sc_dev.dv_xname, 3078 rxstat, rssi0, 3079 le32toh(sc->sc_rxdescs[i].ar_buf1), 3080 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3081 3082 /* 3083 * Make sure the packet fits in one buffer. This should 3084 * always be the case. 3085 */ 3086 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3087 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3088 printf("%s: incoming packet spilled, resetting\n", 3089 sc->sc_dev.dv_xname); 3090 (void)atw_init(ifp); 3091 return; 3092 } 3093 3094 /* 3095 * If an error occurred, update stats, clear the status 3096 * word, and leave the packet buffer in place. It will 3097 * simply be reused the next time the ring comes around. 3098 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3099 * error. 3100 */ 3101 3102 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3103 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3104 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3105 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3106 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3107 ATW_RXSTAT_ICVE)) != 0)) { 3108 #define PRINTERR(bit, str) \ 3109 if (rxstat & (bit)) \ 3110 printf("%s: receive error: %s\n", \ 3111 sc->sc_dev.dv_xname, str) 3112 ifp->if_ierrors++; 3113 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3114 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3115 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3116 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3117 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3118 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3119 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3120 #undef PRINTERR 3121 ATW_INIT_RXDESC(sc, i); 3122 continue; 3123 } 3124 3125 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3126 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3127 3128 /* 3129 * No errors; receive the packet. Note the ADM8211 3130 * includes the CRC in promiscuous mode. 3131 */ 3132 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3133 3134 /* 3135 * Allocate a new mbuf cluster. If that fails, we are 3136 * out of memory, and must drop the packet and recycle 3137 * the buffer that's already attached to this descriptor. 3138 */ 3139 m = rxs->rxs_mbuf; 3140 if (atw_add_rxbuf(sc, i) != 0) { 3141 ifp->if_ierrors++; 3142 ATW_INIT_RXDESC(sc, i); 3143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3145 continue; 3146 } 3147 3148 ifp->if_ipackets++; 3149 if (sc->sc_opmode & ATW_NAR_PR) 3150 len -= IEEE80211_CRC_LEN; 3151 m->m_pkthdr.rcvif = ifp; 3152 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3153 3154 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3155 rate = 0; 3156 else 3157 rate = rate_tbl[rate0]; 3158 3159 /* The RSSI comes straight from a register in the 3160 * baseband processor. I know that for the RF3000, 3161 * the RSSI register also contains the antenna-selection 3162 * bits. Mask those off. 3163 * 3164 * TBD Treat other basebands. 3165 */ 3166 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3167 rssi = rssi0 & RF3000_RSSI_MASK; 3168 else 3169 rssi = rssi0; 3170 3171 #if NBPFILTER > 0 3172 /* Pass this up to any BPF listeners. */ 3173 if (sc->sc_radiobpf != NULL) { 3174 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3175 3176 tap->ar_rate = rate; 3177 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3178 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3179 3180 /* TBD verify units are dB */ 3181 tap->ar_antsignal = (int)rssi; 3182 /* TBD tap->ar_flags */ 3183 3184 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3185 tap->ar_ihdr.it_len, m); 3186 } 3187 #endif /* NPBFILTER > 0 */ 3188 3189 wh = mtod(m, struct ieee80211_frame_min *); 3190 ni = ieee80211_find_rxnode(ic, wh); 3191 if (atw_hw_decrypted(sc, wh)) { 3192 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3193 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3194 } 3195 ieee80211_input(ic, m, ni, (int)rssi, 0); 3196 ieee80211_free_node(ni); 3197 } 3198 3199 /* Update the receive pointer. */ 3200 sc->sc_rxptr = i; 3201 } 3202 3203 /* 3204 * atw_txintr: 3205 * 3206 * Helper; handle transmit interrupts. 3207 */ 3208 void 3209 atw_txintr(struct atw_softc *sc) 3210 { 3211 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3212 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3213 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3214 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3215 3216 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3217 struct ifnet *ifp = &sc->sc_if; 3218 struct atw_txsoft *txs; 3219 u_int32_t txstat; 3220 3221 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3222 sc->sc_dev.dv_xname, sc->sc_flags)); 3223 3224 /* 3225 * Go through our Tx list and free mbufs for those 3226 * frames that have been transmitted. 3227 */ 3228 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3229 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3230 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3231 3232 #ifdef ATW_DEBUG 3233 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3234 int i; 3235 printf(" txsoft %p transmit chain:\n", txs); 3236 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3237 txs->txs_ndescs - 1, 3238 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3239 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3240 printf(" descriptor %d:\n", i); 3241 printf(" at_status: 0x%08x\n", 3242 le32toh(sc->sc_txdescs[i].at_stat)); 3243 printf(" at_flags: 0x%08x\n", 3244 le32toh(sc->sc_txdescs[i].at_flags)); 3245 printf(" at_buf1: 0x%08x\n", 3246 le32toh(sc->sc_txdescs[i].at_buf1)); 3247 printf(" at_buf2: 0x%08x\n", 3248 le32toh(sc->sc_txdescs[i].at_buf2)); 3249 if (i == txs->txs_lastdesc) 3250 break; 3251 } 3252 } 3253 #endif 3254 3255 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3256 if (txstat & ATW_TXSTAT_OWN) 3257 break; 3258 3259 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3260 3261 sc->sc_txfree += txs->txs_ndescs; 3262 3263 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3264 0, txs->txs_dmamap->dm_mapsize, 3265 BUS_DMASYNC_POSTWRITE); 3266 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3267 m_freem(txs->txs_mbuf); 3268 txs->txs_mbuf = NULL; 3269 3270 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3271 3272 ifp->if_flags &= ~IFF_OACTIVE; 3273 3274 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3275 (txstat & TXSTAT_ERRMASK) != 0) { 3276 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3277 txstat_buf, sizeof(txstat_buf)); 3278 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3279 txstat_buf, 3280 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3281 } 3282 3283 /* 3284 * Check for errors and collisions. 3285 */ 3286 if (txstat & ATW_TXSTAT_TUF) 3287 sc->sc_stats.ts_tx_tuf++; 3288 if (txstat & ATW_TXSTAT_TLT) 3289 sc->sc_stats.ts_tx_tlt++; 3290 if (txstat & ATW_TXSTAT_TRT) 3291 sc->sc_stats.ts_tx_trt++; 3292 if (txstat & ATW_TXSTAT_TRO) 3293 sc->sc_stats.ts_tx_tro++; 3294 if (txstat & ATW_TXSTAT_SOFBR) { 3295 sc->sc_stats.ts_tx_sofbr++; 3296 } 3297 3298 if ((txstat & ATW_TXSTAT_ES) == 0) 3299 ifp->if_collisions += 3300 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3301 else 3302 ifp->if_oerrors++; 3303 3304 ifp->if_opackets++; 3305 } 3306 3307 /* 3308 * If there are no more pending transmissions, cancel the watchdog 3309 * timer. 3310 */ 3311 if (txs == NULL) 3312 sc->sc_tx_timer = 0; 3313 #undef TXSTAT_ERRMASK 3314 #undef TXSTAT_FMT 3315 } 3316 3317 /* 3318 * atw_watchdog: [ifnet interface function] 3319 * 3320 * Watchdog timer handler. 3321 */ 3322 void 3323 atw_watchdog(struct ifnet *ifp) 3324 { 3325 struct atw_softc *sc = ifp->if_softc; 3326 struct ieee80211com *ic = &sc->sc_ic; 3327 3328 ifp->if_timer = 0; 3329 if (ATW_IS_ENABLED(sc) == 0) 3330 return; 3331 3332 if (sc->sc_rescan_timer) { 3333 if (--sc->sc_rescan_timer == 0) 3334 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3335 } 3336 if (sc->sc_tx_timer) { 3337 if (--sc->sc_tx_timer == 0 && 3338 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3339 printf("%s: transmit timeout\n", ifp->if_xname); 3340 ifp->if_oerrors++; 3341 (void)atw_init(ifp); 3342 atw_start(ifp); 3343 } 3344 } 3345 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3346 ifp->if_timer = 1; 3347 ieee80211_watchdog(ic); 3348 } 3349 3350 #ifdef ATW_DEBUG 3351 static void 3352 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3353 { 3354 struct atw_softc *sc = ifp->if_softc; 3355 struct mbuf *m; 3356 int i, noctets = 0; 3357 3358 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3359 m0->m_pkthdr.len); 3360 3361 for (m = m0; m; m = m->m_next) { 3362 if (m->m_len == 0) 3363 continue; 3364 for (i = 0; i < m->m_len; i++) { 3365 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3366 if (++noctets % 24 == 0) 3367 printf("\n"); 3368 } 3369 } 3370 printf("%s%s: %d bytes emitted\n", 3371 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3372 } 3373 #endif /* ATW_DEBUG */ 3374 3375 /* 3376 * atw_start: [ifnet interface function] 3377 * 3378 * Start packet transmission on the interface. 3379 */ 3380 void 3381 atw_start(struct ifnet *ifp) 3382 { 3383 struct atw_softc *sc = ifp->if_softc; 3384 struct ieee80211_key *k; 3385 struct ieee80211com *ic = &sc->sc_ic; 3386 struct ieee80211_node *ni; 3387 struct ieee80211_frame_min *whm; 3388 struct ieee80211_frame *wh; 3389 struct atw_frame *hh; 3390 struct mbuf *m0, *m; 3391 struct atw_txsoft *txs, *last_txs; 3392 struct atw_txdesc *txd; 3393 int do_encrypt, npkt, rate; 3394 bus_dmamap_t dmamap; 3395 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3396 3397 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3398 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3399 3400 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3401 return; 3402 3403 /* 3404 * Remember the previous number of free descriptors and 3405 * the first descriptor we'll use. 3406 */ 3407 ofree = sc->sc_txfree; 3408 firsttx = sc->sc_txnext; 3409 3410 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3411 sc->sc_dev.dv_xname, ofree, firsttx)); 3412 3413 /* 3414 * Loop through the send queue, setting up transmit descriptors 3415 * until we drain the queue, or use up all available transmit 3416 * descriptors. 3417 */ 3418 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3419 sc->sc_txfree != 0) { 3420 3421 /* 3422 * Grab a packet off the management queue, if it 3423 * is not empty. Otherwise, from the data queue. 3424 */ 3425 IF_DEQUEUE(&ic->ic_mgtq, m0); 3426 if (m0 != NULL) { 3427 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3428 m0->m_pkthdr.rcvif = NULL; 3429 } else { 3430 /* send no data packets until we are associated */ 3431 if (ic->ic_state != IEEE80211_S_RUN) 3432 break; 3433 IFQ_DEQUEUE(&ifp->if_snd, m0); 3434 if (m0 == NULL) 3435 break; 3436 #if NBPFILTER > 0 3437 if (ifp->if_bpf != NULL) 3438 bpf_mtap(ifp->if_bpf, m0); 3439 #endif /* NBPFILTER > 0 */ 3440 ni = ieee80211_find_txnode(ic, 3441 mtod(m0, struct ether_header *)->ether_dhost); 3442 if (ni == NULL) { 3443 ifp->if_oerrors++; 3444 break; 3445 } 3446 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3447 ieee80211_free_node(ni); 3448 ifp->if_oerrors++; 3449 break; 3450 } 3451 } 3452 3453 rate = MAX(ieee80211_get_rate(ic), 2); 3454 3455 whm = mtod(m0, struct ieee80211_frame_min *); 3456 3457 do_encrypt = ((whm->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3458 if (do_encrypt) 3459 k = &ic->ic_nw_keys[ic->ic_def_txkey]; 3460 else 3461 k = NULL; 3462 3463 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3464 ic->ic_flags, ic->ic_fragthreshold, rate, 3465 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3466 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3467 m_freem(m0); 3468 break; 3469 } 3470 3471 /* XXX Misleading if fragmentation is enabled. Better 3472 * to fragment in software? 3473 */ 3474 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3475 3476 #if NBPFILTER > 0 3477 /* 3478 * Pass the packet to any BPF listeners. 3479 */ 3480 if (ic->ic_rawbpf != NULL) 3481 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3482 3483 if (sc->sc_radiobpf != NULL) { 3484 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3485 3486 tap->at_rate = rate; 3487 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3488 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3489 3490 /* TBD tap->at_flags */ 3491 3492 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3493 tap->at_ihdr.it_len, m0); 3494 } 3495 #endif /* NBPFILTER > 0 */ 3496 3497 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3498 3499 if (ni != NULL) 3500 ieee80211_free_node(ni); 3501 3502 if (m0 == NULL) { 3503 ifp->if_oerrors++; 3504 break; 3505 } 3506 3507 /* just to make sure. */ 3508 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3509 3510 if (m0 == NULL) { 3511 ifp->if_oerrors++; 3512 break; 3513 } 3514 3515 hh = mtod(m0, struct atw_frame *); 3516 wh = &hh->atw_ihdr; 3517 3518 /* Copy everything we need from the 802.11 header: 3519 * Frame Control; address 1, address 3, or addresses 3520 * 3 and 4. NIC fills in BSSID, SA. 3521 */ 3522 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3523 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3524 panic("%s: illegal WDS frame", 3525 sc->sc_dev.dv_xname); 3526 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3527 } else 3528 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3529 3530 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3531 3532 /* initialize remaining Tx parameters */ 3533 memset(&hh->u, 0, sizeof(hh->u)); 3534 3535 hh->atw_rate = rate * 5; 3536 /* XXX this could be incorrect if M_FCS. _encap should 3537 * probably strip FCS just in case it sticks around in 3538 * bridged packets. 3539 */ 3540 hh->atw_service = 0x00; /* XXX guess */ 3541 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3542 sizeof(struct atw_frame)); 3543 3544 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3545 hh->atw_rtylmt = 3; 3546 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3547 if (do_encrypt) { 3548 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3549 hh->atw_keyid = ic->ic_def_txkey; 3550 } 3551 3552 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3553 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3554 if (txs->txs_d0.d_residue) 3555 hh->atw_head_plcplen |= htole16(0x8000); 3556 if (txs->txs_dn.d_residue) 3557 hh->atw_tail_plcplen |= htole16(0x8000); 3558 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3559 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3560 3561 /* never fragment multicast frames */ 3562 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3563 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3564 } else if (sc->sc_flags & ATWF_RTSCTS) { 3565 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3566 } 3567 3568 #ifdef ATW_DEBUG 3569 hh->atw_fragnum = 0; 3570 3571 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3572 printf("%s: dst = %s, rate = 0x%02x, " 3573 "service = 0x%02x, paylen = 0x%04x\n", 3574 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3575 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3576 3577 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3578 "dur1 = 0x%04x, dur2 = 0x%04x, " 3579 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3580 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3581 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3582 hh->atw_tail_dur, hh->atw_head_dur); 3583 3584 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3585 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3586 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3587 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3588 3589 printf("%s: keyid = %d\n", 3590 sc->sc_dev.dv_xname, hh->atw_keyid); 3591 3592 atw_dump_pkt(ifp, m0); 3593 } 3594 #endif /* ATW_DEBUG */ 3595 3596 dmamap = txs->txs_dmamap; 3597 3598 /* 3599 * Load the DMA map. Copy and try (once) again if the packet 3600 * didn't fit in the alloted number of segments. 3601 */ 3602 for (first = 1; 3603 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3604 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3605 first = 0) { 3606 MGETHDR(m, M_DONTWAIT, MT_DATA); 3607 if (m == NULL) { 3608 printf("%s: unable to allocate Tx mbuf\n", 3609 sc->sc_dev.dv_xname); 3610 break; 3611 } 3612 if (m0->m_pkthdr.len > MHLEN) { 3613 MCLGET(m, M_DONTWAIT); 3614 if ((m->m_flags & M_EXT) == 0) { 3615 printf("%s: unable to allocate Tx " 3616 "cluster\n", sc->sc_dev.dv_xname); 3617 m_freem(m); 3618 break; 3619 } 3620 } 3621 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3622 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3623 m_freem(m0); 3624 m0 = m; 3625 m = NULL; 3626 } 3627 if (error != 0) { 3628 printf("%s: unable to load Tx buffer, " 3629 "error = %d\n", sc->sc_dev.dv_xname, error); 3630 m_freem(m0); 3631 break; 3632 } 3633 3634 /* 3635 * Ensure we have enough descriptors free to describe 3636 * the packet. 3637 */ 3638 if (dmamap->dm_nsegs > sc->sc_txfree) { 3639 /* 3640 * Not enough free descriptors to transmit 3641 * this packet. Unload the DMA map and 3642 * drop the packet. Notify the upper layer 3643 * that there are no more slots left. 3644 * 3645 * XXX We could allocate an mbuf and copy, but 3646 * XXX it is worth it? 3647 */ 3648 bus_dmamap_unload(sc->sc_dmat, dmamap); 3649 m_freem(m0); 3650 break; 3651 } 3652 3653 /* 3654 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3655 */ 3656 3657 /* Sync the DMA map. */ 3658 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3659 BUS_DMASYNC_PREWRITE); 3660 3661 /* XXX arbitrary retry limit; 8 because I have seen it in 3662 * use already and maybe 0 means "no tries" ! 3663 */ 3664 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3665 3666 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3667 sc->sc_dev.dv_xname, rate * 5)); 3668 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3669 3670 /* 3671 * Initialize the transmit descriptors. 3672 */ 3673 for (nexttx = sc->sc_txnext, seg = 0; 3674 seg < dmamap->dm_nsegs; 3675 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3676 /* 3677 * If this is the first descriptor we're 3678 * enqueueing, don't set the OWN bit just 3679 * yet. That could cause a race condition. 3680 * We'll do it below. 3681 */ 3682 txd = &sc->sc_txdescs[nexttx]; 3683 txd->at_ctl = ctl | 3684 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3685 3686 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3687 txd->at_flags = 3688 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3689 ATW_TXFLAG_TBS1_MASK)) | 3690 ((nexttx == (ATW_NTXDESC - 1)) 3691 ? htole32(ATW_TXFLAG_TER) : 0); 3692 lasttx = nexttx; 3693 } 3694 3695 IASSERT(lasttx != -1, ("bad lastx")); 3696 /* Set `first segment' and `last segment' appropriately. */ 3697 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3698 htole32(ATW_TXFLAG_FS); 3699 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3700 3701 #ifdef ATW_DEBUG 3702 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3703 printf(" txsoft %p transmit chain:\n", txs); 3704 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3705 printf(" descriptor %d:\n", seg); 3706 printf(" at_ctl: 0x%08x\n", 3707 le32toh(sc->sc_txdescs[seg].at_ctl)); 3708 printf(" at_flags: 0x%08x\n", 3709 le32toh(sc->sc_txdescs[seg].at_flags)); 3710 printf(" at_buf1: 0x%08x\n", 3711 le32toh(sc->sc_txdescs[seg].at_buf1)); 3712 printf(" at_buf2: 0x%08x\n", 3713 le32toh(sc->sc_txdescs[seg].at_buf2)); 3714 if (seg == lasttx) 3715 break; 3716 } 3717 } 3718 #endif 3719 3720 /* Sync the descriptors we're using. */ 3721 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3722 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3723 3724 /* 3725 * Store a pointer to the packet so we can free it later, 3726 * and remember what txdirty will be once the packet is 3727 * done. 3728 */ 3729 txs->txs_mbuf = m0; 3730 txs->txs_firstdesc = sc->sc_txnext; 3731 txs->txs_lastdesc = lasttx; 3732 txs->txs_ndescs = dmamap->dm_nsegs; 3733 3734 /* Advance the tx pointer. */ 3735 sc->sc_txfree -= dmamap->dm_nsegs; 3736 sc->sc_txnext = nexttx; 3737 3738 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3739 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3740 3741 last_txs = txs; 3742 } 3743 3744 if (txs == NULL || sc->sc_txfree == 0) { 3745 /* No more slots left; notify upper layer. */ 3746 ifp->if_flags |= IFF_OACTIVE; 3747 } 3748 3749 if (sc->sc_txfree != ofree) { 3750 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3751 sc->sc_dev.dv_xname, lasttx, firsttx)); 3752 /* 3753 * Cause a transmit interrupt to happen on the 3754 * last packet we enqueued. 3755 */ 3756 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3757 ATW_CDTXSYNC(sc, lasttx, 1, 3758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3759 3760 /* 3761 * The entire packet chain is set up. Give the 3762 * first descriptor to the chip now. 3763 */ 3764 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3765 ATW_CDTXSYNC(sc, firsttx, 1, 3766 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3767 3768 /* Wake up the transmitter. */ 3769 ATW_WRITE(sc, ATW_TDR, 0x1); 3770 3771 /* Set a watchdog timer in case the chip flakes out. */ 3772 sc->sc_tx_timer = 5; 3773 ifp->if_timer = 1; 3774 } 3775 } 3776 3777 /* 3778 * atw_power: 3779 * 3780 * Power management (suspend/resume) hook. 3781 */ 3782 void 3783 atw_power(int why, void *arg) 3784 { 3785 struct atw_softc *sc = arg; 3786 struct ifnet *ifp = &sc->sc_if; 3787 int s; 3788 3789 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3790 3791 s = splnet(); 3792 switch (why) { 3793 case PWR_STANDBY: 3794 /* XXX do nothing. */ 3795 break; 3796 case PWR_SUSPEND: 3797 atw_stop(ifp, 0); 3798 if (sc->sc_power != NULL) 3799 (*sc->sc_power)(sc, why); 3800 break; 3801 case PWR_RESUME: 3802 if (ifp->if_flags & IFF_UP) { 3803 if (sc->sc_power != NULL) 3804 (*sc->sc_power)(sc, why); 3805 atw_init(ifp); 3806 } 3807 break; 3808 case PWR_SOFTSUSPEND: 3809 case PWR_SOFTSTANDBY: 3810 case PWR_SOFTRESUME: 3811 break; 3812 } 3813 splx(s); 3814 } 3815 3816 /* 3817 * atw_ioctl: [ifnet interface function] 3818 * 3819 * Handle control requests from the operator. 3820 */ 3821 int 3822 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3823 { 3824 struct atw_softc *sc = ifp->if_softc; 3825 struct ifreq *ifr = (struct ifreq *)data; 3826 int s, error = 0; 3827 3828 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3829 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3830 return ENXIO; 3831 3832 s = splnet(); 3833 3834 switch (cmd) { 3835 case SIOCSIFFLAGS: 3836 if (ifp->if_flags & IFF_UP) { 3837 if (ATW_IS_ENABLED(sc)) { 3838 /* 3839 * To avoid rescanning another access point, 3840 * do not call atw_init() here. Instead, 3841 * only reflect media settings. 3842 */ 3843 atw_filter_setup(sc); 3844 } else 3845 error = atw_init(ifp); 3846 } else if (ATW_IS_ENABLED(sc)) 3847 atw_stop(ifp, 1); 3848 break; 3849 case SIOCADDMULTI: 3850 case SIOCDELMULTI: 3851 error = (cmd == SIOCADDMULTI) ? 3852 ether_addmulti(ifr, &sc->sc_ec) : 3853 ether_delmulti(ifr, &sc->sc_ec); 3854 if (error == ENETRESET) { 3855 if (ifp->if_flags & IFF_RUNNING) 3856 atw_filter_setup(sc); /* do not rescan */ 3857 error = 0; 3858 } 3859 break; 3860 default: 3861 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3862 if (error == ENETRESET) { 3863 if (ATW_IS_ENABLED(sc)) 3864 error = atw_init(ifp); 3865 else 3866 error = 0; 3867 } 3868 break; 3869 } 3870 3871 /* Try to get more packets going. */ 3872 if (ATW_IS_ENABLED(sc)) 3873 atw_start(ifp); 3874 3875 splx(s); 3876 return (error); 3877 } 3878 3879 static int 3880 atw_media_change(struct ifnet *ifp) 3881 { 3882 int error; 3883 3884 error = ieee80211_media_change(ifp); 3885 if (error == ENETRESET) { 3886 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3887 (IFF_RUNNING|IFF_UP)) 3888 atw_init(ifp); /* XXX lose error */ 3889 error = 0; 3890 } 3891 return error; 3892 } 3893 3894 static void 3895 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3896 { 3897 struct atw_softc *sc = ifp->if_softc; 3898 3899 if (ATW_IS_ENABLED(sc) == 0) { 3900 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3901 imr->ifm_status = 0; 3902 return; 3903 } 3904 ieee80211_media_status(ifp, imr); 3905 } 3906
Indexes created Wed Sep 24 05:09:52 GMT 2025