atw.c revision 1.97
1 /* $NetBSD: atw.c,v 1.97 2005/12/29 21:40:41 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.97 2005/12/29 21:40:41 dyoung Exp $"); 45 46 #include "bpfilter.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/callout.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/time.h> 59 60 #include <machine/endian.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #include <net80211/ieee80211_netbsd.h> 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 80 #include <dev/ic/atwreg.h> 81 #include <dev/ic/rf3000reg.h> 82 #include <dev/ic/si4136reg.h> 83 #include <dev/ic/atwvar.h> 84 #include <dev/ic/smc93cx6var.h> 85 86 /* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94 /* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142 int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144 int atw_pseudo_milli = 1; 145 int atw_magic_delay1 = 100 * 1000; 146 int atw_magic_delay2 = 100 * 1000; 147 /* more magic multi-millisecond delays (units: microseconds) */ 148 int atw_nar_delay = 20 * 1000; 149 int atw_magic_delay4 = 10 * 1000; 150 int atw_rf_delay1 = 10 * 1000; 151 int atw_rf_delay2 = 5 * 1000; 152 int atw_plcphd_delay = 2 * 1000; 153 int atw_bbp_io_enable_delay = 20 * 1000; 154 int atw_bbp_io_disable_delay = 2 * 1000; 155 int atw_writewep_delay = 1000; 156 int atw_beacon_len_adjust = 4; 157 int atw_dwelltime = 200; 158 int atw_xindiv2 = 0; 159 160 #ifdef ATW_DEBUG 161 int atw_debug = 0; 162 163 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170 static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171 static void atw_print_regs(struct atw_softc *, const char *); 172 173 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174 # ifdef ATW_BBPDEBUG 175 static void atw_rf3000_print(struct atw_softc *); 176 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177 # endif /* ATW_BBPDEBUG */ 178 179 # ifdef ATW_SYNDEBUG 180 static void atw_si4126_print(struct atw_softc *); 181 static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182 # endif /* ATW_SYNDEBUG */ 183 184 #else 185 #define ATW_DPRINTF(x) 186 #define ATW_DPRINTF2(x) 187 #define ATW_DPRINTF3(x) 188 #define DPRINTF(sc, x) /* nothing */ 189 #define DPRINTF2(sc, x) /* nothing */ 190 #define DPRINTF3(sc, x) /* nothing */ 191 #endif 192 193 /* ifnet methods */ 194 int atw_init(struct ifnet *); 195 int atw_ioctl(struct ifnet *, u_long, caddr_t); 196 void atw_start(struct ifnet *); 197 void atw_stop(struct ifnet *, int); 198 void atw_watchdog(struct ifnet *); 199 200 /* Device attachment */ 201 void atw_attach(struct atw_softc *); 202 int atw_detach(struct atw_softc *); 203 204 /* Rx/Tx process */ 205 int atw_add_rxbuf(struct atw_softc *, int); 206 void atw_idle(struct atw_softc *, u_int32_t); 207 void atw_rxdrain(struct atw_softc *); 208 void atw_txdrain(struct atw_softc *); 209 210 /* Device (de)activation and power state */ 211 void atw_disable(struct atw_softc *); 212 int atw_enable(struct atw_softc *); 213 void atw_power(int, void *); 214 void atw_reset(struct atw_softc *); 215 void atw_shutdown(void *); 216 217 /* Interrupt handlers */ 218 void atw_linkintr(struct atw_softc *, u_int32_t); 219 void atw_rxintr(struct atw_softc *); 220 void atw_txintr(struct atw_softc *); 221 222 /* 802.11 state machine */ 223 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224 static void atw_next_scan(void *); 225 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227 static int atw_tune(struct atw_softc *); 228 229 /* Device initialization */ 230 static void atw_bbp_io_init(struct atw_softc *); 231 static void atw_cfp_init(struct atw_softc *); 232 static void atw_cmdr_init(struct atw_softc *); 233 static void atw_ifs_init(struct atw_softc *); 234 static void atw_nar_init(struct atw_softc *); 235 static void atw_response_times_init(struct atw_softc *); 236 static void atw_rf_reset(struct atw_softc *); 237 static void atw_test1_init(struct atw_softc *); 238 static void atw_tofs0_init(struct atw_softc *); 239 static void atw_tofs2_init(struct atw_softc *); 240 static void atw_txlmt_init(struct atw_softc *); 241 static void atw_wcsr_init(struct atw_softc *); 242 243 /* Key management */ 244 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247 static void atw_key_update_begin(struct ieee80211com *); 248 static void atw_key_update_end(struct ieee80211com *); 249 250 /* RAM/ROM utilities */ 251 static void atw_clear_sram(struct atw_softc *); 252 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253 static int atw_read_srom(struct atw_softc *); 254 255 /* BSS setup */ 256 static void atw_predict_beacon(struct atw_softc *); 257 static void atw_start_beacon(struct atw_softc *, int); 258 static void atw_write_bssid(struct atw_softc *); 259 static void atw_write_ssid(struct atw_softc *); 260 static void atw_write_sup_rates(struct atw_softc *); 261 static void atw_write_wep(struct atw_softc *); 262 263 /* Media */ 264 static int atw_media_change(struct ifnet *); 265 266 static void atw_filter_setup(struct atw_softc *); 267 268 /* 802.11 utilities */ 269 static uint64_t atw_get_tsft(struct atw_softc *); 270 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 271 uint32_t); 272 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 273 static void atw_node_free(struct ieee80211_node *); 274 static void atw_change_ibss(struct atw_softc *); 275 276 /* 277 * Tuner/transceiver/modem 278 */ 279 static void atw_bbp_io_enable(struct atw_softc *, int); 280 281 /* RFMD RF3000 Baseband Processor */ 282 static int atw_rf3000_init(struct atw_softc *); 283 static int atw_rf3000_tune(struct atw_softc *, u_int); 284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 285 286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 287 static void atw_si4126_tune(struct atw_softc *, u_int); 288 static void atw_si4126_write(struct atw_softc *, u_int, u_int); 289 290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 292 293 const char *atw_tx_state[] = { 294 "STOPPED", 295 "RUNNING - read descriptor", 296 "RUNNING - transmitting", 297 "RUNNING - filling fifo", /* XXX */ 298 "SUSPENDED", 299 "RUNNING -- write descriptor", 300 "RUNNING -- write last descriptor", 301 "RUNNING - fifo full" 302 }; 303 304 const char *atw_rx_state[] = { 305 "STOPPED", 306 "RUNNING - read descriptor", 307 "RUNNING - check this packet, pre-fetch next", 308 "RUNNING - wait for reception", 309 "SUSPENDED", 310 "RUNNING - write descriptor", 311 "RUNNING - flush fifo", 312 "RUNNING - fifo drain" 313 }; 314 315 int 316 atw_activate(struct device *self, enum devact act) 317 { 318 struct atw_softc *sc = (struct atw_softc *)self; 319 int rv = 0, s; 320 321 s = splnet(); 322 switch (act) { 323 case DVACT_ACTIVATE: 324 rv = EOPNOTSUPP; 325 break; 326 327 case DVACT_DEACTIVATE: 328 if_deactivate(&sc->sc_if); 329 break; 330 } 331 splx(s); 332 return rv; 333 } 334 335 /* 336 * atw_enable: 337 * 338 * Enable the ADM8211 chip. 339 */ 340 int 341 atw_enable(struct atw_softc *sc) 342 { 343 344 if (ATW_IS_ENABLED(sc) == 0) { 345 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 346 printf("%s: device enable failed\n", 347 sc->sc_dev.dv_xname); 348 return (EIO); 349 } 350 sc->sc_flags |= ATWF_ENABLED; 351 } 352 return (0); 353 } 354 355 /* 356 * atw_disable: 357 * 358 * Disable the ADM8211 chip. 359 */ 360 void 361 atw_disable(struct atw_softc *sc) 362 { 363 if (!ATW_IS_ENABLED(sc)) 364 return; 365 if (sc->sc_disable != NULL) 366 (*sc->sc_disable)(sc); 367 sc->sc_flags &= ~ATWF_ENABLED; 368 } 369 370 /* Returns -1 on failure. */ 371 static int 372 atw_read_srom(struct atw_softc *sc) 373 { 374 struct seeprom_descriptor sd; 375 uint32_t test0, fail_bits; 376 377 (void)memset(&sd, 0, sizeof(sd)); 378 379 test0 = ATW_READ(sc, ATW_TEST0); 380 381 switch (sc->sc_rev) { 382 case ATW_REVISION_BA: 383 case ATW_REVISION_CA: 384 fail_bits = ATW_TEST0_EPNE; 385 break; 386 default: 387 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 388 break; 389 } 390 if ((test0 & fail_bits) != 0) { 391 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 392 return -1; 393 } 394 395 switch (test0 & ATW_TEST0_EPTYP_MASK) { 396 case ATW_TEST0_EPTYP_93c66: 397 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 398 sc->sc_sromsz = 512; 399 sd.sd_chip = C56_66; 400 break; 401 case ATW_TEST0_EPTYP_93c46: 402 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 403 sc->sc_sromsz = 128; 404 sd.sd_chip = C46; 405 break; 406 default: 407 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 408 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 409 return -1; 410 } 411 412 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 413 414 if (sc->sc_srom == NULL) { 415 printf("%s: unable to allocate SROM buffer\n", 416 sc->sc_dev.dv_xname); 417 return -1; 418 } 419 420 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 421 422 /* ADM8211 has a single 32-bit register for controlling the 423 * 93cx6 SROM. Bit SRS enables the serial port. There is no 424 * "ready" bit. The ADM8211 input/output sense is the reverse 425 * of read_seeprom's. 426 */ 427 sd.sd_tag = sc->sc_st; 428 sd.sd_bsh = sc->sc_sh; 429 sd.sd_regsize = 4; 430 sd.sd_control_offset = ATW_SPR; 431 sd.sd_status_offset = ATW_SPR; 432 sd.sd_dataout_offset = ATW_SPR; 433 sd.sd_CK = ATW_SPR_SCLK; 434 sd.sd_CS = ATW_SPR_SCS; 435 sd.sd_DI = ATW_SPR_SDO; 436 sd.sd_DO = ATW_SPR_SDI; 437 sd.sd_MS = ATW_SPR_SRS; 438 sd.sd_RDY = 0; 439 440 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 441 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 442 free(sc->sc_srom, M_DEVBUF); 443 return -1; 444 } 445 #ifdef ATW_DEBUG 446 { 447 int i; 448 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 449 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 450 if (((i % 8) == 0) && (i != 0)) { 451 ATW_DPRINTF(("\n\t")); 452 } 453 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 454 } 455 ATW_DPRINTF(("\n")); 456 } 457 #endif /* ATW_DEBUG */ 458 return 0; 459 } 460 461 #ifdef ATW_DEBUG 462 static void 463 atw_print_regs(struct atw_softc *sc, const char *where) 464 { 465 #define PRINTREG(sc, reg) \ 466 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 467 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 468 469 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 470 471 PRINTREG(sc, ATW_PAR); 472 PRINTREG(sc, ATW_FRCTL); 473 PRINTREG(sc, ATW_TDR); 474 PRINTREG(sc, ATW_WTDP); 475 PRINTREG(sc, ATW_RDR); 476 PRINTREG(sc, ATW_WRDP); 477 PRINTREG(sc, ATW_RDB); 478 PRINTREG(sc, ATW_CSR3A); 479 PRINTREG(sc, ATW_TDBD); 480 PRINTREG(sc, ATW_TDBP); 481 PRINTREG(sc, ATW_STSR); 482 PRINTREG(sc, ATW_CSR5A); 483 PRINTREG(sc, ATW_NAR); 484 PRINTREG(sc, ATW_CSR6A); 485 PRINTREG(sc, ATW_IER); 486 PRINTREG(sc, ATW_CSR7A); 487 PRINTREG(sc, ATW_LPC); 488 PRINTREG(sc, ATW_TEST1); 489 PRINTREG(sc, ATW_SPR); 490 PRINTREG(sc, ATW_TEST0); 491 PRINTREG(sc, ATW_WCSR); 492 PRINTREG(sc, ATW_WPDR); 493 PRINTREG(sc, ATW_GPTMR); 494 PRINTREG(sc, ATW_GPIO); 495 PRINTREG(sc, ATW_BBPCTL); 496 PRINTREG(sc, ATW_SYNCTL); 497 PRINTREG(sc, ATW_PLCPHD); 498 PRINTREG(sc, ATW_MMIWADDR); 499 PRINTREG(sc, ATW_MMIRADDR1); 500 PRINTREG(sc, ATW_MMIRADDR2); 501 PRINTREG(sc, ATW_TXBR); 502 PRINTREG(sc, ATW_CSR15A); 503 PRINTREG(sc, ATW_ALCSTAT); 504 PRINTREG(sc, ATW_TOFS2); 505 PRINTREG(sc, ATW_CMDR); 506 PRINTREG(sc, ATW_PCIC); 507 PRINTREG(sc, ATW_PMCSR); 508 PRINTREG(sc, ATW_PAR0); 509 PRINTREG(sc, ATW_PAR1); 510 PRINTREG(sc, ATW_MAR0); 511 PRINTREG(sc, ATW_MAR1); 512 PRINTREG(sc, ATW_ATIMDA0); 513 PRINTREG(sc, ATW_ABDA1); 514 PRINTREG(sc, ATW_BSSID0); 515 PRINTREG(sc, ATW_TXLMT); 516 PRINTREG(sc, ATW_MIBCNT); 517 PRINTREG(sc, ATW_BCNT); 518 PRINTREG(sc, ATW_TSFTH); 519 PRINTREG(sc, ATW_TSC); 520 PRINTREG(sc, ATW_SYNRF); 521 PRINTREG(sc, ATW_BPLI); 522 PRINTREG(sc, ATW_CAP0); 523 PRINTREG(sc, ATW_CAP1); 524 PRINTREG(sc, ATW_RMD); 525 PRINTREG(sc, ATW_CFPP); 526 PRINTREG(sc, ATW_TOFS0); 527 PRINTREG(sc, ATW_TOFS1); 528 PRINTREG(sc, ATW_IFST); 529 PRINTREG(sc, ATW_RSPT); 530 PRINTREG(sc, ATW_TSFTL); 531 PRINTREG(sc, ATW_WEPCTL); 532 PRINTREG(sc, ATW_WESK); 533 PRINTREG(sc, ATW_WEPCNT); 534 PRINTREG(sc, ATW_MACTEST); 535 PRINTREG(sc, ATW_FER); 536 PRINTREG(sc, ATW_FEMR); 537 PRINTREG(sc, ATW_FPSR); 538 PRINTREG(sc, ATW_FFER); 539 #undef PRINTREG 540 } 541 #endif /* ATW_DEBUG */ 542 543 /* 544 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 545 */ 546 void 547 atw_attach(struct atw_softc *sc) 548 { 549 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 551 }; 552 struct ieee80211com *ic = &sc->sc_ic; 553 struct ifnet *ifp = &sc->sc_if; 554 int country_code, error, i, nrate, srom_major; 555 u_int32_t reg; 556 static const char *type_strings[] = {"Intersil (not supported)", 557 "RFMD", "Marvel (not supported)"}; 558 559 sc->sc_txth = atw_txthresh_tab_lo; 560 561 SIMPLEQ_INIT(&sc->sc_txfreeq); 562 SIMPLEQ_INIT(&sc->sc_txdirtyq); 563 564 #ifdef ATW_DEBUG 565 atw_print_regs(sc, "atw_attach"); 566 #endif /* ATW_DEBUG */ 567 568 /* 569 * Allocate the control data structures, and create and load the 570 * DMA map for it. 571 */ 572 if ((error = bus_dmamem_alloc(sc->sc_dmat, 573 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 574 1, &sc->sc_cdnseg, 0)) != 0) { 575 printf("%s: unable to allocate control data, error = %d\n", 576 sc->sc_dev.dv_xname, error); 577 goto fail_0; 578 } 579 580 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 581 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 582 BUS_DMA_COHERENT)) != 0) { 583 printf("%s: unable to map control data, error = %d\n", 584 sc->sc_dev.dv_xname, error); 585 goto fail_1; 586 } 587 588 if ((error = bus_dmamap_create(sc->sc_dmat, 589 sizeof(struct atw_control_data), 1, 590 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 591 printf("%s: unable to create control data DMA map, " 592 "error = %d\n", sc->sc_dev.dv_xname, error); 593 goto fail_2; 594 } 595 596 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 597 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 598 0)) != 0) { 599 printf("%s: unable to load control data DMA map, error = %d\n", 600 sc->sc_dev.dv_xname, error); 601 goto fail_3; 602 } 603 604 /* 605 * Create the transmit buffer DMA maps. 606 */ 607 sc->sc_ntxsegs = ATW_NTXSEGS; 608 for (i = 0; i < ATW_TXQUEUELEN; i++) { 609 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 610 sc->sc_ntxsegs, MCLBYTES, 0, 0, 611 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 612 printf("%s: unable to create tx DMA map %d, " 613 "error = %d\n", sc->sc_dev.dv_xname, i, error); 614 goto fail_4; 615 } 616 } 617 618 /* 619 * Create the receive buffer DMA maps. 620 */ 621 for (i = 0; i < ATW_NRXDESC; i++) { 622 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 623 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 624 printf("%s: unable to create rx DMA map %d, " 625 "error = %d\n", sc->sc_dev.dv_xname, i, error); 626 goto fail_5; 627 } 628 } 629 for (i = 0; i < ATW_NRXDESC; i++) { 630 sc->sc_rxsoft[i].rxs_mbuf = NULL; 631 } 632 633 switch (sc->sc_rev) { 634 case ATW_REVISION_AB: 635 case ATW_REVISION_AF: 636 sc->sc_sramlen = ATW_SRAM_A_SIZE; 637 break; 638 case ATW_REVISION_BA: 639 case ATW_REVISION_CA: 640 sc->sc_sramlen = ATW_SRAM_B_SIZE; 641 break; 642 } 643 644 /* Reset the chip to a known state. */ 645 atw_reset(sc); 646 647 if (atw_read_srom(sc) == -1) 648 return; 649 650 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 651 ATW_SR_RFTYPE_MASK); 652 653 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 654 ATW_SR_BBPTYPE_MASK); 655 656 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 657 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 661 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 662 return; 663 } 664 665 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 666 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 667 668 /* XXX There exists a Linux driver which seems to use RFType = 0 for 669 * MARVEL. My bug, or theirs? 670 */ 671 672 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 673 674 switch (sc->sc_rftype) { 675 case ATW_RFTYPE_INTERSIL: 676 reg |= ATW_SYNCTL_CS1; 677 break; 678 case ATW_RFTYPE_RFMD: 679 reg |= ATW_SYNCTL_CS0; 680 break; 681 case ATW_RFTYPE_MARVEL: 682 break; 683 } 684 685 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 686 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 687 688 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 689 690 switch (sc->sc_bbptype) { 691 case ATW_BBPTYPE_INTERSIL: 692 reg |= ATW_BBPCTL_TWI; 693 break; 694 case ATW_BBPTYPE_RFMD: 695 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 696 ATW_BBPCTL_CCA_ACTLO; 697 break; 698 case ATW_BBPTYPE_MARVEL: 699 break; 700 case ATW_C_BBPTYPE_RFMD: 701 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 702 sc->sc_dev.dv_xname); 703 break; 704 } 705 706 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 707 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 708 709 /* 710 * From this point forward, the attachment cannot fail. A failure 711 * before this point releases all resources that may have been 712 * allocated. 713 */ 714 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 715 716 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 717 htole16(sc->sc_srom[ATW_SR_MAC00]), 718 htole16(sc->sc_srom[ATW_SR_MAC01]), 719 htole16(sc->sc_srom[ATW_SR_MAC10]))); 720 721 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 722 ATW_SR_MAJOR_MASK); 723 724 if (srom_major < 2) 725 sc->sc_rf3000_options1 = 0; 726 else if (sc->sc_rev == ATW_REVISION_BA) { 727 sc->sc_rf3000_options1 = 728 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 729 ATW_SR_CR28_MASK); 730 } else 731 sc->sc_rf3000_options1 = 0; 732 733 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 734 ATW_SR_CR29_MASK); 735 736 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 737 ATW_SR_CTRY_MASK); 738 739 #define ADD_CHANNEL(_ic, _chan) do { \ 740 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 741 _ic->ic_channels[_chan].ic_freq = \ 742 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 743 } while (0) 744 745 /* Find available channels */ 746 switch (country_code) { 747 case COUNTRY_MMK2: /* 1-14 */ 748 ADD_CHANNEL(ic, 14); 749 /*FALLTHROUGH*/ 750 case COUNTRY_ETSI: /* 1-13 */ 751 for (i = 1; i <= 13; i++) 752 ADD_CHANNEL(ic, i); 753 break; 754 case COUNTRY_FCC: /* 1-11 */ 755 case COUNTRY_IC: /* 1-11 */ 756 for (i = 1; i <= 11; i++) 757 ADD_CHANNEL(ic, i); 758 break; 759 case COUNTRY_MMK: /* 14 */ 760 ADD_CHANNEL(ic, 14); 761 break; 762 case COUNTRY_FRANCE: /* 10-13 */ 763 for (i = 10; i <= 13; i++) 764 ADD_CHANNEL(ic, i); 765 break; 766 default: /* assume channels 10-11 */ 767 case COUNTRY_SPAIN: /* 10-11 */ 768 for (i = 10; i <= 11; i++) 769 ADD_CHANNEL(ic, i); 770 break; 771 } 772 773 /* Read the MAC address. */ 774 reg = ATW_READ(sc, ATW_PAR0); 775 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 776 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 777 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 778 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 779 reg = ATW_READ(sc, ATW_PAR1); 780 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 781 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 782 783 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 784 printf(" could not get mac address, attach failed\n"); 785 return; 786 } 787 788 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 789 790 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 791 ifp->if_softc = sc; 792 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 793 IFF_NOTRAILERS; 794 ifp->if_ioctl = atw_ioctl; 795 ifp->if_start = atw_start; 796 ifp->if_watchdog = atw_watchdog; 797 ifp->if_init = atw_init; 798 ifp->if_stop = atw_stop; 799 IFQ_SET_READY(&ifp->if_snd); 800 801 ic->ic_ifp = ifp; 802 ic->ic_phytype = IEEE80211_T_DS; 803 ic->ic_opmode = IEEE80211_M_STA; 804 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 805 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 806 807 nrate = 0; 808 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 809 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 810 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 811 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 812 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 813 814 /* 815 * Call MI attach routines. 816 */ 817 818 if_attach(ifp); 819 ieee80211_ifattach(ic); 820 821 sc->sc_newstate = ic->ic_newstate; 822 ic->ic_newstate = atw_newstate; 823 824 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 825 ic->ic_recv_mgmt = atw_recv_mgmt; 826 827 sc->sc_node_free = ic->ic_node_free; 828 ic->ic_node_free = atw_node_free; 829 830 sc->sc_node_alloc = ic->ic_node_alloc; 831 ic->ic_node_alloc = atw_node_alloc; 832 833 ic->ic_crypto.cs_key_delete = atw_key_delete; 834 ic->ic_crypto.cs_key_set = atw_key_set; 835 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 836 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 837 838 /* possibly we should fill in our own sc_send_prresp, since 839 * the ADM8211 is probably sending probe responses in ad hoc 840 * mode. 841 */ 842 843 /* complete initialization */ 844 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 845 callout_init(&sc->sc_scan_ch); 846 847 #if NBPFILTER > 0 848 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 849 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 850 #endif 851 852 /* 853 * Make sure the interface is shutdown during reboot. 854 */ 855 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 856 if (sc->sc_sdhook == NULL) 857 printf("%s: WARNING: unable to establish shutdown hook\n", 858 sc->sc_dev.dv_xname); 859 860 /* 861 * Add a suspend hook to make sure we come back up after a 862 * resume. 863 */ 864 sc->sc_powerhook = powerhook_establish(atw_power, sc); 865 if (sc->sc_powerhook == NULL) 866 printf("%s: WARNING: unable to establish power hook\n", 867 sc->sc_dev.dv_xname); 868 869 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 870 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 871 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 872 873 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 874 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 875 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 876 877 ieee80211_announce(ic); 878 return; 879 880 /* 881 * Free any resources we've allocated during the failed attach 882 * attempt. Do this in reverse order and fall through. 883 */ 884 fail_5: 885 for (i = 0; i < ATW_NRXDESC; i++) { 886 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 887 continue; 888 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 889 } 890 fail_4: 891 for (i = 0; i < ATW_TXQUEUELEN; i++) { 892 if (sc->sc_txsoft[i].txs_dmamap == NULL) 893 continue; 894 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 895 } 896 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 897 fail_3: 898 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 899 fail_2: 900 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 901 sizeof(struct atw_control_data)); 902 fail_1: 903 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 904 fail_0: 905 return; 906 } 907 908 static struct ieee80211_node * 909 atw_node_alloc(struct ieee80211_node_table *nt) 910 { 911 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 912 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 913 914 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 915 return ni; 916 } 917 918 static void 919 atw_node_free(struct ieee80211_node *ni) 920 { 921 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 922 923 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 924 ether_sprintf(ni->ni_bssid))); 925 (*sc->sc_node_free)(ni); 926 } 927 928 929 static void 930 atw_test1_reset(struct atw_softc *sc) 931 { 932 switch (sc->sc_rev) { 933 case ATW_REVISION_BA: 934 if (1 /* XXX condition on transceiver type */) { 935 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 936 } 937 break; 938 case ATW_REVISION_CA: 939 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 940 break; 941 default: 942 break; 943 } 944 } 945 946 /* 947 * atw_reset: 948 * 949 * Perform a soft reset on the ADM8211. 950 */ 951 void 952 atw_reset(struct atw_softc *sc) 953 { 954 int i; 955 uint32_t lpc; 956 957 ATW_WRITE(sc, ATW_NAR, 0x0); 958 DELAY(atw_nar_delay); 959 960 /* Reference driver has a cryptic remark indicating that this might 961 * power-on the chip. I know that it turns off power-saving.... 962 */ 963 ATW_WRITE(sc, ATW_FRCTL, 0x0); 964 965 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 966 967 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 968 if (ATW_READ(sc, ATW_PAR) == 0) 969 break; 970 DELAY(atw_pseudo_milli); 971 } 972 973 /* ... and then pause 100ms longer for good measure. */ 974 DELAY(atw_magic_delay1); 975 976 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 977 978 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 979 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 980 981 atw_test1_reset(sc); 982 /* 983 * Initialize the PCI Access Register. 984 */ 985 sc->sc_busmode = ATW_PAR_PBL_8DW; 986 987 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 988 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 989 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 990 991 /* Turn off maximum power saving, etc. 992 * 993 * XXX Following example of reference driver, should I set 994 * an AID of 1? It didn't seem to help.... 995 */ 996 ATW_WRITE(sc, ATW_FRCTL, 0x0); 997 998 DELAY(atw_magic_delay2); 999 1000 /* Recall EEPROM. */ 1001 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1002 1003 DELAY(atw_magic_delay4); 1004 1005 lpc = ATW_READ(sc, ATW_LPC); 1006 1007 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1008 1009 /* A reset seems to affect the SRAM contents, so put them into 1010 * a known state. 1011 */ 1012 atw_clear_sram(sc); 1013 1014 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1015 } 1016 1017 static void 1018 atw_clear_sram(struct atw_softc *sc) 1019 { 1020 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1021 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1022 /* XXX not for revision 0x20. */ 1023 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1024 } 1025 1026 /* TBD atw_init 1027 * 1028 * set MAC based on ic->ic_bss->myaddr 1029 * write WEP keys 1030 * set TX rate 1031 */ 1032 1033 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1034 * without receiving a beacon with the preferred BSSID & SSID. 1035 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1036 */ 1037 static void 1038 atw_wcsr_init(struct atw_softc *sc) 1039 { 1040 uint32_t wcsr; 1041 1042 wcsr = ATW_READ(sc, ATW_WCSR); 1043 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1044 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1045 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1046 1047 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1048 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1049 } 1050 1051 /* Turn off power management. Set Rx store-and-forward mode. */ 1052 static void 1053 atw_cmdr_init(struct atw_softc *sc) 1054 { 1055 uint32_t cmdr; 1056 cmdr = ATW_READ(sc, ATW_CMDR); 1057 cmdr &= ~ATW_CMDR_APM; 1058 cmdr |= ATW_CMDR_RTE; 1059 cmdr &= ~ATW_CMDR_DRT_MASK; 1060 cmdr |= ATW_CMDR_DRT_SF; 1061 1062 ATW_WRITE(sc, ATW_CMDR, cmdr); 1063 } 1064 1065 static void 1066 atw_tofs2_init(struct atw_softc *sc) 1067 { 1068 uint32_t tofs2; 1069 /* XXX this magic can probably be figured out from the RFMD docs */ 1070 #ifndef ATW_REFSLAVE 1071 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1072 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1073 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1074 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1075 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1076 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1077 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1078 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1079 #else 1080 /* XXX new magic from reference driver source */ 1081 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1082 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1083 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1084 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1085 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1086 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1087 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1088 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1089 #endif 1090 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1091 } 1092 1093 static void 1094 atw_nar_init(struct atw_softc *sc) 1095 { 1096 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1097 } 1098 1099 static void 1100 atw_txlmt_init(struct atw_softc *sc) 1101 { 1102 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1103 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1104 } 1105 1106 static void 1107 atw_test1_init(struct atw_softc *sc) 1108 { 1109 uint32_t test1; 1110 1111 test1 = ATW_READ(sc, ATW_TEST1); 1112 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1113 /* XXX magic 0x1 */ 1114 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1115 ATW_WRITE(sc, ATW_TEST1, test1); 1116 } 1117 1118 static void 1119 atw_rf_reset(struct atw_softc *sc) 1120 { 1121 /* XXX this resets an Intersil RF front-end? */ 1122 /* TBD condition on Intersil RFType? */ 1123 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1124 DELAY(atw_rf_delay1); 1125 ATW_WRITE(sc, ATW_SYNRF, 0); 1126 DELAY(atw_rf_delay2); 1127 } 1128 1129 /* Set 16 TU max duration for the contention-free period (CFP). */ 1130 static void 1131 atw_cfp_init(struct atw_softc *sc) 1132 { 1133 uint32_t cfpp; 1134 1135 cfpp = ATW_READ(sc, ATW_CFPP); 1136 cfpp &= ~ATW_CFPP_CFPMD; 1137 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1138 ATW_WRITE(sc, ATW_CFPP, cfpp); 1139 } 1140 1141 static void 1142 atw_tofs0_init(struct atw_softc *sc) 1143 { 1144 /* XXX I guess that the Cardbus clock is 22MHz? 1145 * I am assuming that the role of ATW_TOFS0_USCNT is 1146 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1147 * very clear on this point. It says in the datasheet that it is 1148 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1149 * and 33MHz; maybe this is the way? I see a binary-only driver write 1150 * these values. These values are also the power-on default. 1151 */ 1152 ATW_WRITE(sc, ATW_TOFS0, 1153 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1154 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1155 } 1156 1157 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1158 static void 1159 atw_ifs_init(struct atw_softc *sc) 1160 { 1161 uint32_t ifst; 1162 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1163 * Go figure. 1164 */ 1165 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1166 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1167 ATW_IFST_SIFS_MASK) | 1168 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1169 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1170 1171 ATW_WRITE(sc, ATW_IFST, ifst); 1172 } 1173 1174 static void 1175 atw_response_times_init(struct atw_softc *sc) 1176 { 1177 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1178 * indicate that the MAC expects at least SIFS + MIRT microseconds 1179 * to pass after it transmits a frame that requires a response; 1180 * it waits at most SIFS + MART microseconds for the response. 1181 * Surely this is not the ACK timeout? 1182 */ 1183 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1184 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1185 } 1186 1187 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1188 * engines read and write baseband registers after Rx and before 1189 * Tx, respectively. 1190 */ 1191 static void 1192 atw_bbp_io_init(struct atw_softc *sc) 1193 { 1194 uint32_t mmiraddr2; 1195 1196 /* XXX The reference driver does this, but is it *really* 1197 * necessary? 1198 */ 1199 switch (sc->sc_rev) { 1200 case ATW_REVISION_AB: 1201 case ATW_REVISION_AF: 1202 mmiraddr2 = 0x0; 1203 break; 1204 default: 1205 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1206 mmiraddr2 &= 1207 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1208 break; 1209 } 1210 1211 switch (sc->sc_bbptype) { 1212 case ATW_BBPTYPE_INTERSIL: 1213 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1214 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1215 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1216 break; 1217 case ATW_BBPTYPE_MARVEL: 1218 /* TBD find out the Marvel settings. */ 1219 break; 1220 case ATW_BBPTYPE_RFMD: 1221 default: 1222 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1223 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1224 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1225 break; 1226 } 1227 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1228 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1229 } 1230 1231 /* 1232 * atw_init: [ ifnet interface function ] 1233 * 1234 * Initialize the interface. Must be called at splnet(). 1235 */ 1236 int 1237 atw_init(struct ifnet *ifp) 1238 { 1239 struct atw_softc *sc = ifp->if_softc; 1240 struct ieee80211com *ic = &sc->sc_ic; 1241 struct atw_txsoft *txs; 1242 struct atw_rxsoft *rxs; 1243 int i, error = 0; 1244 1245 if ((error = atw_enable(sc)) != 0) 1246 goto out; 1247 1248 /* 1249 * Cancel any pending I/O. This also resets. 1250 */ 1251 atw_stop(ifp, 0); 1252 1253 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1254 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1255 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1256 1257 atw_wcsr_init(sc); 1258 1259 atw_cmdr_init(sc); 1260 1261 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1262 * 1263 * XXX Set transmit power for ATIM, RTS, Beacon. 1264 */ 1265 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1266 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1267 1268 atw_tofs2_init(sc); 1269 1270 atw_nar_init(sc); 1271 1272 atw_txlmt_init(sc); 1273 1274 atw_test1_init(sc); 1275 1276 atw_rf_reset(sc); 1277 1278 atw_cfp_init(sc); 1279 1280 atw_tofs0_init(sc); 1281 1282 atw_ifs_init(sc); 1283 1284 /* XXX Fall asleep after one second of inactivity. 1285 * XXX A frame may only dribble in for 65536us. 1286 */ 1287 ATW_WRITE(sc, ATW_RMD, 1288 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1289 1290 atw_response_times_init(sc); 1291 1292 atw_bbp_io_init(sc); 1293 1294 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1295 1296 if ((error = atw_rf3000_init(sc)) != 0) 1297 goto out; 1298 1299 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1300 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1301 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1302 1303 /* 1304 * Initialize the transmit descriptor ring. 1305 */ 1306 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1307 for (i = 0; i < ATW_NTXDESC; i++) { 1308 sc->sc_txdescs[i].at_ctl = 0; 1309 /* no transmit chaining */ 1310 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1311 sc->sc_txdescs[i].at_buf2 = 1312 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1313 } 1314 /* use ring mode */ 1315 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1316 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1317 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1318 sc->sc_txfree = ATW_NTXDESC; 1319 sc->sc_txnext = 0; 1320 1321 /* 1322 * Initialize the transmit job descriptors. 1323 */ 1324 SIMPLEQ_INIT(&sc->sc_txfreeq); 1325 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1326 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1327 txs = &sc->sc_txsoft[i]; 1328 txs->txs_mbuf = NULL; 1329 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1330 } 1331 1332 /* 1333 * Initialize the receive descriptor and receive job 1334 * descriptor rings. 1335 */ 1336 for (i = 0; i < ATW_NRXDESC; i++) { 1337 rxs = &sc->sc_rxsoft[i]; 1338 if (rxs->rxs_mbuf == NULL) { 1339 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1340 printf("%s: unable to allocate or map rx " 1341 "buffer %d, error = %d\n", 1342 sc->sc_dev.dv_xname, i, error); 1343 /* 1344 * XXX Should attempt to run with fewer receive 1345 * XXX buffers instead of just failing. 1346 */ 1347 atw_rxdrain(sc); 1348 goto out; 1349 } 1350 } else 1351 ATW_INIT_RXDESC(sc, i); 1352 } 1353 sc->sc_rxptr = 0; 1354 1355 /* 1356 * Initialize the interrupt mask and enable interrupts. 1357 */ 1358 /* normal interrupts */ 1359 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1360 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1361 1362 /* abnormal interrupts */ 1363 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1364 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1365 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1366 1367 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1368 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1369 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1370 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1371 ATW_INTR_TRT; 1372 1373 sc->sc_linkint_mask &= sc->sc_inten; 1374 sc->sc_rxint_mask &= sc->sc_inten; 1375 sc->sc_txint_mask &= sc->sc_inten; 1376 1377 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1378 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1379 1380 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1381 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1382 1383 /* 1384 * Give the transmit and receive rings to the ADM8211. 1385 */ 1386 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1387 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1388 1389 sc->sc_txthresh = 0; 1390 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1391 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1392 1393 /* common 802.11 configuration */ 1394 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1395 switch (ic->ic_opmode) { 1396 case IEEE80211_M_STA: 1397 break; 1398 case IEEE80211_M_AHDEMO: /* XXX */ 1399 case IEEE80211_M_IBSS: 1400 ic->ic_flags |= IEEE80211_F_IBSSON; 1401 /*FALLTHROUGH*/ 1402 case IEEE80211_M_HOSTAP: /* XXX */ 1403 break; 1404 case IEEE80211_M_MONITOR: /* XXX */ 1405 break; 1406 } 1407 1408 switch (ic->ic_opmode) { 1409 case IEEE80211_M_AHDEMO: 1410 case IEEE80211_M_HOSTAP: 1411 #ifndef IEEE80211_NO_HOSTAP 1412 ic->ic_bss->ni_intval = ic->ic_lintval; 1413 ic->ic_bss->ni_rssi = 0; 1414 ic->ic_bss->ni_rstamp = 0; 1415 #endif /* !IEEE80211_NO_HOSTAP */ 1416 break; 1417 default: /* XXX */ 1418 break; 1419 } 1420 1421 sc->sc_wepctl = 0; 1422 1423 atw_write_ssid(sc); 1424 atw_write_sup_rates(sc); 1425 atw_write_wep(sc); 1426 1427 ic->ic_state = IEEE80211_S_INIT; 1428 1429 /* 1430 * Set the receive filter. This will start the transmit and 1431 * receive processes. 1432 */ 1433 atw_filter_setup(sc); 1434 1435 /* 1436 * Start the receive process. 1437 */ 1438 ATW_WRITE(sc, ATW_RDR, 0x1); 1439 1440 /* 1441 * Note that the interface is now running. 1442 */ 1443 ifp->if_flags |= IFF_RUNNING; 1444 ifp->if_flags &= ~IFF_OACTIVE; 1445 1446 /* send no beacons, yet. */ 1447 atw_start_beacon(sc, 0); 1448 1449 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1450 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1451 else 1452 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1453 out: 1454 if (error) { 1455 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1456 sc->sc_tx_timer = 0; 1457 ifp->if_timer = 0; 1458 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1459 } 1460 #ifdef ATW_DEBUG 1461 atw_print_regs(sc, "end of init"); 1462 #endif /* ATW_DEBUG */ 1463 1464 return (error); 1465 } 1466 1467 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1468 * 0: MAC control of RF3000/Si4126. 1469 * 1470 * Applies power, or selects RF front-end? Sets reset condition. 1471 * 1472 * TBD support non-RFMD BBP, non-SiLabs synth. 1473 */ 1474 static void 1475 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1476 { 1477 if (enable) { 1478 ATW_WRITE(sc, ATW_SYNRF, 1479 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1480 DELAY(atw_bbp_io_enable_delay); 1481 } else { 1482 ATW_WRITE(sc, ATW_SYNRF, 0); 1483 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1484 } 1485 } 1486 1487 static int 1488 atw_tune(struct atw_softc *sc) 1489 { 1490 int rc; 1491 u_int chan; 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 1494 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1495 if (chan == IEEE80211_CHAN_ANY) 1496 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1497 1498 if (chan == sc->sc_cur_chan) 1499 return 0; 1500 1501 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1502 sc->sc_cur_chan, chan)); 1503 1504 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1505 1506 atw_si4126_tune(sc, chan); 1507 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1508 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1509 chan); 1510 1511 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1512 DELAY(atw_nar_delay); 1513 ATW_WRITE(sc, ATW_RDR, 0x1); 1514 1515 if (rc == 0) 1516 sc->sc_cur_chan = chan; 1517 1518 return rc; 1519 } 1520 1521 #ifdef ATW_SYNDEBUG 1522 static void 1523 atw_si4126_print(struct atw_softc *sc) 1524 { 1525 struct ifnet *ifp = &sc->sc_if; 1526 u_int addr, val; 1527 1528 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1529 return; 1530 1531 for (addr = 0; addr <= 8; addr++) { 1532 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1533 if (atw_si4126_read(sc, addr, &val) == 0) { 1534 printf("<unknown> (quitting print-out)\n"); 1535 break; 1536 } 1537 printf("%05x\n", val); 1538 } 1539 } 1540 #endif /* ATW_SYNDEBUG */ 1541 1542 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1543 * 1544 * The RF/IF synthesizer produces two reference frequencies for 1545 * the RF2948B transceiver. The first frequency the RF2948B requires 1546 * is two times the so-called "intermediate frequency" (IF). Since 1547 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1548 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1549 * frequency required by the transceiver is the radio frequency 1550 * (RF). This is a superheterodyne transceiver; for f(chan) the 1551 * center frequency of the channel we are tuning, RF = f(chan) - 1552 * IF. 1553 * 1554 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1555 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1556 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1557 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1558 */ 1559 static void 1560 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1561 { 1562 u_int mhz; 1563 u_int R; 1564 u_int32_t gpio; 1565 u_int16_t gain; 1566 1567 #ifdef ATW_SYNDEBUG 1568 atw_si4126_print(sc); 1569 #endif /* ATW_SYNDEBUG */ 1570 1571 if (chan == 14) 1572 mhz = 2484; 1573 else 1574 mhz = 2412 + 5 * (chan - 1); 1575 1576 /* Tune IF to 748MHz to suit the IF LO input of the 1577 * RF2494B, which is 2 x IF. No need to set an IF divider 1578 * because an IF in 526MHz - 952MHz is allowed. 1579 * 1580 * XIN is 44.000MHz, so divide it by two to get allowable 1581 * range of 2-25MHz. SiLabs tells me that this is not 1582 * strictly necessary. 1583 */ 1584 1585 if (atw_xindiv2) 1586 R = 44; 1587 else 1588 R = 88; 1589 1590 /* Power-up RF, IF synthesizers. */ 1591 atw_si4126_write(sc, SI4126_POWER, 1592 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1593 1594 /* set LPWR, too? */ 1595 atw_si4126_write(sc, SI4126_MAIN, 1596 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1597 1598 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1599 * set KP2 to 1. 1600 * 1601 * REFDIF This is different from the reference driver, which 1602 * always sets SI4126_GAIN to 0. 1603 */ 1604 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1605 1606 atw_si4126_write(sc, SI4126_GAIN, gain); 1607 1608 /* XIN = 44MHz. 1609 * 1610 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1611 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1612 * 1613 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1614 * so that 1496/88 * 44MHz = 748MHz. 1615 */ 1616 atw_si4126_write(sc, SI4126_IFN, 1496); 1617 1618 atw_si4126_write(sc, SI4126_IFR, R); 1619 1620 #ifndef ATW_REFSLAVE 1621 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1622 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1623 * which has no RF1! 1624 */ 1625 atw_si4126_write(sc, SI4126_RF1R, R); 1626 1627 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1628 #endif 1629 1630 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1631 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1632 * Now let's multiply it to mhz. So mhz - IF = N. 1633 */ 1634 atw_si4126_write(sc, SI4126_RF2R, R); 1635 1636 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1637 1638 /* wait 100us from power-up for RF, IF to settle */ 1639 DELAY(100); 1640 1641 gpio = ATW_READ(sc, ATW_GPIO); 1642 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1643 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1644 1645 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1646 /* Set a Prism RF front-end to a special mode for channel 14? 1647 * 1648 * Apparently the SMC2635W needs this, although I don't think 1649 * it has a Prism RF. 1650 */ 1651 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1652 } 1653 ATW_WRITE(sc, ATW_GPIO, gpio); 1654 1655 #ifdef ATW_SYNDEBUG 1656 atw_si4126_print(sc); 1657 #endif /* ATW_SYNDEBUG */ 1658 } 1659 1660 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1661 * diversity. 1662 * 1663 * !!! 1664 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1665 * !!! 1666 */ 1667 static int 1668 atw_rf3000_init(struct atw_softc *sc) 1669 { 1670 int rc = 0; 1671 1672 atw_bbp_io_enable(sc, 1); 1673 1674 /* CCA is acquisition sensitive */ 1675 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1676 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1677 1678 if (rc != 0) 1679 goto out; 1680 1681 /* enable diversity */ 1682 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1683 1684 if (rc != 0) 1685 goto out; 1686 1687 /* sensible setting from a binary-only driver */ 1688 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1689 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1690 1691 if (rc != 0) 1692 goto out; 1693 1694 /* magic from a binary-only driver */ 1695 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1696 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1697 1698 if (rc != 0) 1699 goto out; 1700 1701 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1702 1703 if (rc != 0) 1704 goto out; 1705 1706 /* XXX Reference driver remarks that Abocom sets this to 50. 1707 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1708 * in the "reserved" area of register RF3000_OPTIONS1. 1709 */ 1710 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1711 1712 if (rc != 0) 1713 goto out; 1714 1715 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1716 1717 if (rc != 0) 1718 goto out; 1719 1720 out: 1721 atw_bbp_io_enable(sc, 0); 1722 return rc; 1723 } 1724 1725 #ifdef ATW_BBPDEBUG 1726 static void 1727 atw_rf3000_print(struct atw_softc *sc) 1728 { 1729 struct ifnet *ifp = &sc->sc_if; 1730 u_int addr, val; 1731 1732 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1733 return; 1734 1735 for (addr = 0x01; addr <= 0x15; addr++) { 1736 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1737 if (atw_rf3000_read(sc, addr, &val) != 0) { 1738 printf("<unknown> (quitting print-out)\n"); 1739 break; 1740 } 1741 printf("%08x\n", val); 1742 } 1743 } 1744 #endif /* ATW_BBPDEBUG */ 1745 1746 /* Set the power settings on the BBP for channel `chan'. */ 1747 static int 1748 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1749 { 1750 int rc = 0; 1751 u_int32_t reg; 1752 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1753 1754 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1755 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1756 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1757 1758 /* odd channels: LSB, even channels: MSB */ 1759 if (chan % 2 == 1) { 1760 txpower &= 0xFF; 1761 lpf_cutoff &= 0xFF; 1762 lna_gs_thresh &= 0xFF; 1763 } else { 1764 txpower >>= 8; 1765 lpf_cutoff >>= 8; 1766 lna_gs_thresh >>= 8; 1767 } 1768 1769 #ifdef ATW_BBPDEBUG 1770 atw_rf3000_print(sc); 1771 #endif /* ATW_BBPDEBUG */ 1772 1773 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1774 "lna_gs_thresh %02x\n", 1775 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1776 1777 atw_bbp_io_enable(sc, 1); 1778 1779 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1780 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1781 goto out; 1782 1783 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1784 goto out; 1785 1786 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1787 goto out; 1788 1789 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1790 1791 if (rc != 0) 1792 goto out; 1793 1794 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1795 1796 if (rc != 0) 1797 goto out; 1798 1799 #ifdef ATW_BBPDEBUG 1800 atw_rf3000_print(sc); 1801 #endif /* ATW_BBPDEBUG */ 1802 1803 out: 1804 atw_bbp_io_enable(sc, 0); 1805 1806 /* set beacon, rts, atim transmit power */ 1807 reg = ATW_READ(sc, ATW_PLCPHD); 1808 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1809 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1810 ATW_PLCPHD_SERVICE_MASK); 1811 ATW_WRITE(sc, ATW_PLCPHD, reg); 1812 DELAY(atw_plcphd_delay); 1813 1814 return rc; 1815 } 1816 1817 /* Write a register on the RF3000 baseband processor using the 1818 * registers provided by the ADM8211 for this purpose. 1819 * 1820 * Return 0 on success. 1821 */ 1822 static int 1823 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1824 { 1825 u_int32_t reg; 1826 int i; 1827 1828 reg = sc->sc_bbpctl_wr | 1829 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1830 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1831 1832 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1833 ATW_WRITE(sc, ATW_BBPCTL, reg); 1834 DELAY(2 * atw_pseudo_milli); 1835 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1836 break; 1837 } 1838 1839 if (i < 0) { 1840 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1841 return ETIMEDOUT; 1842 } 1843 return 0; 1844 } 1845 1846 /* Read a register on the RF3000 baseband processor using the registers 1847 * the ADM8211 provides for this purpose. 1848 * 1849 * The 7-bit register address is addr. Record the 8-bit data in the register 1850 * in *val. 1851 * 1852 * Return 0 on success. 1853 * 1854 * XXX This does not seem to work. The ADM8211 must require more or 1855 * different magic to read the chip than to write it. Possibly some 1856 * of the magic I have derived from a binary-only driver concerns 1857 * the "chip address" (see the RF3000 manual). 1858 */ 1859 #ifdef ATW_BBPDEBUG 1860 static int 1861 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1862 { 1863 u_int32_t reg; 1864 int i; 1865 1866 for (i = 1000; --i >= 0; ) { 1867 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1868 break; 1869 DELAY(100); 1870 } 1871 1872 if (i < 0) { 1873 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1874 sc->sc_dev.dv_xname); 1875 return ETIMEDOUT; 1876 } 1877 1878 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1879 1880 ATW_WRITE(sc, ATW_BBPCTL, reg); 1881 1882 for (i = 1000; --i >= 0; ) { 1883 DELAY(100); 1884 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1885 break; 1886 } 1887 1888 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1889 1890 if (i < 0) { 1891 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1892 sc->sc_dev.dv_xname, reg); 1893 return ETIMEDOUT; 1894 } 1895 if (val != NULL) 1896 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1897 return 0; 1898 } 1899 #endif /* ATW_BBPDEBUG */ 1900 1901 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1902 * provided by the ADM8211 for that purpose. 1903 * 1904 * val is 18 bits of data, and val is the 4-bit address of the register. 1905 * 1906 * Return 0 on success. 1907 */ 1908 static void 1909 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1910 { 1911 uint32_t bits, mask, reg; 1912 const int nbits = 22; 1913 1914 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1915 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1916 1917 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1918 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1919 1920 reg = ATW_SYNRF_SELSYN; 1921 /* reference driver: reset Si4126 serial bus to initial 1922 * conditions? 1923 */ 1924 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1925 ATW_WRITE(sc, ATW_SYNRF, reg); 1926 1927 for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) { 1928 if ((bits & mask) != 0) 1929 reg |= ATW_SYNRF_SYNDATA; 1930 else 1931 reg &= ~ATW_SYNRF_SYNDATA; 1932 ATW_WRITE(sc, ATW_SYNRF, reg); 1933 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1934 ATW_WRITE(sc, ATW_SYNRF, reg); 1935 } 1936 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1937 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1938 } 1939 1940 /* Read 18-bit data from the 4-bit address addr in Si4126 1941 * RF synthesizer and write the data to *val. Return 0 on success. 1942 * 1943 * XXX This does not seem to work. The ADM8211 must require more or 1944 * different magic to read the chip than to write it. 1945 */ 1946 #ifdef ATW_SYNDEBUG 1947 static int 1948 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1949 { 1950 u_int32_t reg; 1951 int i; 1952 1953 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1954 1955 for (i = 1000; --i >= 0; ) { 1956 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1957 break; 1958 DELAY(100); 1959 } 1960 1961 if (i < 0) { 1962 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1963 sc->sc_dev.dv_xname); 1964 return ETIMEDOUT; 1965 } 1966 1967 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1968 1969 ATW_WRITE(sc, ATW_SYNCTL, reg); 1970 1971 for (i = 1000; --i >= 0; ) { 1972 DELAY(100); 1973 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1974 break; 1975 } 1976 1977 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1978 1979 if (i < 0) { 1980 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1981 sc->sc_dev.dv_xname, reg); 1982 return ETIMEDOUT; 1983 } 1984 if (val != NULL) 1985 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1986 ATW_SYNCTL_DATA_MASK); 1987 return 0; 1988 } 1989 #endif /* ATW_SYNDEBUG */ 1990 1991 /* XXX is the endianness correct? test. */ 1992 #define atw_calchash(addr) \ 1993 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1994 1995 /* 1996 * atw_filter_setup: 1997 * 1998 * Set the ADM8211's receive filter. 1999 */ 2000 static void 2001 atw_filter_setup(struct atw_softc *sc) 2002 { 2003 struct ieee80211com *ic = &sc->sc_ic; 2004 struct ethercom *ec = &sc->sc_ec; 2005 struct ifnet *ifp = &sc->sc_if; 2006 int hash; 2007 u_int32_t hashes[2]; 2008 struct ether_multi *enm; 2009 struct ether_multistep step; 2010 2011 /* According to comments in tlp_al981_filter_setup 2012 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2013 * multicast filter to be set while it is running. Hopefully 2014 * the ADM8211 is not the same! 2015 */ 2016 if ((ifp->if_flags & IFF_RUNNING) != 0) 2017 atw_idle(sc, ATW_NAR_SR); 2018 2019 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2020 ifp->if_flags &= ~IFF_ALLMULTI; 2021 2022 /* XXX in scan mode, do not filter packets. Maybe this is 2023 * unnecessary. 2024 */ 2025 if (ic->ic_state == IEEE80211_S_SCAN || 2026 (ifp->if_flags & IFF_PROMISC) != 0) { 2027 sc->sc_opmode |= ATW_NAR_PR; 2028 goto allmulti; 2029 } 2030 2031 hashes[0] = hashes[1] = 0x0; 2032 2033 /* 2034 * Program the 64-bit multicast hash filter. 2035 */ 2036 ETHER_FIRST_MULTI(step, ec, enm); 2037 while (enm != NULL) { 2038 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2039 ETHER_ADDR_LEN) != 0) 2040 goto allmulti; 2041 2042 hash = atw_calchash(enm->enm_addrlo); 2043 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2044 ETHER_NEXT_MULTI(step, enm); 2045 sc->sc_opmode |= ATW_NAR_MM; 2046 } 2047 ifp->if_flags &= ~IFF_ALLMULTI; 2048 goto setit; 2049 2050 allmulti: 2051 sc->sc_opmode |= ATW_NAR_MM; 2052 ifp->if_flags |= IFF_ALLMULTI; 2053 hashes[0] = hashes[1] = 0xffffffff; 2054 2055 setit: 2056 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2057 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2058 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2059 DELAY(atw_nar_delay); 2060 2061 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2062 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2063 } 2064 2065 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2066 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2067 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2068 * no beacon with the preferred BSSID and SSID in the number of 2069 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2070 */ 2071 static void 2072 atw_write_bssid(struct atw_softc *sc) 2073 { 2074 struct ieee80211com *ic = &sc->sc_ic; 2075 u_int8_t *bssid; 2076 2077 bssid = ic->ic_bss->ni_bssid; 2078 2079 ATW_WRITE(sc, ATW_BSSID0, 2080 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2081 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2082 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2083 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2084 2085 ATW_WRITE(sc, ATW_ABDA1, 2086 (ATW_READ(sc, ATW_ABDA1) & 2087 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2088 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2089 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2090 2091 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2092 ether_sprintf(sc->sc_bssid))); 2093 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2094 2095 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2096 } 2097 2098 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2099 * 16-bit word. 2100 */ 2101 static void 2102 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2103 { 2104 u_int i; 2105 u_int8_t *ptr; 2106 2107 memcpy(&sc->sc_sram[ofs], buf, buflen); 2108 2109 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2110 2111 KASSERT(buflen + ofs <= sc->sc_sramlen); 2112 2113 ptr = &sc->sc_sram[ofs]; 2114 2115 for (i = 0; i < buflen; i += 2) { 2116 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2117 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2118 DELAY(atw_writewep_delay); 2119 2120 ATW_WRITE(sc, ATW_WESK, 2121 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2122 DELAY(atw_writewep_delay); 2123 } 2124 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2125 2126 if (sc->sc_if.if_flags & IFF_DEBUG) { 2127 int n_octets = 0; 2128 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2129 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2130 for (i = 0; i < buflen; i++) { 2131 printf(" %02x", ptr[i]); 2132 if (++n_octets % 24 == 0) 2133 printf("\n"); 2134 } 2135 if (n_octets % 24 != 0) 2136 printf("\n"); 2137 } 2138 } 2139 2140 static int 2141 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2142 { 2143 struct atw_softc *sc = ic->ic_ifp->if_softc; 2144 u_int keyix = k->wk_keyix; 2145 2146 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2147 2148 if (keyix >= IEEE80211_WEP_NKID) 2149 return 0; 2150 if (k->wk_keylen != 0) 2151 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2152 2153 return 1; 2154 } 2155 2156 static int 2157 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2158 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2159 { 2160 struct atw_softc *sc = ic->ic_ifp->if_softc; 2161 2162 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2163 2164 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2165 return 0; 2166 2167 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2168 2169 return 1; 2170 } 2171 2172 static void 2173 atw_key_update_begin(struct ieee80211com *ic) 2174 { 2175 #ifdef ATW_DEBUG 2176 struct ifnet *ifp = ic->ic_ifp; 2177 struct atw_softc *sc = ifp->if_softc; 2178 #endif 2179 2180 DPRINTF(sc, ("%s:\n", __func__)); 2181 } 2182 2183 static void 2184 atw_key_update_end(struct ieee80211com *ic) 2185 { 2186 struct ifnet *ifp = ic->ic_ifp; 2187 struct atw_softc *sc = ifp->if_softc; 2188 2189 DPRINTF(sc, ("%s:\n", __func__)); 2190 2191 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2192 return; 2193 if (ATW_IS_ENABLED(sc) == 0) 2194 return; 2195 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2196 atw_write_wep(sc); 2197 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2198 } 2199 2200 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2201 static void 2202 atw_write_wep(struct atw_softc *sc) 2203 { 2204 struct ieee80211com *ic = &sc->sc_ic; 2205 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2206 u_int8_t buf[IEEE80211_WEP_NKID] 2207 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2208 u_int32_t reg; 2209 int i; 2210 2211 sc->sc_wepctl = 0; 2212 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2213 2214 memset(&buf[0][0], 0, sizeof(buf)); 2215 2216 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2217 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2218 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2219 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2220 buf[i][1] = ATW_WEP_ENABLED; 2221 } else { 2222 buf[i][1] = 0; 2223 continue; 2224 } 2225 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2226 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2227 ic->ic_nw_keys[i].wk_keylen - 1); 2228 } 2229 2230 reg = ATW_READ(sc, ATW_MACTEST); 2231 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2232 reg &= ~ATW_MACTEST_KEYID_MASK; 2233 reg |= LSHIFT(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2234 ATW_WRITE(sc, ATW_MACTEST, reg); 2235 2236 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2237 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2238 2239 switch (sc->sc_rev) { 2240 case ATW_REVISION_AB: 2241 case ATW_REVISION_AF: 2242 /* Bypass WEP on Rx. */ 2243 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2244 break; 2245 default: 2246 break; 2247 } 2248 2249 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2250 sizeof(buf)); 2251 2252 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2253 } 2254 2255 static void 2256 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2257 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2258 { 2259 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2260 2261 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2262 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2263 return; 2264 2265 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2266 2267 switch (subtype) { 2268 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2269 case IEEE80211_FC0_SUBTYPE_BEACON: 2270 if (ic->ic_opmode == IEEE80211_M_IBSS && 2271 ic->ic_state == IEEE80211_S_RUN) { 2272 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2273 (void)ieee80211_ibss_merge(ni); 2274 } 2275 break; 2276 default: 2277 break; 2278 } 2279 return; 2280 } 2281 2282 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2283 * In ad hoc mode, the SSID is written to the beacons sent by the 2284 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2285 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2286 * indications. 2287 */ 2288 static void 2289 atw_write_ssid(struct atw_softc *sc) 2290 { 2291 struct ieee80211com *ic = &sc->sc_ic; 2292 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2293 * it only expects the element length, not its ID. 2294 */ 2295 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2296 2297 memset(buf, 0, sizeof(buf)); 2298 buf[0] = ic->ic_bss->ni_esslen; 2299 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2300 2301 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2302 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2303 } 2304 2305 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2306 * In ad hoc mode, the supported rates are written to beacons sent by the 2307 * ADM8211. 2308 */ 2309 static void 2310 atw_write_sup_rates(struct atw_softc *sc) 2311 { 2312 struct ieee80211com *ic = &sc->sc_ic; 2313 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2314 * supported rates 2315 */ 2316 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2317 2318 memset(buf, 0, sizeof(buf)); 2319 2320 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2321 2322 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2323 ic->ic_bss->ni_rates.rs_nrates); 2324 2325 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2326 } 2327 2328 /* Start/stop sending beacons. */ 2329 void 2330 atw_start_beacon(struct atw_softc *sc, int start) 2331 { 2332 struct ieee80211com *ic = &sc->sc_ic; 2333 uint16_t chan; 2334 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2335 size_t len; 2336 2337 if (ATW_IS_ENABLED(sc) == 0) 2338 return; 2339 2340 /* start beacons */ 2341 len = sizeof(struct ieee80211_frame) + 2342 8 /* timestamp */ + 2 /* beacon interval */ + 2343 2 /* capability info */ + 2344 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2345 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2346 3 /* DS parameters */ + 2347 IEEE80211_CRC_LEN; 2348 2349 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2350 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2351 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2352 2353 ATW_WRITE(sc, ATW_BCNT, bcnt); 2354 ATW_WRITE(sc, ATW_CAP1, cap1); 2355 2356 if (!start) 2357 return; 2358 2359 /* TBD use ni_capinfo */ 2360 2361 capinfo = 0; 2362 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2363 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2364 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2365 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2366 2367 switch (ic->ic_opmode) { 2368 case IEEE80211_M_IBSS: 2369 len += 4; /* IBSS parameters */ 2370 capinfo |= IEEE80211_CAPINFO_IBSS; 2371 break; 2372 case IEEE80211_M_HOSTAP: 2373 /* XXX 6-byte minimum TIM */ 2374 len += atw_beacon_len_adjust; 2375 capinfo |= IEEE80211_CAPINFO_ESS; 2376 break; 2377 default: 2378 return; 2379 } 2380 2381 /* set listen interval 2382 * XXX do software units agree w/ hardware? 2383 */ 2384 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2385 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2386 2387 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2388 2389 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2390 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2391 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2392 2393 ATW_WRITE(sc, ATW_BCNT, bcnt); 2394 ATW_WRITE(sc, ATW_BPLI, bpli); 2395 ATW_WRITE(sc, ATW_CAP0, cap0); 2396 ATW_WRITE(sc, ATW_CAP1, cap1); 2397 2398 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2399 sc->sc_dev.dv_xname, bcnt)); 2400 2401 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2402 sc->sc_dev.dv_xname, cap1)); 2403 } 2404 2405 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2406 static inline uint32_t 2407 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2408 { 2409 /* Following the reference driver's lead, I compute 2410 * 2411 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2412 * 2413 * without using 64-bit arithmetic, using the following 2414 * relationship: 2415 * 2416 * (0x100000000 * H + L) % m 2417 * = ((0x100000000 % m) * H + L) % m 2418 * = (((0xffffffff + 1) % m) * H + L) % m 2419 * = ((0xffffffff % m + 1 % m) * H + L) % m 2420 * = ((0xffffffff % m + 1) * H + L) % m 2421 */ 2422 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2423 } 2424 2425 static uint64_t 2426 atw_get_tsft(struct atw_softc *sc) 2427 { 2428 int i; 2429 uint32_t tsfth, tsftl; 2430 for (i = 0; i < 2; i++) { 2431 tsfth = ATW_READ(sc, ATW_TSFTH); 2432 tsftl = ATW_READ(sc, ATW_TSFTL); 2433 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2434 break; 2435 } 2436 return ((uint64_t)tsfth << 32) | tsftl; 2437 } 2438 2439 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2440 * the ieee80211com. 2441 * 2442 * Predict the next target beacon transmission time (TBTT) and 2443 * write it to the ADM8211. 2444 */ 2445 static void 2446 atw_predict_beacon(struct atw_softc *sc) 2447 { 2448 #define TBTTOFS 20 /* TU */ 2449 2450 struct ieee80211com *ic = &sc->sc_ic; 2451 uint64_t tsft; 2452 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2453 union { 2454 uint64_t word; 2455 uint8_t tstamp[8]; 2456 } u; 2457 2458 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2459 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2460 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2461 tsft = atw_get_tsft(sc); 2462 u.word = htole64(tsft); 2463 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2464 sizeof(ic->ic_bss->ni_tstamp)); 2465 } else 2466 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2467 2468 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2469 2470 tsftl = tsft & 0xFFFFFFFF; 2471 tsfth = tsft >> 32; 2472 2473 /* We sent/received the last beacon `past' microseconds 2474 * after the interval divided the TSF timer. 2475 */ 2476 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2477 2478 /* Skip ten beacons so that the TBTT cannot pass before 2479 * we've programmed it. Ten is an arbitrary number. 2480 */ 2481 tbtt = past_even + ival * 10; 2482 2483 ATW_WRITE(sc, ATW_TOFS1, 2484 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2485 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2486 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2487 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2488 #undef TBTTOFS 2489 } 2490 2491 static void 2492 atw_next_scan(void *arg) 2493 { 2494 struct atw_softc *sc = arg; 2495 struct ieee80211com *ic = &sc->sc_ic; 2496 int s; 2497 2498 /* don't call atw_start w/o network interrupts blocked */ 2499 s = splnet(); 2500 if (ic->ic_state == IEEE80211_S_SCAN) 2501 ieee80211_next_scan(ic); 2502 splx(s); 2503 } 2504 2505 /* Synchronize the hardware state with the software state. */ 2506 static int 2507 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2508 { 2509 struct ifnet *ifp = ic->ic_ifp; 2510 struct atw_softc *sc = ifp->if_softc; 2511 enum ieee80211_state ostate; 2512 int error = 0; 2513 2514 ostate = ic->ic_state; 2515 callout_stop(&sc->sc_scan_ch); 2516 atw_start_beacon(sc, 0); 2517 2518 switch (nstate) { 2519 case IEEE80211_S_ASSOC: 2520 error = atw_tune(sc); 2521 break; 2522 case IEEE80211_S_INIT: 2523 callout_stop(&sc->sc_scan_ch); 2524 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2525 break; 2526 case IEEE80211_S_SCAN: 2527 error = atw_tune(sc); 2528 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2529 atw_next_scan, sc); 2530 break; 2531 case IEEE80211_S_AUTH: 2532 error = atw_tune(sc); 2533 break; 2534 case IEEE80211_S_RUN: 2535 error = atw_tune(sc); 2536 atw_write_bssid(sc); 2537 atw_write_ssid(sc); 2538 atw_write_sup_rates(sc); 2539 2540 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2541 ic->ic_opmode == IEEE80211_M_MONITOR) 2542 break; 2543 2544 /* set listen interval 2545 * XXX do software units agree w/ hardware? 2546 */ 2547 ATW_WRITE(sc, ATW_BPLI, 2548 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2549 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2550 ATW_BPLI_LI_MASK)); 2551 2552 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2553 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2554 2555 atw_predict_beacon(sc); 2556 atw_start_beacon(sc, 2557 ic->ic_opmode == IEEE80211_M_HOSTAP || 2558 ic->ic_opmode == IEEE80211_M_IBSS); 2559 break; 2560 } 2561 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2562 } 2563 2564 /* 2565 * atw_add_rxbuf: 2566 * 2567 * Add a receive buffer to the indicated descriptor. 2568 */ 2569 int 2570 atw_add_rxbuf(struct atw_softc *sc, int idx) 2571 { 2572 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2573 struct mbuf *m; 2574 int error; 2575 2576 MGETHDR(m, M_DONTWAIT, MT_DATA); 2577 if (m == NULL) 2578 return (ENOBUFS); 2579 2580 MCLGET(m, M_DONTWAIT); 2581 if ((m->m_flags & M_EXT) == 0) { 2582 m_freem(m); 2583 return (ENOBUFS); 2584 } 2585 2586 if (rxs->rxs_mbuf != NULL) 2587 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2588 2589 rxs->rxs_mbuf = m; 2590 2591 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2592 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2593 BUS_DMA_READ|BUS_DMA_NOWAIT); 2594 if (error) { 2595 printf("%s: can't load rx DMA map %d, error = %d\n", 2596 sc->sc_dev.dv_xname, idx, error); 2597 panic("atw_add_rxbuf"); /* XXX */ 2598 } 2599 2600 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2601 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2602 2603 ATW_INIT_RXDESC(sc, idx); 2604 2605 return (0); 2606 } 2607 2608 /* 2609 * Release any queued transmit buffers. 2610 */ 2611 void 2612 atw_txdrain(struct atw_softc *sc) 2613 { 2614 struct atw_txsoft *txs; 2615 2616 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2617 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2618 if (txs->txs_mbuf != NULL) { 2619 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2620 m_freem(txs->txs_mbuf); 2621 txs->txs_mbuf = NULL; 2622 } 2623 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2624 sc->sc_txfree += txs->txs_ndescs; 2625 } 2626 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2627 sc->sc_tx_timer = 0; 2628 } 2629 2630 /* 2631 * atw_stop: [ ifnet interface function ] 2632 * 2633 * Stop transmission on the interface. 2634 */ 2635 void 2636 atw_stop(struct ifnet *ifp, int disable) 2637 { 2638 struct atw_softc *sc = ifp->if_softc; 2639 struct ieee80211com *ic = &sc->sc_ic; 2640 2641 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2642 2643 /* Disable interrupts. */ 2644 ATW_WRITE(sc, ATW_IER, 0); 2645 2646 /* Stop the transmit and receive processes. */ 2647 sc->sc_opmode = 0; 2648 ATW_WRITE(sc, ATW_NAR, 0); 2649 DELAY(atw_nar_delay); 2650 ATW_WRITE(sc, ATW_TDBD, 0); 2651 ATW_WRITE(sc, ATW_TDBP, 0); 2652 ATW_WRITE(sc, ATW_RDB, 0); 2653 2654 atw_txdrain(sc); 2655 2656 if (disable) { 2657 atw_rxdrain(sc); 2658 atw_disable(sc); 2659 } 2660 2661 /* 2662 * Mark the interface down and cancel the watchdog timer. 2663 */ 2664 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2665 sc->sc_tx_timer = 0; 2666 ifp->if_timer = 0; 2667 2668 if (!disable) 2669 atw_reset(sc); 2670 } 2671 2672 /* 2673 * atw_rxdrain: 2674 * 2675 * Drain the receive queue. 2676 */ 2677 void 2678 atw_rxdrain(struct atw_softc *sc) 2679 { 2680 struct atw_rxsoft *rxs; 2681 int i; 2682 2683 for (i = 0; i < ATW_NRXDESC; i++) { 2684 rxs = &sc->sc_rxsoft[i]; 2685 if (rxs->rxs_mbuf == NULL) 2686 continue; 2687 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2688 m_freem(rxs->rxs_mbuf); 2689 rxs->rxs_mbuf = NULL; 2690 } 2691 } 2692 2693 /* 2694 * atw_detach: 2695 * 2696 * Detach an ADM8211 interface. 2697 */ 2698 int 2699 atw_detach(struct atw_softc *sc) 2700 { 2701 struct ifnet *ifp = &sc->sc_if; 2702 struct atw_rxsoft *rxs; 2703 struct atw_txsoft *txs; 2704 int i; 2705 2706 /* 2707 * Succeed now if there isn't any work to do. 2708 */ 2709 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2710 return (0); 2711 2712 callout_stop(&sc->sc_scan_ch); 2713 2714 ieee80211_ifdetach(&sc->sc_ic); 2715 if_detach(ifp); 2716 2717 for (i = 0; i < ATW_NRXDESC; i++) { 2718 rxs = &sc->sc_rxsoft[i]; 2719 if (rxs->rxs_mbuf != NULL) { 2720 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2721 m_freem(rxs->rxs_mbuf); 2722 rxs->rxs_mbuf = NULL; 2723 } 2724 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2725 } 2726 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2727 txs = &sc->sc_txsoft[i]; 2728 if (txs->txs_mbuf != NULL) { 2729 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2730 m_freem(txs->txs_mbuf); 2731 txs->txs_mbuf = NULL; 2732 } 2733 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2734 } 2735 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2736 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2737 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2738 sizeof(struct atw_control_data)); 2739 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2740 2741 shutdownhook_disestablish(sc->sc_sdhook); 2742 powerhook_disestablish(sc->sc_powerhook); 2743 2744 if (sc->sc_srom) 2745 free(sc->sc_srom, M_DEVBUF); 2746 2747 return (0); 2748 } 2749 2750 /* atw_shutdown: make sure the interface is stopped at reboot time. */ 2751 void 2752 atw_shutdown(void *arg) 2753 { 2754 struct atw_softc *sc = arg; 2755 2756 atw_stop(&sc->sc_if, 1); 2757 } 2758 2759 int 2760 atw_intr(void *arg) 2761 { 2762 struct atw_softc *sc = arg; 2763 struct ifnet *ifp = &sc->sc_if; 2764 u_int32_t status, rxstatus, txstatus, linkstatus; 2765 int handled = 0, txthresh; 2766 2767 #ifdef DEBUG 2768 if (ATW_IS_ENABLED(sc) == 0) 2769 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2770 #endif 2771 2772 /* 2773 * If the interface isn't running, the interrupt couldn't 2774 * possibly have come from us. 2775 */ 2776 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2777 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2778 return (0); 2779 2780 for (;;) { 2781 status = ATW_READ(sc, ATW_STSR); 2782 2783 if (status) 2784 ATW_WRITE(sc, ATW_STSR, status); 2785 2786 #ifdef ATW_DEBUG 2787 #define PRINTINTR(flag) do { \ 2788 if ((status & flag) != 0) { \ 2789 printf("%s" #flag, delim); \ 2790 delim = ","; \ 2791 } \ 2792 } while (0) 2793 2794 if (atw_debug > 1 && status) { 2795 const char *delim = "<"; 2796 2797 printf("%s: reg[STSR] = %x", 2798 sc->sc_dev.dv_xname, status); 2799 2800 PRINTINTR(ATW_INTR_FBE); 2801 PRINTINTR(ATW_INTR_LINKOFF); 2802 PRINTINTR(ATW_INTR_LINKON); 2803 PRINTINTR(ATW_INTR_RCI); 2804 PRINTINTR(ATW_INTR_RDU); 2805 PRINTINTR(ATW_INTR_REIS); 2806 PRINTINTR(ATW_INTR_RPS); 2807 PRINTINTR(ATW_INTR_TCI); 2808 PRINTINTR(ATW_INTR_TDU); 2809 PRINTINTR(ATW_INTR_TLT); 2810 PRINTINTR(ATW_INTR_TPS); 2811 PRINTINTR(ATW_INTR_TRT); 2812 PRINTINTR(ATW_INTR_TUF); 2813 PRINTINTR(ATW_INTR_BCNTC); 2814 PRINTINTR(ATW_INTR_ATIME); 2815 PRINTINTR(ATW_INTR_TBTT); 2816 PRINTINTR(ATW_INTR_TSCZ); 2817 PRINTINTR(ATW_INTR_TSFTF); 2818 printf(">\n"); 2819 } 2820 #undef PRINTINTR 2821 #endif /* ATW_DEBUG */ 2822 2823 if ((status & sc->sc_inten) == 0) 2824 break; 2825 2826 handled = 1; 2827 2828 rxstatus = status & sc->sc_rxint_mask; 2829 txstatus = status & sc->sc_txint_mask; 2830 linkstatus = status & sc->sc_linkint_mask; 2831 2832 if (linkstatus) { 2833 atw_linkintr(sc, linkstatus); 2834 } 2835 2836 if (rxstatus) { 2837 /* Grab any new packets. */ 2838 atw_rxintr(sc); 2839 2840 if (rxstatus & ATW_INTR_RDU) { 2841 printf("%s: receive ring overrun\n", 2842 sc->sc_dev.dv_xname); 2843 /* Get the receive process going again. */ 2844 ATW_WRITE(sc, ATW_RDR, 0x1); 2845 break; 2846 } 2847 } 2848 2849 if (txstatus) { 2850 /* Sweep up transmit descriptors. */ 2851 atw_txintr(sc); 2852 2853 if (txstatus & ATW_INTR_TLT) 2854 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2855 sc->sc_dev.dv_xname)); 2856 2857 if (txstatus & ATW_INTR_TRT) 2858 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2859 sc->sc_dev.dv_xname)); 2860 2861 /* If Tx under-run, increase our transmit threshold 2862 * if another is available. 2863 */ 2864 txthresh = sc->sc_txthresh + 1; 2865 if ((txstatus & ATW_INTR_TUF) && 2866 sc->sc_txth[txthresh].txth_name != NULL) { 2867 /* Idle the transmit process. */ 2868 atw_idle(sc, ATW_NAR_ST); 2869 2870 sc->sc_txthresh = txthresh; 2871 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2872 sc->sc_opmode |= 2873 sc->sc_txth[txthresh].txth_opmode; 2874 printf("%s: transmit underrun; new " 2875 "threshold: %s\n", sc->sc_dev.dv_xname, 2876 sc->sc_txth[txthresh].txth_name); 2877 2878 /* Set the new threshold and restart 2879 * the transmit process. 2880 */ 2881 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2882 DELAY(atw_nar_delay); 2883 ATW_WRITE(sc, ATW_RDR, 0x1); 2884 /* XXX Log every Nth underrun from 2885 * XXX now on? 2886 */ 2887 } 2888 } 2889 2890 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2891 if (status & ATW_INTR_TPS) 2892 printf("%s: transmit process stopped\n", 2893 sc->sc_dev.dv_xname); 2894 if (status & ATW_INTR_RPS) 2895 printf("%s: receive process stopped\n", 2896 sc->sc_dev.dv_xname); 2897 (void)atw_init(ifp); 2898 break; 2899 } 2900 2901 if (status & ATW_INTR_FBE) { 2902 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2903 (void)atw_init(ifp); 2904 break; 2905 } 2906 2907 /* 2908 * Not handled: 2909 * 2910 * Transmit buffer unavailable -- normal 2911 * condition, nothing to do, really. 2912 * 2913 * Early receive interrupt -- not available on 2914 * all chips, we just use RI. We also only 2915 * use single-segment receive DMA, so this 2916 * is mostly useless. 2917 * 2918 * TBD others 2919 */ 2920 } 2921 2922 /* Try to get more packets going. */ 2923 atw_start(ifp); 2924 2925 return (handled); 2926 } 2927 2928 /* 2929 * atw_idle: 2930 * 2931 * Cause the transmit and/or receive processes to go idle. 2932 * 2933 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2934 * process in STSR if I clear SR or ST after the process has already 2935 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2936 * do not seem to be too reliable. Perhaps I have the sense of the 2937 * Rx bits switched with the Tx bits? 2938 */ 2939 void 2940 atw_idle(struct atw_softc *sc, u_int32_t bits) 2941 { 2942 u_int32_t ackmask = 0, opmode, stsr, test0; 2943 int i, s; 2944 2945 s = splnet(); 2946 2947 opmode = sc->sc_opmode & ~bits; 2948 2949 if (bits & ATW_NAR_SR) 2950 ackmask |= ATW_INTR_RPS; 2951 2952 if (bits & ATW_NAR_ST) { 2953 ackmask |= ATW_INTR_TPS; 2954 /* set ATW_NAR_HF to flush TX FIFO. */ 2955 opmode |= ATW_NAR_HF; 2956 } 2957 2958 ATW_WRITE(sc, ATW_NAR, opmode); 2959 DELAY(atw_nar_delay); 2960 2961 for (i = 0; i < 1000; i++) { 2962 stsr = ATW_READ(sc, ATW_STSR); 2963 if ((stsr & ackmask) == ackmask) 2964 break; 2965 DELAY(10); 2966 } 2967 2968 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2969 2970 if ((stsr & ackmask) == ackmask) 2971 goto out; 2972 2973 test0 = ATW_READ(sc, ATW_TEST0); 2974 2975 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2976 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2977 printf("%s: transmit process not idle [%s]\n", 2978 sc->sc_dev.dv_xname, 2979 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2980 printf("%s: bits %08x test0 %08x stsr %08x\n", 2981 sc->sc_dev.dv_xname, bits, test0, stsr); 2982 } 2983 2984 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2985 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2986 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2987 sc->sc_dev.dv_xname, 2988 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2989 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2990 sc->sc_dev.dv_xname, bits, test0, stsr)); 2991 } 2992 out: 2993 if ((bits & ATW_NAR_ST) != 0) 2994 atw_txdrain(sc); 2995 splx(s); 2996 return; 2997 } 2998 2999 /* 3000 * atw_linkintr: 3001 * 3002 * Helper; handle link-status interrupts. 3003 */ 3004 void 3005 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3006 { 3007 struct ieee80211com *ic = &sc->sc_ic; 3008 3009 if (ic->ic_state != IEEE80211_S_RUN) 3010 return; 3011 3012 if (linkstatus & ATW_INTR_LINKON) { 3013 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3014 sc->sc_rescan_timer = 0; 3015 } else if (linkstatus & ATW_INTR_LINKOFF) { 3016 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3017 if (ic->ic_opmode != IEEE80211_M_STA) 3018 return; 3019 sc->sc_rescan_timer = 3; 3020 sc->sc_if.if_timer = 1; 3021 } 3022 } 3023 3024 static inline int 3025 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3026 { 3027 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3028 return 0; 3029 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3030 return 0; 3031 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3032 } 3033 3034 /* 3035 * atw_rxintr: 3036 * 3037 * Helper; handle receive interrupts. 3038 */ 3039 void 3040 atw_rxintr(struct atw_softc *sc) 3041 { 3042 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3043 struct ieee80211com *ic = &sc->sc_ic; 3044 struct ieee80211_node *ni; 3045 struct ieee80211_frame_min *wh; 3046 struct ifnet *ifp = &sc->sc_if; 3047 struct atw_rxsoft *rxs; 3048 struct mbuf *m; 3049 u_int32_t rxstat; 3050 int i, len, rate, rate0; 3051 u_int32_t rssi, rssi0; 3052 3053 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3054 rxs = &sc->sc_rxsoft[i]; 3055 3056 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3057 3058 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3059 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3060 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3061 3062 if (rxstat & ATW_RXSTAT_OWN) 3063 break; /* We have processed all receive buffers. */ 3064 3065 DPRINTF3(sc, 3066 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3067 sc->sc_dev.dv_xname, 3068 rxstat, rssi0, 3069 le32toh(sc->sc_rxdescs[i].ar_buf1), 3070 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3071 3072 /* 3073 * Make sure the packet fits in one buffer. This should 3074 * always be the case. 3075 */ 3076 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3077 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3078 printf("%s: incoming packet spilled, resetting\n", 3079 sc->sc_dev.dv_xname); 3080 (void)atw_init(ifp); 3081 return; 3082 } 3083 3084 /* 3085 * If an error occurred, update stats, clear the status 3086 * word, and leave the packet buffer in place. It will 3087 * simply be reused the next time the ring comes around. 3088 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3089 * error. 3090 */ 3091 3092 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3093 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3094 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3095 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3096 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3097 ATW_RXSTAT_ICVE)) != 0)) { 3098 #define PRINTERR(bit, str) \ 3099 if (rxstat & (bit)) \ 3100 printf("%s: receive error: %s\n", \ 3101 sc->sc_dev.dv_xname, str) 3102 ifp->if_ierrors++; 3103 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3104 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3105 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3106 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3107 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3108 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3109 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3110 #undef PRINTERR 3111 ATW_INIT_RXDESC(sc, i); 3112 continue; 3113 } 3114 3115 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3116 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3117 3118 /* 3119 * No errors; receive the packet. Note the ADM8211 3120 * includes the CRC in promiscuous mode. 3121 */ 3122 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3123 3124 /* 3125 * Allocate a new mbuf cluster. If that fails, we are 3126 * out of memory, and must drop the packet and recycle 3127 * the buffer that's already attached to this descriptor. 3128 */ 3129 m = rxs->rxs_mbuf; 3130 if (atw_add_rxbuf(sc, i) != 0) { 3131 ifp->if_ierrors++; 3132 ATW_INIT_RXDESC(sc, i); 3133 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3134 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3135 continue; 3136 } 3137 3138 ifp->if_ipackets++; 3139 if (sc->sc_opmode & ATW_NAR_PR) 3140 len -= IEEE80211_CRC_LEN; 3141 m->m_pkthdr.rcvif = ifp; 3142 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3143 3144 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3145 rate = 0; 3146 else 3147 rate = rate_tbl[rate0]; 3148 3149 /* The RSSI comes straight from a register in the 3150 * baseband processor. I know that for the RF3000, 3151 * the RSSI register also contains the antenna-selection 3152 * bits. Mask those off. 3153 * 3154 * TBD Treat other basebands. 3155 */ 3156 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3157 rssi = rssi0 & RF3000_RSSI_MASK; 3158 else 3159 rssi = rssi0; 3160 3161 #if NBPFILTER > 0 3162 /* Pass this up to any BPF listeners. */ 3163 if (sc->sc_radiobpf != NULL) { 3164 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3165 3166 tap->ar_rate = rate; 3167 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3168 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3169 3170 /* TBD verify units are dB */ 3171 tap->ar_antsignal = (int)rssi; 3172 /* TBD tap->ar_flags */ 3173 3174 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3175 tap->ar_ihdr.it_len, m); 3176 } 3177 #endif /* NPBFILTER > 0 */ 3178 3179 wh = mtod(m, struct ieee80211_frame_min *); 3180 ni = ieee80211_find_rxnode(ic, wh); 3181 if (atw_hw_decrypted(sc, wh)) { 3182 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3183 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3184 } 3185 ieee80211_input(ic, m, ni, (int)rssi, 0); 3186 ieee80211_free_node(ni); 3187 } 3188 3189 /* Update the receive pointer. */ 3190 sc->sc_rxptr = i; 3191 } 3192 3193 /* 3194 * atw_txintr: 3195 * 3196 * Helper; handle transmit interrupts. 3197 */ 3198 void 3199 atw_txintr(struct atw_softc *sc) 3200 { 3201 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3202 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3203 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3204 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3205 3206 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3207 struct ifnet *ifp = &sc->sc_if; 3208 struct atw_txsoft *txs; 3209 u_int32_t txstat; 3210 3211 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3212 sc->sc_dev.dv_xname, sc->sc_flags)); 3213 3214 /* 3215 * Go through our Tx list and free mbufs for those 3216 * frames that have been transmitted. 3217 */ 3218 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3219 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3220 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3221 3222 #ifdef ATW_DEBUG 3223 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3224 int i; 3225 printf(" txsoft %p transmit chain:\n", txs); 3226 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3227 txs->txs_ndescs - 1, 3228 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3229 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3230 printf(" descriptor %d:\n", i); 3231 printf(" at_status: 0x%08x\n", 3232 le32toh(sc->sc_txdescs[i].at_stat)); 3233 printf(" at_flags: 0x%08x\n", 3234 le32toh(sc->sc_txdescs[i].at_flags)); 3235 printf(" at_buf1: 0x%08x\n", 3236 le32toh(sc->sc_txdescs[i].at_buf1)); 3237 printf(" at_buf2: 0x%08x\n", 3238 le32toh(sc->sc_txdescs[i].at_buf2)); 3239 if (i == txs->txs_lastdesc) 3240 break; 3241 } 3242 } 3243 #endif 3244 3245 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3246 if (txstat & ATW_TXSTAT_OWN) 3247 break; 3248 3249 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3250 3251 sc->sc_txfree += txs->txs_ndescs; 3252 3253 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3254 0, txs->txs_dmamap->dm_mapsize, 3255 BUS_DMASYNC_POSTWRITE); 3256 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3257 m_freem(txs->txs_mbuf); 3258 txs->txs_mbuf = NULL; 3259 3260 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3261 3262 ifp->if_flags &= ~IFF_OACTIVE; 3263 3264 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3265 (txstat & TXSTAT_ERRMASK) != 0) { 3266 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3267 txstat_buf, sizeof(txstat_buf)); 3268 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3269 txstat_buf, 3270 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3271 } 3272 3273 /* 3274 * Check for errors and collisions. 3275 */ 3276 if (txstat & ATW_TXSTAT_TUF) 3277 sc->sc_stats.ts_tx_tuf++; 3278 if (txstat & ATW_TXSTAT_TLT) 3279 sc->sc_stats.ts_tx_tlt++; 3280 if (txstat & ATW_TXSTAT_TRT) 3281 sc->sc_stats.ts_tx_trt++; 3282 if (txstat & ATW_TXSTAT_TRO) 3283 sc->sc_stats.ts_tx_tro++; 3284 if (txstat & ATW_TXSTAT_SOFBR) { 3285 sc->sc_stats.ts_tx_sofbr++; 3286 } 3287 3288 if ((txstat & ATW_TXSTAT_ES) == 0) 3289 ifp->if_collisions += 3290 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3291 else 3292 ifp->if_oerrors++; 3293 3294 ifp->if_opackets++; 3295 } 3296 3297 /* 3298 * If there are no more pending transmissions, cancel the watchdog 3299 * timer. 3300 */ 3301 if (txs == NULL) 3302 sc->sc_tx_timer = 0; 3303 #undef TXSTAT_ERRMASK 3304 #undef TXSTAT_FMT 3305 } 3306 3307 /* 3308 * atw_watchdog: [ifnet interface function] 3309 * 3310 * Watchdog timer handler. 3311 */ 3312 void 3313 atw_watchdog(struct ifnet *ifp) 3314 { 3315 struct atw_softc *sc = ifp->if_softc; 3316 struct ieee80211com *ic = &sc->sc_ic; 3317 3318 ifp->if_timer = 0; 3319 if (ATW_IS_ENABLED(sc) == 0) 3320 return; 3321 3322 if (sc->sc_rescan_timer) { 3323 if (--sc->sc_rescan_timer == 0) 3324 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3325 } 3326 if (sc->sc_tx_timer) { 3327 if (--sc->sc_tx_timer == 0 && 3328 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3329 printf("%s: transmit timeout\n", ifp->if_xname); 3330 ifp->if_oerrors++; 3331 (void)atw_init(ifp); 3332 atw_start(ifp); 3333 } 3334 } 3335 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3336 ifp->if_timer = 1; 3337 ieee80211_watchdog(ic); 3338 } 3339 3340 #ifdef ATW_DEBUG 3341 static void 3342 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3343 { 3344 struct atw_softc *sc = ifp->if_softc; 3345 struct mbuf *m; 3346 int i, noctets = 0; 3347 3348 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3349 m0->m_pkthdr.len); 3350 3351 for (m = m0; m; m = m->m_next) { 3352 if (m->m_len == 0) 3353 continue; 3354 for (i = 0; i < m->m_len; i++) { 3355 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3356 if (++noctets % 24 == 0) 3357 printf("\n"); 3358 } 3359 } 3360 printf("%s%s: %d bytes emitted\n", 3361 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3362 } 3363 #endif /* ATW_DEBUG */ 3364 3365 /* 3366 * atw_start: [ifnet interface function] 3367 * 3368 * Start packet transmission on the interface. 3369 */ 3370 void 3371 atw_start(struct ifnet *ifp) 3372 { 3373 struct atw_softc *sc = ifp->if_softc; 3374 struct ieee80211_key *k; 3375 struct ieee80211com *ic = &sc->sc_ic; 3376 struct ieee80211_node *ni; 3377 struct ieee80211_frame_min *whm; 3378 struct ieee80211_frame *wh; 3379 struct atw_frame *hh; 3380 struct mbuf *m0, *m; 3381 struct atw_txsoft *txs, *last_txs; 3382 struct atw_txdesc *txd; 3383 int do_encrypt, npkt, rate; 3384 bus_dmamap_t dmamap; 3385 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3386 3387 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3388 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3389 3390 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3391 return; 3392 3393 /* 3394 * Remember the previous number of free descriptors and 3395 * the first descriptor we'll use. 3396 */ 3397 ofree = sc->sc_txfree; 3398 firsttx = sc->sc_txnext; 3399 3400 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3401 sc->sc_dev.dv_xname, ofree, firsttx)); 3402 3403 /* 3404 * Loop through the send queue, setting up transmit descriptors 3405 * until we drain the queue, or use up all available transmit 3406 * descriptors. 3407 */ 3408 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3409 sc->sc_txfree != 0) { 3410 3411 /* 3412 * Grab a packet off the management queue, if it 3413 * is not empty. Otherwise, from the data queue. 3414 */ 3415 IF_DEQUEUE(&ic->ic_mgtq, m0); 3416 if (m0 != NULL) { 3417 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3418 m0->m_pkthdr.rcvif = NULL; 3419 } else { 3420 /* send no data packets until we are associated */ 3421 if (ic->ic_state != IEEE80211_S_RUN) 3422 break; 3423 IFQ_DEQUEUE(&ifp->if_snd, m0); 3424 if (m0 == NULL) 3425 break; 3426 #if NBPFILTER > 0 3427 if (ifp->if_bpf != NULL) 3428 bpf_mtap(ifp->if_bpf, m0); 3429 #endif /* NBPFILTER > 0 */ 3430 ni = ieee80211_find_txnode(ic, 3431 mtod(m0, struct ether_header *)->ether_dhost); 3432 if (ni == NULL) { 3433 ifp->if_oerrors++; 3434 break; 3435 } 3436 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3437 ieee80211_free_node(ni); 3438 ifp->if_oerrors++; 3439 break; 3440 } 3441 } 3442 3443 rate = MAX(ieee80211_get_rate(ic), 2); 3444 3445 whm = mtod(m0, struct ieee80211_frame_min *); 3446 3447 do_encrypt = ((whm->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3448 if (do_encrypt) 3449 k = &ic->ic_nw_keys[ic->ic_def_txkey]; 3450 else 3451 k = NULL; 3452 3453 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3454 ic->ic_flags, ic->ic_fragthreshold, rate, 3455 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3456 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3457 m_freem(m0); 3458 break; 3459 } 3460 3461 /* XXX Misleading if fragmentation is enabled. Better 3462 * to fragment in software? 3463 */ 3464 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3465 3466 #if NBPFILTER > 0 3467 /* 3468 * Pass the packet to any BPF listeners. 3469 */ 3470 if (ic->ic_rawbpf != NULL) 3471 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3472 3473 if (sc->sc_radiobpf != NULL) { 3474 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3475 3476 tap->at_rate = rate; 3477 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3478 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3479 3480 /* TBD tap->at_flags */ 3481 3482 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3483 tap->at_ihdr.it_len, m0); 3484 } 3485 #endif /* NBPFILTER > 0 */ 3486 3487 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3488 3489 if (ni != NULL) 3490 ieee80211_free_node(ni); 3491 3492 if (m0 == NULL) { 3493 ifp->if_oerrors++; 3494 break; 3495 } 3496 3497 /* just to make sure. */ 3498 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3499 3500 if (m0 == NULL) { 3501 ifp->if_oerrors++; 3502 break; 3503 } 3504 3505 hh = mtod(m0, struct atw_frame *); 3506 wh = &hh->atw_ihdr; 3507 3508 /* Copy everything we need from the 802.11 header: 3509 * Frame Control; address 1, address 3, or addresses 3510 * 3 and 4. NIC fills in BSSID, SA. 3511 */ 3512 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3513 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3514 panic("%s: illegal WDS frame", 3515 sc->sc_dev.dv_xname); 3516 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3517 } else 3518 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3519 3520 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3521 3522 /* initialize remaining Tx parameters */ 3523 memset(&hh->u, 0, sizeof(hh->u)); 3524 3525 hh->atw_rate = rate * 5; 3526 /* XXX this could be incorrect if M_FCS. _encap should 3527 * probably strip FCS just in case it sticks around in 3528 * bridged packets. 3529 */ 3530 hh->atw_service = 0x00; /* XXX guess */ 3531 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3532 sizeof(struct atw_frame)); 3533 3534 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3535 hh->atw_rtylmt = 3; 3536 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3537 if (do_encrypt) { 3538 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3539 hh->atw_keyid = ic->ic_def_txkey; 3540 } 3541 3542 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3543 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3544 if (txs->txs_d0.d_residue) 3545 hh->atw_head_plcplen |= htole16(0x8000); 3546 if (txs->txs_dn.d_residue) 3547 hh->atw_tail_plcplen |= htole16(0x8000); 3548 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3549 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3550 3551 /* never fragment multicast frames */ 3552 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3553 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3554 } else if (sc->sc_flags & ATWF_RTSCTS) { 3555 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3556 } 3557 3558 #ifdef ATW_DEBUG 3559 hh->atw_fragnum = 0; 3560 3561 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3562 printf("%s: dst = %s, rate = 0x%02x, " 3563 "service = 0x%02x, paylen = 0x%04x\n", 3564 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3565 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3566 3567 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3568 "dur1 = 0x%04x, dur2 = 0x%04x, " 3569 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3570 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3571 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3572 hh->atw_tail_dur, hh->atw_head_dur); 3573 3574 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3575 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3576 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3577 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3578 3579 printf("%s: keyid = %d\n", 3580 sc->sc_dev.dv_xname, hh->atw_keyid); 3581 3582 atw_dump_pkt(ifp, m0); 3583 } 3584 #endif /* ATW_DEBUG */ 3585 3586 dmamap = txs->txs_dmamap; 3587 3588 /* 3589 * Load the DMA map. Copy and try (once) again if the packet 3590 * didn't fit in the alloted number of segments. 3591 */ 3592 for (first = 1; 3593 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3594 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3595 first = 0) { 3596 MGETHDR(m, M_DONTWAIT, MT_DATA); 3597 if (m == NULL) { 3598 printf("%s: unable to allocate Tx mbuf\n", 3599 sc->sc_dev.dv_xname); 3600 break; 3601 } 3602 if (m0->m_pkthdr.len > MHLEN) { 3603 MCLGET(m, M_DONTWAIT); 3604 if ((m->m_flags & M_EXT) == 0) { 3605 printf("%s: unable to allocate Tx " 3606 "cluster\n", sc->sc_dev.dv_xname); 3607 m_freem(m); 3608 break; 3609 } 3610 } 3611 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3612 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3613 m_freem(m0); 3614 m0 = m; 3615 m = NULL; 3616 } 3617 if (error != 0) { 3618 printf("%s: unable to load Tx buffer, " 3619 "error = %d\n", sc->sc_dev.dv_xname, error); 3620 m_freem(m0); 3621 break; 3622 } 3623 3624 /* 3625 * Ensure we have enough descriptors free to describe 3626 * the packet. 3627 */ 3628 if (dmamap->dm_nsegs > sc->sc_txfree) { 3629 /* 3630 * Not enough free descriptors to transmit 3631 * this packet. Unload the DMA map and 3632 * drop the packet. Notify the upper layer 3633 * that there are no more slots left. 3634 * 3635 * XXX We could allocate an mbuf and copy, but 3636 * XXX it is worth it? 3637 */ 3638 bus_dmamap_unload(sc->sc_dmat, dmamap); 3639 m_freem(m0); 3640 break; 3641 } 3642 3643 /* 3644 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3645 */ 3646 3647 /* Sync the DMA map. */ 3648 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3649 BUS_DMASYNC_PREWRITE); 3650 3651 /* XXX arbitrary retry limit; 8 because I have seen it in 3652 * use already and maybe 0 means "no tries" ! 3653 */ 3654 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3655 3656 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3657 sc->sc_dev.dv_xname, rate * 5)); 3658 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3659 3660 /* 3661 * Initialize the transmit descriptors. 3662 */ 3663 for (nexttx = sc->sc_txnext, seg = 0; 3664 seg < dmamap->dm_nsegs; 3665 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3666 /* 3667 * If this is the first descriptor we're 3668 * enqueueing, don't set the OWN bit just 3669 * yet. That could cause a race condition. 3670 * We'll do it below. 3671 */ 3672 txd = &sc->sc_txdescs[nexttx]; 3673 txd->at_ctl = ctl | 3674 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3675 3676 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3677 txd->at_flags = 3678 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3679 ATW_TXFLAG_TBS1_MASK)) | 3680 ((nexttx == (ATW_NTXDESC - 1)) 3681 ? htole32(ATW_TXFLAG_TER) : 0); 3682 lasttx = nexttx; 3683 } 3684 3685 IASSERT(lasttx != -1, ("bad lastx")); 3686 /* Set `first segment' and `last segment' appropriately. */ 3687 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3688 htole32(ATW_TXFLAG_FS); 3689 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3690 3691 #ifdef ATW_DEBUG 3692 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3693 printf(" txsoft %p transmit chain:\n", txs); 3694 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3695 printf(" descriptor %d:\n", seg); 3696 printf(" at_ctl: 0x%08x\n", 3697 le32toh(sc->sc_txdescs[seg].at_ctl)); 3698 printf(" at_flags: 0x%08x\n", 3699 le32toh(sc->sc_txdescs[seg].at_flags)); 3700 printf(" at_buf1: 0x%08x\n", 3701 le32toh(sc->sc_txdescs[seg].at_buf1)); 3702 printf(" at_buf2: 0x%08x\n", 3703 le32toh(sc->sc_txdescs[seg].at_buf2)); 3704 if (seg == lasttx) 3705 break; 3706 } 3707 } 3708 #endif 3709 3710 /* Sync the descriptors we're using. */ 3711 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3712 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3713 3714 /* 3715 * Store a pointer to the packet so we can free it later, 3716 * and remember what txdirty will be once the packet is 3717 * done. 3718 */ 3719 txs->txs_mbuf = m0; 3720 txs->txs_firstdesc = sc->sc_txnext; 3721 txs->txs_lastdesc = lasttx; 3722 txs->txs_ndescs = dmamap->dm_nsegs; 3723 3724 /* Advance the tx pointer. */ 3725 sc->sc_txfree -= dmamap->dm_nsegs; 3726 sc->sc_txnext = nexttx; 3727 3728 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3729 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3730 3731 last_txs = txs; 3732 } 3733 3734 if (txs == NULL || sc->sc_txfree == 0) { 3735 /* No more slots left; notify upper layer. */ 3736 ifp->if_flags |= IFF_OACTIVE; 3737 } 3738 3739 if (sc->sc_txfree != ofree) { 3740 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3741 sc->sc_dev.dv_xname, lasttx, firsttx)); 3742 /* 3743 * Cause a transmit interrupt to happen on the 3744 * last packet we enqueued. 3745 */ 3746 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3747 ATW_CDTXSYNC(sc, lasttx, 1, 3748 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3749 3750 /* 3751 * The entire packet chain is set up. Give the 3752 * first descriptor to the chip now. 3753 */ 3754 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3755 ATW_CDTXSYNC(sc, firsttx, 1, 3756 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3757 3758 /* Wake up the transmitter. */ 3759 ATW_WRITE(sc, ATW_TDR, 0x1); 3760 3761 /* Set a watchdog timer in case the chip flakes out. */ 3762 sc->sc_tx_timer = 5; 3763 ifp->if_timer = 1; 3764 } 3765 } 3766 3767 /* 3768 * atw_power: 3769 * 3770 * Power management (suspend/resume) hook. 3771 */ 3772 void 3773 atw_power(int why, void *arg) 3774 { 3775 struct atw_softc *sc = arg; 3776 struct ifnet *ifp = &sc->sc_if; 3777 int s; 3778 3779 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3780 3781 s = splnet(); 3782 switch (why) { 3783 case PWR_STANDBY: 3784 /* XXX do nothing. */ 3785 break; 3786 case PWR_SUSPEND: 3787 atw_stop(ifp, 0); 3788 if (sc->sc_power != NULL) 3789 (*sc->sc_power)(sc, why); 3790 break; 3791 case PWR_RESUME: 3792 if (ifp->if_flags & IFF_UP) { 3793 if (sc->sc_power != NULL) 3794 (*sc->sc_power)(sc, why); 3795 atw_init(ifp); 3796 } 3797 break; 3798 case PWR_SOFTSUSPEND: 3799 case PWR_SOFTSTANDBY: 3800 case PWR_SOFTRESUME: 3801 break; 3802 } 3803 splx(s); 3804 } 3805 3806 /* 3807 * atw_ioctl: [ifnet interface function] 3808 * 3809 * Handle control requests from the operator. 3810 */ 3811 int 3812 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3813 { 3814 struct atw_softc *sc = ifp->if_softc; 3815 struct ifreq *ifr = (struct ifreq *)data; 3816 int s, error = 0; 3817 3818 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3819 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3820 return ENXIO; 3821 3822 s = splnet(); 3823 3824 switch (cmd) { 3825 case SIOCSIFFLAGS: 3826 if (ifp->if_flags & IFF_UP) { 3827 if (ATW_IS_ENABLED(sc)) { 3828 /* 3829 * To avoid rescanning another access point, 3830 * do not call atw_init() here. Instead, 3831 * only reflect media settings. 3832 */ 3833 atw_filter_setup(sc); 3834 } else 3835 error = atw_init(ifp); 3836 } else if (ATW_IS_ENABLED(sc)) 3837 atw_stop(ifp, 1); 3838 break; 3839 case SIOCADDMULTI: 3840 case SIOCDELMULTI: 3841 error = (cmd == SIOCADDMULTI) ? 3842 ether_addmulti(ifr, &sc->sc_ec) : 3843 ether_delmulti(ifr, &sc->sc_ec); 3844 if (error == ENETRESET) { 3845 if (ifp->if_flags & IFF_RUNNING) 3846 atw_filter_setup(sc); /* do not rescan */ 3847 error = 0; 3848 } 3849 break; 3850 default: 3851 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3852 if (error == ENETRESET) { 3853 if (ATW_IS_ENABLED(sc)) 3854 error = atw_init(ifp); 3855 else 3856 error = 0; 3857 } 3858 break; 3859 } 3860 3861 /* Try to get more packets going. */ 3862 if (ATW_IS_ENABLED(sc)) 3863 atw_start(ifp); 3864 3865 splx(s); 3866 return (error); 3867 } 3868 3869 static int 3870 atw_media_change(struct ifnet *ifp) 3871 { 3872 int error; 3873 3874 error = ieee80211_media_change(ifp); 3875 if (error == ENETRESET) { 3876 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3877 (IFF_RUNNING|IFF_UP)) 3878 atw_init(ifp); /* XXX lose error */ 3879 error = 0; 3880 } 3881 return error; 3882 } 3883
Indexes created Fri Sep 26 20:09:58 GMT 2025