atwreg.h revision 1.13
1 /* $NetBSD: atwreg.h,v 1.13 2006/03/08 00:24:06 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 #include <lib/libkern/libkern.h> 51 52 /* ADM8211 Host Control and Status Registers */ 53 54 #define ATW_PAR 0x00 /* PCI access */ 55 #define ATW_FRCTL 0x04 /* Frame control */ 56 #define ATW_TDR 0x08 /* Transmit demand */ 57 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 58 #define ATW_RDR 0x10 /* Receive demand */ 59 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 60 #define ATW_RDB 0x18 /* Receive descriptor base address */ 61 #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 62 #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 63 * high-priority packet 64 */ 65 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 66 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 67 #define ATW_STSR 0x28 /* Status */ 68 #define ATW_CSR5A 0x2C /* Unused */ 69 #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 70 * broadcast/multicast packet 71 */ 72 #define ATW_NAR 0x30 /* Network access */ 73 #define ATW_CSR6A 0x34 /* Unused */ 74 #define ATW_IER 0x38 /* Interrupt enable */ 75 #define ATW_CSR7A 0x3C 76 #define ATW_LPC 0x40 /* Lost packet counter */ 77 #define ATW_TEST1 0x44 /* Test register 1 */ 78 #define ATW_SPR 0x48 /* Serial port */ 79 #define ATW_TEST0 0x4C /* Test register 0 */ 80 #define ATW_WCSR 0x50 /* Wake-up control/status */ 81 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 82 #define ATW_GPTMR 0x58 /* General purpose timer */ 83 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 84 #define ATW_BBPCTL 0x60 /* BBP control port */ 85 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 86 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 87 #define ATW_MMIWADDR 0x6C /* MMI write address */ 88 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 89 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 90 #define ATW_TXBR 0x78 /* Transmit burst counter */ 91 #define ATW_CSR15A 0x7C /* Unused */ 92 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 93 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 94 #define ATW_CMDR 0x88 /* Command */ 95 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 96 #define ATW_PMCSR 0x90 /* Power management command and status */ 97 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 98 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 99 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 100 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 101 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 102 * frame DA, byte[3:0] 103 */ 104 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 105 * ATIM frame DA byte[5:4] 106 */ 107 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 108 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 109 * Max TX MSDU lifetime, 16b 110 */ 111 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 112 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 113 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 114 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 115 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 116 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 117 * STA listen interval, 16b. 118 */ 119 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 120 #define ATW_CAP1 0xD0 /* Capability information, 16b. 121 * ATIM window, 1b. 122 */ 123 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 124 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 125 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 126 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 127 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 128 #define ATW_RSPT 0xE8 /* Response time, 24b */ 129 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 130 #define ATW_WEPCTL 0xF0 /* WEP control */ 131 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 132 #define ATW_WEPCNT 0xF8 /* WEP count */ 133 #define ATW_MACTEST 0xFC 134 135 #define ATW_FER 0x100 /* Function event */ 136 #define ATW_FEMR 0x104 /* Function event mask */ 137 #define ATW_FPSR 0x108 /* Function present state */ 138 #define ATW_FFER 0x10C /* Function force event */ 139 140 141 #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 142 * enable 143 */ 144 #define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 145 #define ATW_PAR_MRME BIT(21) /* memory read multiple 146 * enable 147 */ 148 #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 149 * receive suspended state 150 */ 151 #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 152 #define ATW_PAR_CAL_PBL 0x0 153 /* min(8 DW, PBL) */ 154 #define ATW_PAR_CAL_8DW SHIFTIN(0x1, ATW_PAR_CAL_MASK) 155 /* min(16 DW, PBL) */ 156 #define ATW_PAR_CAL_16DW SHIFTIN(0x2, ATW_PAR_CAL_MASK) 157 /* min(32 DW, PBL) */ 158 #define ATW_PAR_CAL_32DW SHIFTIN(0x3, ATW_PAR_CAL_MASK) 159 #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 160 #define ATW_PAR_PBL_UNLIMITED 0x0 161 #define ATW_PAR_PBL_1DW SHIFTIN(0x1, ATW_PAR_PBL_MASK) 162 #define ATW_PAR_PBL_2DW SHIFTIN(0x2, ATW_PAR_PBL_MASK) 163 #define ATW_PAR_PBL_4DW SHIFTIN(0x4, ATW_PAR_PBL_MASK) 164 #define ATW_PAR_PBL_8DW SHIFTIN(0x8, ATW_PAR_PBL_MASK) 165 #define ATW_PAR_PBL_16DW SHIFTIN(0x16, ATW_PAR_PBL_MASK) 166 #define ATW_PAR_PBL_32DW SHIFTIN(0x32, ATW_PAR_PBL_MASK) 167 #define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 168 #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 169 #define ATW_PAR_BAR BIT(1) /* bus arbitration */ 170 #define ATW_PAR_SWR BIT(0) /* software reset */ 171 172 #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 173 #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 174 #define ATW_FRCTL_ORDER BIT(28) /* order bit */ 175 #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 176 #define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe 177 * response 178 * 0: ASIC sends prresp 179 */ 180 #define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons 181 * 0: ASIC sends beacons 182 */ 183 #define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED 184 * 0: ASIC controls link LED 185 */ 186 #define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED 187 * 0: turn off link LED 188 */ 189 #define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28 190 * 1: random 191 */ 192 #define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved" 193 * frames, 0: ignore 194 * reserved frames 195 */ 196 #define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END, 197 * ADM8211C/CR clears 198 */ 199 #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 200 #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 201 #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 202 #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 203 204 #define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 205 #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 206 #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 207 #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 208 #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 209 #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 210 #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 211 #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 212 #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 213 #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 214 #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 215 #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 216 * passed 217 */ 218 #define ATW_INTR_NISS BIT(16) /* normal interrupt status 219 * summary: any of 31, 30, 27, 220 * 24, 14, 12, 6, 2, 0. 221 */ 222 #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 223 * summary: any of 29, 28, 26, 224 * 25, 23, 22, 13, 11, 8, 7, 5, 225 * 4, 3, 1. 226 */ 227 #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 228 * status: moved TX packet to 229 * FIFO 230 */ 231 #define ATW_INTR_FBE BIT(13) /* fatal bus error */ 232 #define ATW_INTR_REIS BIT(12) /* receive early interrupt 233 * status: RX packet filled 234 * its first descriptor 235 */ 236 #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 237 #define ATW_INTR_RPS BIT(8) /* stopped receive process */ 238 #define ATW_INTR_RDU BIT(7) /* receive descriptor 239 * unavailable 240 */ 241 #define ATW_INTR_RCI BIT(6) /* completed packet reception */ 242 #define ATW_INTR_TUF BIT(5) /* transmit underflow */ 243 #define ATW_INTR_TRT BIT(4) /* transmit retry count 244 * expired 245 */ 246 #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 247 #define ATW_INTR_TDU BIT(2) /* transmit descriptor 248 * unavailable 249 */ 250 #define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 251 #define ATW_INTR_TCI BIT(0) /* completed transmit */ 252 #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 253 #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 254 #define ATW_NAR_UTR BIT(29) /* select retry count source */ 255 #define ATW_NAR_PCF BIT(28) /* use one/both transmit 256 * descriptor base addresses 257 */ 258 #define ATW_NAR_CFP BIT(27) /* indicate more TX data to 259 * point coordinator 260 */ 261 #define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode 262 * 1: AP mode 263 */ 264 #define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB 265 * 1: enable TDBB 266 */ 267 #define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH 268 * 1: enable TDBH 269 */ 270 #define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC 271 * poll TDBH once; ASIC clears 272 */ 273 #define ATW_NAR_SF BIT(21) /* store and forward: ignore 274 * TX threshold 275 */ 276 #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 277 #define ATW_NAR_TR_L64 SHIFTIN(0x0, ATW_NAR_TR_MASK) 278 #define ATW_NAR_TR_L160 SHIFTIN(0x2, ATW_NAR_TR_MASK) 279 #define ATW_NAR_TR_L192 SHIFTIN(0x3, ATW_NAR_TR_MASK) 280 #define ATW_NAR_TR_H96 SHIFTIN(0x0, ATW_NAR_TR_MASK) 281 #define ATW_NAR_TR_H288 SHIFTIN(0x2, ATW_NAR_TR_MASK) 282 #define ATW_NAR_TR_H544 SHIFTIN(0x3, ATW_NAR_TR_MASK) 283 #define ATW_NAR_ST BIT(13) /* start/stop transmit */ 284 #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 285 #define ATW_NAR_OM_NORMAL 0x0 286 #define ATW_NAR_OM_LOOPBACK SHIFTIN(0x1, ATW_NAR_OM_MASK) 287 #define ATW_NAR_MM BIT(7) /* RX any multicast */ 288 #define ATW_NAR_PR BIT(6) /* promiscuous mode */ 289 #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 290 #define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported 291 * 0: PCF supported 292 */ 293 #define ATW_NAR_PB BIT(3) /* pass bad packets */ 294 #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 295 #define ATW_NAR_SR BIT(1) /* start/stop receive */ 296 #define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 297 298 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 299 #if 0 300 #define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 301 #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 302 /* normal interrupts: combine with ATW_IER_NIE */ 303 #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 304 #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 305 #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 306 #define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 307 #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 308 #define ATW_IER_TBTTIE BIT(20) /* TBTT */ 309 #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 310 #define ATW_IER_REIE BIT(12) /* RX packet filled its first 311 * descriptor 312 */ 313 #define ATW_IER_RCIE BIT(6) /* completed RX */ 314 #define ATW_IER_TDUIE BIT(2) /* transmit descriptor 315 * unavailable 316 */ 317 #define ATW_IER_TCIE BIT(0) /* completed TX */ 318 /* abnormal interrupts: combine with ATW_IER_AIE */ 319 #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 320 #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 321 #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 322 #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 323 #define ATW_IER_SQLIE BIT(23) /* signal quality */ 324 #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 325 #define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 326 #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 327 #define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 328 #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 329 #define ATW_IER_TUIE BIT(5) /* transmit underflow */ 330 #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 331 #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 332 #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 333 #endif 334 335 #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 336 #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 337 338 #define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control, 339 * 1: read from dxfer_state" 340 */ 341 #define ATW_TEST1_DBGREAD_MASK BITS(30,28) /* "control of read data, 342 * debug only" 343 */ 344 #define ATW_TEST1_TXWP_MASK BITS(27,25) /* select ATW_WTDP content? */ 345 #define ATW_TEST1_TXWP_TDBD SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) 346 #define ATW_TEST1_TXWP_TDBH SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) 347 #define ATW_TEST1_TXWP_TDBB SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) 348 #define ATW_TEST1_TXWP_TDBP SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) 349 #define ATW_TEST1_RSVD0_MASK BITS(24,6) /* reserved */ 350 #define ATW_TEST1_TESTMODE_MASK BITS(5,4) 351 /* normal operation */ 352 #define ATW_TEST1_TESTMODE_NORMAL SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) 353 /* MAC-only mode */ 354 #define ATW_TEST1_TESTMODE_MACONLY SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) 355 /* normal operation */ 356 #define ATW_TEST1_TESTMODE_NORMAL2 SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) 357 /* monitor mode */ 358 #define ATW_TEST1_TESTMODE_MONITOR SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) 359 360 #define ATW_TEST1_DUMP_MASK BITS(3,0) /* select dump signal 361 * from dxfer (huh?) 362 */ 363 364 #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 365 #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 366 #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 367 #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 368 #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 369 370 #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 371 #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 372 373 /* Stopped */ 374 #define ATW_TEST0_TS_STOPPED SHIFTIN(0, ATW_TEST0_TS_MASK) 375 /* Running - fetch transmit descriptor */ 376 #define ATW_TEST0_TS_FETCH SHIFTIN(1, ATW_TEST0_TS_MASK) 377 /* Running - wait for end of transmission */ 378 #define ATW_TEST0_TS_WAIT SHIFTIN(2, ATW_TEST0_TS_MASK) 379 /* Running - read buffer from memory and queue into FIFO */ 380 #define ATW_TEST0_TS_READING SHIFTIN(3, ATW_TEST0_TS_MASK) 381 #define ATW_TEST0_TS_RESERVED1 SHIFTIN(4, ATW_TEST0_TS_MASK) 382 #define ATW_TEST0_TS_RESERVED2 SHIFTIN(5, ATW_TEST0_TS_MASK) 383 /* Suspended */ 384 #define ATW_TEST0_TS_SUSPENDED SHIFTIN(6, ATW_TEST0_TS_MASK) 385 /* Running - close transmit descriptor */ 386 #define ATW_TEST0_TS_CLOSE SHIFTIN(7, ATW_TEST0_TS_MASK) 387 388 /* ADM8211C/CR registers */ 389 /* Suspended */ 390 #define ATW_C_TEST0_TS_SUSPENDED SHIFTIN(4, ATW_TEST0_TS_MASK) 391 /* Descriptor write */ 392 #define ATW_C_TEST0_TS_CLOSE SHIFTIN(5, ATW_TEST0_TS_MASK) 393 /* Last descriptor write */ 394 #define ATW_C_TEST0_TS_CLOSELAST SHIFTIN(6, ATW_TEST0_TS_MASK) 395 /* FIFO full */ 396 #define ATW_C_TEST0_TS_FIFOFULL SHIFTIN(7, ATW_TEST0_TS_MASK) 397 398 #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 399 400 /* Stopped */ 401 #define ATW_TEST0_RS_STOPPED SHIFTIN(0, ATW_TEST0_RS_MASK) 402 /* Running - fetch receive descriptor */ 403 #define ATW_TEST0_RS_FETCH SHIFTIN(1, ATW_TEST0_RS_MASK) 404 /* Running - check for end of receive */ 405 #define ATW_TEST0_RS_CHECK SHIFTIN(2, ATW_TEST0_RS_MASK) 406 /* Running - wait for packet */ 407 #define ATW_TEST0_RS_WAIT SHIFTIN(3, ATW_TEST0_RS_MASK) 408 /* Suspended */ 409 #define ATW_TEST0_RS_SUSPENDED SHIFTIN(4, ATW_TEST0_RS_MASK) 410 /* Running - close receive descriptor */ 411 #define ATW_TEST0_RS_CLOSE SHIFTIN(5, ATW_TEST0_RS_MASK) 412 /* Running - flush current frame from FIFO */ 413 #define ATW_TEST0_RS_FLUSH SHIFTIN(6, ATW_TEST0_RS_MASK) 414 /* Running - queue current frame from FIFO into buffer */ 415 #define ATW_TEST0_RS_QUEUE SHIFTIN(7, ATW_TEST0_RS_MASK) 416 417 #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 418 #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 419 #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 420 * 1: 93c66, 421 * 0: 93c46 422 */ 423 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 424 #define ATW_TEST0_EPTYP_93c46 0 425 #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 426 427 #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 428 #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 429 #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 430 #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 431 #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 432 #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 433 #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 434 * beacons 435 */ 436 #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 437 * range 438 */ 439 #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 440 #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 441 #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 442 #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 443 #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 444 #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 445 /* wake-up reasons correspond to enable bits */ 446 #define ATW_WCSR_KEYUP BIT(6) /* */ 447 #define ATW_WCSR_TSFTW BIT(5) /* */ 448 #define ATW_WCSR_TIMW BIT(4) /* */ 449 #define ATW_WCSR_ATIMW BIT(3) /* */ 450 #define ATW_WCSR_WFR BIT(2) /* */ 451 #define ATW_WCSR_MPR BIT(1) /* */ 452 #define ATW_WCSR_LSO BIT(0) /* */ 453 454 #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 455 #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 456 457 #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 458 #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 459 #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 460 #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 461 #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 462 #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 463 464 #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 465 #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 466 #define ATW_BBPCTL_RF3KADDR_ADDR SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) 467 #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 468 #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 469 #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 470 #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 471 #define ATW_BBPCTL_WR BIT(17) /* start write; reset on 472 * completion 473 */ 474 #define ATW_BBPCTL_RD BIT(16) /* start read; reset on 475 * completion 476 */ 477 #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 478 #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 479 480 #define ATW_SYNCTL_WR BIT(31) /* start write; reset on 481 * completion 482 */ 483 #define ATW_SYNCTL_RD BIT(30) /* start read; reset on 484 * completion 485 */ 486 #define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 487 #define ATW_SYNCTL_CS1 BIT(28) 488 #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 489 * Rx 490 */ 491 #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 492 * 1: MAC; needed by Intersil 493 * BBP 494 */ 495 #define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this 496 * bit. 0: latch data on 497 * negative edge, 1: positive 498 * edge. 499 */ 500 #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 501 #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 502 503 #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 504 * only for beacon, ATIM, and 505 * RTS. 506 */ 507 #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 508 * header; with RFMD BBP, 509 * sets Tx power for beacon, 510 * RTS, ATIM. 511 */ 512 #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 513 514 #define ATW_MMIWADDR_LENLO_MASK BITS(31,24) /* tx: written 4th */ 515 #define ATW_MMIWADDR_LENHI_MASK BITS(23,16) /* tx: written 3rd */ 516 #define ATW_MMIWADDR_GAIN_MASK BITS(15,8) /* tx: written 2nd */ 517 #define ATW_MMIWADDR_RATE_MASK BITS(7,0) /* tx: written 1st */ 518 519 /* was magic 0x100E0C0A */ 520 #define ATW_MMIWADDR_INTERSIL \ 521 (SHIFTIN(0x0c, ATW_MMIWADDR_GAIN_MASK) | \ 522 SHIFTIN(0x0a, ATW_MMIWADDR_RATE_MASK) | \ 523 SHIFTIN(0x0e, ATW_MMIWADDR_LENHI_MASK) | \ 524 SHIFTIN(0x10, ATW_MMIWADDR_LENLO_MASK)) 525 526 /* was magic 0x00009101 527 * 528 * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to 529 * put the RF3000 into auto-increment mode so that it can write Tx gain, 530 * Tx length (high) and Tx length (low) registers back-to-back. 531 */ 532 #define ATW_MMIWADDR_RFMD \ 533 (SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ 534 SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) 535 536 #define ATW_MMIRADDR1_RSVD_MASK BITS(31, 24) 537 #define ATW_MMIRADDR1_PWRLVL_MASK BITS(23, 16) 538 #define ATW_MMIRADDR1_RSSI_MASK BITS(15, 8) 539 #define ATW_MMIRADDR1_RXSTAT_MASK BITS(7, 0) 540 541 /* was magic 0x00007c7e 542 * 543 * TBD document registers for Intersil 3861 baseband 544 */ 545 #define ATW_MMIRADDR1_INTERSIL \ 546 (SHIFTIN(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \ 547 SHIFTIN(0x7e, ATW_MMIRADDR1_RXSTAT_MASK)) 548 549 /* was magic 0x00000301 */ 550 #define ATW_MMIRADDR1_RFMD \ 551 (SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ 552 SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) 553 554 /* was magic 0x00100000 */ 555 #define ATW_MMIRADDR2_INTERSIL \ 556 (SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ 557 SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 558 559 /* was magic 0x7e100000 */ 560 #define ATW_MMIRADDR2_RFMD \ 561 (SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ 562 SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 563 564 #define ATW_MMIRADDR2_ID_MASK BITS(31, 24) /* 1st element ID in WEP table 565 * for Probe Response (huh?) 566 */ 567 /* RXPE is re-asserted after RXPECNT * 22MHz. */ 568 #define ATW_MMIRADDR2_RXPECNT_MASK BITS(23, 16) 569 #define ATW_MMIRADDR2_PROREXT BIT(15) /* Probe Response 570 * 11Mb/s length 571 * extension. 572 */ 573 #define ATW_MMIRADDR2_PRORLEN_MASK BITS(14, 0) /* Probe Response 574 * microsecond length 575 */ 576 577 #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 578 #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 579 #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 580 #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 581 582 #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 583 #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 584 #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 585 #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 586 * 2's complement signed integer 587 */ 588 589 #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 590 * Radio, PHYRST change after 591 * power-up, in 2ms units 592 */ 593 #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 594 * after internal data 595 * transmit end, in us 596 */ 597 #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 598 * after TXPE asserted, in us 599 */ 600 #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 601 * after internal data transmit 602 * end, in us 603 */ 604 #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 605 * after TXPE asserted, in us 606 */ 607 #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 608 * after internal data transmit 609 * end, in us 610 */ 611 #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 612 * after TXPE asserted, in us 613 */ 614 #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 615 * after internal data transmit 616 * end, in us 617 */ 618 619 #define ATW_CMDR_PM BIT(19) /* enables power mgmt 620 * capabilities. 621 */ 622 #define ATW_CMDR_APM BIT(18) /* APM mode, effective when 623 * PM = 1. 624 */ 625 #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 626 #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 627 /* 32 bytes */ 628 #define ATW_CMDR_DRT_8DW SHIFTIN(0x0, ATW_CMDR_DRT_MASK) 629 /* 64 bytes */ 630 #define ATW_CMDR_DRT_16DW SHIFTIN(0x1, ATW_CMDR_DRT_MASK) 631 /* Store & Forward */ 632 #define ATW_CMDR_DRT_SF SHIFTIN(0x2, ATW_CMDR_DRT_MASK) 633 /* Reserved */ 634 #define ATW_CMDR_DRT_RSVD SHIFTIN(0x3, ATW_CMDR_DRT_MASK) 635 #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 636 637 /* TBD PCIC */ 638 639 /* TBD PMCSR */ 640 641 642 #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 643 #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 644 #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 645 #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 646 647 #define ATW_C_PAR1_CTD BITS(16,31) /* Continuous Tx pattern */ 648 #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 649 #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 650 651 #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 652 #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 653 #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 654 #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 655 656 #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 657 #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 658 #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 659 #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 660 661 /* ATIM destination address */ 662 #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 663 #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 664 #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 665 #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 666 667 /* ATIM destination address, BSSID */ 668 #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 669 #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 670 #define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 671 #define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 672 673 /* BSSID */ 674 #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 675 #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 676 #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 677 #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 678 679 #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 680 #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 681 682 #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 683 #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 684 #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 685 #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 686 687 #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 688 #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 689 #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 690 691 /* For ADM8211C/CR */ 692 /* ATW_C_TSC_TIMTABSEL = 1 */ 693 #define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */ 694 #define ATW_C_BCNT_BEANLEN1 BITS(30,16) /* beacon length in us */ 695 /* ATW_C_TSC_TIMTABSEL = 0 */ 696 #define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */ 697 #define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */ 698 699 #define ATW_C_TSC_TIMOFS BITS(31,24) /* I think this is the 700 * SRAM offset for the TIM 701 */ 702 #define ATW_C_TSC_TIMLEN BITS(21,12) /* length of TIM */ 703 #define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */ 704 #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value, 0 705 * disables 706 */ 707 708 #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 709 * 1: ATW_SYNRF controls SYN IF pins. 710 */ 711 #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 712 * 1: ATW_SYNRF controls RF IF pins. 713 */ 714 #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 715 * LERF# pin 716 */ 717 #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 718 * LEIF# pin 719 */ 720 #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 721 * SYNCLK pin 722 */ 723 #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 724 * SYNDATA pin 725 */ 726 #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 727 * PE1 pin 728 */ 729 #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 730 * PE2 pin 731 */ 732 #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 733 * PAPE pin 734 */ 735 #define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of 736 * TRSW pin 737 */ 738 #define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of 739 * TRSWn pin 740 */ 741 #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 742 * some signal used by the 743 * Intersil RF front-end? 744 * Undocumented. 745 */ 746 #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 747 * PHYRST# pin 748 */ 749 /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 750 #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 751 752 #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 753 #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 754 * beacon intervals 755 */ 756 757 #define ATW_C_CAP0_TIMLEN1 BITS(31,24) /* TIM table 1 len in bytes 758 * including TIM ID (XXX huh?) 759 */ 760 #define ATW_C_CAP0_TIMLEN0 BITS(23,16) /* TIM table 0 len in bytes, 761 * including TIM ID (XXX huh?) 762 */ 763 #define ATW_C_CAP0_CWMAX BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? 764 * 5 < CWMAX <= 9 sets max? 765 * 10? 766 * default 0 767 */ 768 #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 769 #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 770 771 #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 772 #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 773 774 #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 775 #define ATW_RMD_CFP BIT(30) /* CFP indicator */ 776 #define ATW_RMD_PCNT BITS(27,16) /* idle time between 777 * awake/ps mode, in seconds 778 */ 779 #define ATW_RMD_RMRD_MASK BITS(15,0) /* max RX reception duration 780 * in us 781 */ 782 783 #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 784 #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 785 #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 786 * intervals 787 */ 788 #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 789 * in 1 microsecond. 790 * Depends PCI bus speed? 791 */ 792 #define ATW_C_TOFS0_TUCNT_MASK BITS(14,10) /* PIFS (microseconds) */ 793 #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 794 795 /* TBD TOFS1 */ 796 #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 797 * microseconds: RF+BBP 798 * latency 799 */ 800 #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 801 * Nth TBTT - TBTTOFS) in 802 * microseconds (huh?). To 803 * match TSFT[25:10] (huh?). 804 */ 805 #define ATW_TBTTPRE_MASK BITS(25, 10) 806 #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 807 * TBTT in TU 808 */ 809 #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 810 #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 811 #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 812 #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 813 814 #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 815 #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 816 #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 817 818 #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 819 #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 820 #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 821 #define ATW_WEPCTL_WR BIT(28) /* */ 822 #define ATW_WEPCTL_RD BIT(27) /* */ 823 #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 824 #define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl 825 * lookup fails, 0: use 826 * shared-key 827 */ 828 #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 829 * revision 0x20. Possibly 830 * selects a different WEP 831 * table. 832 */ 833 #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 834 835 /* set these bits in the second byte of a SRAM shared key record to affect 836 * the use and interpretation of the key in the record. 837 */ 838 #define ATW_WEP_ENABLED BIT(7) 839 #define ATW_WEP_104BIT BIT(6) 840 841 #define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 842 #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 843 844 #define ATW_MACTEST_FORCE_IV BIT(23) 845 #define ATW_MACTEST_FORCE_KEYID BIT(22) 846 #define ATW_MACTEST_KEYID_MASK BITS(21,20) 847 #define ATW_MACTEST_MMI_USETXCLK BIT(11) 848 849 /* Function Event/Status registers */ 850 851 #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 852 #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 853 854 #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 855 #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 856 #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 857 858 #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 859 #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 860 #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 861 #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 862 863 /* Serial EEPROM offsets */ 864 #define ATW_SR_CLASS_CODE (0x00/2) 865 #define ATW_SR_FORMAT_VERSION (0x02/2) 866 #define ATW_SR_MAJOR_MASK BITS(7, 0) 867 #define ATW_SR_MINOR_MASK BITS(15,8) 868 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 869 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 870 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 871 #define ATW_SR_CSR20 (0x16/2) 872 #define ATW_SR_ANT_MASK BITS(12, 10) 873 #define ATW_SR_PWRSCALE_MASK BITS(9, 8) 874 #define ATW_SR_CLKSAVE_MASK BITS(7, 6) 875 #define ATW_SR_RFTYPE_MASK BITS(5, 3) 876 #define ATW_SR_BBPTYPE_MASK BITS(2, 0) 877 #define ATW_SR_CR28_CR03 (0x18/2) 878 #define ATW_SR_CR28_MASK BITS(15,8) 879 #define ATW_SR_CR03_MASK BITS(7, 0) 880 #define ATW_SR_CTRY_CR29 (0x1A/2) 881 #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 882 #define COUNTRY_FCC 0 883 #define COUNTRY_IC 1 884 #define COUNTRY_ETSI 2 885 #define COUNTRY_SPAIN 3 886 #define COUNTRY_FRANCE 4 887 #define COUNTRY_MMK 5 888 #define COUNTRY_MMK2 6 889 #define ATW_SR_CR29_MASK BITS(7, 0) 890 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 891 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 892 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 893 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 894 #define ATW_SR_CR15 (0x28/2) 895 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 896 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 897 #define ATW_SR_CSR18 (0x2E/2) 898 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 899 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 900 #define ATW_SR_CIS_WORDS (0x52/2) 901 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 902 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 903 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 904 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 905 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 906 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 907 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 908 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 909 910 /* Tx descriptor */ 911 struct atw_txdesc { 912 u_int32_t at_ctl; 913 #define at_stat at_ctl 914 u_int32_t at_flags; 915 u_int32_t at_buf1; 916 u_int32_t at_buf2; 917 }; 918 919 #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 920 #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 921 #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 922 #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 923 924 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 925 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 926 #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 927 #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 928 #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 929 #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 930 #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 931 #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 932 * (?) 933 */ 934 #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 935 936 #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 937 #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 938 #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 939 #define ATW_TXFLAG_TER BIT(25) /* end of ring */ 940 #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 941 #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 942 #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 943 944 /* Rx descriptor */ 945 struct atw_rxdesc { 946 u_int32_t ar_stat; 947 u_int32_t ar_ctl; 948 u_int32_t ar_buf1; 949 u_int32_t ar_buf2; 950 }; 951 952 #define ar_rssi ar_ctl 953 954 #define ATW_RXCTL_RER BIT(25) /* end of ring */ 955 #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 956 #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 957 #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 958 959 #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 960 #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 961 * success 962 */ 963 #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 964 #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 965 * truncated. last descriptor 966 * only 967 */ 968 #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 969 #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 970 #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 971 #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 972 #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 973 #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 974 #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 975 * only. 976 */ 977 #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 978 #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 979 #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 980 #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 981 #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 982 #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 983 * descriptor only 984 */ 985 986 /* Static RAM (contains WEP keys, beacon content). Addresses and size 987 * are in 16-bit words. 988 */ 989 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 990 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 991 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 992 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 993 #define ATW_SRAM_MAXSIZE (0x200 * 2) 994 #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE 995 #define ATW_SRAM_B_SIZE (0x1c0 * 2) 996 997
Indexes created Sun Sep 28 16:09:52 GMT 2025