atwreg.h revision 1.18
1 /* $NetBSD: atwreg.h,v 1.18 2007/11/16 04:58:39 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 #include <lib/libkern/libkern.h> 51 #include <dev/ic/rf3000reg.h> 52 #include <dev/ic/hfa3861areg.h> 53 54 /* ADM8211 Host Control and Status Registers */ 55 56 #define ATW_PAR 0x00 /* PCI access */ 57 #define ATW_FRCTL 0x04 /* Frame control */ 58 #define ATW_TDR 0x08 /* Transmit demand */ 59 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 60 #define ATW_RDR 0x10 /* Receive demand */ 61 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 62 #define ATW_RDB 0x18 /* Receive descriptor base address */ 63 #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 64 #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 65 * high-priority packet 66 */ 67 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 68 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 69 #define ATW_STSR 0x28 /* Status */ 70 #define ATW_CSR5A 0x2C /* Unused */ 71 #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 72 * broadcast/multicast packet 73 */ 74 #define ATW_NAR 0x30 /* Network access */ 75 #define ATW_CSR6A 0x34 /* Unused */ 76 #define ATW_IER 0x38 /* Interrupt enable */ 77 #define ATW_CSR7A 0x3C 78 #define ATW_LPC 0x40 /* Lost packet counter */ 79 #define ATW_TEST1 0x44 /* Test register 1 */ 80 #define ATW_SPR 0x48 /* Serial port */ 81 #define ATW_TEST0 0x4C /* Test register 0 */ 82 #define ATW_WCSR 0x50 /* Wake-up control/status */ 83 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 84 #define ATW_GPTMR 0x58 /* General purpose timer */ 85 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 86 #define ATW_BBPCTL 0x60 /* BBP control port */ 87 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 88 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 89 #define ATW_MMIWADDR 0x6C /* MMI write address */ 90 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 91 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 92 #define ATW_TXBR 0x78 /* Transmit burst counter */ 93 #define ATW_CSR15A 0x7C /* Unused */ 94 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 95 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 96 #define ATW_CMDR 0x88 /* Command */ 97 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 98 #define ATW_PMCSR 0x90 /* Power management command and status */ 99 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 100 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 101 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 102 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 103 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 104 * frame DA, byte[3:0] 105 */ 106 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 107 * ATIM frame DA byte[5:4] 108 */ 109 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 110 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 111 * Max TX MSDU lifetime, 16b 112 */ 113 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 114 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 115 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 116 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 117 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 118 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 119 * STA listen interval, 16b. 120 */ 121 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 122 #define ATW_CAP1 0xD0 /* Capability information, 16b. 123 * ATIM window, 1b. 124 */ 125 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 126 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 127 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 128 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 129 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 130 #define ATW_RSPT 0xE8 /* Response time, 24b */ 131 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 132 #define ATW_WEPCTL 0xF0 /* WEP control */ 133 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 134 #define ATW_WEPCNT 0xF8 /* WEP count */ 135 #define ATW_MACTEST 0xFC 136 137 #define ATW_FER 0x100 /* Function event */ 138 #define ATW_FEMR 0x104 /* Function event mask */ 139 #define ATW_FPSR 0x108 /* Function present state */ 140 #define ATW_FFER 0x10C /* Function force event */ 141 142 143 #define ATW_PAR_MWIE __BIT(24) /* memory write and invalidate 144 * enable 145 */ 146 #define ATW_PAR_MRLE __BIT(23) /* memory read line enable */ 147 #define ATW_PAR_MRME __BIT(21) /* memory read multiple 148 * enable 149 */ 150 #define ATW_PAR_RAP_MASK __BITS(17, 18) /* receive auto-polling in 151 * receive suspended state 152 */ 153 #define ATW_PAR_CAL_MASK __BITS(14, 15) /* cache alignment */ 154 #define ATW_PAR_CAL_PBL 0x0 155 /* min(8 DW, PBL) */ 156 #define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK) 157 /* min(16 DW, PBL) */ 158 #define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK) 159 /* min(32 DW, PBL) */ 160 #define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK) 161 #define ATW_PAR_PBL_MASK __BITS(8, 13) /* programmable burst length */ 162 #define ATW_PAR_PBL_UNLIMITED 0x0 163 #define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK) 164 #define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK) 165 #define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK) 166 #define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK) 167 #define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK) 168 #define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK) 169 #define ATW_PAR_BLE __BIT(7) /* big/little endian selection */ 170 #define ATW_PAR_DSL_MASK __BITS(2, 6) /* descriptor skip length */ 171 #define ATW_PAR_BAR __BIT(1) /* bus arbitration */ 172 #define ATW_PAR_SWR __BIT(0) /* software reset */ 173 174 #define ATW_FRCTL_PWRMGMT __BIT(31) /* power management */ 175 #define ATW_FRCTL_VER_MASK __BITS(29, 30) /* protocol version */ 176 #define ATW_FRCTL_ORDER __BIT(28) /* order bit */ 177 #define ATW_FRCTL_MAXPSP __BIT(27) /* maximum power saving */ 178 #define ATW_C_FRCTL_PRSP __BIT(26) /* 1: driver sends probe 179 * response 180 * 0: ASIC sends prresp 181 */ 182 #define ATW_C_FRCTL_DRVBCON __BIT(25) /* 1: driver sends beacons 183 * 0: ASIC sends beacons 184 */ 185 #define ATW_C_FRCTL_DRVLINKCTRL __BIT(24) /* 1: driver controls link LED 186 * 0: ASIC controls link LED 187 */ 188 #define ATW_C_FRCTL_DRVLINKON __BIT(23) /* 1: turn on link LED 189 * 0: turn off link LED 190 */ 191 #define ATW_C_FRCTL_CTX_DATA __BIT(22) /* 0: set by CSR28 192 * 1: random 193 */ 194 #define ATW_C_FRCTL_RSVFRM __BIT(21) /* 1: receive "reserved" 195 * frames, 0: ignore 196 * reserved frames 197 */ 198 #define ATW_C_FRCTL_CFEND __BIT(19) /* write to send CF_END, 199 * ADM8211C/CR clears 200 */ 201 #define ATW_FRCTL_DOZEFRM __BIT(18) /* select pre-sleep frame */ 202 #define ATW_FRCTL_PSAWAKE __BIT(17) /* MAC is awake (?) */ 203 #define ATW_FRCTL_PSMODE __BIT(16) /* MAC is power-saving (?) */ 204 #define ATW_FRCTL_AID_MASK __BITS(0, 15) /* STA Association ID */ 205 206 #define ATW_INTR_PCF __BIT(31) /* started/ended CFP */ 207 #define ATW_INTR_BCNTC __BIT(30) /* transmitted IBSS beacon */ 208 #define ATW_INTR_GPINT __BIT(29) /* GPIO interrupt */ 209 #define ATW_INTR_LINKOFF __BIT(28) /* lost ATW_WCSR_BLN beacons */ 210 #define ATW_INTR_ATIMTC __BIT(27) /* transmitted ATIM */ 211 #define ATW_INTR_TSFTF __BIT(26) /* TSFT out of range */ 212 #define ATW_INTR_TSCZ __BIT(25) /* TSC countdown expired */ 213 #define ATW_INTR_LINKON __BIT(24) /* matched SSID, BSSID */ 214 #define ATW_INTR_SQL __BIT(23) /* Marvel signal quality */ 215 #define ATW_INTR_WEPTD __BIT(22) /* switched WEP table */ 216 #define ATW_INTR_ATIME __BIT(21) /* ended ATIM window */ 217 #define ATW_INTR_TBTT __BIT(20) /* (TBTT) Target Beacon TX Time 218 * passed 219 */ 220 #define ATW_INTR_NISS __BIT(16) /* normal interrupt status 221 * summary: any of 31, 30, 27, 222 * 24, 14, 12, 6, 2, 0. 223 */ 224 #define ATW_INTR_AISS __BIT(15) /* abnormal interrupt status 225 * summary: any of 29, 28, 26, 226 * 25, 23, 22, 13, 11, 8, 7, 5, 227 * 4, 3, 1. 228 */ 229 #define ATW_INTR_TEIS __BIT(14) /* transmit early interrupt 230 * status: moved TX packet to 231 * FIFO 232 */ 233 #define ATW_INTR_FBE __BIT(13) /* fatal bus error */ 234 #define ATW_INTR_REIS __BIT(12) /* receive early interrupt 235 * status: RX packet filled 236 * its first descriptor 237 */ 238 #define ATW_INTR_GPTT __BIT(11) /* general purpose timer expired */ 239 #define ATW_INTR_RPS __BIT(8) /* stopped receive process */ 240 #define ATW_INTR_RDU __BIT(7) /* receive descriptor 241 * unavailable 242 */ 243 #define ATW_INTR_RCI __BIT(6) /* completed packet reception */ 244 #define ATW_INTR_TUF __BIT(5) /* transmit underflow */ 245 #define ATW_INTR_TRT __BIT(4) /* transmit retry count 246 * expired 247 */ 248 #define ATW_INTR_TLT __BIT(3) /* transmit lifetime exceeded */ 249 #define ATW_INTR_TDU __BIT(2) /* transmit descriptor 250 * unavailable 251 */ 252 #define ATW_INTR_TPS __BIT(1) /* stopped transmit process */ 253 #define ATW_INTR_TCI __BIT(0) /* completed transmit */ 254 #define ATW_NAR_TXCF __BIT(31) /* stop process on TX failure */ 255 #define ATW_NAR_HF __BIT(30) /* flush TX FIFO to host (?) */ 256 #define ATW_NAR_UTR __BIT(29) /* select retry count source */ 257 #define ATW_NAR_PCF __BIT(28) /* use one/both transmit 258 * descriptor base addresses 259 */ 260 #define ATW_NAR_CFP __BIT(27) /* indicate more TX data to 261 * point coordinator 262 */ 263 #define ATW_C_NAR_APSTA __BIT(26) /* 0: STA mode 264 * 1: AP mode 265 */ 266 #define ATW_C_NAR_TDBBE __BIT(25) /* 0: disable TDBB 267 * 1: enable TDBB 268 */ 269 #define ATW_C_NAR_TDBHE __BIT(24) /* 0: disable TDBH 270 * 1: enable TDBH 271 */ 272 #define ATW_C_NAR_TDBHT __BIT(23) /* write 1 to make ASIC 273 * poll TDBH once; ASIC clears 274 */ 275 #define ATW_NAR_SF __BIT(21) /* store and forward: ignore 276 * TX threshold 277 */ 278 #define ATW_NAR_TR_MASK __BITS(14, 15) /* TX threshold */ 279 #define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK) 280 #define ATW_NAR_TR_L160 __SHIFTIN(0x2, ATW_NAR_TR_MASK) 281 #define ATW_NAR_TR_L192 __SHIFTIN(0x3, ATW_NAR_TR_MASK) 282 #define ATW_NAR_TR_H96 __SHIFTIN(0x0, ATW_NAR_TR_MASK) 283 #define ATW_NAR_TR_H288 __SHIFTIN(0x2, ATW_NAR_TR_MASK) 284 #define ATW_NAR_TR_H544 __SHIFTIN(0x3, ATW_NAR_TR_MASK) 285 #define ATW_NAR_ST __BIT(13) /* start/stop transmit */ 286 #define ATW_NAR_OM_MASK __BITS(10, 11) /* operating mode */ 287 #define ATW_NAR_OM_NORMAL 0x0 288 #define ATW_NAR_OM_LOOPBACK __SHIFTIN(0x1, ATW_NAR_OM_MASK) 289 #define ATW_NAR_MM __BIT(7) /* RX any multicast */ 290 #define ATW_NAR_PR __BIT(6) /* promiscuous mode */ 291 #define ATW_NAR_EA __BIT(5) /* match ad hoc packets (?) */ 292 #define ATW_NAR_DISPCF __BIT(4) /* 1: PCF *not* supported 293 * 0: PCF supported 294 */ 295 #define ATW_NAR_PB __BIT(3) /* pass bad packets */ 296 #define ATW_NAR_STPDMA __BIT(2) /* stop DMA, abort packet */ 297 #define ATW_NAR_SR __BIT(1) /* start/stop receive */ 298 #define ATW_NAR_CTX __BIT(0) /* continuous TX mode */ 299 300 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 301 #if 0 302 #define ATW_IER_NIE __BIT(16) /* normal interrupt enable */ 303 #define ATW_IER_AIE __BIT(15) /* abnormal interrupt enable */ 304 /* normal interrupts: combine with ATW_IER_NIE */ 305 #define ATW_IER_PCFIE __BIT(31) /* STA entered CFP */ 306 #define ATW_IER_BCNTCIE __BIT(30) /* STA TX'd beacon */ 307 #define ATW_IER_ATIMTCIE __BIT(27) /* transmitted ATIM */ 308 #define ATW_IER_LINKONIE __BIT(24) /* matched beacon */ 309 #define ATW_IER_ATIMIE __BIT(21) /* ended ATIM window */ 310 #define ATW_IER_TBTTIE __BIT(20) /* TBTT */ 311 #define ATW_IER_TEIE __BIT(14) /* moved TX packet to FIFO */ 312 #define ATW_IER_REIE __BIT(12) /* RX packet filled its first 313 * descriptor 314 */ 315 #define ATW_IER_RCIE __BIT(6) /* completed RX */ 316 #define ATW_IER_TDUIE __BIT(2) /* transmit descriptor 317 * unavailable 318 */ 319 #define ATW_IER_TCIE __BIT(0) /* completed TX */ 320 /* abnormal interrupts: combine with ATW_IER_AIE */ 321 #define ATW_IER_GPIE __BIT(29) /* GPIO interrupt */ 322 #define ATW_IER_LINKOFFIE __BIT(28) /* lost beacon */ 323 #define ATW_IER_TSFTFIE __BIT(26) /* TSFT out of range */ 324 #define ATW_IER_TSCIE __BIT(25) /* TSC countdown expired */ 325 #define ATW_IER_SQLIE __BIT(23) /* signal quality */ 326 #define ATW_IER_WEPIE __BIT(22) /* finished WEP table switch */ 327 #define ATW_IER_FBEIE __BIT(13) /* fatal bus error */ 328 #define ATW_IER_GPTIE __BIT(11) /* general purpose timer expired */ 329 #define ATW_IER_RPSIE __BIT(8) /* stopped receive process */ 330 #define ATW_IER_RUIE __BIT(7) /* receive descriptor unavailable */ 331 #define ATW_IER_TUIE __BIT(5) /* transmit underflow */ 332 #define ATW_IER_TRTIE __BIT(4) /* exceeded transmit retry count */ 333 #define ATW_IER_TLTTIE __BIT(3) /* transmit lifetime exceeded */ 334 #define ATW_IER_TPSIE __BIT(1) /* stopped transmit process */ 335 #endif 336 337 #define ATW_LPC_LPCO __BIT(16) /* lost packet counter overflow */ 338 #define ATW_LPC_LPC_MASK __BITS(0, 15) /* lost packet counter */ 339 340 #define ATW_TEST1_CONTROL __BIT(31) /* "0: read from dxfer_control, 341 * 1: read from dxfer_state" 342 */ 343 #define ATW_TEST1_DBGREAD_MASK __BITS(30,28) /* "control of read data, 344 * debug only" 345 */ 346 #define ATW_TEST1_TXWP_MASK __BITS(27,25) /* select ATW_WTDP content? */ 347 #define ATW_TEST1_TXWP_TDBD __SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) 348 #define ATW_TEST1_TXWP_TDBH __SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) 349 #define ATW_TEST1_TXWP_TDBB __SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) 350 #define ATW_TEST1_TXWP_TDBP __SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) 351 #define ATW_TEST1_RSVD0_MASK __BITS(24,6) /* reserved */ 352 #define ATW_TEST1_TESTMODE_MASK __BITS(5,4) 353 /* normal operation */ 354 #define ATW_TEST1_TESTMODE_NORMAL __SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) 355 /* MAC-only mode */ 356 #define ATW_TEST1_TESTMODE_MACONLY __SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) 357 /* normal operation */ 358 #define ATW_TEST1_TESTMODE_NORMAL2 __SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) 359 /* monitor mode */ 360 #define ATW_TEST1_TESTMODE_MONITOR __SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) 361 362 #define ATW_TEST1_DUMP_MASK __BITS(3,0) /* select dump signal 363 * from dxfer (huh?) 364 */ 365 366 #define ATW_SPR_SRS __BIT(11) /* activate SEEPROM access */ 367 #define ATW_SPR_SDO __BIT(3) /* data out of SEEPROM */ 368 #define ATW_SPR_SDI __BIT(2) /* data into SEEPROM */ 369 #define ATW_SPR_SCLK __BIT(1) /* SEEPROM clock */ 370 #define ATW_SPR_SCS __BIT(0) /* SEEPROM chip select */ 371 372 #define ATW_TEST0_BE_MASK __BITS(31, 29) /* Bus error state */ 373 #define ATW_TEST0_TS_MASK __BITS(28, 26) /* Transmit process state */ 374 375 /* Stopped */ 376 #define ATW_TEST0_TS_STOPPED __SHIFTIN(0, ATW_TEST0_TS_MASK) 377 /* Running - fetch transmit descriptor */ 378 #define ATW_TEST0_TS_FETCH __SHIFTIN(1, ATW_TEST0_TS_MASK) 379 /* Running - wait for end of transmission */ 380 #define ATW_TEST0_TS_WAIT __SHIFTIN(2, ATW_TEST0_TS_MASK) 381 /* Running - read buffer from memory and queue into FIFO */ 382 #define ATW_TEST0_TS_READING __SHIFTIN(3, ATW_TEST0_TS_MASK) 383 #define ATW_TEST0_TS_RESERVED1 __SHIFTIN(4, ATW_TEST0_TS_MASK) 384 #define ATW_TEST0_TS_RESERVED2 __SHIFTIN(5, ATW_TEST0_TS_MASK) 385 /* Suspended */ 386 #define ATW_TEST0_TS_SUSPENDED __SHIFTIN(6, ATW_TEST0_TS_MASK) 387 /* Running - close transmit descriptor */ 388 #define ATW_TEST0_TS_CLOSE __SHIFTIN(7, ATW_TEST0_TS_MASK) 389 390 /* ADM8211C/CR registers */ 391 /* Suspended */ 392 #define ATW_C_TEST0_TS_SUSPENDED __SHIFTIN(4, ATW_TEST0_TS_MASK) 393 /* Descriptor write */ 394 #define ATW_C_TEST0_TS_CLOSE __SHIFTIN(5, ATW_TEST0_TS_MASK) 395 /* Last descriptor write */ 396 #define ATW_C_TEST0_TS_CLOSELAST __SHIFTIN(6, ATW_TEST0_TS_MASK) 397 /* FIFO full */ 398 #define ATW_C_TEST0_TS_FIFOFULL __SHIFTIN(7, ATW_TEST0_TS_MASK) 399 400 #define ATW_TEST0_RS_MASK __BITS(25, 23) /* Receive process state */ 401 402 /* Stopped */ 403 #define ATW_TEST0_RS_STOPPED __SHIFTIN(0, ATW_TEST0_RS_MASK) 404 /* Running - fetch receive descriptor */ 405 #define ATW_TEST0_RS_FETCH __SHIFTIN(1, ATW_TEST0_RS_MASK) 406 /* Running - check for end of receive */ 407 #define ATW_TEST0_RS_CHECK __SHIFTIN(2, ATW_TEST0_RS_MASK) 408 /* Running - wait for packet */ 409 #define ATW_TEST0_RS_WAIT __SHIFTIN(3, ATW_TEST0_RS_MASK) 410 /* Suspended */ 411 #define ATW_TEST0_RS_SUSPENDED __SHIFTIN(4, ATW_TEST0_RS_MASK) 412 /* Running - close receive descriptor */ 413 #define ATW_TEST0_RS_CLOSE __SHIFTIN(5, ATW_TEST0_RS_MASK) 414 /* Running - flush current frame from FIFO */ 415 #define ATW_TEST0_RS_FLUSH __SHIFTIN(6, ATW_TEST0_RS_MASK) 416 /* Running - queue current frame from FIFO into buffer */ 417 #define ATW_TEST0_RS_QUEUE __SHIFTIN(7, ATW_TEST0_RS_MASK) 418 419 #define ATW_TEST0_EPNE __BIT(18) /* SEEPROM not detected */ 420 #define ATW_TEST0_EPSNM __BIT(17) /* SEEPROM bad signature */ 421 #define ATW_TEST0_EPTYP_MASK __BIT(16) /* SEEPROM type 422 * 1: 93c66, 423 * 0: 93c46 424 */ 425 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 426 #define ATW_TEST0_EPTYP_93c46 0 427 #define ATW_TEST0_EPRLD __BIT(15) /* recall SEEPROM (write 1) */ 428 429 #define ATW_WCSR_CRCT __BIT(30) /* CRC-16 type */ 430 #define ATW_WCSR_WP1E __BIT(29) /* match wake-up pattern 1 */ 431 #define ATW_WCSR_WP2E __BIT(28) /* match wake-up pattern 2 */ 432 #define ATW_WCSR_WP3E __BIT(27) /* match wake-up pattern 3 */ 433 #define ATW_WCSR_WP4E __BIT(26) /* match wake-up pattern 4 */ 434 #define ATW_WCSR_WP5E __BIT(25) /* match wake-up pattern 5 */ 435 #define ATW_WCSR_BLN_MASK __BITS(21, 23) /* lose link after BLN lost 436 * beacons 437 */ 438 #define ATW_WCSR_TSFTWE __BIT(20) /* wake up on TSFT out of 439 * range 440 */ 441 #define ATW_WCSR_TIMWE __BIT(19) /* wake up on TIM */ 442 #define ATW_WCSR_ATIMWE __BIT(18) /* wake up on ATIM */ 443 #define ATW_WCSR_KEYWE __BIT(17) /* wake up on key update */ 444 #define ATW_WCSR_WFRE __BIT(10) /* wake up on wake-up frame */ 445 #define ATW_WCSR_MPRE __BIT(9) /* wake up on magic packet */ 446 #define ATW_WCSR_LSOE __BIT(8) /* wake up on link loss */ 447 /* wake-up reasons correspond to enable bits */ 448 #define ATW_WCSR_KEYUP __BIT(6) /* */ 449 #define ATW_WCSR_TSFTW __BIT(5) /* */ 450 #define ATW_WCSR_TIMW __BIT(4) /* */ 451 #define ATW_WCSR_ATIMW __BIT(3) /* */ 452 #define ATW_WCSR_WFR __BIT(2) /* */ 453 #define ATW_WCSR_MPR __BIT(1) /* */ 454 #define ATW_WCSR_LSO __BIT(0) /* */ 455 456 #define ATW_GPTMR_COM_MASK __BIT(16) /* continuous operation mode */ 457 #define ATW_GPTMR_GTV_MASK __BITS(0, 15) /* set countdown in 204us ticks */ 458 459 #define ATW_GPIO_EC1_MASK __BITS(25, 24) /* GPIO1 event configuration */ 460 #define ATW_GPIO_LAT_MASK __BITS(21, 20) /* input latch */ 461 #define ATW_GPIO_INTEN_MASK __BITS(19, 18) /* interrupt enable */ 462 #define ATW_GPIO_EN_MASK __BITS(17, 12) /* output enable */ 463 #define ATW_GPIO_O_MASK __BITS(11, 6) /* output value */ 464 #define ATW_GPIO_I_MASK __BITS(5, 0) /* pin static input */ 465 466 /* Intersil 3-wire interface */ 467 #define ATW_BBPCTL_TWI __BIT(31) 468 #define ATW_BBPCTL_RF3KADDR_MASK __BITS(30, 24) /* Address for RF3000 */ 469 #define ATW_BBPCTL_RF3KADDR_ADDR __SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) 470 /* data-out on negative edge */ 471 #define ATW_BBPCTL_NEGEDGE_DO __BIT(23) 472 /* data-in on negative edge */ 473 #define ATW_BBPCTL_NEGEDGE_DI __BIT(22) 474 #define ATW_BBPCTL_CCA_ACTLO __BIT(21) /* CCA low when busy */ 475 #define ATW_BBPCTL_TYPE_MASK __BITS(20, 18) /* BBP type */ 476 /* start write; reset on completion */ 477 #define ATW_BBPCTL_WR __BIT(17) 478 #define ATW_BBPCTL_RD __BIT(16) /* start read; reset on 479 * completion 480 */ 481 #define ATW_BBPCTL_ADDR_MASK __BITS(15, 8) /* BBP address */ 482 #define ATW_BBPCTL_DATA_MASK __BITS(7, 0) /* BBP data */ 483 484 #define ATW_SYNCTL_WR __BIT(31) /* start write; reset on 485 * completion 486 */ 487 #define ATW_SYNCTL_RD __BIT(30) /* start read; reset on 488 * completion 489 */ 490 #define ATW_SYNCTL_CS0 __BIT(29) /* chip select */ 491 #define ATW_SYNCTL_CS1 __BIT(28) 492 #define ATW_SYNCTL_CAL __BIT(27) /* generate RF CAL pulse after 493 * Rx 494 */ 495 #define ATW_SYNCTL_SELCAL __BIT(26) /* RF CAL source, 0: CAL bit, 496 * 1: MAC; needed by Intersil 497 * BBP 498 */ 499 #define ATW_C_SYNCTL_MMICE __BIT(25) /* ADM8211C/CR define this 500 * bit. 0: latch data on 501 * negative edge, 1: positive 502 * edge. 503 */ 504 #define ATW_SYNCTL_RFTYPE_MASK __BITS(24, 22) /* RF type */ 505 #define ATW_SYNCTL_DATA_MASK __BITS(21, 0) /* synthesizer setting */ 506 507 #define ATW_PLCPHD_SIGNAL_MASK __BITS(31, 24) /* signal field in PLCP header, 508 * only for beacon, ATIM, and 509 * RTS. 510 */ 511 #define ATW_PLCPHD_SERVICE_MASK __BITS(23, 16) /* service field in PLCP 512 * header; with RFMD BBP, 513 * sets Tx power for beacon, 514 * RTS, ATIM. 515 */ 516 #define ATW_PLCPHD_PMBL __BIT(15) /* 0: long preamble, 1: short */ 517 518 #define ATW_MMIWADDR_LENLO_MASK __BITS(31,24) /* tx: written 4th */ 519 #define ATW_MMIWADDR_LENHI_MASK __BITS(23,16) /* tx: written 3rd */ 520 #define ATW_MMIWADDR_GAIN_MASK __BITS(15,8) /* tx: written 2nd */ 521 #define ATW_MMIWADDR_RATE_MASK __BITS(7,0) /* tx: written 1st */ 522 523 /* was magic 0x100E0C0A */ 524 #define ATW_MMIWADDR_INTERSIL \ 525 (__SHIFTIN(HFA3861A_CR6, ATW_MMIWADDR_GAIN_MASK) | \ 526 __SHIFTIN(HFA3861A_CR5, ATW_MMIWADDR_RATE_MASK) | \ 527 __SHIFTIN(HFA3861A_CR7, ATW_MMIWADDR_LENHI_MASK) | \ 528 __SHIFTIN(HFA3861A_CR8, ATW_MMIWADDR_LENLO_MASK)) 529 530 /* was magic 0x00009101 531 * 532 * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to 533 * put the RF3000 into auto-increment mode so that it can write Tx gain, 534 * Tx length (high) and Tx length (low) registers back-to-back. 535 */ 536 #define ATW_MMIWADDR_RFMD \ 537 (__SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ 538 __SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) 539 540 #define ATW_MMIRADDR1_RSVD_MASK __BITS(31, 24) 541 #define ATW_MMIRADDR1_PWRLVL_MASK __BITS(23, 16) 542 #define ATW_MMIRADDR1_RSSI_MASK __BITS(15, 8) 543 #define ATW_MMIRADDR1_RXSTAT_MASK __BITS(7, 0) 544 545 /* was magic 0x00007c7e */ 546 #define ATW_MMIRADDR1_INTERSIL \ 547 (__SHIFTIN(HFA3861A_CR61, ATW_MMIRADDR1_RSSI_MASK) | \ 548 __SHIFTIN(HFA3861A_CR62, ATW_MMIRADDR1_RXSTAT_MASK)) 549 550 /* was magic 0x00000301 */ 551 #define ATW_MMIRADDR1_RFMD \ 552 (__SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ 553 __SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) 554 555 /* was magic 0x00100000 */ 556 #define ATW_MMIRADDR2_INTERSIL \ 557 (__SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ 558 __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 559 560 /* was magic 0x7e100000 */ 561 #define ATW_MMIRADDR2_RFMD \ 562 (__SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ 563 __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 564 565 #define ATW_MMIRADDR2_ID_MASK __BITS(31, 24) /* 1st element ID in WEP table 566 * for Probe Response (huh?) 567 */ 568 /* RXPE is re-asserted after RXPECNT * 22MHz. */ 569 #define ATW_MMIRADDR2_RXPECNT_MASK __BITS(23, 16) 570 #define ATW_MMIRADDR2_PROREXT __BIT(15) /* Probe Response 571 * 11Mb/s length 572 * extension. 573 */ 574 #define ATW_MMIRADDR2_PRORLEN_MASK __BITS(14, 0) /* Probe Response 575 * microsecond length 576 */ 577 578 /* auto-update BBP with ALCSET */ 579 #define ATW_TXBR_ALCUPDATE_MASK __BIT(31) 580 #define ATW_TXBR_TBCNT_MASK __BITS(16, 20) /* transmit burst count */ 581 #define ATW_TXBR_ALCSET_MASK __BITS(8, 15) /* TX power level set point */ 582 #define ATW_TXBR_ALCREF_MASK __BITS(0, 7) /* TX power level reference point */ 583 584 #define ATW_ALCSTAT_MCOV_MASK __BIT(27) /* MPDU count overflow */ 585 #define ATW_ALCSTAT_ESOV_MASK __BIT(26) /* error sum overflow */ 586 #define ATW_ALCSTAT_MCNT_MASK __BITS(16, 25) /* MPDU count, unsigned integer */ 587 #define ATW_ALCSTAT_ERSUM_MASK __BITS(0, 15) /* power error sum, 588 * 2's complement signed integer 589 */ 590 591 #define ATW_TOFS2_PWR1UP_MASK __BITS(31, 28) /* delay of Tx/Rx from PE1, 592 * Radio, PHYRST change after 593 * power-up, in 2ms units 594 */ 595 #define ATW_TOFS2_PWR0PAPE_MASK __BITS(27, 24) /* delay of PAPE going low 596 * after internal data 597 * transmit end, in us 598 */ 599 #define ATW_TOFS2_PWR1PAPE_MASK __BITS(23, 20) /* delay of PAPE going high 600 * after TXPE asserted, in us 601 */ 602 #define ATW_TOFS2_PWR0TRSW_MASK __BITS(19, 16) /* delay of TRSW going low 603 * after internal data transmit 604 * end, in us 605 */ 606 #define ATW_TOFS2_PWR1TRSW_MASK __BITS(15, 12) /* delay of TRSW going high 607 * after TXPE asserted, in us 608 */ 609 #define ATW_TOFS2_PWR0PE2_MASK __BITS(11, 8) /* delay of PE2 going low 610 * after internal data transmit 611 * end, in us 612 */ 613 #define ATW_TOFS2_PWR1PE2_MASK __BITS(7, 4) /* delay of PE2 going high 614 * after TXPE asserted, in us 615 */ 616 #define ATW_TOFS2_PWR0TXPE_MASK __BITS(3, 0) /* delay of TXPE going low 617 * after internal data transmit 618 * end, in us 619 */ 620 621 #define ATW_CMDR_PM __BIT(19) /* enables power mgmt 622 * capabilities. 623 */ 624 #define ATW_CMDR_APM __BIT(18) /* APM mode, effective when 625 * PM = 1. 626 */ 627 #define ATW_CMDR_RTE __BIT(4) /* enable Rx FIFO threshold */ 628 #define ATW_CMDR_DRT_MASK __BITS(3, 2) /* drain Rx FIFO threshold */ 629 /* 32 bytes */ 630 #define ATW_CMDR_DRT_8DW __SHIFTIN(0x0, ATW_CMDR_DRT_MASK) 631 /* 64 bytes */ 632 #define ATW_CMDR_DRT_16DW __SHIFTIN(0x1, ATW_CMDR_DRT_MASK) 633 /* Store & Forward */ 634 #define ATW_CMDR_DRT_SF __SHIFTIN(0x2, ATW_CMDR_DRT_MASK) 635 /* Reserved */ 636 #define ATW_CMDR_DRT_RSVD __SHIFTIN(0x3, ATW_CMDR_DRT_MASK) 637 #define ATW_CMDR_SINT_MASK __BIT(1) /* software interrupt---huh? */ 638 639 /* TBD PCIC */ 640 641 /* TBD PMCSR */ 642 643 644 #define ATW_PAR0_PAB0_MASK __BITS(0, 7) /* MAC address byte 0 */ 645 #define ATW_PAR0_PAB1_MASK __BITS(8, 15) /* MAC address byte 1 */ 646 #define ATW_PAR0_PAB2_MASK __BITS(16, 23) /* MAC address byte 2 */ 647 #define ATW_PAR0_PAB3_MASK __BITS(24, 31) /* MAC address byte 3 */ 648 649 #define ATW_C_PAR1_CTD __BITS(16,31) /* Continuous Tx pattern */ 650 #define ATW_PAR1_PAB5_MASK __BITS(8, 15) /* MAC address byte 5 */ 651 #define ATW_PAR1_PAB4_MASK __BITS(0, 7) /* MAC address byte 4 */ 652 653 #define ATW_MAR0_MAB3_MASK __BITS(31, 24) /* multicast table bits 31:24 */ 654 #define ATW_MAR0_MAB2_MASK __BITS(23, 16) /* multicast table bits 23:16 */ 655 #define ATW_MAR0_MAB1_MASK __BITS(15, 8) /* multicast table bits 15:8 */ 656 #define ATW_MAR0_MAB0_MASK __BITS(7, 0) /* multicast table bits 7:0 */ 657 658 #define ATW_MAR1_MAB7_MASK __BITS(31, 24) /* multicast table bits 63:56 */ 659 #define ATW_MAR1_MAB6_MASK __BITS(23, 16) /* multicast table bits 55:48 */ 660 #define ATW_MAR1_MAB5_MASK __BITS(15, 8) /* multicast table bits 47:40 */ 661 #define ATW_MAR1_MAB4_MASK __BITS(7, 0) /* multicast table bits 39:32 */ 662 663 /* ATIM destination address */ 664 #define ATW_ATIMDA0_ATIMB3_MASK __BITS(31,24) 665 #define ATW_ATIMDA0_ATIMB2_MASK __BITS(23,16) 666 #define ATW_ATIMDA0_ATIMB1_MASK __BITS(15,8) 667 #define ATW_ATIMDA0_ATIMB0_MASK __BITS(7,0) 668 669 /* ATIM destination address, BSSID */ 670 #define ATW_ABDA1_BSSIDB5_MASK __BITS(31,24) 671 #define ATW_ABDA1_BSSIDB4_MASK __BITS(23,16) 672 #define ATW_ABDA1_ATIMB5_MASK __BITS(15,8) 673 #define ATW_ABDA1_ATIMB4_MASK __BITS(7,0) 674 675 /* BSSID */ 676 #define ATW_BSSID0_BSSIDB3_MASK __BITS(31,24) 677 #define ATW_BSSID0_BSSIDB2_MASK __BITS(23,16) 678 #define ATW_BSSID0_BSSIDB1_MASK __BITS(15,8) 679 #define ATW_BSSID0_BSSIDB0_MASK __BITS(7,0) 680 681 #define ATW_TXLMT_MTMLT_MASK __BITS(31,16) /* max TX MSDU lifetime in TU */ 682 #define ATW_TXLMT_SRTYLIM_MASK __BITS(7,0) /* short retry limit */ 683 684 #define ATW_MIBCNT_FFCNT_MASK __BITS(31,24) /* FCS failure count */ 685 #define ATW_MIBCNT_AFCNT_MASK __BITS(23,16) /* ACK failure count */ 686 #define ATW_MIBCNT_RSCNT_MASK __BITS(15,8) /* RTS success count */ 687 #define ATW_MIBCNT_RFCNT_MASK __BITS(7,0) /* RTS failure count */ 688 689 #define ATW_BCNT_PLCPH_MASK __BITS(23,16) /* 11M PLCP length (us) */ 690 #define ATW_BCNT_PLCPL_MASK __BITS(15,8) /* 5.5M PLCP length (us) */ 691 #define ATW_BCNT_BCNT_MASK __BITS(7,0) /* byte count of beacon frame */ 692 693 /* For ADM8211C/CR */ 694 /* ATW_C_TSC_TIMTABSEL = 1 */ 695 #define ATW_C_BCNT_EXTEN1 __BIT(31) /* 11M beacon len. extension */ 696 #define ATW_C_BCNT_BEANLEN1 __BITS(30,16) /* beacon length in us */ 697 /* ATW_C_TSC_TIMTABSEL = 0 */ 698 #define ATW_C_BCNT_EXTEN0 __BIT(15) /* 11M beacon len. extension */ 699 #define ATW_C_BCNT_BEANLEN0 __BIT(14,0) /* beacon length in us */ 700 701 #define ATW_C_TSC_TIMOFS __BITS(31,24) /* I think this is the 702 * SRAM offset for the TIM 703 */ 704 #define ATW_C_TSC_TIMLEN __BITS(21,12) /* length of TIM */ 705 #define ATW_C_TSC_TIMTABSEL __BIT(4) /* select TIM table 0 or 1 */ 706 #define ATW_TSC_TSC_MASK __BITS(3,0) /* TSFT countdown value, 0 707 * disables 708 */ 709 710 #define ATW_SYNRF_SELSYN __BIT(31) /* 0: MAC controls SYN IF pins, 711 * 1: ATW_SYNRF 712 * controls SYN IF 713 * pins. 714 */ 715 #define ATW_SYNRF_SELRF __BIT(30) /* 0: MAC controls RF IF pins, 716 * 1: ATW_SYNRF 717 * controls RF IF pins. 718 */ 719 #define ATW_SYNRF_LERF __BIT(29) /* if SELSYN = 1, direct control 720 * of LERF# pin 721 */ 722 #define ATW_SYNRF_LEIF __BIT(28) /* if SELSYN = 1, direct control 723 * of LEIF# pin 724 */ 725 #define ATW_SYNRF_SYNCLK __BIT(27) /* if SELSYN = 1, direct control 726 * of SYNCLK pin 727 */ 728 #define ATW_SYNRF_SYNDATA __BIT(26) /* if SELSYN = 1, direct control 729 * of SYNDATA pin 730 */ 731 #define ATW_SYNRF_PE1 __BIT(25) /* if SELRF = 1, direct control 732 * of PE1 pin 733 */ 734 #define ATW_SYNRF_PE2 __BIT(24) /* if SELRF = 1, direct control 735 * of PE2 pin 736 */ 737 #define ATW_SYNRF_PAPE __BIT(23) /* if SELRF = 1, direct control 738 * of PAPE pin 739 */ 740 #define ATW_C_SYNRF_TRSW __BIT(22) /* if SELRF = 1, direct control 741 * of TRSW pin 742 */ 743 #define ATW_C_SYNRF_TRSWN __BIT(21) /* if SELRF = 1, direct control 744 * of TRSWn pin 745 */ 746 #define ATW_SYNRF_INTERSIL_EN __BIT(20) /* if SELRF = 1, enables 747 * some signal used by the 748 * Intersil RF front-end? 749 * Undocumented. 750 */ 751 #define ATW_SYNRF_PHYRST __BIT(18) /* if SELRF = 1, direct control 752 * of PHYRST# pin 753 */ 754 /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 755 #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 756 757 #define ATW_BPLI_BP_MASK __BITS(31,16) /* beacon interval in TU */ 758 #define ATW_BPLI_LI_MASK __BITS(15,0) /* STA listen interval in 759 * beacon intervals 760 */ 761 762 #define ATW_C_CAP0_TIMLEN1 __BITS(31,24) /* TIM table 1 len in bytes 763 * including TIM ID (XXX huh?) 764 */ 765 #define ATW_C_CAP0_TIMLEN0 __BITS(23,16) /* TIM table 0 len in bytes, 766 * including TIM ID (XXX huh?) 767 */ 768 #define ATW_C_CAP0_CWMAX __BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? 769 * 5 < CWMAX <= 9 sets max? 770 * 10? 771 * default 0 772 */ 773 #define ATW_CAP0_RCVDTIM __BIT(4) /* receive every DTIM */ 774 #define ATW_CAP0_CHN_MASK __BITS(3,0) /* current DSSS channel */ 775 776 #define ATW_CAP1_CAPI_MASK __BITS(31,16) /* capability information */ 777 #define ATW_CAP1_ATIMW_MASK __BITS(15,0) /* ATIM window in TU */ 778 779 #define ATW_RMD_ATIMST __BIT(31) /* ATIM frame TX status */ 780 #define ATW_RMD_CFP __BIT(30) /* CFP indicator */ 781 #define ATW_RMD_PCNT __BITS(27,16) /* idle time between 782 * awake/ps mode, in seconds 783 */ 784 #define ATW_RMD_RMRD_MASK __BITS(15,0) /* max RX reception duration 785 * in us 786 */ 787 788 #define ATW_CFPP_CFPP __BITS(31,24) /* CFP unit DTIM */ 789 #define ATW_CFPP_CFPMD __BITS(23,8) /* CFP max duration in TU */ 790 #define ATW_CFPP_DTIMP __BITS(7,0) /* DTIM period in beacon 791 * intervals 792 */ 793 #define ATW_TOFS0_USCNT_MASK __BITS(29,24) /* number of system clocks 794 * in 1 microsecond. 795 * Depends PCI bus speed? 796 */ 797 #define ATW_C_TOFS0_TUCNT_MASK __BITS(14,10) /* PIFS (microseconds) */ 798 #define ATW_TOFS0_TUCNT_MASK __BITS(9,0) /* TU counter in microseconds */ 799 800 /* TBD TOFS1 */ 801 #define ATW_TOFS1_TSFTOFSR_MASK __BITS(31,24) /* RX TSFT offset in 802 * microseconds: RF+BBP 803 * latency 804 */ 805 #define ATW_TOFS1_TBTTPRE_MASK __BITS(23,8) /* prediction time, (next 806 * Nth TBTT - TBTTOFS) in 807 * microseconds (huh?). To 808 * match TSFT[25:10] (huh?). 809 */ 810 #define ATW_TBTTPRE_MASK __BITS(25, 10) 811 #define ATW_TOFS1_TBTTOFS_MASK __BITS(7,0) /* wake-up time offset before 812 * TBTT in TU 813 */ 814 #define ATW_IFST_SLOT_MASK __BITS(27,23) /* SLOT time in us */ 815 #define ATW_IFST_SIFS_MASK __BITS(22,15) /* SIFS time in us */ 816 #define ATW_IFST_DIFS_MASK __BITS(14,9) /* DIFS time in us */ 817 #define ATW_IFST_EIFS_MASK __BITS(8,0) /* EIFS time in us */ 818 819 #define ATW_RSPT_MART_MASK __BITS(31,16) /* max response time in us */ 820 #define ATW_RSPT_MIRT_MASK __BITS(15,8) /* min response time in us */ 821 #define ATW_RSPT_TSFTOFST_MASK __BITS(7,0) /* TX TSFT offset in us */ 822 823 #define ATW_WEPCTL_WEPENABLE __BIT(31) /* enable WEP engine */ 824 #define ATW_WEPCTL_AUTOSWITCH __BIT(30) /* auto-switch enable (huh?) */ 825 #define ATW_WEPCTL_CURTBL __BIT(29) /* current table in use */ 826 #define ATW_WEPCTL_WR __BIT(28) /* */ 827 #define ATW_WEPCTL_RD __BIT(27) /* */ 828 #define ATW_WEPCTL_WEPRXBYP __BIT(25) /* bypass WEP on RX */ 829 #define ATW_WEPCTL_SHKEY __BIT(24) /* 1: pass to host if tbl 830 * lookup fails, 0: use 831 * shared-key 832 */ 833 #define ATW_WEPCTL_UNKNOWN0 __BIT(23) /* has something to do with 834 * revision 0x20. Possibly 835 * selects a different WEP 836 * table. 837 */ 838 #define ATW_WEPCTL_TBLADD_MASK __BITS(8,0) /* add to table */ 839 840 /* set these bits in the second byte of a SRAM shared key record to affect 841 * the use and interpretation of the key in the record. 842 */ 843 #define ATW_WEP_ENABLED __BIT(7) 844 #define ATW_WEP_104BIT __BIT(6) 845 846 #define ATW_WESK_DATA_MASK __BITS(15,0) /* data */ 847 #define ATW_WEPCNT_WIEC_MASK __BITS(15,0) /* WEP ICV error count */ 848 849 #define ATW_MACTEST_FORCE_IV __BIT(23) 850 #define ATW_MACTEST_FORCE_KEYID __BIT(22) 851 #define ATW_MACTEST_KEYID_MASK __BITS(21,20) 852 #define ATW_MACTEST_MMI_USETXCLK __BIT(11) 853 854 /* Function Event/Status registers */ 855 856 /* interrupt: set regardless of mask */ 857 #define ATW_FER_INTR __BIT(15) 858 /* general wake-up: set regardless of mask */ 859 #define ATW_FER_GWAKE __BIT(4) 860 861 #define ATW_FEMR_INTR_EN __BIT(15) /* enable INTA# */ 862 #define ATW_FEMR_WAKEUP_EN __BIT(14) /* enable wake-up */ 863 #define ATW_FEMR_GWAKE_EN __BIT(4) /* enable general wake-up */ 864 865 #define ATW_FPSR_INTR_STATUS __BIT(15) /* interrupt status */ 866 #define ATW_FPSR_WAKEUP_STATUS __BIT(4) /* CSTSCHG state */ 867 /* activate INTA (if not masked) */ 868 #define ATW_FFER_INTA_FORCE __BIT(15) 869 /* activate CSTSCHG (if not masked) */ 870 #define ATW_FFER_GWAKE_FORCE __BIT(4) 871 872 /* Serial EEPROM offsets */ 873 #define ATW_SR_CLASS_CODE (0x00/2) 874 #define ATW_SR_FORMAT_VERSION (0x02/2) 875 #define ATW_SR_MAJOR_MASK __BITS(7, 0) 876 #define ATW_SR_MINOR_MASK __BITS(15,8) 877 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 878 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 879 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 880 #define ATW_SR_CSR20 (0x16/2) 881 #define ATW_SR_ANT_MASK __BITS(12, 10) 882 #define ATW_SR_PWRSCALE_MASK __BITS(9, 8) 883 #define ATW_SR_CLKSAVE_MASK __BITS(7, 6) 884 #define ATW_SR_RFTYPE_MASK __BITS(5, 3) 885 #define ATW_SR_BBPTYPE_MASK __BITS(2, 0) 886 #define ATW_SR_CR28_CR03 (0x18/2) 887 #define ATW_SR_CR28_MASK __BITS(15,8) 888 #define ATW_SR_CR03_MASK __BITS(7, 0) 889 #define ATW_SR_CTRY_CR29 (0x1A/2) 890 #define ATW_SR_CTRY_MASK __BITS(15,8) /* country code */ 891 #define COUNTRY_FCC 0 892 #define COUNTRY_IC 1 893 #define COUNTRY_ETSI 2 894 #define COUNTRY_SPAIN 3 895 #define COUNTRY_FRANCE 4 896 #define COUNTRY_MMK 5 897 #define COUNTRY_MMK2 6 898 #define ATW_SR_CR29_MASK __BITS(7, 0) 899 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 900 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 901 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 902 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 903 #define ATW_SR_CR15 (0x28/2) 904 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 905 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 906 #define ATW_SR_CSR18 (0x2E/2) 907 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 908 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 909 #define ATW_SR_CIS_WORDS (0x52/2) 910 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 911 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 912 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 913 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 914 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 915 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 916 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 917 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 918 919 /* Tx descriptor */ 920 struct atw_txdesc { 921 volatile uint32_t at_ctl; 922 #define at_stat at_ctl 923 volatile uint32_t at_flags; 924 volatile uint32_t at_buf1; 925 volatile uint32_t at_buf2; 926 } __attribute__((__packed__, __aligned__(4))); 927 928 #define ATW_TXCTL_OWN __BIT(31) /* 1: ready to transmit */ 929 #define ATW_TXCTL_DONE __BIT(30) /* 0: not processed */ 930 #define ATW_TXCTL_TXDR_MASK __BITS(27,20) /* TX data rate (?) */ 931 #define ATW_TXCTL_TL_MASK __BITS(19,0) /* retry limit, 0 - 255 */ 932 933 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 934 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 935 #define ATW_TXSTAT_ES __BIT(29) /* 0: TX successful */ 936 #define ATW_TXSTAT_TLT __BIT(28) /* TX lifetime expired */ 937 #define ATW_TXSTAT_TRT __BIT(27) /* TX retry limit expired */ 938 #define ATW_TXSTAT_TUF __BIT(26) /* TX under-run error */ 939 #define ATW_TXSTAT_TRO __BIT(25) /* TX over-run error */ 940 #define ATW_TXSTAT_SOFBR __BIT(24) /* packet size != buffer size 941 * (?) 942 */ 943 #define ATW_TXSTAT_ARC_MASK __BITS(11,0) /* accumulated retry count */ 944 945 #define ATW_TXFLAG_IC __BIT(31) /* interrupt on completion */ 946 #define ATW_TXFLAG_LS __BIT(30) /* packet's last descriptor */ 947 #define ATW_TXFLAG_FS __BIT(29) /* packet's first descriptor */ 948 #define ATW_TXFLAG_TER __BIT(25) /* end of ring */ 949 #define ATW_TXFLAG_TCH __BIT(24) /* at_buf2 is 2nd chain */ 950 #define ATW_TXFLAG_TBS2_MASK __BITS(23,12) /* at_buf2 byte count */ 951 #define ATW_TXFLAG_TBS1_MASK __BITS(11,0) /* at_buf1 byte count */ 952 953 /* Rx descriptor */ 954 struct atw_rxdesc { 955 volatile uint32_t ar_stat; 956 volatile uint32_t ar_ctlrssi; 957 volatile uint32_t ar_buf1; 958 volatile uint32_t ar_buf2; 959 } __attribute__((__packed__, __aligned__(4))); 960 961 #define ATW_RXCTL_RER __BIT(25) /* end of ring */ 962 #define ATW_RXCTL_RCH __BIT(24) /* ar_buf2 is 2nd chain */ 963 #define ATW_RXCTL_RBS2_MASK __BITS(23,12) /* ar_buf2 byte count */ 964 #define ATW_RXCTL_RBS1_MASK __BITS(11,0) /* ar_buf1 byte count */ 965 966 #define ATW_RXSTAT_OWN __BIT(31) /* 1: NIC may fill descriptor */ 967 #define ATW_RXSTAT_ES __BIT(30) /* error summary, 0 on 968 * success 969 */ 970 #define ATW_RXSTAT_SQL __BIT(29) /* has signal quality (?) */ 971 #define ATW_RXSTAT_DE __BIT(28) /* descriptor error---packet is 972 * truncated. last descriptor 973 * only 974 */ 975 #define ATW_RXSTAT_FS __BIT(27) /* packet's first descriptor */ 976 #define ATW_RXSTAT_LS __BIT(26) /* packet's last descriptor */ 977 #define ATW_RXSTAT_PCF __BIT(25) /* received during CFP */ 978 #define ATW_RXSTAT_SFDE __BIT(24) /* PLCP SFD error */ 979 #define ATW_RXSTAT_SIGE __BIT(23) /* PLCP signal error */ 980 #define ATW_RXSTAT_CRC16E __BIT(22) /* PLCP CRC16 error */ 981 #define ATW_RXSTAT_RXTOE __BIT(21) /* RX time-out, last descriptor 982 * only. 983 */ 984 #define ATW_RXSTAT_CRC32E __BIT(20) /* CRC32 error */ 985 #define ATW_RXSTAT_ICVE __BIT(19) /* WEP ICV error */ 986 #define ATW_RXSTAT_DA1 __BIT(17) /* DA bit 1, admin'd address */ 987 #define ATW_RXSTAT_DA0 __BIT(16) /* DA bit 0, group address */ 988 #define ATW_RXSTAT_RXDR_MASK __BITS(15,12) /* RX data rate */ 989 #define ATW_RXSTAT_FL_MASK __BITS(11,0) /* RX frame length, last 990 * descriptor only 991 */ 992 993 /* Static RAM (contains WEP keys, beacon content). Addresses and size 994 * are in 16-bit words. 995 */ 996 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 997 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 998 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 999 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 1000 #define ATW_SRAM_MAXSIZE (0x200 * 2) 1001 #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE 1002 #define ATW_SRAM_B_SIZE (0x1c0 * 2) 1003 1004
Indexes created Tue Sep 30 07:10:03 GMT 2025