atwreg.h revision 1.2
1 /* $NetBSD: atwreg.h,v 1.2 2003/10/13 16:35:49 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 /* Macros for bit twiddling. */ 51 52 /* nth bit, BIT(0) == 0x1. */ 53 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 54 55 /* bits m through n, m < n. */ 56 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 57 58 /* find least significant bit that is set */ 59 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 60 61 /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 62 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 63 64 #define MASK_TO_SHIFT(m) ((GTEQ_POWER(LOWEST_SET_BIT((m)), 31) ? 31 : \ 65 (GTEQ_POWER(LOWEST_SET_BIT((m)), 30) ? 30 : \ 66 (GTEQ_POWER(LOWEST_SET_BIT((m)), 29) ? 29 : \ 67 (GTEQ_POWER(LOWEST_SET_BIT((m)), 28) ? 28 : \ 68 (GTEQ_POWER(LOWEST_SET_BIT((m)), 27) ? 27 : \ 69 (GTEQ_POWER(LOWEST_SET_BIT((m)), 26) ? 26 : \ 70 (GTEQ_POWER(LOWEST_SET_BIT((m)), 25) ? 25 : \ 71 (GTEQ_POWER(LOWEST_SET_BIT((m)), 24) ? 24 : \ 72 (GTEQ_POWER(LOWEST_SET_BIT((m)), 23) ? 23 : \ 73 (GTEQ_POWER(LOWEST_SET_BIT((m)), 22) ? 22 : \ 74 (GTEQ_POWER(LOWEST_SET_BIT((m)), 21) ? 21 : \ 75 (GTEQ_POWER(LOWEST_SET_BIT((m)), 20) ? 20 : \ 76 (GTEQ_POWER(LOWEST_SET_BIT((m)), 19) ? 19 : \ 77 (GTEQ_POWER(LOWEST_SET_BIT((m)), 18) ? 18 : \ 78 (GTEQ_POWER(LOWEST_SET_BIT((m)), 17) ? 17 : \ 79 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) ? 16 : \ 80 (GTEQ_POWER(LOWEST_SET_BIT((m)), 15) ? 15 : \ 81 (GTEQ_POWER(LOWEST_SET_BIT((m)), 14) ? 14 : \ 82 (GTEQ_POWER(LOWEST_SET_BIT((m)), 13) ? 13 : \ 83 (GTEQ_POWER(LOWEST_SET_BIT((m)), 12) ? 12 : \ 84 (GTEQ_POWER(LOWEST_SET_BIT((m)), 11) ? 11 : \ 85 (GTEQ_POWER(LOWEST_SET_BIT((m)), 10) ? 10 : \ 86 (GTEQ_POWER(LOWEST_SET_BIT((m)), 9) ? 9 : \ 87 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) ? 8 : \ 88 (GTEQ_POWER(LOWEST_SET_BIT((m)), 7) ? 7 : \ 89 (GTEQ_POWER(LOWEST_SET_BIT((m)), 6) ? 6 : \ 90 (GTEQ_POWER(LOWEST_SET_BIT((m)), 5) ? 5 : \ 91 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) ? 4 : \ 92 (GTEQ_POWER(LOWEST_SET_BIT((m)), 3) ? 3 : \ 93 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) ? 2 : \ 94 (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0)))))))))))))))))))))))))))))))) 95 96 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 97 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 98 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 99 100 /* ADM8211 Host Control and Status Registers */ 101 102 #define ATW_PAR 0x00 /* PCI access */ 103 #define ATW_FRCTL 0x04 /* Frame control */ 104 #define ATW_TDR 0x08 /* Transmit demand */ 105 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 106 #define ATW_RDR 0x10 /* Receive demand */ 107 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 108 #define ATW_RDB 0x18 /* Receive descriptor base address */ 109 #define ATW_CSR3A 0x1C /* Unused */ 110 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 111 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 112 #define ATW_STSR 0x28 /* Status */ 113 #define ATW_CSR5A 0x2C /* Unused */ 114 #define ATW_NAR 0x30 /* Network access */ 115 #define ATW_CSR6A 0x34 /* Unused */ 116 #define ATW_IER 0x38 /* Interrupt enable */ 117 #define ATW_CSR7A 0x3C 118 #define ATW_LPC 0x40 /* Lost packet counter */ 119 #define ATW_TEST1 0x44 /* Test register 1 */ 120 #define ATW_SPR 0x48 /* Serial port */ 121 #define ATW_TEST0 0x4C /* Test register 0 */ 122 #define ATW_WCSR 0x50 /* Wake-up control/status */ 123 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 124 #define ATW_GPTMR 0x58 /* General purpose timer */ 125 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 126 #define ATW_BBPCTL 0x60 /* BBP control port */ 127 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 128 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 129 #define ATW_MMIWADDR 0x6C /* MMI write address */ 130 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 131 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 132 #define ATW_TXBR 0x78 /* Transmit burst counter */ 133 #define ATW_CSR15A 0x7C /* Unused */ 134 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 135 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 136 #define ATW_CMDR 0x88 /* Command */ 137 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 138 #define ATW_PMCSR 0x90 /* Power management command and status */ 139 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 140 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 141 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 142 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 143 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 144 * frame DA, byte[3:0] 145 */ 146 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 147 * ATIM frame DA byte[5:4] 148 */ 149 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 150 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 151 * Max TX MSDU lifetime, 16b 152 */ 153 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 154 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 155 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 156 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 157 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 158 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 159 * STA listen interval, 16b. 160 */ 161 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 162 #define ATW_CAP1 0xD0 /* Capability information, 16b. 163 * ATIM window, 1b. 164 */ 165 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 166 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 167 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 168 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 169 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 170 #define ATW_RSPT 0xE8 /* Response time, 24b */ 171 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 172 #define ATW_WEPCTL 0xF0 /* WEP control */ 173 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 174 #define ATW_WEPCNT 0xF8 /* WEP count */ 175 #define ATW_MACTEST 0xFC 176 177 #define ATW_FER 0x100 /* Function event */ 178 #define ATW_FEMR 0x104 /* Function event mask */ 179 #define ATW_FPSR 0x108 /* Function present state */ 180 #define ATW_FFER 0x10C /* Function force event */ 181 182 183 #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 184 * enable 185 */ 186 #define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 187 #define ATW_PAR_MRME BIT(21) /* memory read multiple 188 * enable 189 */ 190 #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 191 * receive suspended state 192 */ 193 #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 194 #define ATW_PAR_CAL_PBL 0x0 195 /* min(8 DW, PBL) */ 196 #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 197 /* min(16 DW, PBL) */ 198 #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 199 /* min(32 DW, PBL) */ 200 #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 201 #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 202 #define ATW_PAR_PBL_UNLIMITED 0x0 203 #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 204 #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 205 #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 206 #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 207 #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 208 #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 209 #define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 210 #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 211 #define ATW_PAR_BAR BIT(1) /* bus arbitration */ 212 #define ATW_PAR_SWR BIT(0) /* software reset */ 213 214 #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 215 #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 216 #define ATW_FRCTL_ORDER BIT(28) /* order bit */ 217 #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 218 #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 219 #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 220 #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 221 #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 222 223 #define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 224 #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 225 #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 226 #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 227 #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 228 #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 229 #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 230 #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 231 #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 232 #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 233 #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 234 #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 235 * passed 236 */ 237 #define ATW_INTR_NISS BIT(16) /* normal interrupt status 238 * summary: any of 31, 30, 27, 239 * 24, 14, 12, 6, 2, 0. 240 */ 241 #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 242 * summary: any of 29, 28, 26, 243 * 25, 23, 22, 13, 11, 8, 7, 5, 244 * 4, 3, 1. 245 */ 246 #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 247 * status: moved TX packet to 248 * FIFO 249 */ 250 #define ATW_INTR_FBE BIT(13) /* fatal bus error */ 251 #define ATW_INTR_REIS BIT(12) /* receive early interrupt 252 * status: RX packet filled 253 * its first descriptor 254 */ 255 #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 256 #define ATW_INTR_RPS BIT(8) /* stopped receive process */ 257 #define ATW_INTR_RDU BIT(7) /* receive descriptor 258 * unavailable 259 */ 260 #define ATW_INTR_RCI BIT(6) /* completed packet reception */ 261 #define ATW_INTR_TUF BIT(5) /* transmit underflow */ 262 #define ATW_INTR_TRT BIT(4) /* transmit retry count 263 * expired 264 */ 265 #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 266 #define ATW_INTR_TDU BIT(2) /* transmit descriptor 267 * unavailable 268 */ 269 #define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 270 #define ATW_INTR_TCI BIT(0) /* completed transmit */ 271 #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 272 #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 273 #define ATW_NAR_UTR BIT(29) /* select retry count source */ 274 #define ATW_NAR_PCF BIT(28) /* use one/both transmit 275 * descriptor base addresses 276 */ 277 #define ATW_NAR_CFP BIT(27) /* indicate more TX data to 278 * point coordinator 279 */ 280 #define ATW_NAR_SF BIT(21) /* store and forward: ignore 281 * TX threshold 282 */ 283 #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 284 #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 285 #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 286 #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 287 #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 288 #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 289 #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 290 #define ATW_NAR_ST BIT(13) /* start/stop transmit */ 291 #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 292 #define ATW_NAR_OM_NORMAL 0x0 293 #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 294 #define ATW_NAR_MM BIT(7) /* RX any multicast */ 295 #define ATW_NAR_PR BIT(6) /* promiscuous mode */ 296 #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 297 #define ATW_NAR_PB BIT(3) /* pass bad packets */ 298 #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 299 #define ATW_NAR_SR BIT(1) /* start/stop receive */ 300 #define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 301 302 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 303 #if 0 304 #define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 305 #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 306 /* normal interrupts: combine with ATW_IER_NIE */ 307 #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 308 #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 309 #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 310 #define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 311 #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 312 #define ATW_IER_TBTTIE BIT(20) /* TBTT */ 313 #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 314 #define ATW_IER_REIE BIT(12) /* RX packet filled its first 315 * descriptor 316 */ 317 #define ATW_IER_RCIE BIT(6) /* completed RX */ 318 #define ATW_IER_TDUIE BIT(2) /* transmit descriptor 319 * unavailable 320 */ 321 #define ATW_IER_TCIE BIT(0) /* completed TX */ 322 /* abnormal interrupts: combine with ATW_IER_AIE */ 323 #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 324 #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 325 #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 326 #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 327 #define ATW_IER_SQLIE BIT(23) /* signal quality */ 328 #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 329 #define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 330 #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 331 #define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 332 #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 333 #define ATW_IER_TUIE BIT(5) /* transmit underflow */ 334 #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 335 #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 336 #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 337 #endif 338 339 #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 340 #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 341 342 #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 343 #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 344 #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 345 #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 346 #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 347 348 /* TBD CSR_TEST0 */ 349 #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 350 #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 351 352 /* Stopped */ 353 #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 354 /* Running - fetch transmit descriptor */ 355 #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 356 /* Running - wait for end of transmission */ 357 #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 358 /* Running - read buffer from memory and queue into FIFO */ 359 #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 360 #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 361 #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 362 /* Suspended */ 363 #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 364 /* Running - close transmit descriptor */ 365 #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 366 367 #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 368 369 /* Stopped */ 370 #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 371 /* Running - fetch receive descriptor */ 372 #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 373 /* Running - check for end of receive */ 374 #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 375 /* Running - wait for packet */ 376 #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 377 /* Suspended */ 378 #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 379 /* Running - close receive descriptor */ 380 #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 381 /* Running - flush current frame from FIFO */ 382 #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 383 /* Running - queue current frame from FIFO into buffer */ 384 #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 385 386 #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 387 #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 388 #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 389 * 1: 93c66, 390 * 0: 93c46 391 */ 392 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 393 #define ATW_TEST0_EPTYP_93c46 0 394 #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 395 396 #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 397 #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 398 #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 399 #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 400 #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 401 #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 402 #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 403 * beacons 404 */ 405 #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 406 * range 407 */ 408 #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 409 #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 410 #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 411 #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 412 #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 413 #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 414 /* wake-up reasons correspond to enable bits */ 415 #define ATW_WCSR_KEYUP BIT(6) /* */ 416 #define ATW_WCSR_TSFTW BIT(5) /* */ 417 #define ATW_WCSR_TIMW BIT(4) /* */ 418 #define ATW_WCSR_ATIMW BIT(3) /* */ 419 #define ATW_WCSR_WFR BIT(2) /* */ 420 #define ATW_WCSR_MPR BIT(1) /* */ 421 #define ATW_WCSR_LSO BIT(0) /* */ 422 423 #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 424 #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 425 426 #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 427 #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 428 #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 429 #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 430 #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 431 #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 432 433 #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 434 #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 435 #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 436 #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 437 #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 438 #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 439 #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 440 #define ATW_BBPCTL_WR BIT(17) /* start write; reset on 441 * completion 442 */ 443 #define ATW_BBPCTL_RD BIT(16) /* start read; reset on 444 * completion 445 */ 446 #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 447 #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 448 449 #define ATW_SYNCTL_WR BIT(31) /* start write; reset on 450 * completion 451 */ 452 #define ATW_SYNCTL_RD BIT(30) /* start read; reset on 453 * completion 454 */ 455 #define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 456 #define ATW_SYNCTL_CS1 BIT(28) 457 #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 458 * Rx 459 */ 460 #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 461 * 1: MAC; needed by Intersil 462 * BBP 463 */ 464 #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 465 #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 466 467 #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 468 * only for beacon, ATIM, and 469 * RTS. 470 */ 471 #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 472 * header 473 */ 474 #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 475 476 #define ATW_MMIWADDR_INTERSIL 0x100E0C0A 477 #define ATW_MMIWADDR_RFMD 0x00009101 478 479 #define ATW_MMIRADDR1_INTERSIL 0x00007c7e 480 #define ATW_MMIRADDR1_RFMD 0x00000301 481 482 #define ATW_MMIRADDR2_INTERSIL 0x00100000 483 #define ATW_MMIRADDR2_RFMD 0x7e100000 484 485 #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 486 #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 487 #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 488 #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 489 490 #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 491 #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 492 #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 493 #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 494 * 2's complement signed integer 495 */ 496 497 #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 498 * Radio, PHYRST change after 499 * power-up, in 2ms units 500 */ 501 #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 502 * after internal data 503 * transmit end, in us 504 */ 505 #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 506 * after TXPE asserted, in us 507 */ 508 #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 509 * after internal data transmit 510 * end, in us 511 */ 512 #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 513 * after TXPE asserted, in us 514 */ 515 #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 516 * after internal data transmit 517 * end, in us 518 */ 519 #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 520 * after TXPE asserted, in us 521 */ 522 #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 523 * after internal data transmit 524 * end, in us 525 */ 526 527 #define ATW_CMDR_PM BIT(19) /* enables power mgmt 528 * capabilities. 529 */ 530 #define ATW_CMDR_APM BIT(18) /* APM mode, effective when 531 * PM = 1. 532 */ 533 #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 534 #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 535 #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 536 537 /* TBD PCIC */ 538 539 /* TBD PMCSR */ 540 541 542 #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 543 #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 544 #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 545 #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 546 547 #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 548 #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 549 550 #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 551 #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 552 #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 553 #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 554 555 #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 556 #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 557 #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 558 #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 559 560 /* ATIM destination address */ 561 #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 562 #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 563 #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 564 #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 565 566 /* ATIM destination address, BSSID */ 567 #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 568 #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 569 #define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 570 #define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 571 572 /* BSSID */ 573 #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 574 #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 575 #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 576 #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 577 578 #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 579 #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 580 581 #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 582 #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 583 #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 584 #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 585 586 #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 587 #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 588 #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 589 590 #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value */ 591 592 #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 593 * 1: ATW_SYNRF controls SYN IF pins. 594 */ 595 #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 596 * 1: ATW_SYNRF controls RF IF pins. 597 */ 598 #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 599 * LERF# pin 600 */ 601 #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 602 * LEIF# pin 603 */ 604 #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 605 * SYNCLK pin 606 */ 607 #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 608 * SYNDATA pin 609 */ 610 #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 611 * PE1 pin 612 */ 613 #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 614 * PE2 pin 615 */ 616 #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 617 * PAPE pin 618 */ 619 #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 620 * some signal used by the 621 * Intersil RF front-end? 622 * Undocumented. 623 */ 624 #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 625 * PHYRST# pin 626 */ 627 628 #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 629 #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 630 * beacon intervals 631 */ 632 633 #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 634 #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 635 636 #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 637 #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 638 639 #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 640 #define ATW_RMD_CFP BIT(30) /* CFP indicator */ 641 #define ATW_RMD_PCNT BITS(27,16) /* idle time between 642 * awake/ps mode 643 */ 644 #define ATW_RMD_RMRD BITS(15,0) /* max RX reception duration 645 * in us 646 */ 647 648 #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 649 #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 650 #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 651 * intervals 652 */ 653 #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 654 * in 1 microsecond. 655 * Depends PCI bus speed? 656 */ 657 #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 658 659 /* TBD TOFS1 */ 660 #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 661 * microseconds: RF+BBP 662 * latency 663 */ 664 #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 665 * Nth TBTT - TBTTOFS) in 666 * microseconds (huh?). To 667 * match TSFT[25:10] (huh?). 668 */ 669 #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 670 * TBTT in TU 671 */ 672 #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 673 #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 674 #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 675 #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 676 677 #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 678 #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 679 #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 680 681 #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 682 #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 683 #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 684 #define ATW_WEPCTL_WR BIT(28) /* */ 685 #define ATW_WEPCTL_RD BIT(27) /* */ 686 #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 687 #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 688 * revision 0x20. Possibly 689 * selects a different WEP 690 * table. 691 */ 692 #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 693 694 /* set these bits in the second byte of a SRAM shared key record to affect 695 * the use and interpretation of the key in the record. 696 */ 697 #define ATW_WEP_ENABLED BIT(7) 698 #define ATW_WEP_104BIT BIT(6) 699 700 #define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 701 #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 702 703 #define ATW_MACTEST_FORCE_IV BIT(23) 704 #define ATW_MACTEST_FORCE_KEYID BIT(22) 705 #define ATW_MACTEST_KEYID_MASK BITS(21,20) 706 #define ATW_MACTEST_MMI_USETXCLK BIT(11) 707 708 /* Function Event/Status registers */ 709 710 #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 711 #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 712 713 #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 714 #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 715 #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 716 717 #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 718 #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 719 #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 720 #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 721 722 /* Serial EEPROM offsets */ 723 #define ATW_SR_CLASS_CODE (0x00/2) 724 #define ATW_SR_FORMAT_VERSION (0x02/2) 725 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 726 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 727 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 728 #define ATW_SR_CSR20 (0x16/2) 729 #define ATW_SR_ANT_MASK BITS(12, 10) 730 #define ATW_SR_PWRSCALE_MASK BITS(9, 8) 731 #define ATW_SR_CLKSAVE_MASK BITS(7, 6) 732 #define ATW_SR_RFTYPE_MASK BITS(5, 3) 733 #define ATW_SR_BBPTYPE_MASK BITS(2, 0) 734 #define ATW_SR_CR28_CR03 (0x18/2) 735 #define ATW_SR_CTRY_CR29 (0x1A/2) 736 #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 737 #define COUNTRY_FCC 0 738 #define COUNTRY_IC 1 739 #define COUNTRY_ETSI 2 740 #define COUNTRY_SPAIN 3 741 #define COUNTRY_FRANCE 4 742 #define COUNTRY_MMK 5 743 #define COUNTRY_MMK2 6 744 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 745 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 746 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 747 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 748 #define ATW_SR_CR15 (0x28/2) 749 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 750 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 751 #define ATW_SR_CSR18 (0x2E/2) 752 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 753 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 754 #define ATW_SR_CIS_WORDS (0x52/2) 755 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 756 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 757 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 758 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 759 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 760 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 761 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 762 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 763 764 /* Tx descriptor */ 765 struct atw_txdesc { 766 u_int32_t at_ctl; 767 #define at_stat at_ctl 768 u_int32_t at_flags; 769 u_int32_t at_buf1; 770 u_int32_t at_buf2; 771 }; 772 773 #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 774 #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 775 #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 776 #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 777 778 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 779 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 780 #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 781 #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 782 #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 783 #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 784 #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 785 #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 786 * (?) 787 */ 788 #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 789 790 #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 791 #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 792 #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 793 #define ATW_TXFLAG_TER BIT(25) /* end of ring */ 794 #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 795 #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 796 #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 797 798 /* Rx descriptor */ 799 struct atw_rxdesc { 800 u_int32_t ar_stat; 801 u_int32_t ar_ctl; 802 u_int32_t ar_buf1; 803 u_int32_t ar_buf2; 804 }; 805 806 #define ar_rssi ar_ctl 807 808 #define ATW_RXCTL_RER BIT(25) /* end of ring */ 809 #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 810 #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 811 #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 812 813 #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 814 #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 815 * success 816 */ 817 #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 818 #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 819 * truncated. last descriptor 820 * only 821 */ 822 #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 823 #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 824 #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 825 #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 826 #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 827 #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 828 #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 829 * only. 830 */ 831 #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 832 #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 833 #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 834 #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 835 #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 836 #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 837 * descriptor only 838 */ 839 840 /* Static RAM (contains WEP keys, beacon content). Addresses and size 841 * are in 16-bit words. 842 */ 843 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 844 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 845 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 846 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 847 #define ATW_SRAM_SIZE (0x200 * 2) 848 849 /* 850 * Registers for Silicon Laboratories Si4126/Si4126 RF synthesizer. 851 */ 852 #define SI4126_MAIN 0 /* main configuration */ 853 #define SI4126_MAIN_AUXSEL_MASK BITS(13, 12) 854 #define SI4126_MAIN_IFDIV_MASK BITS(11, 10) 855 #define SI4126_MAIN_XINDIV2 BIT(6) 856 #define SI4126_MAIN_LPWR BIT(5) 857 #define SI4126_MAIN_AUTOPDB BIT(3) 858 #define SI4126_GAIN 1 /* phase detector gain */ 859 #define SI4126_GAIN_KPI_MASK BITS(5, 4) 860 #define SI4126_GAIN_KP2_MASK BITS(3, 2) 861 #define SI4126_GAIN_KP1_MASK BITS(1, 0) 862 #define SI4126_POWER 2 /* powerdown */ 863 #define SI4126_POWER_PDIB BIT(1) 864 #define SI4126_POWER_PDRB BIT(0) 865 #define SI4126_RF1N 3 /* RF1 N divider */ 866 #define SI4126_RF2N 4 /* RF2 N divider */ 867 #define SI4126_IFN 5 /* IF N divider */ 868 #define SI4126_RF1R 6 /* RF1 R divider */ 869 #define SI4126_RF2R 7 /* RF2 R divider */ 870 #define SI4126_IFR 8 /* IF R divider */ 871 872 /* 873 * Registers for RF Microdevices RF3000 spread-spectrum baseband modem. 874 */ 875 #define RF3000_CTL 0x01 /* modem control */ 876 #define RF3000_RXSTAT RF3000_CTL /* RX status */ 877 #define RF3000_CTL_MODE_MASK BITS(7, 4) 878 #define RF3000_RXSTAT_ACQ BIT(2) 879 #define RF3000_RXSTAT_SFD BIT(1) 880 #define RF3000_RXSTAT_CRC BIT(0) 881 #define RF3000_CCACTL 0x02 /* CCA control */ 882 /* CCA mode */ 883 #define RF3000_CCACTL_MODE_MASK BITS(7, 6) 884 #define RF3000_CCACTL_MODE_RSSIT 0 /* RSSI threshold */ 885 #define RF3000_CCACTL_MODE_ACQ 1 /* acquisition */ 886 #define RF3000_CCACTL_MODE_BOTH 2 /* threshold or acq. */ 887 /* RSSI threshold for CCA */ 888 #define RF3000_CCACTL_RSSIT_MASK BITS(5, 0) 889 #define RF3000_DIVCTL 0x03 /* diversity control */ 890 #define RF3000_DIVCTL_ENABLE BIT(7) /* enable diversity */ 891 #define RF3000_DIVCTL_ANTSEL BIT(6) /* if ENABLE = 0, set 892 * ANT SEL 893 */ 894 #define RF3000_RSSI RF3000_DIVCTL /* RSSI value */ 895 #define RF3000_RSSI_MASK BITS(5, 0) 896 #define RF3000_GAINCTL 0x11 /* TX variable gain control */ 897 #define RF3000_GAINCTL_TXVGC_MASK BITS(7, 2) 898 #define RF3000_GAINCTL_SCRAMBLER BIT(1) 899 #define RF3000_LOGAINCAL 0x14 /* low gain calibration */ 900 #define RF3000_LOGAINCAL_CAL_MASK BITS(5, 0) 901 #define RF3000_HIGAINCAL 0x15 /* high gain calibration */ 902 #define RF3000_HIGAINCAL_CAL_MASK BITS(5, 0) 903 #define RF3000_HIGAINCAL_DSSSPAD BIT(6) /* 6dB gain pad for DSSS 904 * modes (meaning?) 905 */ 906 #define RF3000_MAGIC0 0x1C /* magic register derived from 907 * a binary-only driver 908 */ 909 #define RF3000_MAGIC0_VAL 0x00 910 #define RF3000_MAGIC1 0x1D /* magic register derived from 911 * a binary-only driver 912 */ 913 #define RF3000_MAGIC1_VAL 0x80 914 915
Indexes created Mon Sep 29 21:09:56 GMT 2025