atwreg.h revision 1.20
1 /* $NetBSD: atwreg.h,v 1.20 2008/05/04 12:43:45 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* glossary */ 32 33 /* DTIM Delivery Traffic Indication Map, sent by AP 34 * ATIM Ad Hoc Traffic Indication Map 35 * TU 1024 microseconds 36 * TSF time synchronization function 37 * TBTT target beacon transmission time 38 * DIFS distributed inter-frame space 39 * SIFS short inter-frame space 40 * EIFS extended inter-frame space 41 */ 42 43 #include <lib/libkern/libkern.h> 44 #include <dev/ic/rf3000reg.h> 45 #include <dev/ic/hfa3861areg.h> 46 47 /* ADM8211 Host Control and Status Registers */ 48 49 #define ATW_PAR 0x00 /* PCI access */ 50 #define ATW_FRCTL 0x04 /* Frame control */ 51 #define ATW_TDR 0x08 /* Transmit demand */ 52 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 53 #define ATW_RDR 0x10 /* Receive demand */ 54 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 55 #define ATW_RDB 0x18 /* Receive descriptor base address */ 56 #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 57 #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 58 * high-priority packet 59 */ 60 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 61 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 62 #define ATW_STSR 0x28 /* Status */ 63 #define ATW_CSR5A 0x2C /* Unused */ 64 #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 65 * broadcast/multicast packet 66 */ 67 #define ATW_NAR 0x30 /* Network access */ 68 #define ATW_CSR6A 0x34 /* Unused */ 69 #define ATW_IER 0x38 /* Interrupt enable */ 70 #define ATW_CSR7A 0x3C 71 #define ATW_LPC 0x40 /* Lost packet counter */ 72 #define ATW_TEST1 0x44 /* Test register 1 */ 73 #define ATW_SPR 0x48 /* Serial port */ 74 #define ATW_TEST0 0x4C /* Test register 0 */ 75 #define ATW_WCSR 0x50 /* Wake-up control/status */ 76 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 77 #define ATW_GPTMR 0x58 /* General purpose timer */ 78 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 79 #define ATW_BBPCTL 0x60 /* BBP control port */ 80 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 81 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 82 #define ATW_MMIWADDR 0x6C /* MMI write address */ 83 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 84 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 85 #define ATW_TXBR 0x78 /* Transmit burst counter */ 86 #define ATW_CSR15A 0x7C /* Unused */ 87 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 88 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 89 #define ATW_CMDR 0x88 /* Command */ 90 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 91 #define ATW_PMCSR 0x90 /* Power management command and status */ 92 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 93 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 94 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 95 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 96 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 97 * frame DA, byte[3:0] 98 */ 99 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 100 * ATIM frame DA byte[5:4] 101 */ 102 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 103 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 104 * Max TX MSDU lifetime, 16b 105 */ 106 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 107 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 108 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 109 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 110 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 111 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 112 * STA listen interval, 16b. 113 */ 114 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 115 #define ATW_CAP1 0xD0 /* Capability information, 16b. 116 * ATIM window, 1b. 117 */ 118 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 119 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 120 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 121 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 122 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 123 #define ATW_RSPT 0xE8 /* Response time, 24b */ 124 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 125 #define ATW_WEPCTL 0xF0 /* WEP control */ 126 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 127 #define ATW_WEPCNT 0xF8 /* WEP count */ 128 #define ATW_MACTEST 0xFC 129 130 #define ATW_FER 0x100 /* Function event */ 131 #define ATW_FEMR 0x104 /* Function event mask */ 132 #define ATW_FPSR 0x108 /* Function present state */ 133 #define ATW_FFER 0x10C /* Function force event */ 134 135 136 #define ATW_PAR_MWIE __BIT(24) /* memory write and invalidate 137 * enable 138 */ 139 #define ATW_PAR_MRLE __BIT(23) /* memory read line enable */ 140 #define ATW_PAR_MRME __BIT(21) /* memory read multiple 141 * enable 142 */ 143 #define ATW_PAR_RAP_MASK __BITS(17, 18) /* receive auto-polling in 144 * receive suspended state 145 */ 146 #define ATW_PAR_CAL_MASK __BITS(14, 15) /* cache alignment */ 147 #define ATW_PAR_CAL_PBL 0x0 148 /* min(8 DW, PBL) */ 149 #define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK) 150 /* min(16 DW, PBL) */ 151 #define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK) 152 /* min(32 DW, PBL) */ 153 #define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK) 154 #define ATW_PAR_PBL_MASK __BITS(8, 13) /* programmable burst length */ 155 #define ATW_PAR_PBL_UNLIMITED 0x0 156 #define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK) 157 #define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK) 158 #define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK) 159 #define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK) 160 #define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK) 161 #define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK) 162 #define ATW_PAR_BLE __BIT(7) /* big/little endian selection */ 163 #define ATW_PAR_DSL_MASK __BITS(2, 6) /* descriptor skip length */ 164 #define ATW_PAR_BAR __BIT(1) /* bus arbitration */ 165 #define ATW_PAR_SWR __BIT(0) /* software reset */ 166 167 #define ATW_FRCTL_PWRMGMT __BIT(31) /* power management */ 168 #define ATW_FRCTL_VER_MASK __BITS(29, 30) /* protocol version */ 169 #define ATW_FRCTL_ORDER __BIT(28) /* order bit */ 170 #define ATW_FRCTL_MAXPSP __BIT(27) /* maximum power saving */ 171 #define ATW_C_FRCTL_PRSP __BIT(26) /* 1: driver sends probe 172 * response 173 * 0: ASIC sends prresp 174 */ 175 #define ATW_C_FRCTL_DRVBCON __BIT(25) /* 1: driver sends beacons 176 * 0: ASIC sends beacons 177 */ 178 #define ATW_C_FRCTL_DRVLINKCTRL __BIT(24) /* 1: driver controls link LED 179 * 0: ASIC controls link LED 180 */ 181 #define ATW_C_FRCTL_DRVLINKON __BIT(23) /* 1: turn on link LED 182 * 0: turn off link LED 183 */ 184 #define ATW_C_FRCTL_CTX_DATA __BIT(22) /* 0: set by CSR28 185 * 1: random 186 */ 187 #define ATW_C_FRCTL_RSVFRM __BIT(21) /* 1: receive "reserved" 188 * frames, 0: ignore 189 * reserved frames 190 */ 191 #define ATW_C_FRCTL_CFEND __BIT(19) /* write to send CF_END, 192 * ADM8211C/CR clears 193 */ 194 #define ATW_FRCTL_DOZEFRM __BIT(18) /* select pre-sleep frame */ 195 #define ATW_FRCTL_PSAWAKE __BIT(17) /* MAC is awake (?) */ 196 #define ATW_FRCTL_PSMODE __BIT(16) /* MAC is power-saving (?) */ 197 #define ATW_FRCTL_AID_MASK __BITS(0, 15) /* STA Association ID */ 198 199 #define ATW_INTR_PCF __BIT(31) /* started/ended CFP */ 200 #define ATW_INTR_BCNTC __BIT(30) /* transmitted IBSS beacon */ 201 #define ATW_INTR_GPINT __BIT(29) /* GPIO interrupt */ 202 #define ATW_INTR_LINKOFF __BIT(28) /* lost ATW_WCSR_BLN beacons */ 203 #define ATW_INTR_ATIMTC __BIT(27) /* transmitted ATIM */ 204 #define ATW_INTR_TSFTF __BIT(26) /* TSFT out of range */ 205 #define ATW_INTR_TSCZ __BIT(25) /* TSC countdown expired */ 206 #define ATW_INTR_LINKON __BIT(24) /* matched SSID, BSSID */ 207 #define ATW_INTR_SQL __BIT(23) /* Marvel signal quality */ 208 #define ATW_INTR_WEPTD __BIT(22) /* switched WEP table */ 209 #define ATW_INTR_ATIME __BIT(21) /* ended ATIM window */ 210 #define ATW_INTR_TBTT __BIT(20) /* (TBTT) Target Beacon TX Time 211 * passed 212 */ 213 #define ATW_INTR_NISS __BIT(16) /* normal interrupt status 214 * summary: any of 31, 30, 27, 215 * 24, 14, 12, 6, 2, 0. 216 */ 217 #define ATW_INTR_AISS __BIT(15) /* abnormal interrupt status 218 * summary: any of 29, 28, 26, 219 * 25, 23, 22, 13, 11, 8, 7, 5, 220 * 4, 3, 1. 221 */ 222 #define ATW_INTR_TEIS __BIT(14) /* transmit early interrupt 223 * status: moved TX packet to 224 * FIFO 225 */ 226 #define ATW_INTR_FBE __BIT(13) /* fatal bus error */ 227 #define ATW_INTR_REIS __BIT(12) /* receive early interrupt 228 * status: RX packet filled 229 * its first descriptor 230 */ 231 #define ATW_INTR_GPTT __BIT(11) /* general purpose timer expired */ 232 #define ATW_INTR_RPS __BIT(8) /* stopped receive process */ 233 #define ATW_INTR_RDU __BIT(7) /* receive descriptor 234 * unavailable 235 */ 236 #define ATW_INTR_RCI __BIT(6) /* completed packet reception */ 237 #define ATW_INTR_TUF __BIT(5) /* transmit underflow */ 238 #define ATW_INTR_TRT __BIT(4) /* transmit retry count 239 * expired 240 */ 241 #define ATW_INTR_TLT __BIT(3) /* transmit lifetime exceeded */ 242 #define ATW_INTR_TDU __BIT(2) /* transmit descriptor 243 * unavailable 244 */ 245 #define ATW_INTR_TPS __BIT(1) /* stopped transmit process */ 246 #define ATW_INTR_TCI __BIT(0) /* completed transmit */ 247 #define ATW_NAR_TXCF __BIT(31) /* stop process on TX failure */ 248 #define ATW_NAR_HF __BIT(30) /* flush TX FIFO to host (?) */ 249 #define ATW_NAR_UTR __BIT(29) /* select retry count source */ 250 #define ATW_NAR_PCF __BIT(28) /* use one/both transmit 251 * descriptor base addresses 252 */ 253 #define ATW_NAR_CFP __BIT(27) /* indicate more TX data to 254 * point coordinator 255 */ 256 #define ATW_C_NAR_APSTA __BIT(26) /* 0: STA mode 257 * 1: AP mode 258 */ 259 #define ATW_C_NAR_TDBBE __BIT(25) /* 0: disable TDBB 260 * 1: enable TDBB 261 */ 262 #define ATW_C_NAR_TDBHE __BIT(24) /* 0: disable TDBH 263 * 1: enable TDBH 264 */ 265 #define ATW_C_NAR_TDBHT __BIT(23) /* write 1 to make ASIC 266 * poll TDBH once; ASIC clears 267 */ 268 #define ATW_NAR_SF __BIT(21) /* store and forward: ignore 269 * TX threshold 270 */ 271 #define ATW_NAR_TR_MASK __BITS(14, 15) /* TX threshold */ 272 #define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK) 273 #define ATW_NAR_TR_L160 __SHIFTIN(0x2, ATW_NAR_TR_MASK) 274 #define ATW_NAR_TR_L192 __SHIFTIN(0x3, ATW_NAR_TR_MASK) 275 #define ATW_NAR_TR_H96 __SHIFTIN(0x0, ATW_NAR_TR_MASK) 276 #define ATW_NAR_TR_H288 __SHIFTIN(0x2, ATW_NAR_TR_MASK) 277 #define ATW_NAR_TR_H544 __SHIFTIN(0x3, ATW_NAR_TR_MASK) 278 #define ATW_NAR_ST __BIT(13) /* start/stop transmit */ 279 #define ATW_NAR_OM_MASK __BITS(10, 11) /* operating mode */ 280 #define ATW_NAR_OM_NORMAL 0x0 281 #define ATW_NAR_OM_LOOPBACK __SHIFTIN(0x1, ATW_NAR_OM_MASK) 282 #define ATW_NAR_MM __BIT(7) /* RX any multicast */ 283 #define ATW_NAR_PR __BIT(6) /* promiscuous mode */ 284 #define ATW_NAR_EA __BIT(5) /* match ad hoc packets (?) */ 285 #define ATW_NAR_DISPCF __BIT(4) /* 1: PCF *not* supported 286 * 0: PCF supported 287 */ 288 #define ATW_NAR_PB __BIT(3) /* pass bad packets */ 289 #define ATW_NAR_STPDMA __BIT(2) /* stop DMA, abort packet */ 290 #define ATW_NAR_SR __BIT(1) /* start/stop receive */ 291 #define ATW_NAR_CTX __BIT(0) /* continuous TX mode */ 292 293 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 294 #if 0 295 #define ATW_IER_NIE __BIT(16) /* normal interrupt enable */ 296 #define ATW_IER_AIE __BIT(15) /* abnormal interrupt enable */ 297 /* normal interrupts: combine with ATW_IER_NIE */ 298 #define ATW_IER_PCFIE __BIT(31) /* STA entered CFP */ 299 #define ATW_IER_BCNTCIE __BIT(30) /* STA TX'd beacon */ 300 #define ATW_IER_ATIMTCIE __BIT(27) /* transmitted ATIM */ 301 #define ATW_IER_LINKONIE __BIT(24) /* matched beacon */ 302 #define ATW_IER_ATIMIE __BIT(21) /* ended ATIM window */ 303 #define ATW_IER_TBTTIE __BIT(20) /* TBTT */ 304 #define ATW_IER_TEIE __BIT(14) /* moved TX packet to FIFO */ 305 #define ATW_IER_REIE __BIT(12) /* RX packet filled its first 306 * descriptor 307 */ 308 #define ATW_IER_RCIE __BIT(6) /* completed RX */ 309 #define ATW_IER_TDUIE __BIT(2) /* transmit descriptor 310 * unavailable 311 */ 312 #define ATW_IER_TCIE __BIT(0) /* completed TX */ 313 /* abnormal interrupts: combine with ATW_IER_AIE */ 314 #define ATW_IER_GPIE __BIT(29) /* GPIO interrupt */ 315 #define ATW_IER_LINKOFFIE __BIT(28) /* lost beacon */ 316 #define ATW_IER_TSFTFIE __BIT(26) /* TSFT out of range */ 317 #define ATW_IER_TSCIE __BIT(25) /* TSC countdown expired */ 318 #define ATW_IER_SQLIE __BIT(23) /* signal quality */ 319 #define ATW_IER_WEPIE __BIT(22) /* finished WEP table switch */ 320 #define ATW_IER_FBEIE __BIT(13) /* fatal bus error */ 321 #define ATW_IER_GPTIE __BIT(11) /* general purpose timer expired */ 322 #define ATW_IER_RPSIE __BIT(8) /* stopped receive process */ 323 #define ATW_IER_RUIE __BIT(7) /* receive descriptor unavailable */ 324 #define ATW_IER_TUIE __BIT(5) /* transmit underflow */ 325 #define ATW_IER_TRTIE __BIT(4) /* exceeded transmit retry count */ 326 #define ATW_IER_TLTTIE __BIT(3) /* transmit lifetime exceeded */ 327 #define ATW_IER_TPSIE __BIT(1) /* stopped transmit process */ 328 #endif 329 330 #define ATW_LPC_LPCO __BIT(16) /* lost packet counter overflow */ 331 #define ATW_LPC_LPC_MASK __BITS(0, 15) /* lost packet counter */ 332 333 #define ATW_TEST1_CONTROL __BIT(31) /* "0: read from dxfer_control, 334 * 1: read from dxfer_state" 335 */ 336 #define ATW_TEST1_DBGREAD_MASK __BITS(30,28) /* "control of read data, 337 * debug only" 338 */ 339 #define ATW_TEST1_TXWP_MASK __BITS(27,25) /* select ATW_WTDP content? */ 340 #define ATW_TEST1_TXWP_TDBD __SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) 341 #define ATW_TEST1_TXWP_TDBH __SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) 342 #define ATW_TEST1_TXWP_TDBB __SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) 343 #define ATW_TEST1_TXWP_TDBP __SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) 344 #define ATW_TEST1_RSVD0_MASK __BITS(24,6) /* reserved */ 345 #define ATW_TEST1_TESTMODE_MASK __BITS(5,4) 346 /* normal operation */ 347 #define ATW_TEST1_TESTMODE_NORMAL __SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) 348 /* MAC-only mode */ 349 #define ATW_TEST1_TESTMODE_MACONLY __SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) 350 /* normal operation */ 351 #define ATW_TEST1_TESTMODE_NORMAL2 __SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) 352 /* monitor mode */ 353 #define ATW_TEST1_TESTMODE_MONITOR __SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) 354 355 #define ATW_TEST1_DUMP_MASK __BITS(3,0) /* select dump signal 356 * from dxfer (huh?) 357 */ 358 359 #define ATW_SPR_SRS __BIT(11) /* activate SEEPROM access */ 360 #define ATW_SPR_SDO __BIT(3) /* data out of SEEPROM */ 361 #define ATW_SPR_SDI __BIT(2) /* data into SEEPROM */ 362 #define ATW_SPR_SCLK __BIT(1) /* SEEPROM clock */ 363 #define ATW_SPR_SCS __BIT(0) /* SEEPROM chip select */ 364 365 #define ATW_TEST0_BE_MASK __BITS(31, 29) /* Bus error state */ 366 #define ATW_TEST0_TS_MASK __BITS(28, 26) /* Transmit process state */ 367 368 /* Stopped */ 369 #define ATW_TEST0_TS_STOPPED __SHIFTIN(0, ATW_TEST0_TS_MASK) 370 /* Running - fetch transmit descriptor */ 371 #define ATW_TEST0_TS_FETCH __SHIFTIN(1, ATW_TEST0_TS_MASK) 372 /* Running - wait for end of transmission */ 373 #define ATW_TEST0_TS_WAIT __SHIFTIN(2, ATW_TEST0_TS_MASK) 374 /* Running - read buffer from memory and queue into FIFO */ 375 #define ATW_TEST0_TS_READING __SHIFTIN(3, ATW_TEST0_TS_MASK) 376 #define ATW_TEST0_TS_RESERVED1 __SHIFTIN(4, ATW_TEST0_TS_MASK) 377 #define ATW_TEST0_TS_RESERVED2 __SHIFTIN(5, ATW_TEST0_TS_MASK) 378 /* Suspended */ 379 #define ATW_TEST0_TS_SUSPENDED __SHIFTIN(6, ATW_TEST0_TS_MASK) 380 /* Running - close transmit descriptor */ 381 #define ATW_TEST0_TS_CLOSE __SHIFTIN(7, ATW_TEST0_TS_MASK) 382 383 /* ADM8211C/CR registers */ 384 /* Suspended */ 385 #define ATW_C_TEST0_TS_SUSPENDED __SHIFTIN(4, ATW_TEST0_TS_MASK) 386 /* Descriptor write */ 387 #define ATW_C_TEST0_TS_CLOSE __SHIFTIN(5, ATW_TEST0_TS_MASK) 388 /* Last descriptor write */ 389 #define ATW_C_TEST0_TS_CLOSELAST __SHIFTIN(6, ATW_TEST0_TS_MASK) 390 /* FIFO full */ 391 #define ATW_C_TEST0_TS_FIFOFULL __SHIFTIN(7, ATW_TEST0_TS_MASK) 392 393 #define ATW_TEST0_RS_MASK __BITS(25, 23) /* Receive process state */ 394 395 /* Stopped */ 396 #define ATW_TEST0_RS_STOPPED __SHIFTIN(0, ATW_TEST0_RS_MASK) 397 /* Running - fetch receive descriptor */ 398 #define ATW_TEST0_RS_FETCH __SHIFTIN(1, ATW_TEST0_RS_MASK) 399 /* Running - check for end of receive */ 400 #define ATW_TEST0_RS_CHECK __SHIFTIN(2, ATW_TEST0_RS_MASK) 401 /* Running - wait for packet */ 402 #define ATW_TEST0_RS_WAIT __SHIFTIN(3, ATW_TEST0_RS_MASK) 403 /* Suspended */ 404 #define ATW_TEST0_RS_SUSPENDED __SHIFTIN(4, ATW_TEST0_RS_MASK) 405 /* Running - close receive descriptor */ 406 #define ATW_TEST0_RS_CLOSE __SHIFTIN(5, ATW_TEST0_RS_MASK) 407 /* Running - flush current frame from FIFO */ 408 #define ATW_TEST0_RS_FLUSH __SHIFTIN(6, ATW_TEST0_RS_MASK) 409 /* Running - queue current frame from FIFO into buffer */ 410 #define ATW_TEST0_RS_QUEUE __SHIFTIN(7, ATW_TEST0_RS_MASK) 411 412 #define ATW_TEST0_EPNE __BIT(18) /* SEEPROM not detected */ 413 #define ATW_TEST0_EPSNM __BIT(17) /* SEEPROM bad signature */ 414 #define ATW_TEST0_EPTYP_MASK __BIT(16) /* SEEPROM type 415 * 1: 93c66, 416 * 0: 93c46 417 */ 418 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 419 #define ATW_TEST0_EPTYP_93c46 0 420 #define ATW_TEST0_EPRLD __BIT(15) /* recall SEEPROM (write 1) */ 421 422 #define ATW_WCSR_CRCT __BIT(30) /* CRC-16 type */ 423 #define ATW_WCSR_WP1E __BIT(29) /* match wake-up pattern 1 */ 424 #define ATW_WCSR_WP2E __BIT(28) /* match wake-up pattern 2 */ 425 #define ATW_WCSR_WP3E __BIT(27) /* match wake-up pattern 3 */ 426 #define ATW_WCSR_WP4E __BIT(26) /* match wake-up pattern 4 */ 427 #define ATW_WCSR_WP5E __BIT(25) /* match wake-up pattern 5 */ 428 #define ATW_WCSR_BLN_MASK __BITS(21, 23) /* lose link after BLN lost 429 * beacons 430 */ 431 #define ATW_WCSR_TSFTWE __BIT(20) /* wake up on TSFT out of 432 * range 433 */ 434 #define ATW_WCSR_TIMWE __BIT(19) /* wake up on TIM */ 435 #define ATW_WCSR_ATIMWE __BIT(18) /* wake up on ATIM */ 436 #define ATW_WCSR_KEYWE __BIT(17) /* wake up on key update */ 437 #define ATW_WCSR_WFRE __BIT(10) /* wake up on wake-up frame */ 438 #define ATW_WCSR_MPRE __BIT(9) /* wake up on magic packet */ 439 #define ATW_WCSR_LSOE __BIT(8) /* wake up on link loss */ 440 /* wake-up reasons correspond to enable bits */ 441 #define ATW_WCSR_KEYUP __BIT(6) /* */ 442 #define ATW_WCSR_TSFTW __BIT(5) /* */ 443 #define ATW_WCSR_TIMW __BIT(4) /* */ 444 #define ATW_WCSR_ATIMW __BIT(3) /* */ 445 #define ATW_WCSR_WFR __BIT(2) /* */ 446 #define ATW_WCSR_MPR __BIT(1) /* */ 447 #define ATW_WCSR_LSO __BIT(0) /* */ 448 449 #define ATW_GPTMR_COM_MASK __BIT(16) /* continuous operation mode */ 450 #define ATW_GPTMR_GTV_MASK __BITS(0, 15) /* set countdown in 204us ticks */ 451 452 #define ATW_GPIO_EC1_MASK __BITS(25, 24) /* GPIO1 event configuration */ 453 #define ATW_GPIO_LAT_MASK __BITS(21, 20) /* input latch */ 454 #define ATW_GPIO_INTEN_MASK __BITS(19, 18) /* interrupt enable */ 455 #define ATW_GPIO_EN_MASK __BITS(17, 12) /* output enable */ 456 #define ATW_GPIO_O_MASK __BITS(11, 6) /* output value */ 457 #define ATW_GPIO_I_MASK __BITS(5, 0) /* pin static input */ 458 459 /* Intersil 3-wire interface */ 460 #define ATW_BBPCTL_TWI __BIT(31) 461 #define ATW_BBPCTL_RF3KADDR_MASK __BITS(30, 24) /* Address for RF3000 */ 462 #define ATW_BBPCTL_RF3KADDR_ADDR __SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) 463 /* data-out on negative edge */ 464 #define ATW_BBPCTL_NEGEDGE_DO __BIT(23) 465 /* data-in on negative edge */ 466 #define ATW_BBPCTL_NEGEDGE_DI __BIT(22) 467 #define ATW_BBPCTL_CCA_ACTLO __BIT(21) /* CCA low when busy */ 468 #define ATW_BBPCTL_TYPE_MASK __BITS(20, 18) /* BBP type */ 469 /* start write; reset on completion */ 470 #define ATW_BBPCTL_WR __BIT(17) 471 #define ATW_BBPCTL_RD __BIT(16) /* start read; reset on 472 * completion 473 */ 474 #define ATW_BBPCTL_ADDR_MASK __BITS(15, 8) /* BBP address */ 475 #define ATW_BBPCTL_DATA_MASK __BITS(7, 0) /* BBP data */ 476 477 #define ATW_SYNCTL_WR __BIT(31) /* start write; reset on 478 * completion 479 */ 480 #define ATW_SYNCTL_RD __BIT(30) /* start read; reset on 481 * completion 482 */ 483 #define ATW_SYNCTL_CS0 __BIT(29) /* chip select */ 484 #define ATW_SYNCTL_CS1 __BIT(28) 485 #define ATW_SYNCTL_CAL __BIT(27) /* generate RF CAL pulse after 486 * Rx 487 */ 488 #define ATW_SYNCTL_SELCAL __BIT(26) /* RF CAL source, 0: CAL bit, 489 * 1: MAC; needed by Intersil 490 * BBP 491 */ 492 #define ATW_C_SYNCTL_MMICE __BIT(25) /* ADM8211C/CR define this 493 * bit. 0: latch data on 494 * negative edge, 1: positive 495 * edge. 496 */ 497 #define ATW_SYNCTL_RFTYPE_MASK __BITS(24, 22) /* RF type */ 498 #define ATW_SYNCTL_DATA_MASK __BITS(21, 0) /* synthesizer setting */ 499 500 #define ATW_PLCPHD_SIGNAL_MASK __BITS(31, 24) /* signal field in PLCP header, 501 * only for beacon, ATIM, and 502 * RTS. 503 */ 504 #define ATW_PLCPHD_SERVICE_MASK __BITS(23, 16) /* service field in PLCP 505 * header; with RFMD BBP, 506 * sets Tx power for beacon, 507 * RTS, ATIM. 508 */ 509 #define ATW_PLCPHD_PMBL __BIT(15) /* 0: long preamble, 1: short */ 510 511 #define ATW_MMIWADDR_LENLO_MASK __BITS(31,24) /* tx: written 4th */ 512 #define ATW_MMIWADDR_LENHI_MASK __BITS(23,16) /* tx: written 3rd */ 513 #define ATW_MMIWADDR_GAIN_MASK __BITS(15,8) /* tx: written 2nd */ 514 #define ATW_MMIWADDR_RATE_MASK __BITS(7,0) /* tx: written 1st */ 515 516 /* was magic 0x100E0C0A */ 517 #define ATW_MMIWADDR_INTERSIL \ 518 (__SHIFTIN(HFA3861A_CR6, ATW_MMIWADDR_GAIN_MASK) | \ 519 __SHIFTIN(HFA3861A_CR5, ATW_MMIWADDR_RATE_MASK) | \ 520 __SHIFTIN(HFA3861A_CR7, ATW_MMIWADDR_LENHI_MASK) | \ 521 __SHIFTIN(HFA3861A_CR8, ATW_MMIWADDR_LENLO_MASK)) 522 523 /* was magic 0x00009101 524 * 525 * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to 526 * put the RF3000 into auto-increment mode so that it can write Tx gain, 527 * Tx length (high) and Tx length (low) registers back-to-back. 528 */ 529 #define ATW_MMIWADDR_RFMD \ 530 (__SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ 531 __SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) 532 533 #define ATW_MMIRADDR1_RSVD_MASK __BITS(31, 24) 534 #define ATW_MMIRADDR1_PWRLVL_MASK __BITS(23, 16) 535 #define ATW_MMIRADDR1_RSSI_MASK __BITS(15, 8) 536 #define ATW_MMIRADDR1_RXSTAT_MASK __BITS(7, 0) 537 538 /* was magic 0x00007c7e */ 539 #define ATW_MMIRADDR1_INTERSIL \ 540 (__SHIFTIN(HFA3861A_CR61, ATW_MMIRADDR1_RSSI_MASK) | \ 541 __SHIFTIN(HFA3861A_CR62, ATW_MMIRADDR1_RXSTAT_MASK)) 542 543 /* was magic 0x00000301 */ 544 #define ATW_MMIRADDR1_RFMD \ 545 (__SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ 546 __SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) 547 548 /* was magic 0x00100000 */ 549 #define ATW_MMIRADDR2_INTERSIL \ 550 (__SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ 551 __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 552 553 /* was magic 0x7e100000 */ 554 #define ATW_MMIRADDR2_RFMD \ 555 (__SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ 556 __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 557 558 #define ATW_MMIRADDR2_ID_MASK __BITS(31, 24) /* 1st element ID in WEP table 559 * for Probe Response (huh?) 560 */ 561 /* RXPE is re-asserted after RXPECNT * 22MHz. */ 562 #define ATW_MMIRADDR2_RXPECNT_MASK __BITS(23, 16) 563 #define ATW_MMIRADDR2_PROREXT __BIT(15) /* Probe Response 564 * 11Mb/s length 565 * extension. 566 */ 567 #define ATW_MMIRADDR2_PRORLEN_MASK __BITS(14, 0) /* Probe Response 568 * microsecond length 569 */ 570 571 /* auto-update BBP with ALCSET */ 572 #define ATW_TXBR_ALCUPDATE_MASK __BIT(31) 573 #define ATW_TXBR_TBCNT_MASK __BITS(16, 20) /* transmit burst count */ 574 #define ATW_TXBR_ALCSET_MASK __BITS(8, 15) /* TX power level set point */ 575 #define ATW_TXBR_ALCREF_MASK __BITS(0, 7) /* TX power level reference point */ 576 577 #define ATW_ALCSTAT_MCOV_MASK __BIT(27) /* MPDU count overflow */ 578 #define ATW_ALCSTAT_ESOV_MASK __BIT(26) /* error sum overflow */ 579 #define ATW_ALCSTAT_MCNT_MASK __BITS(16, 25) /* MPDU count, unsigned integer */ 580 #define ATW_ALCSTAT_ERSUM_MASK __BITS(0, 15) /* power error sum, 581 * 2's complement signed integer 582 */ 583 584 #define ATW_TOFS2_PWR1UP_MASK __BITS(31, 28) /* delay of Tx/Rx from PE1, 585 * Radio, PHYRST change after 586 * power-up, in 2ms units 587 */ 588 #define ATW_TOFS2_PWR0PAPE_MASK __BITS(27, 24) /* delay of PAPE going low 589 * after internal data 590 * transmit end, in us 591 */ 592 #define ATW_TOFS2_PWR1PAPE_MASK __BITS(23, 20) /* delay of PAPE going high 593 * after TXPE asserted, in us 594 */ 595 #define ATW_TOFS2_PWR0TRSW_MASK __BITS(19, 16) /* delay of TRSW going low 596 * after internal data transmit 597 * end, in us 598 */ 599 #define ATW_TOFS2_PWR1TRSW_MASK __BITS(15, 12) /* delay of TRSW going high 600 * after TXPE asserted, in us 601 */ 602 #define ATW_TOFS2_PWR0PE2_MASK __BITS(11, 8) /* delay of PE2 going low 603 * after internal data transmit 604 * end, in us 605 */ 606 #define ATW_TOFS2_PWR1PE2_MASK __BITS(7, 4) /* delay of PE2 going high 607 * after TXPE asserted, in us 608 */ 609 #define ATW_TOFS2_PWR0TXPE_MASK __BITS(3, 0) /* delay of TXPE going low 610 * after internal data transmit 611 * end, in us 612 */ 613 614 #define ATW_CMDR_PM __BIT(19) /* enables power mgmt 615 * capabilities. 616 */ 617 #define ATW_CMDR_APM __BIT(18) /* APM mode, effective when 618 * PM = 1. 619 */ 620 #define ATW_CMDR_RTE __BIT(4) /* enable Rx FIFO threshold */ 621 #define ATW_CMDR_DRT_MASK __BITS(3, 2) /* drain Rx FIFO threshold */ 622 /* 32 bytes */ 623 #define ATW_CMDR_DRT_8DW __SHIFTIN(0x0, ATW_CMDR_DRT_MASK) 624 /* 64 bytes */ 625 #define ATW_CMDR_DRT_16DW __SHIFTIN(0x1, ATW_CMDR_DRT_MASK) 626 /* Store & Forward */ 627 #define ATW_CMDR_DRT_SF __SHIFTIN(0x2, ATW_CMDR_DRT_MASK) 628 /* Reserved */ 629 #define ATW_CMDR_DRT_RSVD __SHIFTIN(0x3, ATW_CMDR_DRT_MASK) 630 #define ATW_CMDR_SINT_MASK __BIT(1) /* software interrupt---huh? */ 631 632 /* TBD PCIC */ 633 634 /* TBD PMCSR */ 635 636 637 #define ATW_PAR0_PAB0_MASK __BITS(0, 7) /* MAC address byte 0 */ 638 #define ATW_PAR0_PAB1_MASK __BITS(8, 15) /* MAC address byte 1 */ 639 #define ATW_PAR0_PAB2_MASK __BITS(16, 23) /* MAC address byte 2 */ 640 #define ATW_PAR0_PAB3_MASK __BITS(24, 31) /* MAC address byte 3 */ 641 642 #define ATW_C_PAR1_CTD __BITS(16,31) /* Continuous Tx pattern */ 643 #define ATW_PAR1_PAB5_MASK __BITS(8, 15) /* MAC address byte 5 */ 644 #define ATW_PAR1_PAB4_MASK __BITS(0, 7) /* MAC address byte 4 */ 645 646 #define ATW_MAR0_MAB3_MASK __BITS(31, 24) /* multicast table bits 31:24 */ 647 #define ATW_MAR0_MAB2_MASK __BITS(23, 16) /* multicast table bits 23:16 */ 648 #define ATW_MAR0_MAB1_MASK __BITS(15, 8) /* multicast table bits 15:8 */ 649 #define ATW_MAR0_MAB0_MASK __BITS(7, 0) /* multicast table bits 7:0 */ 650 651 #define ATW_MAR1_MAB7_MASK __BITS(31, 24) /* multicast table bits 63:56 */ 652 #define ATW_MAR1_MAB6_MASK __BITS(23, 16) /* multicast table bits 55:48 */ 653 #define ATW_MAR1_MAB5_MASK __BITS(15, 8) /* multicast table bits 47:40 */ 654 #define ATW_MAR1_MAB4_MASK __BITS(7, 0) /* multicast table bits 39:32 */ 655 656 /* ATIM destination address */ 657 #define ATW_ATIMDA0_ATIMB3_MASK __BITS(31,24) 658 #define ATW_ATIMDA0_ATIMB2_MASK __BITS(23,16) 659 #define ATW_ATIMDA0_ATIMB1_MASK __BITS(15,8) 660 #define ATW_ATIMDA0_ATIMB0_MASK __BITS(7,0) 661 662 /* ATIM destination address, BSSID */ 663 #define ATW_ABDA1_BSSIDB5_MASK __BITS(31,24) 664 #define ATW_ABDA1_BSSIDB4_MASK __BITS(23,16) 665 #define ATW_ABDA1_ATIMB5_MASK __BITS(15,8) 666 #define ATW_ABDA1_ATIMB4_MASK __BITS(7,0) 667 668 /* BSSID */ 669 #define ATW_BSSID0_BSSIDB3_MASK __BITS(31,24) 670 #define ATW_BSSID0_BSSIDB2_MASK __BITS(23,16) 671 #define ATW_BSSID0_BSSIDB1_MASK __BITS(15,8) 672 #define ATW_BSSID0_BSSIDB0_MASK __BITS(7,0) 673 674 #define ATW_TXLMT_MTMLT_MASK __BITS(31,16) /* max TX MSDU lifetime in TU */ 675 #define ATW_TXLMT_SRTYLIM_MASK __BITS(7,0) /* short retry limit */ 676 677 #define ATW_MIBCNT_FFCNT_MASK __BITS(31,24) /* FCS failure count */ 678 #define ATW_MIBCNT_AFCNT_MASK __BITS(23,16) /* ACK failure count */ 679 #define ATW_MIBCNT_RSCNT_MASK __BITS(15,8) /* RTS success count */ 680 #define ATW_MIBCNT_RFCNT_MASK __BITS(7,0) /* RTS failure count */ 681 682 #define ATW_BCNT_PLCPH_MASK __BITS(23,16) /* 11M PLCP length (us) */ 683 #define ATW_BCNT_PLCPL_MASK __BITS(15,8) /* 5.5M PLCP length (us) */ 684 #define ATW_BCNT_BCNT_MASK __BITS(7,0) /* byte count of beacon frame */ 685 686 /* For ADM8211C/CR */ 687 /* ATW_C_TSC_TIMTABSEL = 1 */ 688 #define ATW_C_BCNT_EXTEN1 __BIT(31) /* 11M beacon len. extension */ 689 #define ATW_C_BCNT_BEANLEN1 __BITS(30,16) /* beacon length in us */ 690 /* ATW_C_TSC_TIMTABSEL = 0 */ 691 #define ATW_C_BCNT_EXTEN0 __BIT(15) /* 11M beacon len. extension */ 692 #define ATW_C_BCNT_BEANLEN0 __BIT(14,0) /* beacon length in us */ 693 694 #define ATW_C_TSC_TIMOFS __BITS(31,24) /* I think this is the 695 * SRAM offset for the TIM 696 */ 697 #define ATW_C_TSC_TIMLEN __BITS(21,12) /* length of TIM */ 698 #define ATW_C_TSC_TIMTABSEL __BIT(4) /* select TIM table 0 or 1 */ 699 #define ATW_TSC_TSC_MASK __BITS(3,0) /* TSFT countdown value, 0 700 * disables 701 */ 702 703 #define ATW_SYNRF_SELSYN __BIT(31) /* 0: MAC controls SYN IF pins, 704 * 1: ATW_SYNRF 705 * controls SYN IF 706 * pins. 707 */ 708 #define ATW_SYNRF_SELRF __BIT(30) /* 0: MAC controls RF IF pins, 709 * 1: ATW_SYNRF 710 * controls RF IF pins. 711 */ 712 #define ATW_SYNRF_LERF __BIT(29) /* if SELSYN = 1, direct control 713 * of LERF# pin 714 */ 715 #define ATW_SYNRF_LEIF __BIT(28) /* if SELSYN = 1, direct control 716 * of LEIF# pin 717 */ 718 #define ATW_SYNRF_SYNCLK __BIT(27) /* if SELSYN = 1, direct control 719 * of SYNCLK pin 720 */ 721 #define ATW_SYNRF_SYNDATA __BIT(26) /* if SELSYN = 1, direct control 722 * of SYNDATA pin 723 */ 724 #define ATW_SYNRF_PE1 __BIT(25) /* if SELRF = 1, direct control 725 * of PE1 pin 726 */ 727 #define ATW_SYNRF_PE2 __BIT(24) /* if SELRF = 1, direct control 728 * of PE2 pin 729 */ 730 #define ATW_SYNRF_PAPE __BIT(23) /* if SELRF = 1, direct control 731 * of PAPE pin 732 */ 733 #define ATW_C_SYNRF_TRSW __BIT(22) /* if SELRF = 1, direct control 734 * of TRSW pin 735 */ 736 #define ATW_C_SYNRF_TRSWN __BIT(21) /* if SELRF = 1, direct control 737 * of TRSWn pin 738 */ 739 #define ATW_SYNRF_INTERSIL_EN __BIT(20) /* if SELRF = 1, enables 740 * some signal used by the 741 * Intersil RF front-end? 742 * Undocumented. 743 */ 744 #define ATW_SYNRF_PHYRST __BIT(18) /* if SELRF = 1, direct control 745 * of PHYRST# pin 746 */ 747 /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 748 #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 749 750 #define ATW_BPLI_BP_MASK __BITS(31,16) /* beacon interval in TU */ 751 #define ATW_BPLI_LI_MASK __BITS(15,0) /* STA listen interval in 752 * beacon intervals 753 */ 754 755 #define ATW_C_CAP0_TIMLEN1 __BITS(31,24) /* TIM table 1 len in bytes 756 * including TIM ID (XXX huh?) 757 */ 758 #define ATW_C_CAP0_TIMLEN0 __BITS(23,16) /* TIM table 0 len in bytes, 759 * including TIM ID (XXX huh?) 760 */ 761 #define ATW_C_CAP0_CWMAX __BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? 762 * 5 < CWMAX <= 9 sets max? 763 * 10? 764 * default 0 765 */ 766 #define ATW_CAP0_RCVDTIM __BIT(4) /* receive every DTIM */ 767 #define ATW_CAP0_CHN_MASK __BITS(3,0) /* current DSSS channel */ 768 769 #define ATW_CAP1_CAPI_MASK __BITS(31,16) /* capability information */ 770 #define ATW_CAP1_ATIMW_MASK __BITS(15,0) /* ATIM window in TU */ 771 772 #define ATW_RMD_ATIMST __BIT(31) /* ATIM frame TX status */ 773 #define ATW_RMD_CFP __BIT(30) /* CFP indicator */ 774 #define ATW_RMD_PCNT __BITS(27,16) /* idle time between 775 * awake/ps mode, in seconds 776 */ 777 #define ATW_RMD_RMRD_MASK __BITS(15,0) /* max RX reception duration 778 * in us 779 */ 780 781 #define ATW_CFPP_CFPP __BITS(31,24) /* CFP unit DTIM */ 782 #define ATW_CFPP_CFPMD __BITS(23,8) /* CFP max duration in TU */ 783 #define ATW_CFPP_DTIMP __BITS(7,0) /* DTIM period in beacon 784 * intervals 785 */ 786 #define ATW_TOFS0_USCNT_MASK __BITS(29,24) /* number of system clocks 787 * in 1 microsecond. 788 * Depends PCI bus speed? 789 */ 790 #define ATW_C_TOFS0_TUCNT_MASK __BITS(14,10) /* PIFS (microseconds) */ 791 #define ATW_TOFS0_TUCNT_MASK __BITS(9,0) /* TU counter in microseconds */ 792 793 /* TBD TOFS1 */ 794 #define ATW_TOFS1_TSFTOFSR_MASK __BITS(31,24) /* RX TSFT offset in 795 * microseconds: RF+BBP 796 * latency 797 */ 798 #define ATW_TOFS1_TBTTPRE_MASK __BITS(23,8) /* prediction time, (next 799 * Nth TBTT - TBTTOFS) in 800 * microseconds (huh?). To 801 * match TSFT[25:10] (huh?). 802 */ 803 #define ATW_TBTTPRE_MASK __BITS(25, 10) 804 #define ATW_TOFS1_TBTTOFS_MASK __BITS(7,0) /* wake-up time offset before 805 * TBTT in TU 806 */ 807 #define ATW_IFST_SLOT_MASK __BITS(27,23) /* SLOT time in us */ 808 #define ATW_IFST_SIFS_MASK __BITS(22,15) /* SIFS time in us */ 809 #define ATW_IFST_DIFS_MASK __BITS(14,9) /* DIFS time in us */ 810 #define ATW_IFST_EIFS_MASK __BITS(8,0) /* EIFS time in us */ 811 812 #define ATW_RSPT_MART_MASK __BITS(31,16) /* max response time in us */ 813 #define ATW_RSPT_MIRT_MASK __BITS(15,8) /* min response time in us */ 814 #define ATW_RSPT_TSFTOFST_MASK __BITS(7,0) /* TX TSFT offset in us */ 815 816 #define ATW_WEPCTL_WEPENABLE __BIT(31) /* enable WEP engine */ 817 #define ATW_WEPCTL_AUTOSWITCH __BIT(30) /* auto-switch enable (huh?) */ 818 #define ATW_WEPCTL_CURTBL __BIT(29) /* current table in use */ 819 #define ATW_WEPCTL_WR __BIT(28) /* */ 820 #define ATW_WEPCTL_RD __BIT(27) /* */ 821 #define ATW_WEPCTL_WEPRXBYP __BIT(25) /* bypass WEP on RX */ 822 #define ATW_WEPCTL_SHKEY __BIT(24) /* 1: pass to host if tbl 823 * lookup fails, 0: use 824 * shared-key 825 */ 826 #define ATW_WEPCTL_UNKNOWN0 __BIT(23) /* has something to do with 827 * revision 0x20. Possibly 828 * selects a different WEP 829 * table. 830 */ 831 #define ATW_WEPCTL_TBLADD_MASK __BITS(8,0) /* add to table */ 832 833 /* set these bits in the second byte of a SRAM shared key record to affect 834 * the use and interpretation of the key in the record. 835 */ 836 #define ATW_WEP_ENABLED __BIT(7) 837 #define ATW_WEP_104BIT __BIT(6) 838 839 #define ATW_WESK_DATA_MASK __BITS(15,0) /* data */ 840 #define ATW_WEPCNT_WIEC_MASK __BITS(15,0) /* WEP ICV error count */ 841 842 #define ATW_MACTEST_FORCE_IV __BIT(23) 843 #define ATW_MACTEST_FORCE_KEYID __BIT(22) 844 #define ATW_MACTEST_KEYID_MASK __BITS(21,20) 845 #define ATW_MACTEST_MMI_USETXCLK __BIT(11) 846 847 /* Function Event/Status registers */ 848 849 /* interrupt: set regardless of mask */ 850 #define ATW_FER_INTR __BIT(15) 851 /* general wake-up: set regardless of mask */ 852 #define ATW_FER_GWAKE __BIT(4) 853 854 #define ATW_FEMR_INTR_EN __BIT(15) /* enable INTA# */ 855 #define ATW_FEMR_WAKEUP_EN __BIT(14) /* enable wake-up */ 856 #define ATW_FEMR_GWAKE_EN __BIT(4) /* enable general wake-up */ 857 858 #define ATW_FPSR_INTR_STATUS __BIT(15) /* interrupt status */ 859 #define ATW_FPSR_WAKEUP_STATUS __BIT(4) /* CSTSCHG state */ 860 /* activate INTA (if not masked) */ 861 #define ATW_FFER_INTA_FORCE __BIT(15) 862 /* activate CSTSCHG (if not masked) */ 863 #define ATW_FFER_GWAKE_FORCE __BIT(4) 864 865 /* Serial EEPROM offsets */ 866 #define ATW_SR_CLASS_CODE (0x00/2) 867 #define ATW_SR_FORMAT_VERSION (0x02/2) 868 #define ATW_SR_MAJOR_MASK __BITS(7, 0) 869 #define ATW_SR_MINOR_MASK __BITS(15,8) 870 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 871 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 872 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 873 #define ATW_SR_CSR20 (0x16/2) 874 #define ATW_SR_ANT_MASK __BITS(12, 10) 875 #define ATW_SR_PWRSCALE_MASK __BITS(9, 8) 876 #define ATW_SR_CLKSAVE_MASK __BITS(7, 6) 877 #define ATW_SR_RFTYPE_MASK __BITS(5, 3) 878 #define ATW_SR_BBPTYPE_MASK __BITS(2, 0) 879 #define ATW_SR_CR28_CR03 (0x18/2) 880 #define ATW_SR_CR28_MASK __BITS(15,8) 881 #define ATW_SR_CR03_MASK __BITS(7, 0) 882 #define ATW_SR_CTRY_CR29 (0x1A/2) 883 #define ATW_SR_CTRY_MASK __BITS(15,8) /* country code */ 884 #define COUNTRY_FCC 0 885 #define COUNTRY_IC 1 886 #define COUNTRY_ETSI 2 887 #define COUNTRY_SPAIN 3 888 #define COUNTRY_FRANCE 4 889 #define COUNTRY_MMK 5 890 #define COUNTRY_MMK2 6 891 #define ATW_SR_CR29_MASK __BITS(7, 0) 892 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 893 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 894 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 895 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 896 #define ATW_SR_CR15 (0x28/2) 897 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 898 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 899 #define ATW_SR_CSR18 (0x2E/2) 900 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 901 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 902 #define ATW_SR_CIS_WORDS (0x52/2) 903 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 904 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 905 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 906 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 907 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 908 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 909 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 910 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 911 912 /* Tx descriptor */ 913 struct atw_txdesc { 914 volatile uint32_t at_ctl; 915 #define at_stat at_ctl 916 volatile uint32_t at_flags; 917 volatile uint32_t at_buf1; 918 volatile uint32_t at_buf2; 919 } __attribute__((__packed__, __aligned__(4))); 920 921 #define ATW_TXCTL_OWN __BIT(31) /* 1: ready to transmit */ 922 #define ATW_TXCTL_DONE __BIT(30) /* 0: not processed */ 923 #define ATW_TXCTL_TXDR_MASK __BITS(27,20) /* TX data rate (?) */ 924 #define ATW_TXCTL_TL_MASK __BITS(19,0) /* retry limit, 0 - 255 */ 925 926 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 927 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 928 #define ATW_TXSTAT_ES __BIT(29) /* 0: TX successful */ 929 #define ATW_TXSTAT_TLT __BIT(28) /* TX lifetime expired */ 930 #define ATW_TXSTAT_TRT __BIT(27) /* TX retry limit expired */ 931 #define ATW_TXSTAT_TUF __BIT(26) /* TX under-run error */ 932 #define ATW_TXSTAT_TRO __BIT(25) /* TX over-run error */ 933 #define ATW_TXSTAT_SOFBR __BIT(24) /* packet size != buffer size 934 * (?) 935 */ 936 #define ATW_TXSTAT_ARC_MASK __BITS(11,0) /* accumulated retry count */ 937 938 #define ATW_TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | \ 939 ATW_TXSTAT_TRT | ATW_TXSTAT_TRO | \ 940 ATW_TXSTAT_SOFBR) 941 #define ATW_TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO" \ 942 "\33ATW_TXSTAT_TUF\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 943 944 #define ATW_TXFLAG_IC __BIT(31) /* interrupt on completion */ 945 #define ATW_TXFLAG_LS __BIT(30) /* packet's last descriptor */ 946 #define ATW_TXFLAG_FS __BIT(29) /* packet's first descriptor */ 947 #define ATW_TXFLAG_TER __BIT(25) /* end of ring */ 948 #define ATW_TXFLAG_TCH __BIT(24) /* at_buf2 is 2nd chain */ 949 #define ATW_TXFLAG_TBS2_MASK __BITS(23,12) /* at_buf2 byte count */ 950 #define ATW_TXFLAG_TBS1_MASK __BITS(11,0) /* at_buf1 byte count */ 951 952 /* Rx descriptor */ 953 struct atw_rxdesc { 954 volatile uint32_t ar_stat; 955 volatile uint32_t ar_ctlrssi; 956 volatile uint32_t ar_buf1; 957 volatile uint32_t ar_buf2; 958 } __attribute__((__packed__, __aligned__(4))); 959 960 #define ATW_RXCTL_RER __BIT(25) /* end of ring */ 961 #define ATW_RXCTL_RCH __BIT(24) /* ar_buf2 is 2nd chain */ 962 #define ATW_RXCTL_RBS2_MASK __BITS(23,12) /* ar_buf2 byte count */ 963 #define ATW_RXCTL_RBS1_MASK __BITS(11,0) /* ar_buf1 byte count */ 964 965 #define ATW_RXSTAT_OWN __BIT(31) /* 1: NIC may fill descriptor */ 966 #define ATW_RXSTAT_ES __BIT(30) /* error summary, 0 on 967 * success 968 */ 969 #define ATW_RXSTAT_SQL __BIT(29) /* has signal quality (?) */ 970 #define ATW_RXSTAT_DE __BIT(28) /* descriptor error---packet is 971 * truncated. last descriptor 972 * only 973 */ 974 #define ATW_RXSTAT_FS __BIT(27) /* packet's first descriptor */ 975 #define ATW_RXSTAT_LS __BIT(26) /* packet's last descriptor */ 976 #define ATW_RXSTAT_PCF __BIT(25) /* received during CFP */ 977 #define ATW_RXSTAT_SFDE __BIT(24) /* PLCP SFD error */ 978 #define ATW_RXSTAT_SIGE __BIT(23) /* PLCP signal error */ 979 #define ATW_RXSTAT_CRC16E __BIT(22) /* PLCP CRC16 error */ 980 #define ATW_RXSTAT_RXTOE __BIT(21) /* RX time-out, last descriptor 981 * only. 982 */ 983 #define ATW_RXSTAT_CRC32E __BIT(20) /* CRC32 error */ 984 #define ATW_RXSTAT_ICVE __BIT(19) /* WEP ICV error */ 985 #define ATW_RXSTAT_DA1 __BIT(17) /* DA bit 1, admin'd address */ 986 #define ATW_RXSTAT_DA0 __BIT(16) /* DA bit 0, group address */ 987 #define ATW_RXSTAT_RXDR_MASK __BITS(15,12) /* RX data rate */ 988 #define ATW_RXSTAT_FL_MASK __BITS(11,0) /* RX frame length, last 989 * descriptor only 990 */ 991 992 /* Static RAM (contains WEP keys, beacon content). Addresses and size 993 * are in 16-bit words. 994 */ 995 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 996 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 997 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 998 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 999 #define ATW_SRAM_MAXSIZE (0x200 * 2) 1000 #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE 1001 #define ATW_SRAM_B_SIZE (0x1c0 * 2) 1002 1003
Indexes created Tue Sep 30 20:09:53 GMT 2025