atwreg.h revision 1.3
1 /* $NetBSD: atwreg.h,v 1.3 2003/12/07 04:22:57 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 /* Macros for bit twiddling. */ 51 52 /* nth bit, BIT(0) == 0x1. */ 53 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 54 55 /* bits m through n, m < n. */ 56 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 57 58 /* find least significant bit that is set */ 59 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 60 61 /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 62 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 63 64 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 65 66 #define MASK_TO_SHIFT4(m) \ 67 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 68 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 69 : MASK_TO_SHIFT2((m))) 70 71 #define MASK_TO_SHIFT8(m) \ 72 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 73 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 74 : MASK_TO_SHIFT4((m))) 75 76 #define MASK_TO_SHIFT16(m) \ 77 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 78 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 79 : MASK_TO_SHIFT8((m))) 80 81 #define MASK_TO_SHIFT(m) \ 82 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 83 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 84 : MASK_TO_SHIFT16((m))) 85 86 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 87 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 88 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 89 90 /* ADM8211 Host Control and Status Registers */ 91 92 #define ATW_PAR 0x00 /* PCI access */ 93 #define ATW_FRCTL 0x04 /* Frame control */ 94 #define ATW_TDR 0x08 /* Transmit demand */ 95 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 96 #define ATW_RDR 0x10 /* Receive demand */ 97 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 98 #define ATW_RDB 0x18 /* Receive descriptor base address */ 99 #define ATW_CSR3A 0x1C /* Unused */ 100 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 101 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 102 #define ATW_STSR 0x28 /* Status */ 103 #define ATW_CSR5A 0x2C /* Unused */ 104 #define ATW_NAR 0x30 /* Network access */ 105 #define ATW_CSR6A 0x34 /* Unused */ 106 #define ATW_IER 0x38 /* Interrupt enable */ 107 #define ATW_CSR7A 0x3C 108 #define ATW_LPC 0x40 /* Lost packet counter */ 109 #define ATW_TEST1 0x44 /* Test register 1 */ 110 #define ATW_SPR 0x48 /* Serial port */ 111 #define ATW_TEST0 0x4C /* Test register 0 */ 112 #define ATW_WCSR 0x50 /* Wake-up control/status */ 113 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 114 #define ATW_GPTMR 0x58 /* General purpose timer */ 115 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 116 #define ATW_BBPCTL 0x60 /* BBP control port */ 117 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 118 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 119 #define ATW_MMIWADDR 0x6C /* MMI write address */ 120 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 121 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 122 #define ATW_TXBR 0x78 /* Transmit burst counter */ 123 #define ATW_CSR15A 0x7C /* Unused */ 124 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 125 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 126 #define ATW_CMDR 0x88 /* Command */ 127 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 128 #define ATW_PMCSR 0x90 /* Power management command and status */ 129 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 130 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 131 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 132 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 133 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 134 * frame DA, byte[3:0] 135 */ 136 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 137 * ATIM frame DA byte[5:4] 138 */ 139 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 140 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 141 * Max TX MSDU lifetime, 16b 142 */ 143 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 144 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 145 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 146 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 147 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 148 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 149 * STA listen interval, 16b. 150 */ 151 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 152 #define ATW_CAP1 0xD0 /* Capability information, 16b. 153 * ATIM window, 1b. 154 */ 155 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 156 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 157 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 158 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 159 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 160 #define ATW_RSPT 0xE8 /* Response time, 24b */ 161 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 162 #define ATW_WEPCTL 0xF0 /* WEP control */ 163 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 164 #define ATW_WEPCNT 0xF8 /* WEP count */ 165 #define ATW_MACTEST 0xFC 166 167 #define ATW_FER 0x100 /* Function event */ 168 #define ATW_FEMR 0x104 /* Function event mask */ 169 #define ATW_FPSR 0x108 /* Function present state */ 170 #define ATW_FFER 0x10C /* Function force event */ 171 172 173 #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 174 * enable 175 */ 176 #define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 177 #define ATW_PAR_MRME BIT(21) /* memory read multiple 178 * enable 179 */ 180 #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 181 * receive suspended state 182 */ 183 #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 184 #define ATW_PAR_CAL_PBL 0x0 185 /* min(8 DW, PBL) */ 186 #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 187 /* min(16 DW, PBL) */ 188 #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 189 /* min(32 DW, PBL) */ 190 #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 191 #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 192 #define ATW_PAR_PBL_UNLIMITED 0x0 193 #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 194 #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 195 #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 196 #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 197 #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 198 #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 199 #define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 200 #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 201 #define ATW_PAR_BAR BIT(1) /* bus arbitration */ 202 #define ATW_PAR_SWR BIT(0) /* software reset */ 203 204 #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 205 #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 206 #define ATW_FRCTL_ORDER BIT(28) /* order bit */ 207 #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 208 #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 209 #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 210 #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 211 #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 212 213 #define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 214 #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 215 #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 216 #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 217 #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 218 #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 219 #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 220 #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 221 #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 222 #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 223 #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 224 #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 225 * passed 226 */ 227 #define ATW_INTR_NISS BIT(16) /* normal interrupt status 228 * summary: any of 31, 30, 27, 229 * 24, 14, 12, 6, 2, 0. 230 */ 231 #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 232 * summary: any of 29, 28, 26, 233 * 25, 23, 22, 13, 11, 8, 7, 5, 234 * 4, 3, 1. 235 */ 236 #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 237 * status: moved TX packet to 238 * FIFO 239 */ 240 #define ATW_INTR_FBE BIT(13) /* fatal bus error */ 241 #define ATW_INTR_REIS BIT(12) /* receive early interrupt 242 * status: RX packet filled 243 * its first descriptor 244 */ 245 #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 246 #define ATW_INTR_RPS BIT(8) /* stopped receive process */ 247 #define ATW_INTR_RDU BIT(7) /* receive descriptor 248 * unavailable 249 */ 250 #define ATW_INTR_RCI BIT(6) /* completed packet reception */ 251 #define ATW_INTR_TUF BIT(5) /* transmit underflow */ 252 #define ATW_INTR_TRT BIT(4) /* transmit retry count 253 * expired 254 */ 255 #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 256 #define ATW_INTR_TDU BIT(2) /* transmit descriptor 257 * unavailable 258 */ 259 #define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 260 #define ATW_INTR_TCI BIT(0) /* completed transmit */ 261 #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 262 #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 263 #define ATW_NAR_UTR BIT(29) /* select retry count source */ 264 #define ATW_NAR_PCF BIT(28) /* use one/both transmit 265 * descriptor base addresses 266 */ 267 #define ATW_NAR_CFP BIT(27) /* indicate more TX data to 268 * point coordinator 269 */ 270 #define ATW_NAR_SF BIT(21) /* store and forward: ignore 271 * TX threshold 272 */ 273 #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 274 #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 275 #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 276 #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 277 #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 278 #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 279 #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 280 #define ATW_NAR_ST BIT(13) /* start/stop transmit */ 281 #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 282 #define ATW_NAR_OM_NORMAL 0x0 283 #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 284 #define ATW_NAR_MM BIT(7) /* RX any multicast */ 285 #define ATW_NAR_PR BIT(6) /* promiscuous mode */ 286 #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 287 #define ATW_NAR_PB BIT(3) /* pass bad packets */ 288 #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 289 #define ATW_NAR_SR BIT(1) /* start/stop receive */ 290 #define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 291 292 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 293 #if 0 294 #define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 295 #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 296 /* normal interrupts: combine with ATW_IER_NIE */ 297 #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 298 #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 299 #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 300 #define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 301 #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 302 #define ATW_IER_TBTTIE BIT(20) /* TBTT */ 303 #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 304 #define ATW_IER_REIE BIT(12) /* RX packet filled its first 305 * descriptor 306 */ 307 #define ATW_IER_RCIE BIT(6) /* completed RX */ 308 #define ATW_IER_TDUIE BIT(2) /* transmit descriptor 309 * unavailable 310 */ 311 #define ATW_IER_TCIE BIT(0) /* completed TX */ 312 /* abnormal interrupts: combine with ATW_IER_AIE */ 313 #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 314 #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 315 #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 316 #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 317 #define ATW_IER_SQLIE BIT(23) /* signal quality */ 318 #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 319 #define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 320 #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 321 #define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 322 #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 323 #define ATW_IER_TUIE BIT(5) /* transmit underflow */ 324 #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 325 #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 326 #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 327 #endif 328 329 #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 330 #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 331 332 #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 333 #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 334 #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 335 #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 336 #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 337 338 /* TBD CSR_TEST0 */ 339 #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 340 #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 341 342 /* Stopped */ 343 #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 344 /* Running - fetch transmit descriptor */ 345 #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 346 /* Running - wait for end of transmission */ 347 #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 348 /* Running - read buffer from memory and queue into FIFO */ 349 #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 350 #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 351 #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 352 /* Suspended */ 353 #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 354 /* Running - close transmit descriptor */ 355 #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 356 357 #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 358 359 /* Stopped */ 360 #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 361 /* Running - fetch receive descriptor */ 362 #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 363 /* Running - check for end of receive */ 364 #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 365 /* Running - wait for packet */ 366 #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 367 /* Suspended */ 368 #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 369 /* Running - close receive descriptor */ 370 #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 371 /* Running - flush current frame from FIFO */ 372 #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 373 /* Running - queue current frame from FIFO into buffer */ 374 #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 375 376 #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 377 #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 378 #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 379 * 1: 93c66, 380 * 0: 93c46 381 */ 382 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 383 #define ATW_TEST0_EPTYP_93c46 0 384 #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 385 386 #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 387 #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 388 #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 389 #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 390 #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 391 #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 392 #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 393 * beacons 394 */ 395 #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 396 * range 397 */ 398 #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 399 #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 400 #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 401 #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 402 #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 403 #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 404 /* wake-up reasons correspond to enable bits */ 405 #define ATW_WCSR_KEYUP BIT(6) /* */ 406 #define ATW_WCSR_TSFTW BIT(5) /* */ 407 #define ATW_WCSR_TIMW BIT(4) /* */ 408 #define ATW_WCSR_ATIMW BIT(3) /* */ 409 #define ATW_WCSR_WFR BIT(2) /* */ 410 #define ATW_WCSR_MPR BIT(1) /* */ 411 #define ATW_WCSR_LSO BIT(0) /* */ 412 413 #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 414 #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 415 416 #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 417 #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 418 #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 419 #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 420 #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 421 #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 422 423 #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 424 #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 425 #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 426 #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 427 #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 428 #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 429 #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 430 #define ATW_BBPCTL_WR BIT(17) /* start write; reset on 431 * completion 432 */ 433 #define ATW_BBPCTL_RD BIT(16) /* start read; reset on 434 * completion 435 */ 436 #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 437 #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 438 439 #define ATW_SYNCTL_WR BIT(31) /* start write; reset on 440 * completion 441 */ 442 #define ATW_SYNCTL_RD BIT(30) /* start read; reset on 443 * completion 444 */ 445 #define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 446 #define ATW_SYNCTL_CS1 BIT(28) 447 #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 448 * Rx 449 */ 450 #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 451 * 1: MAC; needed by Intersil 452 * BBP 453 */ 454 #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 455 #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 456 457 #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 458 * only for beacon, ATIM, and 459 * RTS. 460 */ 461 #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 462 * header 463 */ 464 #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 465 466 #define ATW_MMIWADDR_INTERSIL 0x100E0C0A 467 #define ATW_MMIWADDR_RFMD 0x00009101 468 469 #define ATW_MMIRADDR1_INTERSIL 0x00007c7e 470 #define ATW_MMIRADDR1_RFMD 0x00000301 471 472 #define ATW_MMIRADDR2_INTERSIL 0x00100000 473 #define ATW_MMIRADDR2_RFMD 0x7e100000 474 475 #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 476 #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 477 #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 478 #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 479 480 #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 481 #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 482 #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 483 #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 484 * 2's complement signed integer 485 */ 486 487 #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 488 * Radio, PHYRST change after 489 * power-up, in 2ms units 490 */ 491 #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 492 * after internal data 493 * transmit end, in us 494 */ 495 #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 496 * after TXPE asserted, in us 497 */ 498 #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 499 * after internal data transmit 500 * end, in us 501 */ 502 #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 503 * after TXPE asserted, in us 504 */ 505 #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 506 * after internal data transmit 507 * end, in us 508 */ 509 #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 510 * after TXPE asserted, in us 511 */ 512 #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 513 * after internal data transmit 514 * end, in us 515 */ 516 517 #define ATW_CMDR_PM BIT(19) /* enables power mgmt 518 * capabilities. 519 */ 520 #define ATW_CMDR_APM BIT(18) /* APM mode, effective when 521 * PM = 1. 522 */ 523 #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 524 #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 525 #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 526 527 /* TBD PCIC */ 528 529 /* TBD PMCSR */ 530 531 532 #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 533 #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 534 #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 535 #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 536 537 #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 538 #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 539 540 #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 541 #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 542 #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 543 #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 544 545 #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 546 #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 547 #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 548 #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 549 550 /* ATIM destination address */ 551 #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 552 #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 553 #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 554 #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 555 556 /* ATIM destination address, BSSID */ 557 #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 558 #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 559 #define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 560 #define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 561 562 /* BSSID */ 563 #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 564 #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 565 #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 566 #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 567 568 #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 569 #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 570 571 #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 572 #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 573 #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 574 #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 575 576 #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 577 #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 578 #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 579 580 #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value */ 581 582 #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 583 * 1: ATW_SYNRF controls SYN IF pins. 584 */ 585 #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 586 * 1: ATW_SYNRF controls RF IF pins. 587 */ 588 #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 589 * LERF# pin 590 */ 591 #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 592 * LEIF# pin 593 */ 594 #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 595 * SYNCLK pin 596 */ 597 #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 598 * SYNDATA pin 599 */ 600 #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 601 * PE1 pin 602 */ 603 #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 604 * PE2 pin 605 */ 606 #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 607 * PAPE pin 608 */ 609 #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 610 * some signal used by the 611 * Intersil RF front-end? 612 * Undocumented. 613 */ 614 #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 615 * PHYRST# pin 616 */ 617 618 #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 619 #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 620 * beacon intervals 621 */ 622 623 #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 624 #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 625 626 #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 627 #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 628 629 #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 630 #define ATW_RMD_CFP BIT(30) /* CFP indicator */ 631 #define ATW_RMD_PCNT BITS(27,16) /* idle time between 632 * awake/ps mode 633 */ 634 #define ATW_RMD_RMRD BITS(15,0) /* max RX reception duration 635 * in us 636 */ 637 638 #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 639 #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 640 #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 641 * intervals 642 */ 643 #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 644 * in 1 microsecond. 645 * Depends PCI bus speed? 646 */ 647 #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 648 649 /* TBD TOFS1 */ 650 #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 651 * microseconds: RF+BBP 652 * latency 653 */ 654 #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 655 * Nth TBTT - TBTTOFS) in 656 * microseconds (huh?). To 657 * match TSFT[25:10] (huh?). 658 */ 659 #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 660 * TBTT in TU 661 */ 662 #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 663 #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 664 #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 665 #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 666 667 #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 668 #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 669 #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 670 671 #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 672 #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 673 #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 674 #define ATW_WEPCTL_WR BIT(28) /* */ 675 #define ATW_WEPCTL_RD BIT(27) /* */ 676 #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 677 #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 678 * revision 0x20. Possibly 679 * selects a different WEP 680 * table. 681 */ 682 #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 683 684 /* set these bits in the second byte of a SRAM shared key record to affect 685 * the use and interpretation of the key in the record. 686 */ 687 #define ATW_WEP_ENABLED BIT(7) 688 #define ATW_WEP_104BIT BIT(6) 689 690 #define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 691 #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 692 693 #define ATW_MACTEST_FORCE_IV BIT(23) 694 #define ATW_MACTEST_FORCE_KEYID BIT(22) 695 #define ATW_MACTEST_KEYID_MASK BITS(21,20) 696 #define ATW_MACTEST_MMI_USETXCLK BIT(11) 697 698 /* Function Event/Status registers */ 699 700 #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 701 #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 702 703 #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 704 #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 705 #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 706 707 #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 708 #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 709 #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 710 #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 711 712 /* Serial EEPROM offsets */ 713 #define ATW_SR_CLASS_CODE (0x00/2) 714 #define ATW_SR_FORMAT_VERSION (0x02/2) 715 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 716 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 717 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 718 #define ATW_SR_CSR20 (0x16/2) 719 #define ATW_SR_ANT_MASK BITS(12, 10) 720 #define ATW_SR_PWRSCALE_MASK BITS(9, 8) 721 #define ATW_SR_CLKSAVE_MASK BITS(7, 6) 722 #define ATW_SR_RFTYPE_MASK BITS(5, 3) 723 #define ATW_SR_BBPTYPE_MASK BITS(2, 0) 724 #define ATW_SR_CR28_CR03 (0x18/2) 725 #define ATW_SR_CTRY_CR29 (0x1A/2) 726 #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 727 #define COUNTRY_FCC 0 728 #define COUNTRY_IC 1 729 #define COUNTRY_ETSI 2 730 #define COUNTRY_SPAIN 3 731 #define COUNTRY_FRANCE 4 732 #define COUNTRY_MMK 5 733 #define COUNTRY_MMK2 6 734 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 735 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 736 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 737 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 738 #define ATW_SR_CR15 (0x28/2) 739 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 740 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 741 #define ATW_SR_CSR18 (0x2E/2) 742 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 743 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 744 #define ATW_SR_CIS_WORDS (0x52/2) 745 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 746 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 747 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 748 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 749 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 750 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 751 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 752 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 753 754 /* Tx descriptor */ 755 struct atw_txdesc { 756 u_int32_t at_ctl; 757 #define at_stat at_ctl 758 u_int32_t at_flags; 759 u_int32_t at_buf1; 760 u_int32_t at_buf2; 761 }; 762 763 #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 764 #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 765 #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 766 #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 767 768 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 769 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 770 #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 771 #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 772 #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 773 #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 774 #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 775 #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 776 * (?) 777 */ 778 #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 779 780 #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 781 #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 782 #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 783 #define ATW_TXFLAG_TER BIT(25) /* end of ring */ 784 #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 785 #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 786 #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 787 788 /* Rx descriptor */ 789 struct atw_rxdesc { 790 u_int32_t ar_stat; 791 u_int32_t ar_ctl; 792 u_int32_t ar_buf1; 793 u_int32_t ar_buf2; 794 }; 795 796 #define ar_rssi ar_ctl 797 798 #define ATW_RXCTL_RER BIT(25) /* end of ring */ 799 #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 800 #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 801 #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 802 803 #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 804 #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 805 * success 806 */ 807 #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 808 #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 809 * truncated. last descriptor 810 * only 811 */ 812 #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 813 #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 814 #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 815 #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 816 #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 817 #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 818 #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 819 * only. 820 */ 821 #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 822 #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 823 #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 824 #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 825 #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 826 #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 827 * descriptor only 828 */ 829 830 /* Static RAM (contains WEP keys, beacon content). Addresses and size 831 * are in 16-bit words. 832 */ 833 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 834 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 835 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 836 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 837 #define ATW_SRAM_SIZE (0x200 * 2) 838 839 /* 840 * Registers for Silicon Laboratories Si4126/Si4126 RF synthesizer. 841 */ 842 #define SI4126_MAIN 0 /* main configuration */ 843 #define SI4126_MAIN_AUXSEL_MASK BITS(13, 12) 844 #define SI4126_MAIN_IFDIV_MASK BITS(11, 10) 845 #define SI4126_MAIN_XINDIV2 BIT(6) 846 #define SI4126_MAIN_LPWR BIT(5) 847 #define SI4126_MAIN_AUTOPDB BIT(3) 848 #define SI4126_GAIN 1 /* phase detector gain */ 849 #define SI4126_GAIN_KPI_MASK BITS(5, 4) 850 #define SI4126_GAIN_KP2_MASK BITS(3, 2) 851 #define SI4126_GAIN_KP1_MASK BITS(1, 0) 852 #define SI4126_POWER 2 /* powerdown */ 853 #define SI4126_POWER_PDIB BIT(1) 854 #define SI4126_POWER_PDRB BIT(0) 855 #define SI4126_RF1N 3 /* RF1 N divider */ 856 #define SI4126_RF2N 4 /* RF2 N divider */ 857 #define SI4126_IFN 5 /* IF N divider */ 858 #define SI4126_RF1R 6 /* RF1 R divider */ 859 #define SI4126_RF2R 7 /* RF2 R divider */ 860 #define SI4126_IFR 8 /* IF R divider */ 861 862 /* 863 * Registers for RF Microdevices RF3000 spread-spectrum baseband modem. 864 */ 865 #define RF3000_CTL 0x01 /* modem control */ 866 #define RF3000_RXSTAT RF3000_CTL /* RX status */ 867 #define RF3000_CTL_MODE_MASK BITS(7, 4) 868 #define RF3000_RXSTAT_ACQ BIT(2) 869 #define RF3000_RXSTAT_SFD BIT(1) 870 #define RF3000_RXSTAT_CRC BIT(0) 871 #define RF3000_CCACTL 0x02 /* CCA control */ 872 /* CCA mode */ 873 #define RF3000_CCACTL_MODE_MASK BITS(7, 6) 874 #define RF3000_CCACTL_MODE_RSSIT 0 /* RSSI threshold */ 875 #define RF3000_CCACTL_MODE_ACQ 1 /* acquisition */ 876 #define RF3000_CCACTL_MODE_BOTH 2 /* threshold or acq. */ 877 /* RSSI threshold for CCA */ 878 #define RF3000_CCACTL_RSSIT_MASK BITS(5, 0) 879 #define RF3000_DIVCTL 0x03 /* diversity control */ 880 #define RF3000_DIVCTL_ENABLE BIT(7) /* enable diversity */ 881 #define RF3000_DIVCTL_ANTSEL BIT(6) /* if ENABLE = 0, set 882 * ANT SEL 883 */ 884 #define RF3000_RSSI RF3000_DIVCTL /* RSSI value */ 885 #define RF3000_RSSI_MASK BITS(5, 0) 886 #define RF3000_GAINCTL 0x11 /* TX variable gain control */ 887 #define RF3000_GAINCTL_TXVGC_MASK BITS(7, 2) 888 #define RF3000_GAINCTL_SCRAMBLER BIT(1) 889 #define RF3000_LOGAINCAL 0x14 /* low gain calibration */ 890 #define RF3000_LOGAINCAL_CAL_MASK BITS(5, 0) 891 #define RF3000_HIGAINCAL 0x15 /* high gain calibration */ 892 #define RF3000_HIGAINCAL_CAL_MASK BITS(5, 0) 893 #define RF3000_HIGAINCAL_DSSSPAD BIT(6) /* 6dB gain pad for DSSS 894 * modes (meaning?) 895 */ 896 #define RF3000_MAGIC0 0x1C /* magic register derived from 897 * a binary-only driver 898 */ 899 #define RF3000_MAGIC0_VAL 0x00 900 #define RF3000_MAGIC1 0x1D /* magic register derived from 901 * a binary-only driver 902 */ 903 #define RF3000_MAGIC1_VAL 0x80 904 905
Indexes created Mon Sep 29 21:09:56 GMT 2025