atwreg.h revision 1.9
1 /* $NetBSD: atwreg.h,v 1.9 2004/07/15 05:46:31 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 /* Macros for bit twiddling. */ 51 52 #ifndef _BIT_TWIDDLE 53 #define _BIT_TWIDDLE 54 /* nth bit, BIT(0) == 0x1. */ 55 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 56 57 /* bits m through n, m < n. */ 58 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 59 60 /* find least significant bit that is set */ 61 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 62 63 /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 64 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 65 66 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 67 68 #define MASK_TO_SHIFT4(m) \ 69 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 70 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 71 : MASK_TO_SHIFT2((m))) 72 73 #define MASK_TO_SHIFT8(m) \ 74 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 75 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 76 : MASK_TO_SHIFT4((m))) 77 78 #define MASK_TO_SHIFT16(m) \ 79 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 80 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 81 : MASK_TO_SHIFT8((m))) 82 83 #define MASK_TO_SHIFT(m) \ 84 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 85 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 86 : MASK_TO_SHIFT16((m))) 87 88 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 89 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 90 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 91 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 92 93 #endif /* _BIT_TWIDDLE */ 94 95 /* ADM8211 Host Control and Status Registers */ 96 97 #define ATW_PAR 0x00 /* PCI access */ 98 #define ATW_FRCTL 0x04 /* Frame control */ 99 #define ATW_TDR 0x08 /* Transmit demand */ 100 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 101 #define ATW_RDR 0x10 /* Receive demand */ 102 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 103 #define ATW_RDB 0x18 /* Receive descriptor base address */ 104 #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 105 #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 106 * high-priority packet 107 */ 108 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 109 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 110 #define ATW_STSR 0x28 /* Status */ 111 #define ATW_CSR5A 0x2C /* Unused */ 112 #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 113 * broadcast/multicast packet 114 */ 115 #define ATW_NAR 0x30 /* Network access */ 116 #define ATW_CSR6A 0x34 /* Unused */ 117 #define ATW_IER 0x38 /* Interrupt enable */ 118 #define ATW_CSR7A 0x3C 119 #define ATW_LPC 0x40 /* Lost packet counter */ 120 #define ATW_TEST1 0x44 /* Test register 1 */ 121 #define ATW_SPR 0x48 /* Serial port */ 122 #define ATW_TEST0 0x4C /* Test register 0 */ 123 #define ATW_WCSR 0x50 /* Wake-up control/status */ 124 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 125 #define ATW_GPTMR 0x58 /* General purpose timer */ 126 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 127 #define ATW_BBPCTL 0x60 /* BBP control port */ 128 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 129 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 130 #define ATW_MMIWADDR 0x6C /* MMI write address */ 131 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 132 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 133 #define ATW_TXBR 0x78 /* Transmit burst counter */ 134 #define ATW_CSR15A 0x7C /* Unused */ 135 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 136 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 137 #define ATW_CMDR 0x88 /* Command */ 138 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 139 #define ATW_PMCSR 0x90 /* Power management command and status */ 140 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 141 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 142 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 143 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 144 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 145 * frame DA, byte[3:0] 146 */ 147 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 148 * ATIM frame DA byte[5:4] 149 */ 150 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 151 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 152 * Max TX MSDU lifetime, 16b 153 */ 154 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 155 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 156 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 157 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 158 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 159 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 160 * STA listen interval, 16b. 161 */ 162 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 163 #define ATW_CAP1 0xD0 /* Capability information, 16b. 164 * ATIM window, 1b. 165 */ 166 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 167 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 168 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 169 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 170 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 171 #define ATW_RSPT 0xE8 /* Response time, 24b */ 172 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 173 #define ATW_WEPCTL 0xF0 /* WEP control */ 174 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 175 #define ATW_WEPCNT 0xF8 /* WEP count */ 176 #define ATW_MACTEST 0xFC 177 178 #define ATW_FER 0x100 /* Function event */ 179 #define ATW_FEMR 0x104 /* Function event mask */ 180 #define ATW_FPSR 0x108 /* Function present state */ 181 #define ATW_FFER 0x10C /* Function force event */ 182 183 184 #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 185 * enable 186 */ 187 #define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 188 #define ATW_PAR_MRME BIT(21) /* memory read multiple 189 * enable 190 */ 191 #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 192 * receive suspended state 193 */ 194 #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 195 #define ATW_PAR_CAL_PBL 0x0 196 /* min(8 DW, PBL) */ 197 #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 198 /* min(16 DW, PBL) */ 199 #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 200 /* min(32 DW, PBL) */ 201 #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 202 #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 203 #define ATW_PAR_PBL_UNLIMITED 0x0 204 #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 205 #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 206 #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 207 #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 208 #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 209 #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 210 #define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 211 #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 212 #define ATW_PAR_BAR BIT(1) /* bus arbitration */ 213 #define ATW_PAR_SWR BIT(0) /* software reset */ 214 215 #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 216 #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 217 #define ATW_FRCTL_ORDER BIT(28) /* order bit */ 218 #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 219 #define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe 220 * response 221 * 0: ASIC sends prresp 222 */ 223 #define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons 224 * 0: ASIC sends beacons 225 */ 226 #define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED 227 * 0: ASIC controls link LED 228 */ 229 #define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED 230 * 0: turn off link LED 231 */ 232 #define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28 233 * 1: random 234 */ 235 #define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved" 236 * frames, 0: ignore 237 * reserved frames 238 */ 239 #define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END, 240 * ADM8211C/CR clears 241 */ 242 #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 243 #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 244 #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 245 #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 246 247 #define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 248 #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 249 #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 250 #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 251 #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 252 #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 253 #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 254 #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 255 #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 256 #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 257 #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 258 #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 259 * passed 260 */ 261 #define ATW_INTR_NISS BIT(16) /* normal interrupt status 262 * summary: any of 31, 30, 27, 263 * 24, 14, 12, 6, 2, 0. 264 */ 265 #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 266 * summary: any of 29, 28, 26, 267 * 25, 23, 22, 13, 11, 8, 7, 5, 268 * 4, 3, 1. 269 */ 270 #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 271 * status: moved TX packet to 272 * FIFO 273 */ 274 #define ATW_INTR_FBE BIT(13) /* fatal bus error */ 275 #define ATW_INTR_REIS BIT(12) /* receive early interrupt 276 * status: RX packet filled 277 * its first descriptor 278 */ 279 #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 280 #define ATW_INTR_RPS BIT(8) /* stopped receive process */ 281 #define ATW_INTR_RDU BIT(7) /* receive descriptor 282 * unavailable 283 */ 284 #define ATW_INTR_RCI BIT(6) /* completed packet reception */ 285 #define ATW_INTR_TUF BIT(5) /* transmit underflow */ 286 #define ATW_INTR_TRT BIT(4) /* transmit retry count 287 * expired 288 */ 289 #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 290 #define ATW_INTR_TDU BIT(2) /* transmit descriptor 291 * unavailable 292 */ 293 #define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 294 #define ATW_INTR_TCI BIT(0) /* completed transmit */ 295 #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 296 #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 297 #define ATW_NAR_UTR BIT(29) /* select retry count source */ 298 #define ATW_NAR_PCF BIT(28) /* use one/both transmit 299 * descriptor base addresses 300 */ 301 #define ATW_NAR_CFP BIT(27) /* indicate more TX data to 302 * point coordinator 303 */ 304 #define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode 305 * 1: AP mode 306 */ 307 #define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB 308 * 1: enable TDBB 309 */ 310 #define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH 311 * 1: enable TDBH 312 */ 313 #define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC 314 * poll TDBH once; ASIC clears 315 */ 316 #define ATW_NAR_SF BIT(21) /* store and forward: ignore 317 * TX threshold 318 */ 319 #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 320 #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 321 #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 322 #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 323 #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 324 #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 325 #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 326 #define ATW_NAR_ST BIT(13) /* start/stop transmit */ 327 #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 328 #define ATW_NAR_OM_NORMAL 0x0 329 #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 330 #define ATW_NAR_MM BIT(7) /* RX any multicast */ 331 #define ATW_NAR_PR BIT(6) /* promiscuous mode */ 332 #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 333 #define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported 334 * 0: PCF supported 335 */ 336 #define ATW_NAR_PB BIT(3) /* pass bad packets */ 337 #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 338 #define ATW_NAR_SR BIT(1) /* start/stop receive */ 339 #define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 340 341 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 342 #if 0 343 #define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 344 #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 345 /* normal interrupts: combine with ATW_IER_NIE */ 346 #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 347 #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 348 #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 349 #define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 350 #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 351 #define ATW_IER_TBTTIE BIT(20) /* TBTT */ 352 #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 353 #define ATW_IER_REIE BIT(12) /* RX packet filled its first 354 * descriptor 355 */ 356 #define ATW_IER_RCIE BIT(6) /* completed RX */ 357 #define ATW_IER_TDUIE BIT(2) /* transmit descriptor 358 * unavailable 359 */ 360 #define ATW_IER_TCIE BIT(0) /* completed TX */ 361 /* abnormal interrupts: combine with ATW_IER_AIE */ 362 #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 363 #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 364 #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 365 #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 366 #define ATW_IER_SQLIE BIT(23) /* signal quality */ 367 #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 368 #define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 369 #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 370 #define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 371 #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 372 #define ATW_IER_TUIE BIT(5) /* transmit underflow */ 373 #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 374 #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 375 #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 376 #endif 377 378 #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 379 #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 380 381 #define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control, 382 * 1: read from dxfer_state" 383 */ 384 #define ATW_TEST1_DBGREAD_MASK BITS(30,28) /* "control of read data, 385 * debug only" 386 */ 387 #define ATW_TEST1_TXWP_MASK BITS(27,25) /* select ATW_WTDP content? */ 388 #define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK) 389 #define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK) 390 #define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK) 391 #define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK) 392 #define ATW_TEST1_RSVD0_MASK BITS(24,6) /* reserved */ 393 #define ATW_TEST1_TESTMODE_MASK BITS(5,4) 394 #define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ) /* normal operation */ 395 #define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ) /* MAC-only mode */ 396 #define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ) /* normal operation */ 397 #define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ) /* monitor mode */ 398 399 #define ATW_TEST1_DUMP_MASK BITS(3,0) /* select dump signal 400 * from dxfer (huh?) 401 */ 402 403 #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 404 #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 405 #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 406 #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 407 #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 408 409 #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 410 #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 411 412 /* Stopped */ 413 #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 414 /* Running - fetch transmit descriptor */ 415 #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 416 /* Running - wait for end of transmission */ 417 #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 418 /* Running - read buffer from memory and queue into FIFO */ 419 #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 420 #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 421 #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 422 /* Suspended */ 423 #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 424 /* Running - close transmit descriptor */ 425 #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 426 427 /* ADM8211C/CR registers */ 428 /* Suspended */ 429 #define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK) 430 /* Descriptor write */ 431 #define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK) 432 /* Last descriptor write */ 433 #define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK) 434 /* FIFO full */ 435 #define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK) 436 437 #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 438 439 /* Stopped */ 440 #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 441 /* Running - fetch receive descriptor */ 442 #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 443 /* Running - check for end of receive */ 444 #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 445 /* Running - wait for packet */ 446 #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 447 /* Suspended */ 448 #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 449 /* Running - close receive descriptor */ 450 #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 451 /* Running - flush current frame from FIFO */ 452 #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 453 /* Running - queue current frame from FIFO into buffer */ 454 #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 455 456 #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 457 #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 458 #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 459 * 1: 93c66, 460 * 0: 93c46 461 */ 462 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 463 #define ATW_TEST0_EPTYP_93c46 0 464 #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 465 466 #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 467 #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 468 #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 469 #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 470 #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 471 #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 472 #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 473 * beacons 474 */ 475 #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 476 * range 477 */ 478 #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 479 #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 480 #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 481 #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 482 #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 483 #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 484 /* wake-up reasons correspond to enable bits */ 485 #define ATW_WCSR_KEYUP BIT(6) /* */ 486 #define ATW_WCSR_TSFTW BIT(5) /* */ 487 #define ATW_WCSR_TIMW BIT(4) /* */ 488 #define ATW_WCSR_ATIMW BIT(3) /* */ 489 #define ATW_WCSR_WFR BIT(2) /* */ 490 #define ATW_WCSR_MPR BIT(1) /* */ 491 #define ATW_WCSR_LSO BIT(0) /* */ 492 493 #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 494 #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 495 496 #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 497 #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 498 #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 499 #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 500 #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 501 #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 502 503 #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 504 #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 505 #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 506 #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 507 #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 508 #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 509 #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 510 #define ATW_BBPCTL_WR BIT(17) /* start write; reset on 511 * completion 512 */ 513 #define ATW_BBPCTL_RD BIT(16) /* start read; reset on 514 * completion 515 */ 516 #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 517 #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 518 519 #define ATW_SYNCTL_WR BIT(31) /* start write; reset on 520 * completion 521 */ 522 #define ATW_SYNCTL_RD BIT(30) /* start read; reset on 523 * completion 524 */ 525 #define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 526 #define ATW_SYNCTL_CS1 BIT(28) 527 #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 528 * Rx 529 */ 530 #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 531 * 1: MAC; needed by Intersil 532 * BBP 533 */ 534 #define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this 535 * bit. 0: latch data on 536 * negative edge, 1: positive 537 * edge. 538 */ 539 #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 540 #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 541 542 #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 543 * only for beacon, ATIM, and 544 * RTS. 545 */ 546 #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 547 * header; with RFMD BBP, 548 * sets Tx power for beacon, 549 * RTS, ATIM. 550 */ 551 #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 552 553 #define ATW_MMIWADDR_INTERSIL 0x100E0C0A 554 #define ATW_MMIWADDR_RFMD 0x00009101 555 556 #define ATW_MMIRADDR1_INTERSIL 0x00007c7e 557 #define ATW_MMIRADDR1_RFMD 0x00000301 558 559 #define ATW_MMIRADDR2_INTERSIL 0x00100000 560 #define ATW_MMIRADDR2_RFMD 0x7e100000 561 562 #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 563 #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 564 #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 565 #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 566 567 #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 568 #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 569 #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 570 #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 571 * 2's complement signed integer 572 */ 573 574 #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 575 * Radio, PHYRST change after 576 * power-up, in 2ms units 577 */ 578 #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 579 * after internal data 580 * transmit end, in us 581 */ 582 #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 583 * after TXPE asserted, in us 584 */ 585 #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 586 * after internal data transmit 587 * end, in us 588 */ 589 #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 590 * after TXPE asserted, in us 591 */ 592 #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 593 * after internal data transmit 594 * end, in us 595 */ 596 #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 597 * after TXPE asserted, in us 598 */ 599 #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 600 * after internal data transmit 601 * end, in us 602 */ 603 604 #define ATW_CMDR_PM BIT(19) /* enables power mgmt 605 * capabilities. 606 */ 607 #define ATW_CMDR_APM BIT(18) /* APM mode, effective when 608 * PM = 1. 609 */ 610 #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 611 #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 612 /* 32 bytes */ 613 #define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK) 614 /* 64 bytes */ 615 #define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK) 616 /* Store & Forward */ 617 #define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK) 618 /* Reserved */ 619 #define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK) 620 #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 621 622 /* TBD PCIC */ 623 624 /* TBD PMCSR */ 625 626 627 #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 628 #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 629 #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 630 #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 631 632 #define ATW_C_PAR1_CTD BITS(16,31) /* Continuous Tx pattern */ 633 #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 634 #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 635 636 #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 637 #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 638 #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 639 #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 640 641 #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 642 #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 643 #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 644 #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 645 646 /* ATIM destination address */ 647 #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 648 #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 649 #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 650 #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 651 652 /* ATIM destination address, BSSID */ 653 #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 654 #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 655 #define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 656 #define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 657 658 /* BSSID */ 659 #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 660 #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 661 #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 662 #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 663 664 #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 665 #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 666 667 #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 668 #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 669 #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 670 #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 671 672 #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 673 #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 674 #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 675 676 /* For ADM8211C/CR */ 677 /* ATW_C_TSC_TIMTABSEL = 1 */ 678 #define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */ 679 #define ATW_C_BCNT_BEANLEN1 BITS(30,16) /* beacon length in us */ 680 /* ATW_C_TSC_TIMTABSEL = 0 */ 681 #define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */ 682 #define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */ 683 684 #define ATW_C_TSC_TIMOFS BITS(31,24) /* I think this is the 685 * SRAM offset for the TIM 686 */ 687 #define ATW_C_TSC_TIMLEN BITS(21,12) /* length of TIM */ 688 #define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */ 689 #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value, 0 690 * disables 691 */ 692 693 #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 694 * 1: ATW_SYNRF controls SYN IF pins. 695 */ 696 #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 697 * 1: ATW_SYNRF controls RF IF pins. 698 */ 699 #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 700 * LERF# pin 701 */ 702 #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 703 * LEIF# pin 704 */ 705 #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 706 * SYNCLK pin 707 */ 708 #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 709 * SYNDATA pin 710 */ 711 #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 712 * PE1 pin 713 */ 714 #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 715 * PE2 pin 716 */ 717 #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 718 * PAPE pin 719 */ 720 #define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of 721 * TRSW pin 722 */ 723 #define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of 724 * TRSWn pin 725 */ 726 #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 727 * some signal used by the 728 * Intersil RF front-end? 729 * Undocumented. 730 */ 731 #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 732 * PHYRST# pin 733 */ 734 /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 735 #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 736 737 #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 738 #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 739 * beacon intervals 740 */ 741 742 #define ATW_C_CAP0_TIMLEN1 BITS(31,24) /* TIM table 1 len in bytes 743 * including TIM ID (XXX huh?) 744 */ 745 #define ATW_C_CAP0_TIMLEN0 BITS(23,16) /* TIM table 0 len in bytes, 746 * including TIM ID (XXX huh?) 747 */ 748 #define ATW_C_CAP0_CWMAX BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? 749 * 5 < CWMAX <= 9 sets max? 750 * 10? 751 * default 0 752 */ 753 #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 754 #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 755 756 #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 757 #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 758 759 #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 760 #define ATW_RMD_CFP BIT(30) /* CFP indicator */ 761 #define ATW_RMD_PCNT BITS(27,16) /* idle time between 762 * awake/ps mode, in seconds 763 */ 764 #define ATW_RMD_RMRD_MASK BITS(15,0) /* max RX reception duration 765 * in us 766 */ 767 768 #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 769 #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 770 #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 771 * intervals 772 */ 773 #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 774 * in 1 microsecond. 775 * Depends PCI bus speed? 776 */ 777 #define ATW_C_TOFS0_TUCNT_MASK BITS(14,10) /* PIFS (microseconds) */ 778 #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 779 780 /* TBD TOFS1 */ 781 #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 782 * microseconds: RF+BBP 783 * latency 784 */ 785 #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 786 * Nth TBTT - TBTTOFS) in 787 * microseconds (huh?). To 788 * match TSFT[25:10] (huh?). 789 */ 790 #define ATW_TBTTPRE_MASK BITS(25, 10) 791 #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 792 * TBTT in TU 793 */ 794 #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 795 #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 796 #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 797 #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 798 799 #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 800 #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 801 #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 802 803 #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 804 #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 805 #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 806 #define ATW_WEPCTL_WR BIT(28) /* */ 807 #define ATW_WEPCTL_RD BIT(27) /* */ 808 #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 809 #define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl 810 * lookup fails, 0: use 811 * shared-key 812 */ 813 #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 814 * revision 0x20. Possibly 815 * selects a different WEP 816 * table. 817 */ 818 #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 819 820 /* set these bits in the second byte of a SRAM shared key record to affect 821 * the use and interpretation of the key in the record. 822 */ 823 #define ATW_WEP_ENABLED BIT(7) 824 #define ATW_WEP_104BIT BIT(6) 825 826 #define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 827 #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 828 829 #define ATW_MACTEST_FORCE_IV BIT(23) 830 #define ATW_MACTEST_FORCE_KEYID BIT(22) 831 #define ATW_MACTEST_KEYID_MASK BITS(21,20) 832 #define ATW_MACTEST_MMI_USETXCLK BIT(11) 833 834 /* Function Event/Status registers */ 835 836 #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 837 #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 838 839 #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 840 #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 841 #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 842 843 #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 844 #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 845 #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 846 #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 847 848 /* Serial EEPROM offsets */ 849 #define ATW_SR_CLASS_CODE (0x00/2) 850 #define ATW_SR_FORMAT_VERSION (0x02/2) 851 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 852 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 853 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 854 #define ATW_SR_CSR20 (0x16/2) 855 #define ATW_SR_ANT_MASK BITS(12, 10) 856 #define ATW_SR_PWRSCALE_MASK BITS(9, 8) 857 #define ATW_SR_CLKSAVE_MASK BITS(7, 6) 858 #define ATW_SR_RFTYPE_MASK BITS(5, 3) 859 #define ATW_SR_BBPTYPE_MASK BITS(2, 0) 860 #define ATW_SR_CR28_CR03 (0x18/2) 861 #define ATW_SR_CTRY_CR29 (0x1A/2) 862 #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 863 #define COUNTRY_FCC 0 864 #define COUNTRY_IC 1 865 #define COUNTRY_ETSI 2 866 #define COUNTRY_SPAIN 3 867 #define COUNTRY_FRANCE 4 868 #define COUNTRY_MMK 5 869 #define COUNTRY_MMK2 6 870 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 871 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 872 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 873 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 874 #define ATW_SR_CR15 (0x28/2) 875 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 876 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 877 #define ATW_SR_CSR18 (0x2E/2) 878 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 879 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 880 #define ATW_SR_CIS_WORDS (0x52/2) 881 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 882 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 883 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 884 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 885 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 886 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 887 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 888 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 889 890 /* Tx descriptor */ 891 struct atw_txdesc { 892 u_int32_t at_ctl; 893 #define at_stat at_ctl 894 u_int32_t at_flags; 895 u_int32_t at_buf1; 896 u_int32_t at_buf2; 897 }; 898 899 #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 900 #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 901 #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 902 #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 903 904 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 905 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 906 #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 907 #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 908 #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 909 #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 910 #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 911 #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 912 * (?) 913 */ 914 #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 915 916 #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 917 #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 918 #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 919 #define ATW_TXFLAG_TER BIT(25) /* end of ring */ 920 #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 921 #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 922 #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 923 924 /* Rx descriptor */ 925 struct atw_rxdesc { 926 u_int32_t ar_stat; 927 u_int32_t ar_ctl; 928 u_int32_t ar_buf1; 929 u_int32_t ar_buf2; 930 }; 931 932 #define ar_rssi ar_ctl 933 934 #define ATW_RXCTL_RER BIT(25) /* end of ring */ 935 #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 936 #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 937 #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 938 939 #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 940 #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 941 * success 942 */ 943 #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 944 #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 945 * truncated. last descriptor 946 * only 947 */ 948 #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 949 #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 950 #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 951 #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 952 #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 953 #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 954 #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 955 * only. 956 */ 957 #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 958 #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 959 #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 960 #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 961 #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 962 #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 963 * descriptor only 964 */ 965 966 /* Static RAM (contains WEP keys, beacon content). Addresses and size 967 * are in 16-bit words. 968 */ 969 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 970 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 971 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 972 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 973 #define ATW_SRAM_SIZE (0x200 * 2) 974 975
Indexes created Mon Sep 29 21:09:56 GMT 2025