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atwvar.h revision 1.28.4.1
      1  1.28.4.1      yamt /*	$NetBSD: atwvar.h,v 1.28.4.1 2008/05/16 02:24:02 yamt Exp $	*/
      2       1.1    dyoung 
      3       1.1    dyoung /*
      4       1.1    dyoung  * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc.  All rights reserved.
      5       1.1    dyoung  *
      6       1.1    dyoung  * This code is derived from software contributed to The NetBSD Foundation
      7       1.1    dyoung  * by David Young.
      8       1.1    dyoung  *
      9       1.1    dyoung  * Redistribution and use in source and binary forms, with or without
     10       1.1    dyoung  * modification, are permitted provided that the following conditions
     11       1.1    dyoung  * are met:
     12       1.1    dyoung  * 1. Redistributions of source code must retain the above copyright
     13       1.1    dyoung  *    notice, this list of conditions and the following disclaimer.
     14       1.1    dyoung  * 2. Redistributions in binary form must reproduce the above copyright
     15       1.1    dyoung  *    notice, this list of conditions and the following disclaimer in the
     16       1.1    dyoung  *    documentation and/or other materials provided with the distribution.
     17       1.1    dyoung  *
     18  1.28.4.1      yamt  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  1.28.4.1      yamt  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  1.28.4.1      yamt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  1.28.4.1      yamt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22       1.1    dyoung  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23       1.1    dyoung  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24       1.1    dyoung  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25       1.1    dyoung  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26       1.1    dyoung  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  1.28.4.1      yamt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  1.28.4.1      yamt  * POSSIBILITY OF SUCH DAMAGE.
     29       1.1    dyoung  */
     30       1.1    dyoung 
     31       1.1    dyoung #ifndef _DEV_IC_ATWVAR_H_
     32       1.1    dyoung #define	_DEV_IC_ATWVAR_H_
     33       1.1    dyoung 
     34       1.1    dyoung #include <sys/queue.h>
     35       1.1    dyoung #include <sys/callout.h>
     36       1.1    dyoung #include <sys/time.h>
     37       1.1    dyoung 
     38       1.1    dyoung /*
     39       1.1    dyoung  * Some misc. statics, useful for debugging.
     40       1.1    dyoung  */
     41       1.1    dyoung struct atw_stats {
     42       1.1    dyoung 	u_long		ts_tx_tuf;	/* transmit underflow errors */
     43       1.1    dyoung 	u_long		ts_tx_tro;	/* transmit jabber timeouts */
     44       1.1    dyoung 	u_long		ts_tx_trt;	/* retry count exceeded */
     45       1.1    dyoung 	u_long		ts_tx_tlt;	/* lifetime exceeded */
     46       1.1    dyoung 	u_long		ts_tx_sofbr;	/* packet size mismatch */
     47       1.1    dyoung };
     48       1.1    dyoung 
     49       1.1    dyoung /*
     50       1.1    dyoung  * Transmit descriptor list size.  This is arbitrary, but allocate
     51       1.1    dyoung  * enough descriptors for 64 pending transmissions and 16 segments
     52       1.1    dyoung  * per packet.  Since a descriptor holds 2 buffer addresses, that's
     53       1.1    dyoung  * 8 descriptors per packet.  This MUST work out to a power of 2.
     54       1.1    dyoung  */
     55       1.1    dyoung #define	ATW_NTXSEGS		16
     56       1.1    dyoung 
     57       1.1    dyoung #define	ATW_TXQUEUELEN	64
     58       1.1    dyoung #define	ATW_NTXDESC		(ATW_TXQUEUELEN * ATW_NTXSEGS)
     59       1.1    dyoung #define	ATW_NTXDESC_MASK	(ATW_NTXDESC - 1)
     60       1.1    dyoung #define	ATW_NEXTTX(x)		((x + 1) & ATW_NTXDESC_MASK)
     61       1.1    dyoung 
     62       1.1    dyoung /*
     63       1.1    dyoung  * Receive descriptor list size.  We have one Rx buffer per incoming
     64       1.1    dyoung  * packet, so this logic is a little simpler.
     65       1.1    dyoung  */
     66       1.1    dyoung #define	ATW_NRXDESC		64
     67       1.1    dyoung #define	ATW_NRXDESC_MASK	(ATW_NRXDESC - 1)
     68       1.1    dyoung #define	ATW_NEXTRX(x)		((x + 1) & ATW_NRXDESC_MASK)
     69       1.1    dyoung 
     70       1.1    dyoung /*
     71       1.1    dyoung  * Control structures are DMA'd to the ADM8211 chip.  We allocate them in
     72       1.1    dyoung  * a single clump that maps to a single DMA segment to make several things
     73       1.1    dyoung  * easier.
     74       1.1    dyoung  */
     75       1.1    dyoung struct atw_control_data {
     76       1.1    dyoung 	/*
     77       1.1    dyoung 	 * The transmit descriptors.
     78       1.1    dyoung 	 */
     79       1.1    dyoung 	struct atw_txdesc acd_txdescs[ATW_NTXDESC];
     80       1.1    dyoung 
     81       1.1    dyoung 	/*
     82       1.1    dyoung 	 * The receive descriptors.
     83       1.1    dyoung 	 */
     84       1.1    dyoung 	struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
     85       1.1    dyoung };
     86       1.1    dyoung 
     87       1.1    dyoung #define	ATW_CDOFF(x)		offsetof(struct atw_control_data, x)
     88       1.1    dyoung #define	ATW_CDTXOFF(x)	ATW_CDOFF(acd_txdescs[(x)])
     89       1.1    dyoung #define	ATW_CDRXOFF(x)	ATW_CDOFF(acd_rxdescs[(x)])
     90       1.1    dyoung /*
     91       1.1    dyoung  * Software state for transmit jobs.
     92       1.1    dyoung  */
     93       1.1    dyoung struct atw_txsoft {
     94       1.1    dyoung 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
     95       1.1    dyoung 	bus_dmamap_t txs_dmamap;	/* our DMA map */
     96       1.1    dyoung 	int txs_firstdesc;		/* first descriptor in packet */
     97       1.1    dyoung 	int txs_lastdesc;		/* last descriptor in packet */
     98       1.1    dyoung 	int txs_ndescs;			/* number of descriptors */
     99      1.18    dyoung 	struct ieee80211_duration	txs_d0;
    100      1.18    dyoung 	struct ieee80211_duration	txs_dn;
    101       1.1    dyoung 	SIMPLEQ_ENTRY(atw_txsoft) txs_q;
    102       1.1    dyoung };
    103       1.1    dyoung 
    104       1.1    dyoung SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
    105       1.1    dyoung 
    106       1.1    dyoung /*
    107       1.1    dyoung  * Software state for receive jobs.
    108       1.1    dyoung  */
    109       1.1    dyoung struct atw_rxsoft {
    110       1.1    dyoung 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    111       1.1    dyoung 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    112       1.1    dyoung };
    113       1.1    dyoung 
    114       1.1    dyoung /*
    115       1.1    dyoung  * Table which describes the transmit threshold mode.  We generally
    116       1.1    dyoung  * start at index 0.  Whenever we get a transmit underrun, we increment
    117       1.1    dyoung  * our index, falling back if we encounter the NULL terminator.
    118       1.1    dyoung  */
    119       1.1    dyoung struct atw_txthresh_tab {
    120       1.1    dyoung 	u_int32_t txth_opmode;		/* OPMODE bits */
    121       1.1    dyoung 	const char *txth_name;		/* name of mode */
    122       1.1    dyoung };
    123       1.1    dyoung 
    124       1.1    dyoung #define	ATW_TXTHRESH_TAB_LO_RATE {					\
    125       1.1    dyoung 	{ ATW_NAR_TR_L64,	"64 bytes" },				\
    126       1.1    dyoung 	{ ATW_NAR_TR_L160,	"160 bytes" },				\
    127       1.1    dyoung 	{ ATW_NAR_TR_L192,	"192 bytes" },				\
    128       1.1    dyoung 	{ ATW_NAR_SF,		"store and forward" },			\
    129       1.1    dyoung 	{ 0,			NULL },					\
    130       1.1    dyoung }
    131       1.1    dyoung 
    132       1.1    dyoung #define	ATW_TXTHRESH_TAB_HI_RATE {					\
    133       1.1    dyoung 	{ ATW_NAR_TR_H96,	"96 bytes" },				\
    134       1.1    dyoung 	{ ATW_NAR_TR_H288,	"288 bytes" },				\
    135       1.1    dyoung 	{ ATW_NAR_TR_H544,	"544 bytes" },				\
    136       1.1    dyoung 	{ ATW_NAR_SF,		"store and forward" },			\
    137       1.1    dyoung 	{ 0,			NULL },					\
    138       1.1    dyoung }
    139       1.1    dyoung 
    140       1.1    dyoung enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD  = 1,
    141       1.1    dyoung        ATW_RFTYPE_MARVEL = 2 };
    142       1.1    dyoung 
    143       1.1    dyoung enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD  = 1,
    144       1.9    dyoung        ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD  = 5 };
    145       1.1    dyoung 
    146       1.3    dyoung /* Radio capture format for ADMtek. */
    147       1.3    dyoung 
    148       1.3    dyoung #define ATW_RX_RADIOTAP_PRESENT	\
    149       1.3    dyoung 	((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \
    150       1.3    dyoung 	 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
    151       1.3    dyoung 	 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL))
    152       1.3    dyoung 
    153       1.3    dyoung struct atw_rx_radiotap_header {
    154       1.3    dyoung 	struct ieee80211_radiotap_header	ar_ihdr;
    155      1.25    dyoung 	uint8_t					ar_flags;
    156      1.25    dyoung 	uint8_t					ar_rate;
    157      1.25    dyoung 	uint16_t				ar_chan_freq;
    158      1.25    dyoung 	uint16_t				ar_chan_flags;
    159      1.25    dyoung 	uint8_t					ar_antsignal;
    160      1.27     perry } __packed;
    161       1.3    dyoung 
    162      1.24    dyoung #define ATW_TX_RADIOTAP_PRESENT	((1 << IEEE80211_RADIOTAP_RATE) | \
    163       1.3    dyoung 				 (1 << IEEE80211_RADIOTAP_CHANNEL))
    164       1.3    dyoung 
    165       1.3    dyoung struct atw_tx_radiotap_header {
    166       1.3    dyoung 	struct ieee80211_radiotap_header	at_ihdr;
    167      1.25    dyoung 	uint8_t					at_rate;
    168      1.25    dyoung 	uint8_t					at_pad;
    169      1.25    dyoung 	uint16_t				at_chan_freq;
    170      1.25    dyoung 	uint16_t				at_chan_flags;
    171      1.27     perry } __packed;
    172       1.4    dyoung 
    173      1.13    dyoung enum atw_revision {
    174      1.13    dyoung 	ATW_REVISION_AB = 0x11,	/* ADM8211A */
    175      1.13    dyoung 	ATW_REVISION_AF = 0x15,	/* ADM8211A? */
    176      1.13    dyoung 	ATW_REVISION_BA = 0x20,	/* ADM8211B */
    177      1.13    dyoung 	ATW_REVISION_CA = 0x30	/* ADM8211C/CR */
    178      1.13    dyoung };
    179      1.13    dyoung 
    180       1.1    dyoung struct atw_softc {
    181       1.1    dyoung 	struct device		sc_dev;
    182      1.16    dyoung 	struct ethercom		sc_ec;
    183       1.1    dyoung 	struct ieee80211com	sc_ic;
    184       1.1    dyoung 	int			(*sc_enable)(struct atw_softc *);
    185       1.1    dyoung 	void			(*sc_disable)(struct atw_softc *);
    186       1.1    dyoung 	void			(*sc_power)(struct atw_softc *, int);
    187       1.2    dyoung 	int			(*sc_newstate)(struct ieee80211com *,
    188       1.2    dyoung 					enum ieee80211_state, int);
    189       1.2    dyoung 	void			(*sc_recv_mgmt)(struct ieee80211com *,
    190       1.2    dyoung 				    struct mbuf *, struct ieee80211_node *,
    191       1.2    dyoung 				    int, int, u_int32_t);
    192      1.16    dyoung 	struct ieee80211_node	*(*sc_node_alloc)(struct ieee80211_node_table*);
    193      1.16    dyoung 	void			(*sc_node_free)(struct ieee80211_node *);
    194       1.1    dyoung 
    195       1.1    dyoung 	struct atw_stats sc_stats;	/* debugging stats */
    196       1.1    dyoung 
    197       1.1    dyoung 	int			sc_tx_timer;
    198       1.1    dyoung 	int			sc_rescan_timer;
    199       1.1    dyoung 
    200       1.1    dyoung 	bus_space_tag_t		sc_st;		/* bus space tag */
    201       1.1    dyoung 	bus_space_handle_t	sc_sh;		/* bus space handle */
    202       1.1    dyoung 	bus_dma_tag_t		sc_dmat;	/* bus dma tag */
    203       1.1    dyoung 	u_int32_t		sc_cacheline;	/* cache line size */
    204       1.1    dyoung 	u_int32_t		sc_maxburst;	/* maximum burst length */
    205       1.1    dyoung 
    206       1.1    dyoung 	const struct atw_txthresh_tab	*sc_txth;
    207       1.1    dyoung 	int				sc_txthresh; /* current tx threshold */
    208       1.1    dyoung 
    209       1.1    dyoung 	u_int			sc_cur_chan;	/* current channel */
    210       1.1    dyoung 
    211       1.1    dyoung 	int			sc_flags;
    212       1.1    dyoung 
    213       1.1    dyoung 	u_int16_t		*sc_srom;
    214       1.1    dyoung 	u_int16_t		sc_sromsz;
    215       1.1    dyoung 
    216      1.23  christos 	void *			sc_radiobpf;
    217       1.1    dyoung 
    218       1.1    dyoung 	bus_dma_segment_t	sc_cdseg;	/* control data memory */
    219       1.1    dyoung 	int			sc_cdnseg;	/* number of segments */
    220       1.1    dyoung 	bus_dmamap_t		sc_cddmamap;	/* control data DMA map */
    221       1.1    dyoung #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
    222       1.1    dyoung 
    223       1.1    dyoung 	/*
    224       1.1    dyoung 	 * Software state for transmit and receive descriptors.
    225       1.1    dyoung 	 */
    226       1.1    dyoung 	struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
    227       1.1    dyoung 	struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
    228       1.1    dyoung 
    229       1.1    dyoung 	/*
    230       1.1    dyoung 	 * Control data structures.
    231       1.1    dyoung 	 */
    232       1.1    dyoung 	struct atw_control_data *sc_control_data;
    233       1.1    dyoung #define	sc_txdescs	sc_control_data->acd_txdescs
    234       1.1    dyoung #define	sc_rxdescs	sc_control_data->acd_rxdescs
    235       1.1    dyoung #define	sc_setup_desc	sc_control_data->acd_setup_desc
    236       1.1    dyoung 
    237       1.1    dyoung 	int	sc_txfree;		/* number of free Tx descriptors */
    238       1.1    dyoung 	int	sc_txnext;		/* next ready Tx descriptor */
    239       1.1    dyoung 	int	sc_ntxsegs;		/* number of transmit segs per pkt */
    240       1.1    dyoung 
    241       1.1    dyoung 	struct atw_txsq sc_txfreeq;	/* free Tx descsofts */
    242       1.1    dyoung 	struct atw_txsq sc_txdirtyq;	/* dirty Tx descsofts */
    243       1.1    dyoung 
    244       1.1    dyoung 	int	sc_rxptr;		/* next ready RX descriptor/descsoft */
    245       1.1    dyoung 
    246       1.1    dyoung 	u_int32_t	sc_busmode;	/* copy of ATW_PAR */
    247       1.1    dyoung 	u_int32_t	sc_opmode;	/* copy of ATW_NAR */
    248       1.1    dyoung 	u_int32_t	sc_inten;	/* copy of ATW_IER */
    249       1.1    dyoung 	u_int32_t	sc_wepctl;	/* copy of ATW_WEPCTL */
    250       1.1    dyoung 
    251       1.1    dyoung 	u_int32_t	sc_rxint_mask;	/* mask of Rx interrupts we want */
    252       1.1    dyoung 	u_int32_t	sc_txint_mask;	/* mask of Tx interrupts we want */
    253       1.1    dyoung 	u_int32_t	sc_linkint_mask;/* link-state interrupts mask */
    254       1.1    dyoung 
    255       1.1    dyoung 	/* interrupt acknowledge hook */
    256       1.8    dyoung 	void (*sc_intr_ack)(struct atw_softc *);
    257       1.1    dyoung 
    258       1.1    dyoung 	enum atw_rftype		sc_rftype;
    259       1.1    dyoung 	enum atw_bbptype	sc_bbptype;
    260       1.1    dyoung 	u_int32_t	sc_synctl_rd;
    261       1.1    dyoung 	u_int32_t	sc_synctl_wr;
    262       1.1    dyoung 	u_int32_t	sc_bbpctl_rd;
    263       1.1    dyoung 	u_int32_t	sc_bbpctl_wr;
    264       1.1    dyoung 
    265       1.1    dyoung 	void		(*sc_recv_beacon)(struct ieee80211com *, struct mbuf *,
    266       1.1    dyoung 			    int, u_int32_t);
    267       1.1    dyoung 	void		(*sc_recv_prresp)(struct ieee80211com *, struct mbuf *,
    268       1.1    dyoung 			    int, u_int32_t);
    269       1.1    dyoung 
    270       1.1    dyoung 	/* ADM8211 state variables. */
    271      1.12    dyoung 	u_int8_t	sc_sram[ATW_SRAM_MAXSIZE];
    272      1.13    dyoung 	u_int		sc_sramlen;
    273       1.1    dyoung 	u_int8_t	sc_bssid[IEEE80211_ADDR_LEN];
    274      1.13    dyoung 	uint8_t		sc_rev;
    275      1.13    dyoung 	uint8_t		sc_rf3000_options1;
    276      1.13    dyoung 	uint8_t		sc_rf3000_options2;
    277       1.1    dyoung 
    278      1.26    dyoung 	struct evcnt	sc_recv_ev;
    279      1.26    dyoung 	struct evcnt	sc_crc16e_ev;
    280      1.26    dyoung 	struct evcnt	sc_crc32e_ev;
    281      1.26    dyoung 	struct evcnt	sc_icve_ev;
    282      1.26    dyoung 	struct evcnt	sc_sfde_ev;
    283      1.26    dyoung 	struct evcnt	sc_sige_ev;
    284      1.26    dyoung 
    285       1.2    dyoung 	struct callout	sc_scan_ch;
    286       1.3    dyoung 	union {
    287       1.3    dyoung 		struct atw_rx_radiotap_header	tap;
    288       1.3    dyoung 		u_int8_t			pad[64];
    289       1.3    dyoung 	} sc_rxtapu;
    290       1.3    dyoung 	union {
    291       1.3    dyoung 		struct atw_tx_radiotap_header	tap;
    292       1.3    dyoung 		u_int8_t			pad[64];
    293       1.3    dyoung 	} sc_txtapu;
    294       1.1    dyoung };
    295       1.3    dyoung 
    296      1.16    dyoung #define	sc_if		sc_ec.ec_if
    297       1.3    dyoung #define sc_rxtap	sc_rxtapu.tap
    298       1.3    dyoung #define sc_txtap	sc_txtapu.tap
    299       1.1    dyoung 
    300       1.1    dyoung /* XXX this is fragile. try not to introduce any u_int32_t's. */
    301       1.1    dyoung struct atw_frame {
    302       1.1    dyoung /*00*/	u_int8_t			atw_dst[IEEE80211_ADDR_LEN];
    303       1.1    dyoung /*06*/	u_int8_t			atw_rate;	/* TX rate in 100Kbps */
    304       1.1    dyoung /*07*/	u_int8_t			atw_service;	/* 0 */
    305       1.1    dyoung /*08*/	u_int16_t			atw_paylen;	/* payload length */
    306       1.1    dyoung /*0a*/	u_int8_t			atw_fc[2];	/* 802.11 Frame
    307       1.1    dyoung 							 * Control
    308       1.1    dyoung 							 */
    309       1.1    dyoung 	/* 802.11 PLCP Length for first & last fragment */
    310       1.1    dyoung /*0c*/	u_int16_t			atw_tail_plcplen;
    311       1.1    dyoung /*0e*/	u_int16_t			atw_head_plcplen;
    312       1.1    dyoung 	/* 802.11 Duration for first & last fragment */
    313       1.1    dyoung /*10*/	u_int16_t			atw_tail_dur;
    314       1.1    dyoung /*12*/	u_int16_t			atw_head_dur;
    315       1.1    dyoung /*14*/	u_int8_t			atw_addr4[IEEE80211_ADDR_LEN];
    316       1.1    dyoung 	union {
    317       1.1    dyoung 		struct {
    318       1.1    dyoung /*1a*/			u_int16_t	hdrctl;	/*transmission control*/
    319       1.1    dyoung /*1c*/			u_int16_t	fragthr;/* fragmentation threshold
    320       1.1    dyoung 						 * [0:11], zero [12:15].
    321       1.1    dyoung 						 */
    322       1.1    dyoung /*1e*/			u_int8_t	fragnum;/* fragment number [4:7],
    323       1.1    dyoung 						 * zero [0:3].
    324       1.1    dyoung 						 */
    325       1.1    dyoung /*1f*/			u_int8_t	rtylmt;	/* retry limit */
    326       1.1    dyoung /*20*/			u_int8_t	wepkey0[4];/* ??? */
    327       1.1    dyoung /*24*/			u_int8_t	wepkey1[4];/* ??? */
    328       1.1    dyoung /*28*/			u_int8_t	wepkey2[4];/* ??? */
    329       1.1    dyoung /*2c*/			u_int8_t	wepkey3[4];/* ??? */
    330       1.1    dyoung /*30*/			u_int8_t	keyid;
    331       1.1    dyoung /*31*/			u_int8_t	reserved0[7];
    332       1.2    dyoung 		} s1;
    333       1.2    dyoung 		struct {
    334       1.2    dyoung 			u_int8_t		pad[6];
    335       1.2    dyoung 			struct ieee80211_frame	ihdr;
    336       1.2    dyoung 		} s2;
    337       1.1    dyoung 	} u;
    338      1.27     perry } __packed;
    339       1.1    dyoung 
    340       1.2    dyoung #define atw_hdrctl	u.s1.hdrctl
    341       1.2    dyoung #define atw_fragthr	u.s1.fragthr
    342       1.2    dyoung #define atw_fragnum	u.s1.fragnum
    343       1.2    dyoung #define atw_rtylmt	u.s1.rtylmt
    344       1.2    dyoung #define atw_keyid	u.s1.keyid
    345       1.2    dyoung #define atw_ihdr	u.s2.ihdr
    346       1.1    dyoung 
    347      1.21    dyoung #define ATW_HDRCTL_SHORT_PREAMBLE	__BIT(0)	/* use short preamble */
    348      1.21    dyoung #define ATW_HDRCTL_RTSCTS		__BIT(4)	/* send RTS */
    349      1.21    dyoung #define ATW_HDRCTL_WEP			__BIT(5)
    350      1.21    dyoung #define ATW_HDRCTL_UNKNOWN1		__BIT(15) /* MAC adds FCS? */
    351      1.21    dyoung #define ATW_HDRCTL_UNKNOWN2		__BIT(8)
    352       1.1    dyoung 
    353      1.21    dyoung #define ATW_FRAGTHR_FRAGTHR_MASK	__BITS(0, 11)
    354      1.21    dyoung #define ATW_FRAGNUM_FRAGNUM_MASK	__BITS(4, 7)
    355       1.1    dyoung 
    356       1.1    dyoung /* Values for sc_flags. */
    357      1.19    dyoung #define	ATWF_MRL		0x00000001	/* memory read line okay */
    358      1.19    dyoung #define	ATWF_MRM		0x00000002	/* memory read multi okay */
    359      1.19    dyoung #define	ATWF_MWI		0x00000004	/* memory write inval okay */
    360      1.19    dyoung #define	ATWF_SHORT_PREAMBLE	0x00000008	/* short preamble enabled */
    361      1.19    dyoung #define	ATWF_RTSCTS		0x00000010	/* RTS/CTS enabled */
    362      1.19    dyoung #define	ATWF_ATTACHED		0x00000020	/* attach has succeeded */
    363      1.19    dyoung #define	ATWF_ENABLED		0x00000040	/* chip is enabled */
    364      1.19    dyoung #define	ATWF_WEP_SRAM_VALID	0x00000080	/* SRAM matches s/w state */
    365       1.1    dyoung 
    366       1.1    dyoung #define	ATW_IS_ENABLED(sc)	((sc)->sc_flags & ATWF_ENABLED)
    367       1.1    dyoung 
    368       1.1    dyoung #define	ATW_CDTXADDR(sc, x)	((sc)->sc_cddma + ATW_CDTXOFF((x)))
    369       1.1    dyoung #define	ATW_CDRXADDR(sc, x)	((sc)->sc_cddma + ATW_CDRXOFF((x)))
    370       1.1    dyoung 
    371       1.1    dyoung #define	ATW_CDTXSYNC(sc, x, n, ops)					\
    372       1.1    dyoung do {									\
    373       1.1    dyoung 	int __x, __n;							\
    374       1.1    dyoung 									\
    375       1.1    dyoung 	__x = (x);							\
    376       1.1    dyoung 	__n = (n);							\
    377       1.1    dyoung 									\
    378       1.1    dyoung 	/* If it will wrap around, sync to the end of the ring. */	\
    379       1.1    dyoung 	if ((__x + __n) > ATW_NTXDESC) {				\
    380       1.1    dyoung 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
    381       1.1    dyoung 		    ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) *	\
    382       1.1    dyoung 		    (ATW_NTXDESC - __x), (ops));			\
    383       1.1    dyoung 		__n -= (ATW_NTXDESC - __x);				\
    384       1.1    dyoung 		__x = 0;						\
    385       1.1    dyoung 	}								\
    386       1.1    dyoung 									\
    387       1.1    dyoung 	/* Now sync whatever is left. */				\
    388       1.1    dyoung 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    389       1.1    dyoung 	    ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \
    390       1.1    dyoung } while (0)
    391       1.1    dyoung 
    392       1.1    dyoung #define	ATW_CDRXSYNC(sc, x, ops)					\
    393       1.1    dyoung 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    394       1.1    dyoung 	    ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops))
    395       1.1    dyoung 
    396       1.1    dyoung /*
    397       1.1    dyoung  * Note we rely on MCLBYTES being a power of two.  Because the `length'
    398       1.1    dyoung  * field is only 11 bits, we must subtract 1 from the length to avoid
    399       1.1    dyoung  * having it truncated to 0!
    400       1.1    dyoung  */
    401      1.24    dyoung static inline void
    402      1.24    dyoung atw_init_rxdesc(struct atw_softc *sc, int x)
    403      1.24    dyoung {
    404      1.24    dyoung 	struct atw_rxsoft *rxs = &sc->sc_rxsoft[x];
    405      1.24    dyoung 	struct atw_rxdesc *rxd = &sc->sc_rxdescs[x];
    406      1.24    dyoung 	struct mbuf *m = rxs->rxs_mbuf;
    407      1.24    dyoung 
    408      1.24    dyoung 	rxd->ar_buf1 =
    409      1.24    dyoung 	    htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr);
    410      1.24    dyoung 	rxd->ar_buf2 =	/* for descriptor chaining */
    411      1.24    dyoung 	    htole32(ATW_CDRXADDR((sc), ATW_NEXTRX(x)));
    412      1.24    dyoung 	rxd->ar_ctlrssi =
    413      1.24    dyoung 	    htole32(__SHIFTIN(((m->m_ext.ext_size - 1) & ~0x3U),
    414      1.24    dyoung 	                   ATW_RXCTL_RBS1_MASK) |
    415      1.24    dyoung 		    0 /* ATW_RXCTL_RCH */ |
    416      1.24    dyoung 	    (x == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0));
    417      1.24    dyoung 	rxd->ar_stat = htole32(ATW_RXSTAT_OWN);
    418      1.24    dyoung 
    419      1.24    dyoung 	ATW_CDRXSYNC((sc), x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
    420      1.24    dyoung }
    421       1.1    dyoung 
    422       1.1    dyoung /* country codes from ADM8211 SROM */
    423       1.1    dyoung #define	ATW_COUNTRY_FCC 0		/* USA 1-11 */
    424       1.1    dyoung #define	ATW_COUNTRY_IC 1		/* Canada 1-11 */
    425       1.1    dyoung #define	ATW_COUNTRY_ETSI 2		/* European Union (?) 1-13 */
    426       1.1    dyoung #define	ATW_COUNTRY_SPAIN 3		/* 10-11 */
    427       1.1    dyoung #define	ATW_COUNTRY_FRANCE 4		/* 10-13 */
    428       1.1    dyoung #define	ATW_COUNTRY_MKK 5		/* Japan: 14 */
    429       1.1    dyoung #define	ATW_COUNTRY_MKK2 6		/* Japan: 1-14 */
    430       1.2    dyoung 
    431       1.1    dyoung /*
    432       1.1    dyoung  * register space access macros
    433       1.1    dyoung  */
    434       1.1    dyoung #define	ATW_READ(sc, reg)						\
    435       1.1    dyoung 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    436       1.1    dyoung 
    437       1.1    dyoung #define	ATW_WRITE(sc, reg, val)					\
    438       1.1    dyoung 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    439       1.1    dyoung 
    440       1.1    dyoung #define	ATW_SET(sc, reg, mask)					\
    441       1.1    dyoung 	ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
    442       1.1    dyoung 
    443       1.1    dyoung #define	ATW_CLR(sc, reg, mask)					\
    444       1.1    dyoung 	ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
    445       1.1    dyoung 
    446       1.1    dyoung #define	ATW_ISSET(sc, reg, mask)					\
    447       1.1    dyoung 	(ATW_READ((sc), (reg)) & (mask))
    448       1.1    dyoung 
    449       1.8    dyoung void	atw_attach(struct atw_softc *);
    450       1.8    dyoung int	atw_detach(struct atw_softc *);
    451       1.8    dyoung int	atw_activate(struct device *, enum devact);
    452       1.8    dyoung int	atw_intr(void *arg);
    453       1.8    dyoung void	atw_power(int, void *);
    454      1.28    dyoung bool	atw_shutdown(device_t, int);
    455       1.1    dyoung 
    456       1.1    dyoung #endif /* _DEV_IC_ATWVAR_H_ */
    457