awireg.h revision 1.10.52.1
1/* $NetBSD: awireg.h,v 1.10.52.1 2008/02/18 21:05:40 mjf Exp $ */
2
3/*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Bill Sommerfeld
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *        This product includes software developed by the NetBSD
21 *        Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 *    contributors may be used to endorse or promote products derived
24 *    from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef _DEV_IC_AWIREG_H
40#define	_DEV_IC_AWIREG_H
41
42/*
43 * The firmware typically loaded onto Am79C930-based 802.11 interfaces
44 * uses a 32k or larger shared memory buffer to communicate with the
45 * host.
46 *
47 * Depending on the exact configuration of the device, this buffer may
48 * either be mapped into PCMCIA memory space, or accessible a byte at
49 * a type through PCMCIA I/O space.
50 *
51 * This header defines offsets into this shared memory.
52 */
53
54
55/*
56 * LAST_TXD block.  5 32-bit words.
57 *
58 * There are five different output queues; this defines pointers to
59 * the last completed descriptor for each one.
60 */
61#define AWI_LAST_TXD		0x3ec	/* last completed Tx Descr */
62
63#define AWI_LAST_BCAST_TXD		AWI_LAST_TXD+0
64#define AWI_LAST_MGT_TXD		AWI_LAST_TXD+4
65#define AWI_LAST_DATA_TXD		AWI_LAST_TXD+8
66#define AWI_LAST_PS_POLL_TXD		AWI_LAST_TXD+12
67#define AWI_LAST_CF_POLL_TXD		AWI_LAST_TXD+16
68
69/*
70 * Banner block; null-terminated string.
71 *
72 * The doc says it contains
73 * "PCnetMobile:v2.00 mmddyy APIx.x\0"
74 */
75
76#define AWI_BANNER		0x480	/* Version string */
77#define AWI_BANNER_LEN			0x20
78
79/*
80 * Command block protocol:
81 * write command byte to a zero value.
82 * write command status to a zero value.
83 * write arguments to AWI_COMMAND_PARAMS
84 * write command byte to a non-zero value.
85 * wait for command status to be non-zero.
86 * write command byte to a zero value.
87 * write command status to a zero value.
88 */
89
90#define AWI_CMD			0x4a0	/* Command opcode byte */
91
92#define AWI_CMD_IDLE			0x0
93#define AWI_CMD_NOP			0x1
94
95#define AWI_CMD_SET_MIB			0x2
96#define AWI_CMD_GET_MIB			0x9
97#define AWI_CA_MIB_TYPE			(AWI_CMD_PARAMS + 0x0)
98#define AWI_CA_MIB_SIZE			(AWI_CMD_PARAMS + 0x1)
99#define AWI_CA_MIB_INDEX		(AWI_CMD_PARAMS + 0x2)
100#define AWI_CA_MIB_DATA			(AWI_CMD_PARAMS + 0x4)
101#define AWI_MIB_LOCAL				0
102#define AWI_MIB_ADDR				2
103#define AWI_MIB_MAC				3
104#define AWI_MIB_STAT				4
105#define AWI_MIB_MGT				5
106#define AWI_MIB_DRVR				6
107#define AWI_MIB_PHY				7
108
109#define AWI_CMD_INIT_TX			0x3
110#define AWI_CA_TX_LEN			20
111#define AWI_CA_TX_DATA			(AWI_CMD_PARAMS + 0x0)
112#define AWI_CA_TX_MGT			(AWI_CMD_PARAMS + 0x4)
113#define AWI_CA_TX_BCAST		       	(AWI_CMD_PARAMS + 0x8)
114#define AWI_CA_TX_PS			(AWI_CMD_PARAMS + 0xc)
115#define AWI_CA_TX_CF			(AWI_CMD_PARAMS + 0x10)
116
117#define AWI_CMD_FLUSH_TX		0x4
118#define AWI_CA_FTX_LEN			5
119#define AWI_CA_FTX_DATA			(AWI_CMD_PARAMS + 0x0)
120#define AWI_CA_FTX_MGT			(AWI_CMD_PARAMS + 0x1)
121#define AWI_CA_FTX_BCAST		(AWI_CMD_PARAMS + 0x2)
122#define AWI_CA_FTX_PS			(AWI_CMD_PARAMS + 0x3)
123#define AWI_CA_FTX_CF			(AWI_CMD_PARAMS + 0x4)
124
125#define AWI_CMD_INIT_RX			0x5
126#define AWI_CA_IRX_LEN			0x8
127#define AWI_CA_IRX_DATA_DESC		(AWI_CMD_PARAMS + 0x0)	/* return */
128#define AWI_CA_IRX_PS_DESC		(AWI_CMD_PARAMS + 0x4)	/* return */
129
130#define AWI_CMD_KILL_RX			0x6
131
132#define AWI_CMD_SLEEP			0x7
133#define AWI_CA_SLEEP_LEN		8
134#define AWI_CA_WAKEUP			(AWI_CMD_PARAMS + 0x0)	/* uint64 */
135
136#define AWI_CMD_WAKE			0x8
137
138#define AWI_CMD_SCAN			0xa
139#define AWI_CA_SCAN_LEN			6
140#define AWI_CA_SCAN_DURATION		(AWI_CMD_PARAMS + 0x0)
141#define AWI_CA_SCAN_SET			(AWI_CMD_PARAMS + 0x2)
142#define AWI_CA_SCAN_PATTERN		(AWI_CMD_PARAMS + 0x3)
143#define AWI_CA_SCAN_IDX			(AWI_CMD_PARAMS + 0x4)
144#define AWI_CA_SCAN_SUSP		(AWI_CMD_PARAMS + 0x5)
145
146#define AWI_CMD_SYNC			0xb
147#define AWI_CA_SYNC_LEN			20
148#define AWI_CA_SYNC_SET			(AWI_CMD_PARAMS + 0x0)
149#define AWI_CA_SYNC_PATTERN		(AWI_CMD_PARAMS + 0x1)
150#define AWI_CA_SYNC_IDX			(AWI_CMD_PARAMS + 0x2)
151#define AWI_CA_SYNC_STARTBSS		(AWI_CMD_PARAMS + 0x3)
152#define AWI_CA_SYNC_DWELL		(AWI_CMD_PARAMS + 0x4)
153#define AWI_CA_SYNC_MBZ			(AWI_CMD_PARAMS + 0x6)
154#define AWI_CA_SYNC_TIMESTAMP		(AWI_CMD_PARAMS + 0x8)
155#define AWI_CA_SYNC_REFTIME		(AWI_CMD_PARAMS + 0x10)
156
157#define AWI_CMD_RESUME			0xc
158
159#define AWI_CMD_STATUS			0x4a1 	/* Command status */
160
161#define AWI_STAT_IDLE			0x0
162#define AWI_STAT_OK			0x1
163#define AWI_STAT_BADCMD			0x2
164#define AWI_STAT_BADPARM		0x3
165#define AWI_STAT_NOTIMP			0x4
166#define AWI_STAT_BADRES			0x5
167#define AWI_STAT_BADMODE		0x6
168
169#define AWI_ERROR_OFFSET	0x4a2 	/* Offset to erroneous parameter */
170#define AWI_CMD_PARAMS		0x4a4 	/* Command parameters */
171
172#define AWI_CSB			0x4f0 	/* Control/Status block */
173
174#define AWI_SELFTEST		0x4f0
175
176#define AWI_SELFTEST_INIT		0x00 /* initial */
177#define AWI_SELFTEST_FIRMCKSUM		0x01 /* firmware cksum running */
178#define AWI_SELFTEST_HARDWARE		0x02 /* hardware tests running */
179#define AWI_SELFTEST_MIB		0x03 /* mib initializing */
180
181#define AWI_SELFTEST_MIB_FAIL		0xfa
182#define AWI_SELFTEST_RADIO_FAIL		0xfb
183#define AWI_SELFTEST_MAC_FAIL		0xfc
184#define AWI_SELFTEST_FLASH_FAIL		0xfd
185#define AWI_SELFTEST_RAM_FAIL		0xfe
186#define AWI_SELFTEST_PASSED		0xff
187
188#define AWI_STA_STATE		0x4f1
189
190#define AWI_STA_AP			0x20 /* acting as AP */
191#define AWI_STA_NOPSP			0x10 /* Power Saving disabled */
192#define AWI_STA_DOZE			0x08 /* about to go to sleep */
193#define AWI_STA_PSP			0x04 /* enable PSP */
194#define AWI_STA_RXEN			0x02 /* enable RX */
195#define AWI_STA_TXEN			0x01 /* enable TX */
196
197#define AWI_INTSTAT		0x4f3
198#define AWI_INTMASK		0x4f4
199
200/* Bits in AWI_INTSTAT/AWI_INTMASK */
201
202#define AWI_INT_GROGGY			0x80 /* about to wake up */
203#define AWI_INT_CFP_ENDING		0x40 /* cont. free period ending */
204#define AWI_INT_DTIM			0x20 /* beacon outgoing */
205#define AWI_INT_CFP_START		0x10 /* cont. free period starting */
206#define AWI_INT_SCAN_CMPLT		0x08 /* scan complete */
207#define AWI_INT_TX			0x04 /* tx done */
208#define AWI_INT_RX			0x02 /* rx done */
209#define AWI_INT_CMD			0x01 /* cmd done */
210
211/*
212 * The following are used to implement a locking protocol between host
213 * and MAC to protect the interrupt status and mask fields.
214 *
215 * driver: read lockout_host byte; if zero, set lockout_mac to non-zero,
216 *	then reread lockout_host byte; if still zero, host has lock.
217 *	if non-zero, clear lockout_mac, loop.
218 */
219
220#define AWI_LOCKOUT_MAC		0x4f5
221#define AWI_LOCKOUT_HOST	0x4f6
222
223
224#define AWI_INTSTAT2		0x4f7
225#define AWI_INTMASK2		0x4fd
226
227/* Bits in AWI_INTSTAT2/INTMASK2 */
228#define AWI_INT2_RXMGT			0x80 		/* mgt/ps received */
229#define AWI_INT2_RXDATA			0x40 		/* data received */
230#define AWI_INT2_TXMGT			0x10		/* mgt tx done */
231#define AWI_INT2_TXCF			0x08		/* CF tx done */
232#define AWI_INT2_TXPS			0x04		/* PS tx done */
233#define AWI_INT2_TXBCAST		0x02		/* Broadcast tx done */
234#define AWI_INT2_TXDATA			0x01		/* data tx done */
235
236#define AWI_DIS_PWRDN		0x4fc		/* disable powerdown if set */
237
238#define AWI_DRIVERSTATE		0x4fe		/* driver state */
239
240#define AWI_DRV_STATEMASK		0x0f
241
242#define AWI_DRV_RESET			0x0
243#define AWI_DRV_INFSY			0x1 /* inf synced */
244#define AWI_DRV_ADHSC			0x2 /* adhoc scan */
245#define AWI_DRV_ADHSY			0x3 /* adhoc synced */
246#define AWI_DRV_INFSC			0x4 /* inf scanning */
247#define AWI_DRV_INFAUTH			0x5 /* inf authed */
248#define AWI_DRV_INFASSOC		0x6 /* inf associated */
249#define AWI_DRV_INFTOSS			0x7 /* inf handoff */
250#define AWI_DRV_APNONE			0x8 /* AP activity: no assoc */
251#define AWI_DRV_APQUIET			0xc /* AP: >=one assoc, no traffic */
252#define AWI_DRV_APLO			0xd /* AP: >=one assoc, light tfc */
253#define AWI_DRV_APMED			0xe /* AP: >=one assoc, mod tfc */
254#define AWI_DRV_APHIGH			0xf /* AP: >=one assoc, heavy tfc */
255
256#define AWI_DRV_AUTORXLED		0x10
257#define AWI_DRV_AUTOTXLED		0x20
258#define AWI_DRV_RXLED			0x40
259#define AWI_DRV_TXLED			0x80
260
261#define AWI_VBM_OFFSET		0x500	/* Virtual Bit Map */
262#define AWI_VBM_LENGTH		0x501
263#define AWI_VBM_BITMAP		0x502
264
265#define AWI_BUFFERS		0x600	/* Buffers */
266#define	AWI_BUFFERS_END		0x6000
267
268/*
269 * Receive descriptors; there are a linked list of these chained
270 * through the "NEXT" fields, starting from XXX
271 */
272
273#define AWI_RXD_SIZE			0x18
274
275#define AWI_RXD_NEXT			0x4
276#define AWI_RXD_NEXT_LAST		0x80000000
277
278
279#define AWI_RXD_HOST_DESC_STATE		0x9
280
281#define AWI_RXD_ST_OWN		0x80 /* host owns this */
282#define AWI_RXD_ST_CONSUMED	0x40 /* host is done */
283#define AWI_RXD_ST_LF		0x20 /* last frag */
284#define AWI_RXD_ST_CRC		0x08 /* CRC error */
285#define AWI_RXD_ST_OFLO		0x02 /* possible buffer overrun */
286#define AWI_RXD_ST_RXERROR	0x01 /* this frame is borked; discard me */
287
288#define AWI_RXD_RSSI		0xa /* 1 byte: radio strength indicator */
289#define AWI_RXD_INDEX		0xb /* 1 byte: FH hop index or DS channel */
290#define AWI_RXD_LOCALTIME	0xc /* 4 bytes: local time of RX */
291#define AWI_RXD_START_FRAME	0x10 /* 4 bytes: ptr to first received byte */
292#define AWI_RXD_LEN		0x14 /* 2 bytes: rx len in bytes */
293#define AWI_RXD_RATE		0x16 /* 1 byte: rx rate in 1e5 bps */
294
295/*
296 * Transmit descriptors.
297 */
298
299#define AWI_TXD_SIZE		0x18
300
301#define AWI_TXD_START		0x00 /* pointer to start of frame */
302#define AWI_TXD_NEXT		0x04 /* pointer to next TXD */
303#define AWI_TXD_LENGTH		0x08 /* length of frame */
304#define AWI_TXD_STATE		0x0a /* state */
305
306#define AWI_TXD_ST_OWN		0x80 /* MAC owns this  */
307#define AWI_TXD_ST_DONE		0x40 /* MAC is done */
308#define AWI_TXD_ST_REJ		0x20 /* MAC doesn't like */
309#define AWI_TXD_ST_MSDU		0x10 /* MSDU timeout */
310#define AWI_TXD_ST_ABRT		0x08 /* TX aborted */
311#define AWI_TXD_ST_RETURNED	0x04 /* TX returned */
312#define AWI_TXD_ST_RETRY	0x02 /* TX retries exceeded */
313#define AWI_TXD_ST_ERROR	0x01 /* TX error */
314
315#define AWI_TXD_RATE		0x0b /* rate */
316
317#define AWI_RATE_1MBIT		10
318#define AWI_RATE_2MBIT		20
319
320#define AWI_TXD_NDA		0x0c /* num DIFS attempts */
321#define AWI_TXD_NDF		0x0d /* num DIFS failures */
322#define AWI_TXD_NSA		0x0e /* num SIFS attempts */
323#define AWI_TXD_NSF		0x0f /* num SIFS failures */
324
325#define AWI_TXD_NRA		0x14 /* num RTS attempts */
326#define AWI_TXD_NDTA		0x15 /* num data attempts */
327#define AWI_TXD_CTL		0x16 /* control */
328
329#define AWI_TXD_CTL_PSN		0x80	/* preserve sequence in MAC frame */
330#define AWI_TXD_CTL_BURST	0x02    /* host is doing 802.11 fragmt. */
331#define AWI_TXD_CTL_FRAGS	0x01    /* override normal fragmentation */
332
333/*
334 * MIB structures.
335 */
336
337#define	AWI_ESS_ID_SIZE			(IEEE80211_NWID_LEN+2)
338struct awi_mib_local {
339	u_int8_t	Fragmentation_Dis;
340	u_int8_t	Add_PLCP_Dis;
341	u_int8_t	MAC_Hdr_Prsv;
342	u_int8_t	Rx_Mgmt_Que_En;
343	u_int8_t	Re_Assembly_Dis;
344	u_int8_t	Strip_PLCP_Dis;
345	u_int8_t	Rx_Error_Dis;
346	u_int8_t	Power_Saving_Mode_Dis;
347	u_int8_t	Accept_All_Multicast_Dis;
348	u_int8_t	Check_Seq_Cntl_Dis;
349	u_int8_t	Flush_CFP_Queue_On_CF_End;
350	u_int8_t	Network_Mode;
351	u_int8_t	PWD_Lvl;
352	u_int8_t	CFP_Mode;
353	u_int8_t	Tx_Buffer_Offset[4];
354	u_int8_t	Tx_Buffer_Size[4];
355	u_int8_t	Rx_Buffer_Offset[4];
356	u_int8_t	Rx_Buffer_Size[4];
357	u_int8_t	Acting_as_AP;
358	u_int8_t	Fill_CFP;
359} __packed;
360
361struct awi_mib_mac {
362	u_int8_t	_Reserved1[2];
363	u_int8_t	_Reserved2[2];
364	u_int8_t	aRTS_Threshold[2];
365	u_int8_t	aCW_max[2];
366	u_int8_t	aCW_min[2];
367	u_int8_t	aPromiscuous_Enable;
368	u_int8_t	_Reserved3;
369	u_int8_t	_Reserved4[4];
370	u_int8_t	aShort_Retry_Limit;
371	u_int8_t	aLong_Retry_Limit;
372	u_int8_t	aMax_Frame_Length[2];
373	u_int8_t	aFragmentation_Threshold[2];
374	u_int8_t	aProbe_Delay[2];
375	u_int8_t	aMin_Probe_Response_Time[2];
376	u_int8_t	aMax_Probe_Response_Time[2];
377	u_int8_t	aMax_Transmit_MSDU_Lifetime[4];
378	u_int8_t	aMax_Receive_MSDU_Lifetime[4];
379	u_int8_t	aStation_Basic_Rate[2];
380	u_int8_t	aDesired_ESS_ID[AWI_ESS_ID_SIZE];
381} __packed;
382
383struct awi_mib_stat {
384	u_int8_t	aTransmitted_MPDU_Count[4];
385	u_int8_t	aTransmitted_MSDU_Count[4];
386	u_int8_t	aOctets_Transmitted_Cnt[4];
387	u_int8_t	aMulticast_Transmitted_Frame_Count[2];
388	u_int8_t	aBroadcast_Transmitted_Frame_Count[2];
389	u_int8_t	aFailed_Count[4];
390	u_int8_t	aRetry_Count[4];
391	u_int8_t	aMultiple_Retry_Count[4];
392	u_int8_t	aFrame_Duplicate_Count[4];
393	u_int8_t	aRTS_Success_Count[4];
394	u_int8_t	aRTS_Failure_Count[4];
395	u_int8_t	aACK_Failure_Count[4];
396	u_int8_t	aReceived_Frame_Count [4];
397	u_int8_t	aOctets_Received_Count[4];
398	u_int8_t	aMulticast_Received_Count[2];
399	u_int8_t	aBroadcast_Received_Count[2];
400	u_int8_t	aFCS_Error_Count[4];
401	u_int8_t	aError_Count[4];
402	u_int8_t	aWEP_Undecryptable_Count[4];
403} __packed;
404
405struct awi_mib_mgt {
406	u_int8_t	aPower_Mgt_Mode;
407	u_int8_t	aScan_Mode;
408#define	AWI_SCAN_PASSIVE		0x00
409#define	AWI_SCAN_ACTIVE			0x01
410#define	AWI_SCAN_BACKGROUND		0x02
411	u_int8_t	aScan_State;
412	u_int8_t	aDTIM_Period;
413	u_int8_t	aATIM_Window[2];
414	u_int8_t	Wep_Required;
415#define	AWI_WEP_ON			0x10
416#define	AWI_WEP_OFF			0x00
417	u_int8_t	_Reserved1;
418	u_int8_t	aBeacon_Period[2];
419	u_int8_t	aPassive_Scan_Duration[2];
420	u_int8_t	aListen_Interval[2];
421	u_int8_t	aMedium_Occupancy_Limit[2];
422	u_int8_t	aMax_MPDU_Time[2];
423	u_int8_t	aCFP_Max_Duration[2];
424	u_int8_t	aCFP_Rate;
425	u_int8_t	Do_Not_Receive_DTIMs;
426	u_int8_t	aStation_ID[2];
427	u_int8_t	aCurrent_BSS_ID[ETHER_ADDR_LEN];
428	u_int8_t	aCurrent_ESS_ID[AWI_ESS_ID_SIZE];
429} __packed;
430
431#define	AWI_GROUP_ADDR_SIZE	4
432struct awi_mib_addr {
433	u_int8_t	aMAC_Address[ETHER_ADDR_LEN];
434	u_int8_t	aGroup_Addresses[AWI_GROUP_ADDR_SIZE][ETHER_ADDR_LEN];
435	u_int8_t	aTransmit_Enable_Status;
436	u_int8_t	_Reserved1;
437} __packed;
438
439#define AWI_PWR_LEVEL_SIZE 4
440struct awi_mib_phy {
441	u_int8_t	aSlot_Time[2];
442	u_int8_t	aSIFS[2];
443	u_int8_t	aMPDU_Maximum[2];
444	u_int8_t	aHop_Time[2];
445	u_int8_t	aSuprt_Data_Rates[4];
446	u_int8_t	aCurrent_Reg_Domain;
447#define	AWI_REG_DOMAIN_US	0x10
448#define	AWI_REG_DOMAIN_CA	0x20
449#define	AWI_REG_DOMAIN_EU	0x30
450#define	AWI_REG_DOMAIN_ES	0x31
451#define	AWI_REG_DOMAIN_FR	0x32
452#define	AWI_REG_DOMAIN_JP	0x40
453	u_int8_t	aPreamble_Lngth;
454	u_int8_t	aPLCP_Hdr_Lngth;
455	u_int8_t	Pwr_Up_Time[AWI_PWR_LEVEL_SIZE][2];
456	u_int8_t	IEEE_PHY_Type;
457#define	AWI_PHY_TYPE_FH		1
458#define	AWI_PHY_TYPE_DS		2
459#define	AWI_PHY_TYPE_IR		3
460	u_int8_t	RCR_33A_Bits[8];
461} __packed;
462
463#endif /* _DEV_IC_AWIREG_H */
464