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bcmgenet.c revision 1.3
      1  1.3  jmcneill /* $NetBSD: bcmgenet.c,v 1.3 2020/02/27 17:30:07 jmcneill Exp $ */
      2  1.1  jmcneill 
      3  1.1  jmcneill /*-
      4  1.1  jmcneill  * Copyright (c) 2020 Jared McNeill <jmcneill (at) invisible.ca>
      5  1.1  jmcneill  * All rights reserved.
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8  1.1  jmcneill  * modification, are permitted provided that the following conditions
      9  1.1  jmcneill  * are met:
     10  1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12  1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15  1.1  jmcneill  *
     16  1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1  jmcneill  * SUCH DAMAGE.
     27  1.1  jmcneill  */
     28  1.1  jmcneill 
     29  1.1  jmcneill /*
     30  1.1  jmcneill  * Broadcom GENETv5
     31  1.1  jmcneill  */
     32  1.1  jmcneill 
     33  1.1  jmcneill #include "opt_net_mpsafe.h"
     34  1.1  jmcneill #include "opt_ddb.h"
     35  1.1  jmcneill 
     36  1.1  jmcneill #include <sys/cdefs.h>
     37  1.3  jmcneill __KERNEL_RCSID(0, "$NetBSD: bcmgenet.c,v 1.3 2020/02/27 17:30:07 jmcneill Exp $");
     38  1.1  jmcneill 
     39  1.1  jmcneill #include <sys/param.h>
     40  1.1  jmcneill #include <sys/bus.h>
     41  1.1  jmcneill #include <sys/device.h>
     42  1.1  jmcneill #include <sys/intr.h>
     43  1.1  jmcneill #include <sys/systm.h>
     44  1.1  jmcneill #include <sys/kernel.h>
     45  1.1  jmcneill #include <sys/mutex.h>
     46  1.1  jmcneill #include <sys/callout.h>
     47  1.1  jmcneill #include <sys/cprng.h>
     48  1.1  jmcneill 
     49  1.1  jmcneill #include <net/if.h>
     50  1.1  jmcneill #include <net/if_dl.h>
     51  1.1  jmcneill #include <net/if_ether.h>
     52  1.1  jmcneill #include <net/if_media.h>
     53  1.1  jmcneill #include <net/bpf.h>
     54  1.1  jmcneill 
     55  1.1  jmcneill #include <dev/mii/miivar.h>
     56  1.1  jmcneill 
     57  1.1  jmcneill #include <dev/ic/bcmgenetreg.h>
     58  1.1  jmcneill #include <dev/ic/bcmgenetvar.h>
     59  1.1  jmcneill 
     60  1.1  jmcneill CTASSERT(MCLBYTES == 2048);
     61  1.1  jmcneill 
     62  1.1  jmcneill #ifdef GENET_DEBUG
     63  1.1  jmcneill #define	DPRINTF(...)	printf(##__VA_ARGS__)
     64  1.1  jmcneill #else
     65  1.1  jmcneill #define	DPRINTF(...)	((void)0)
     66  1.1  jmcneill #endif
     67  1.1  jmcneill 
     68  1.1  jmcneill #ifdef NET_MPSAFE
     69  1.1  jmcneill #define	GENET_MPSAFE		1
     70  1.1  jmcneill #define	CALLOUT_FLAGS		CALLOUT_MPSAFE
     71  1.1  jmcneill #else
     72  1.1  jmcneill #define	CALLOUT_FLAGS		0
     73  1.1  jmcneill #endif
     74  1.1  jmcneill 
     75  1.1  jmcneill #define	TX_SKIP(n, o)		(((n) + (o)) & (GENET_DMA_DESC_COUNT - 1))
     76  1.1  jmcneill #define	TX_NEXT(n)		TX_SKIP(n, 1)
     77  1.1  jmcneill #define	RX_NEXT(n)		(((n) + 1) & (GENET_DMA_DESC_COUNT - 1))
     78  1.1  jmcneill 
     79  1.1  jmcneill #define	TX_MAX_SEGS		128
     80  1.1  jmcneill #define	TX_DESC_COUNT		GENET_DMA_DESC_COUNT
     81  1.1  jmcneill #define	RX_DESC_COUNT		GENET_DMA_DESC_COUNT
     82  1.1  jmcneill #define	MII_BUSY_RETRY		1000
     83  1.2  jmcneill #define	GENET_MAX_MDF_FILTER	17
     84  1.1  jmcneill 
     85  1.1  jmcneill #define	GENET_LOCK(sc)		mutex_enter(&(sc)->sc_lock)
     86  1.1  jmcneill #define	GENET_UNLOCK(sc)	mutex_exit(&(sc)->sc_lock)
     87  1.1  jmcneill #define	GENET_ASSERT_LOCKED(sc)	KASSERT(mutex_owned(&(sc)->sc_lock))
     88  1.1  jmcneill 
     89  1.1  jmcneill #define	RD4(sc, reg)			\
     90  1.1  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
     91  1.1  jmcneill #define	WR4(sc, reg, val)		\
     92  1.1  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
     93  1.1  jmcneill 
     94  1.1  jmcneill static int
     95  1.1  jmcneill genet_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)
     96  1.1  jmcneill {
     97  1.1  jmcneill 	struct genet_softc *sc = device_private(dev);
     98  1.1  jmcneill 	int retry;
     99  1.1  jmcneill 
    100  1.1  jmcneill 	WR4(sc, GENET_MDIO_CMD,
    101  1.1  jmcneill 	    GENET_MDIO_READ | GENET_MDIO_START_BUSY |
    102  1.1  jmcneill 	    __SHIFTIN(phy, GENET_MDIO_PMD) |
    103  1.1  jmcneill 	    __SHIFTIN(reg, GENET_MDIO_REG));
    104  1.1  jmcneill 	for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
    105  1.1  jmcneill 		if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) {
    106  1.1  jmcneill 			*val = RD4(sc, GENET_MDIO_CMD) & 0xffff;
    107  1.1  jmcneill 			break;
    108  1.1  jmcneill 		}
    109  1.1  jmcneill 		delay(10);
    110  1.1  jmcneill 	}
    111  1.1  jmcneill 
    112  1.1  jmcneill 
    113  1.1  jmcneill 	if (retry == 0) {
    114  1.1  jmcneill 		device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
    115  1.1  jmcneill 		    phy, reg);
    116  1.1  jmcneill 		return ETIMEDOUT;
    117  1.1  jmcneill 	}
    118  1.1  jmcneill 
    119  1.1  jmcneill 	return 0;
    120  1.1  jmcneill }
    121  1.1  jmcneill 
    122  1.1  jmcneill static int
    123  1.1  jmcneill genet_mii_writereg(device_t dev, int phy, int reg, uint16_t val)
    124  1.1  jmcneill {
    125  1.1  jmcneill 	struct genet_softc *sc = device_private(dev);
    126  1.1  jmcneill 	int retry;
    127  1.1  jmcneill 
    128  1.1  jmcneill 	WR4(sc, GENET_MDIO_CMD,
    129  1.1  jmcneill 	    val | GENET_MDIO_WRITE | GENET_MDIO_START_BUSY |
    130  1.1  jmcneill 	    __SHIFTIN(phy, GENET_MDIO_PMD) |
    131  1.1  jmcneill 	    __SHIFTIN(reg, GENET_MDIO_REG));
    132  1.1  jmcneill 	for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
    133  1.1  jmcneill 		if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)
    134  1.1  jmcneill 			break;
    135  1.1  jmcneill 		delay(10);
    136  1.1  jmcneill 	}
    137  1.1  jmcneill 
    138  1.1  jmcneill 	if (retry == 0) {
    139  1.1  jmcneill 		device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
    140  1.1  jmcneill 		    phy, reg);
    141  1.1  jmcneill 		return ETIMEDOUT;
    142  1.1  jmcneill 	}
    143  1.1  jmcneill 
    144  1.1  jmcneill 	return 0;
    145  1.1  jmcneill }
    146  1.1  jmcneill 
    147  1.1  jmcneill static void
    148  1.1  jmcneill genet_update_link(struct genet_softc *sc)
    149  1.1  jmcneill {
    150  1.1  jmcneill 	struct mii_data *mii = &sc->sc_mii;
    151  1.1  jmcneill 	uint32_t val;
    152  1.1  jmcneill 	u_int speed;
    153  1.1  jmcneill 
    154  1.1  jmcneill 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
    155  1.1  jmcneill 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
    156  1.1  jmcneill 		speed = GENET_UMAC_CMD_SPEED_1000;
    157  1.1  jmcneill 	else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
    158  1.1  jmcneill 		speed = GENET_UMAC_CMD_SPEED_100;
    159  1.1  jmcneill 	else
    160  1.1  jmcneill 		speed = GENET_UMAC_CMD_SPEED_10;
    161  1.1  jmcneill 
    162  1.1  jmcneill 	val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
    163  1.1  jmcneill 	val &= ~GENET_EXT_RGMII_OOB_OOB_DISABLE;
    164  1.1  jmcneill 	val |= GENET_EXT_RGMII_OOB_RGMII_LINK;
    165  1.1  jmcneill 	val |= GENET_EXT_RGMII_OOB_RGMII_MODE_EN;
    166  1.1  jmcneill 	if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII)
    167  1.1  jmcneill 		val |= GENET_EXT_RGMII_OOB_ID_MODE_DISABLE;
    168  1.1  jmcneill 	WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
    169  1.1  jmcneill 
    170  1.1  jmcneill 	val = RD4(sc, GENET_UMAC_CMD);
    171  1.1  jmcneill 	val &= ~GENET_UMAC_CMD_SPEED;
    172  1.1  jmcneill 	val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED);
    173  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, val);
    174  1.1  jmcneill }
    175  1.1  jmcneill 
    176  1.1  jmcneill static void
    177  1.1  jmcneill genet_mii_statchg(struct ifnet *ifp)
    178  1.1  jmcneill {
    179  1.1  jmcneill 	struct genet_softc * const sc = ifp->if_softc;
    180  1.1  jmcneill 
    181  1.1  jmcneill 	genet_update_link(sc);
    182  1.1  jmcneill }
    183  1.1  jmcneill 
    184  1.1  jmcneill static void
    185  1.1  jmcneill genet_setup_txdesc(struct genet_softc *sc, int index, int flags,
    186  1.1  jmcneill     bus_addr_t paddr, u_int len)
    187  1.1  jmcneill {
    188  1.1  jmcneill 	uint32_t status;
    189  1.1  jmcneill 
    190  1.1  jmcneill 	status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN);
    191  1.1  jmcneill 	++sc->sc_tx.queued;
    192  1.1  jmcneill 
    193  1.1  jmcneill 	WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
    194  1.1  jmcneill 	WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
    195  1.1  jmcneill 	WR4(sc, GENET_TX_DESC_STATUS(index), status);
    196  1.1  jmcneill }
    197  1.1  jmcneill 
    198  1.1  jmcneill static int
    199  1.1  jmcneill genet_setup_txbuf(struct genet_softc *sc, int index, struct mbuf *m)
    200  1.1  jmcneill {
    201  1.1  jmcneill 	bus_dma_segment_t *segs;
    202  1.1  jmcneill 	int error, nsegs, cur, i;
    203  1.1  jmcneill 	uint32_t flags;
    204  1.1  jmcneill 
    205  1.1  jmcneill 	error = bus_dmamap_load_mbuf(sc->sc_tx.buf_tag,
    206  1.1  jmcneill 	    sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
    207  1.1  jmcneill 	if (error == EFBIG) {
    208  1.1  jmcneill 		device_printf(sc->sc_dev,
    209  1.1  jmcneill 		    "TX packet needs too many DMA segments, dropping...\n");
    210  1.1  jmcneill 		m_freem(m);
    211  1.1  jmcneill 		return 0;
    212  1.1  jmcneill 	}
    213  1.1  jmcneill 	if (error != 0)
    214  1.1  jmcneill 		return 0;
    215  1.1  jmcneill 
    216  1.1  jmcneill 	segs = sc->sc_tx.buf_map[index].map->dm_segs;
    217  1.1  jmcneill 	nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs;
    218  1.1  jmcneill 
    219  1.1  jmcneill 	if (sc->sc_tx.queued >= GENET_DMA_DESC_COUNT - nsegs) {
    220  1.1  jmcneill 		bus_dmamap_unload(sc->sc_tx.buf_tag,
    221  1.1  jmcneill 		    sc->sc_tx.buf_map[index].map);
    222  1.1  jmcneill 		return -1;
    223  1.1  jmcneill 	}
    224  1.1  jmcneill 
    225  1.1  jmcneill 	flags = GENET_TX_DESC_STATUS_SOP |
    226  1.1  jmcneill 		GENET_TX_DESC_STATUS_CRC |
    227  1.1  jmcneill 		GENET_TX_DESC_STATUS_QTAG;
    228  1.1  jmcneill 
    229  1.1  jmcneill 	for (cur = index, i = 0; i < nsegs; i++) {
    230  1.1  jmcneill 		sc->sc_tx.buf_map[cur].mbuf = (i == 0 ? m : NULL);
    231  1.1  jmcneill 		if (i == nsegs - 1)
    232  1.1  jmcneill 			flags |= GENET_TX_DESC_STATUS_EOP;
    233  1.1  jmcneill 
    234  1.1  jmcneill 		genet_setup_txdesc(sc, cur, flags, segs[i].ds_addr,
    235  1.1  jmcneill 		    segs[i].ds_len);
    236  1.1  jmcneill 
    237  1.1  jmcneill 		if (i == 0) {
    238  1.1  jmcneill 			flags &= ~GENET_TX_DESC_STATUS_SOP;
    239  1.1  jmcneill 			flags &= ~GENET_TX_DESC_STATUS_CRC;
    240  1.1  jmcneill 		}
    241  1.1  jmcneill 		cur = TX_NEXT(cur);
    242  1.1  jmcneill 	}
    243  1.1  jmcneill 
    244  1.1  jmcneill 	bus_dmamap_sync(sc->sc_tx.buf_tag, sc->sc_tx.buf_map[index].map,
    245  1.1  jmcneill 	    0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE);
    246  1.1  jmcneill 
    247  1.1  jmcneill 	return nsegs;
    248  1.1  jmcneill }
    249  1.1  jmcneill 
    250  1.1  jmcneill static void
    251  1.1  jmcneill genet_setup_rxdesc(struct genet_softc *sc, int index,
    252  1.1  jmcneill     bus_addr_t paddr, bus_size_t len)
    253  1.1  jmcneill {
    254  1.1  jmcneill 	WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
    255  1.1  jmcneill 	WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
    256  1.1  jmcneill }
    257  1.1  jmcneill 
    258  1.1  jmcneill static int
    259  1.1  jmcneill genet_setup_rxbuf(struct genet_softc *sc, int index, struct mbuf *m)
    260  1.1  jmcneill {
    261  1.1  jmcneill 	int error;
    262  1.1  jmcneill 
    263  1.1  jmcneill 	error = bus_dmamap_load_mbuf(sc->sc_rx.buf_tag,
    264  1.1  jmcneill 	    sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT);
    265  1.1  jmcneill 	if (error != 0)
    266  1.1  jmcneill 		return error;
    267  1.1  jmcneill 
    268  1.1  jmcneill 	bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map,
    269  1.1  jmcneill 	    0, sc->sc_rx.buf_map[index].map->dm_mapsize,
    270  1.1  jmcneill 	    BUS_DMASYNC_PREREAD);
    271  1.1  jmcneill 
    272  1.1  jmcneill 	sc->sc_rx.buf_map[index].mbuf = m;
    273  1.1  jmcneill 	genet_setup_rxdesc(sc, index,
    274  1.1  jmcneill 	    sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr,
    275  1.1  jmcneill 	    sc->sc_rx.buf_map[index].map->dm_segs[0].ds_len);
    276  1.1  jmcneill 
    277  1.1  jmcneill 	return 0;
    278  1.1  jmcneill }
    279  1.1  jmcneill 
    280  1.1  jmcneill static struct mbuf *
    281  1.1  jmcneill genet_alloc_mbufcl(struct genet_softc *sc)
    282  1.1  jmcneill {
    283  1.1  jmcneill 	struct mbuf *m;
    284  1.1  jmcneill 
    285  1.1  jmcneill 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
    286  1.1  jmcneill 	if (m != NULL)
    287  1.1  jmcneill 		m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
    288  1.1  jmcneill 
    289  1.1  jmcneill 	return m;
    290  1.1  jmcneill }
    291  1.1  jmcneill 
    292  1.1  jmcneill static void
    293  1.1  jmcneill genet_enable_intr(struct genet_softc *sc)
    294  1.1  jmcneill {
    295  1.1  jmcneill 	WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
    296  1.1  jmcneill 	    GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
    297  1.1  jmcneill }
    298  1.1  jmcneill 
    299  1.1  jmcneill static void
    300  1.1  jmcneill genet_disable_intr(struct genet_softc *sc)
    301  1.1  jmcneill {
    302  1.1  jmcneill 	/* Disable interrupts */
    303  1.1  jmcneill 	WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
    304  1.1  jmcneill 	WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff);
    305  1.1  jmcneill }
    306  1.1  jmcneill 
    307  1.1  jmcneill static void
    308  1.1  jmcneill genet_tick(void *softc)
    309  1.1  jmcneill {
    310  1.1  jmcneill 	struct genet_softc *sc = softc;
    311  1.1  jmcneill 	struct mii_data *mii = &sc->sc_mii;
    312  1.1  jmcneill #ifndef GENET_MPSAFE
    313  1.1  jmcneill 	int s = splnet();
    314  1.1  jmcneill #endif
    315  1.1  jmcneill 
    316  1.1  jmcneill 	GENET_LOCK(sc);
    317  1.1  jmcneill 	mii_tick(mii);
    318  1.1  jmcneill 	callout_schedule(&sc->sc_stat_ch, hz);
    319  1.1  jmcneill 	GENET_UNLOCK(sc);
    320  1.1  jmcneill 
    321  1.1  jmcneill #ifndef GENET_MPSAFE
    322  1.1  jmcneill 	splx(s);
    323  1.1  jmcneill #endif
    324  1.1  jmcneill }
    325  1.1  jmcneill 
    326  1.1  jmcneill static void
    327  1.2  jmcneill genet_setup_rxfilter_mdf(struct genet_softc *sc, u_int n, const uint8_t *ea)
    328  1.2  jmcneill {
    329  1.2  jmcneill 	uint32_t addr0 = (ea[0] << 8) | ea[1];
    330  1.2  jmcneill 	uint32_t addr1 = (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5];
    331  1.2  jmcneill 
    332  1.2  jmcneill 	WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
    333  1.2  jmcneill 	WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
    334  1.2  jmcneill }
    335  1.2  jmcneill 
    336  1.2  jmcneill static void
    337  1.1  jmcneill genet_setup_rxfilter(struct genet_softc *sc)
    338  1.1  jmcneill {
    339  1.2  jmcneill 	struct ethercom *ec = &sc->sc_ec;
    340  1.2  jmcneill 	struct ifnet *ifp = &ec->ec_if;
    341  1.2  jmcneill 	struct ether_multistep step;
    342  1.2  jmcneill 	struct ether_multi *enm;
    343  1.2  jmcneill 	uint32_t cmd, mdf_ctrl;
    344  1.2  jmcneill 	u_int n;
    345  1.1  jmcneill 
    346  1.1  jmcneill 	GENET_ASSERT_LOCKED(sc);
    347  1.1  jmcneill 
    348  1.2  jmcneill 	ETHER_LOCK(ec);
    349  1.2  jmcneill 
    350  1.2  jmcneill 	cmd = RD4(sc, GENET_UMAC_CMD);
    351  1.2  jmcneill 
    352  1.2  jmcneill 	/*
    353  1.2  jmcneill 	 * Count the required number of hardware filters. We need one
    354  1.2  jmcneill 	 * for each multicast address, plus one for our own address and
    355  1.2  jmcneill 	 * the broadcast address.
    356  1.2  jmcneill 	 */
    357  1.2  jmcneill 	ETHER_FIRST_MULTI(step, ec, enm);
    358  1.2  jmcneill 	for (n = 2; enm != NULL; n++)
    359  1.2  jmcneill 		ETHER_NEXT_MULTI(step, enm);
    360  1.2  jmcneill 
    361  1.2  jmcneill 	if (n > GENET_MAX_MDF_FILTER)
    362  1.2  jmcneill 		ifp->if_flags |= IFF_ALLMULTI;
    363  1.2  jmcneill 	else
    364  1.2  jmcneill 		ifp->if_flags &= ~IFF_ALLMULTI;
    365  1.2  jmcneill 
    366  1.2  jmcneill 	if ((ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) {
    367  1.2  jmcneill 		cmd |= GENET_UMAC_CMD_PROMISC;
    368  1.2  jmcneill 		mdf_ctrl = 0;
    369  1.2  jmcneill 	} else {
    370  1.2  jmcneill 		cmd &= ~GENET_UMAC_CMD_PROMISC;
    371  1.2  jmcneill 		genet_setup_rxfilter_mdf(sc, 0, ifp->if_broadcastaddr);
    372  1.2  jmcneill 		genet_setup_rxfilter_mdf(sc, 1, CLLADDR(ifp->if_sadl));
    373  1.2  jmcneill 		ETHER_FIRST_MULTI(step, ec, enm);
    374  1.2  jmcneill 		for (n = 2; enm != NULL; n++) {
    375  1.2  jmcneill 			genet_setup_rxfilter_mdf(sc, n, enm->enm_addrlo);
    376  1.2  jmcneill 			ETHER_NEXT_MULTI(step, enm);
    377  1.2  jmcneill 		}
    378  1.2  jmcneill 		mdf_ctrl = __BITS(GENET_MAX_MDF_FILTER - 1,
    379  1.2  jmcneill 				  GENET_MAX_MDF_FILTER - n);
    380  1.2  jmcneill 	}
    381  1.2  jmcneill 
    382  1.2  jmcneill 	WR4(sc, GENET_UMAC_CMD, cmd);
    383  1.2  jmcneill 	WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
    384  1.1  jmcneill 
    385  1.2  jmcneill 	ETHER_UNLOCK(ec);
    386  1.1  jmcneill }
    387  1.1  jmcneill 
    388  1.1  jmcneill static int
    389  1.1  jmcneill genet_reset(struct genet_softc *sc)
    390  1.1  jmcneill {
    391  1.1  jmcneill 	uint32_t val;
    392  1.1  jmcneill 
    393  1.1  jmcneill 	val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
    394  1.1  jmcneill 	val |= GENET_SYS_RBUF_FLUSH_RESET;
    395  1.1  jmcneill 	WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
    396  1.1  jmcneill 	delay(10);
    397  1.1  jmcneill 
    398  1.1  jmcneill 	val &= ~GENET_SYS_RBUF_FLUSH_RESET;
    399  1.1  jmcneill 	WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
    400  1.1  jmcneill 	delay(10);
    401  1.1  jmcneill 
    402  1.1  jmcneill 	WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
    403  1.1  jmcneill 	delay(10);
    404  1.1  jmcneill 
    405  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, 0);
    406  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD,
    407  1.1  jmcneill 	    GENET_UMAC_CMD_LCL_LOOP_EN | GENET_UMAC_CMD_SW_RESET);
    408  1.1  jmcneill 	delay(10);
    409  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, 0);
    410  1.1  jmcneill 
    411  1.1  jmcneill 	WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
    412  1.1  jmcneill 	    GENET_UMAC_MIB_RESET_RX | GENET_UMAC_MIB_RESET_TX);
    413  1.1  jmcneill 	WR4(sc, GENET_UMAC_MIB_CTRL, 0);
    414  1.1  jmcneill 
    415  1.1  jmcneill 	WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
    416  1.1  jmcneill 
    417  1.1  jmcneill 	val = RD4(sc, GENET_RBUF_CTRL);
    418  1.1  jmcneill 	val |= GENET_RBUF_ALIGN_2B;
    419  1.1  jmcneill 	WR4(sc, GENET_RBUF_CTRL, val);
    420  1.1  jmcneill 
    421  1.1  jmcneill 	WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
    422  1.1  jmcneill 
    423  1.1  jmcneill 	return 0;
    424  1.1  jmcneill }
    425  1.1  jmcneill 
    426  1.1  jmcneill static void
    427  1.1  jmcneill genet_init_rings(struct genet_softc *sc, int qid)
    428  1.1  jmcneill {
    429  1.1  jmcneill 	uint32_t val;
    430  1.1  jmcneill 
    431  1.1  jmcneill 	/* TX ring */
    432  1.1  jmcneill 
    433  1.1  jmcneill 	sc->sc_tx.queued = 0;
    434  1.1  jmcneill 	sc->sc_tx.cidx = sc->sc_tx.pidx = 0;
    435  1.1  jmcneill 
    436  1.1  jmcneill 	WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
    437  1.1  jmcneill 
    438  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
    439  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
    440  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
    441  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
    442  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
    443  1.1  jmcneill 	    __SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) |
    444  1.1  jmcneill 	    __SHIFTIN(MCLBYTES, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH));
    445  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
    446  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
    447  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
    448  1.1  jmcneill 	    TX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
    449  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
    450  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), 1);
    451  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
    452  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
    453  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
    454  1.1  jmcneill 
    455  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid));	/* enable */
    456  1.1  jmcneill 
    457  1.1  jmcneill 	/* Enable transmit DMA */
    458  1.1  jmcneill 	val = RD4(sc, GENET_TX_DMA_CTRL);
    459  1.1  jmcneill 	val |= GENET_TX_DMA_CTRL_EN;
    460  1.1  jmcneill 	val |= GENET_TX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE);
    461  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_CTRL, val);
    462  1.1  jmcneill 
    463  1.1  jmcneill 	/* RX ring */
    464  1.1  jmcneill 
    465  1.1  jmcneill 	sc->sc_rx.cidx = sc->sc_rx.pidx = 0;
    466  1.1  jmcneill 
    467  1.1  jmcneill 	WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
    468  1.1  jmcneill 
    469  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
    470  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
    471  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
    472  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
    473  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
    474  1.1  jmcneill 	    __SHIFTIN(RX_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) |
    475  1.1  jmcneill 	    __SHIFTIN(MCLBYTES, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH));
    476  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
    477  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
    478  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
    479  1.1  jmcneill 	    RX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
    480  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
    481  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
    482  1.1  jmcneill 	    __SHIFTIN(5, GENET_RX_DMA_XON_XOFF_THRES_LO) |
    483  1.1  jmcneill 	    __SHIFTIN(RX_DESC_COUNT >> 4, GENET_RX_DMA_XON_XOFF_THRES_HI));
    484  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
    485  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
    486  1.1  jmcneill 
    487  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid));	/* enable */
    488  1.1  jmcneill 
    489  1.1  jmcneill 	/* Enable receive DMA */
    490  1.1  jmcneill 	val = RD4(sc, GENET_RX_DMA_CTRL);
    491  1.1  jmcneill 	val |= GENET_RX_DMA_CTRL_EN;
    492  1.1  jmcneill 	val |= GENET_RX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE);
    493  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_CTRL, val);
    494  1.1  jmcneill }
    495  1.1  jmcneill 
    496  1.1  jmcneill static int
    497  1.1  jmcneill genet_init_locked(struct genet_softc *sc)
    498  1.1  jmcneill {
    499  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    500  1.1  jmcneill 	struct mii_data *mii = &sc->sc_mii;
    501  1.1  jmcneill 	uint32_t val;
    502  1.1  jmcneill 	const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
    503  1.1  jmcneill 
    504  1.1  jmcneill 	GENET_ASSERT_LOCKED(sc);
    505  1.1  jmcneill 
    506  1.1  jmcneill 	if ((ifp->if_flags & IFF_RUNNING) != 0)
    507  1.1  jmcneill 		return 0;
    508  1.1  jmcneill 
    509  1.1  jmcneill 	if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII ||
    510  1.1  jmcneill 	    sc->sc_phy_mode == GENET_PHY_MODE_RGMII_RXID)
    511  1.1  jmcneill 		WR4(sc, GENET_SYS_PORT_CTRL,
    512  1.1  jmcneill 		    GENET_SYS_PORT_MODE_EXT_GPHY);
    513  1.1  jmcneill 
    514  1.1  jmcneill 	/* Write hardware address */
    515  1.2  jmcneill 	val = enaddr[3] | (enaddr[2] << 8) | (enaddr[1] << 16) |
    516  1.2  jmcneill 	    (enaddr[0] << 24);
    517  1.1  jmcneill 	WR4(sc, GENET_UMAC_MAC0, val);
    518  1.2  jmcneill 	val = enaddr[5] | (enaddr[4] << 8);
    519  1.1  jmcneill 	WR4(sc, GENET_UMAC_MAC1, val);
    520  1.1  jmcneill 
    521  1.1  jmcneill 	/* Setup RX filter */
    522  1.1  jmcneill 	genet_setup_rxfilter(sc);
    523  1.1  jmcneill 
    524  1.1  jmcneill 	/* Setup TX/RX rings */
    525  1.1  jmcneill 	genet_init_rings(sc, GENET_DMA_DEFAULT_QUEUE);
    526  1.1  jmcneill 
    527  1.1  jmcneill 	/* Enable transmitter and receiver */
    528  1.1  jmcneill 	val = RD4(sc, GENET_UMAC_CMD);
    529  1.1  jmcneill 	val |= GENET_UMAC_CMD_TXEN;
    530  1.1  jmcneill 	val |= GENET_UMAC_CMD_RXEN;
    531  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, val);
    532  1.1  jmcneill 
    533  1.1  jmcneill 	/* Enable interrupts */
    534  1.1  jmcneill 	genet_enable_intr(sc);
    535  1.1  jmcneill 
    536  1.1  jmcneill 	ifp->if_flags |= IFF_RUNNING;
    537  1.1  jmcneill 	ifp->if_flags &= ~IFF_OACTIVE;
    538  1.1  jmcneill 
    539  1.1  jmcneill 	mii_mediachg(mii);
    540  1.1  jmcneill 	callout_schedule(&sc->sc_stat_ch, hz);
    541  1.1  jmcneill 
    542  1.1  jmcneill 	return 0;
    543  1.1  jmcneill }
    544  1.1  jmcneill 
    545  1.1  jmcneill static int
    546  1.1  jmcneill genet_init(struct ifnet *ifp)
    547  1.1  jmcneill {
    548  1.1  jmcneill 	struct genet_softc *sc = ifp->if_softc;
    549  1.1  jmcneill 	int error;
    550  1.1  jmcneill 
    551  1.1  jmcneill 	GENET_LOCK(sc);
    552  1.1  jmcneill 	error = genet_init_locked(sc);
    553  1.1  jmcneill 	GENET_UNLOCK(sc);
    554  1.1  jmcneill 
    555  1.1  jmcneill 	return error;
    556  1.1  jmcneill }
    557  1.1  jmcneill 
    558  1.1  jmcneill static void
    559  1.1  jmcneill genet_stop_locked(struct genet_softc *sc, int disable)
    560  1.1  jmcneill {
    561  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    562  1.1  jmcneill 	uint32_t val;
    563  1.1  jmcneill 
    564  1.1  jmcneill 	GENET_ASSERT_LOCKED(sc);
    565  1.1  jmcneill 
    566  1.1  jmcneill 	callout_stop(&sc->sc_stat_ch);
    567  1.1  jmcneill 
    568  1.1  jmcneill 	mii_down(&sc->sc_mii);
    569  1.1  jmcneill 
    570  1.1  jmcneill 	/* Disable receiver */
    571  1.1  jmcneill 	val = RD4(sc, GENET_UMAC_CMD);
    572  1.1  jmcneill 	val &= ~GENET_UMAC_CMD_RXEN;
    573  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, val);
    574  1.1  jmcneill 
    575  1.1  jmcneill 	/* Stop receive DMA */
    576  1.1  jmcneill 	val = RD4(sc, GENET_RX_DMA_CTRL);
    577  1.1  jmcneill 	val &= ~GENET_RX_DMA_CTRL_EN;
    578  1.1  jmcneill 	WR4(sc, GENET_RX_DMA_CTRL, val);
    579  1.1  jmcneill 
    580  1.1  jmcneill 	/* Stop transmit DMA */
    581  1.1  jmcneill 	val = RD4(sc, GENET_TX_DMA_CTRL);
    582  1.1  jmcneill 	val &= ~GENET_TX_DMA_CTRL_EN;
    583  1.1  jmcneill 	WR4(sc, GENET_TX_DMA_CTRL, val);
    584  1.1  jmcneill 
    585  1.1  jmcneill 	/* Flush data in the TX FIFO */
    586  1.1  jmcneill 	WR4(sc, GENET_UMAC_TX_FLUSH, 1);
    587  1.1  jmcneill 	delay(10);
    588  1.1  jmcneill 	WR4(sc, GENET_UMAC_TX_FLUSH, 0);
    589  1.1  jmcneill 
    590  1.1  jmcneill 	/* Disable transmitter */
    591  1.1  jmcneill 	val = RD4(sc, GENET_UMAC_CMD);
    592  1.1  jmcneill 	val &= ~GENET_UMAC_CMD_TXEN;
    593  1.1  jmcneill 	WR4(sc, GENET_UMAC_CMD, val);
    594  1.1  jmcneill 
    595  1.1  jmcneill 	/* Disable interrupts */
    596  1.1  jmcneill 	genet_disable_intr(sc);
    597  1.1  jmcneill 
    598  1.1  jmcneill 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
    599  1.1  jmcneill }
    600  1.1  jmcneill 
    601  1.1  jmcneill static void
    602  1.1  jmcneill genet_stop(struct ifnet *ifp, int disable)
    603  1.1  jmcneill {
    604  1.1  jmcneill 	struct genet_softc * const sc = ifp->if_softc;
    605  1.1  jmcneill 
    606  1.1  jmcneill 	GENET_LOCK(sc);
    607  1.1  jmcneill 	genet_stop_locked(sc, disable);
    608  1.1  jmcneill 	GENET_UNLOCK(sc);
    609  1.1  jmcneill }
    610  1.1  jmcneill 
    611  1.1  jmcneill static void
    612  1.1  jmcneill genet_rxintr(struct genet_softc *sc, int qid)
    613  1.1  jmcneill {
    614  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    615  1.1  jmcneill 	int error, index, len, n;
    616  1.1  jmcneill 	struct mbuf *m, *m0;
    617  1.1  jmcneill 	uint32_t status, pidx, total;
    618  1.1  jmcneill 
    619  1.1  jmcneill 	pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff;
    620  1.1  jmcneill 	total = (pidx - sc->sc_rx.cidx) & 0xffff;
    621  1.1  jmcneill 
    622  1.1  jmcneill 	DPRINTF("RX pidx=%08x total=%d\n", pidx, total);
    623  1.1  jmcneill 
    624  1.1  jmcneill 	index = sc->sc_rx.cidx & (RX_DESC_COUNT - 1);
    625  1.1  jmcneill 	for (n = 0; n < total; n++) {
    626  1.1  jmcneill 		status = RD4(sc, GENET_RX_DESC_STATUS(index));
    627  1.1  jmcneill 		len = __SHIFTOUT(status, GENET_RX_DESC_STATUS_BUFLEN);
    628  1.1  jmcneill 
    629  1.1  jmcneill 		/* XXX check for errors */
    630  1.1  jmcneill 
    631  1.1  jmcneill 		bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map,
    632  1.1  jmcneill 		    0, sc->sc_rx.buf_map[index].map->dm_mapsize,
    633  1.1  jmcneill 		    BUS_DMASYNC_POSTREAD);
    634  1.1  jmcneill 		bus_dmamap_unload(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map);
    635  1.1  jmcneill 
    636  1.1  jmcneill 		DPRINTF("RX [#%d] index=%02x status=%08x len=%d adj_len=%d\n",
    637  1.1  jmcneill 		    n, index, status, len, len - ETHER_ALIGN);
    638  1.1  jmcneill 
    639  1.1  jmcneill 		if (len > ETHER_ALIGN) {
    640  1.1  jmcneill 			m = sc->sc_rx.buf_map[index].mbuf;
    641  1.1  jmcneill 
    642  1.1  jmcneill 			m_adj(m, ETHER_ALIGN);
    643  1.1  jmcneill 
    644  1.1  jmcneill 			m_set_rcvif(m, ifp);
    645  1.1  jmcneill 			m->m_len = m->m_pkthdr.len = len - ETHER_ALIGN;
    646  1.1  jmcneill 			m->m_nextpkt = NULL;
    647  1.1  jmcneill 
    648  1.1  jmcneill 			if_percpuq_enqueue(ifp->if_percpuq, m);
    649  1.1  jmcneill 		}
    650  1.1  jmcneill 
    651  1.1  jmcneill 		if ((m0 = genet_alloc_mbufcl(sc)) != NULL) {
    652  1.1  jmcneill 			error = genet_setup_rxbuf(sc, index, m0);
    653  1.1  jmcneill 			if (error != 0) {
    654  1.1  jmcneill 				/* XXX hole in RX ring */
    655  1.1  jmcneill 			}
    656  1.1  jmcneill 		} else {
    657  1.1  jmcneill 			if_statinc(ifp, if_ierrors);
    658  1.1  jmcneill 		}
    659  1.1  jmcneill 
    660  1.1  jmcneill 		index = RX_NEXT(index);
    661  1.1  jmcneill 
    662  1.1  jmcneill 		sc->sc_rx.cidx = (sc->sc_rx.cidx + 1) & 0xffff;
    663  1.1  jmcneill 		WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
    664  1.1  jmcneill 	}
    665  1.1  jmcneill }
    666  1.1  jmcneill 
    667  1.1  jmcneill static void
    668  1.1  jmcneill genet_txintr(struct genet_softc *sc, int qid)
    669  1.1  jmcneill {
    670  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    671  1.1  jmcneill 	struct genet_bufmap *bmap;
    672  1.1  jmcneill 	uint32_t cidx, total;
    673  1.1  jmcneill 	int i;
    674  1.1  jmcneill 
    675  1.1  jmcneill 	GENET_ASSERT_LOCKED(sc);
    676  1.1  jmcneill 
    677  1.1  jmcneill 	cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff;
    678  1.1  jmcneill 	total = (cidx - sc->sc_tx.cidx) & 0xffff;
    679  1.1  jmcneill 
    680  1.1  jmcneill 	for (i = sc->sc_tx.next; sc->sc_tx.queued > 0 && total > 0; i = TX_NEXT(i), total--) {
    681  1.1  jmcneill 		/* XXX check for errors */
    682  1.1  jmcneill 
    683  1.1  jmcneill 		bmap = &sc->sc_tx.buf_map[i];
    684  1.1  jmcneill 		if (bmap->mbuf != NULL) {
    685  1.1  jmcneill 			bus_dmamap_sync(sc->sc_tx.buf_tag, bmap->map,
    686  1.1  jmcneill 			    0, bmap->map->dm_mapsize,
    687  1.1  jmcneill 			    BUS_DMASYNC_POSTWRITE);
    688  1.1  jmcneill 			bus_dmamap_unload(sc->sc_tx.buf_tag, bmap->map);
    689  1.1  jmcneill 			m_freem(bmap->mbuf);
    690  1.1  jmcneill 			bmap->mbuf = NULL;
    691  1.1  jmcneill 		}
    692  1.1  jmcneill 
    693  1.1  jmcneill 		--sc->sc_tx.queued;
    694  1.1  jmcneill 		ifp->if_flags &= ~IFF_OACTIVE;
    695  1.1  jmcneill 		if_statinc(ifp, if_opackets);
    696  1.1  jmcneill 	}
    697  1.1  jmcneill 
    698  1.1  jmcneill 	sc->sc_tx.next = i;
    699  1.1  jmcneill 	sc->sc_tx.cidx = cidx;
    700  1.1  jmcneill }
    701  1.1  jmcneill 
    702  1.1  jmcneill static void
    703  1.1  jmcneill genet_start_locked(struct genet_softc *sc)
    704  1.1  jmcneill {
    705  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    706  1.1  jmcneill 	struct mbuf *m;
    707  1.1  jmcneill 	int nsegs, index, cnt;
    708  1.1  jmcneill 
    709  1.1  jmcneill 	GENET_ASSERT_LOCKED(sc);
    710  1.1  jmcneill 
    711  1.1  jmcneill 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
    712  1.1  jmcneill 		return;
    713  1.1  jmcneill 
    714  1.1  jmcneill 	const int qid = GENET_DMA_DEFAULT_QUEUE;
    715  1.1  jmcneill 
    716  1.1  jmcneill 	index = sc->sc_tx.pidx & (TX_DESC_COUNT - 1);
    717  1.1  jmcneill 	cnt = 0;
    718  1.1  jmcneill 
    719  1.1  jmcneill 	for (;;) {
    720  1.1  jmcneill 		IFQ_POLL(&ifp->if_snd, m);
    721  1.1  jmcneill 		if (m == NULL)
    722  1.1  jmcneill 			break;
    723  1.1  jmcneill 
    724  1.1  jmcneill 		nsegs = genet_setup_txbuf(sc, index, m);
    725  1.1  jmcneill 		if (nsegs <= 0) {
    726  1.1  jmcneill 			if (nsegs == -1)
    727  1.1  jmcneill 				ifp->if_flags |= IFF_OACTIVE;
    728  1.1  jmcneill 			break;
    729  1.1  jmcneill 		}
    730  1.1  jmcneill 		IFQ_DEQUEUE(&ifp->if_snd, m);
    731  1.1  jmcneill 		bpf_mtap(ifp, m, BPF_D_OUT);
    732  1.1  jmcneill 
    733  1.1  jmcneill 		index = TX_SKIP(index, nsegs);
    734  1.1  jmcneill 
    735  1.1  jmcneill 		sc->sc_tx.pidx = (sc->sc_tx.pidx + nsegs) & 0xffff;
    736  1.1  jmcneill 		cnt++;
    737  1.1  jmcneill 	}
    738  1.1  jmcneill 
    739  1.1  jmcneill 	if (cnt != 0)
    740  1.1  jmcneill 		WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
    741  1.1  jmcneill }
    742  1.1  jmcneill 
    743  1.1  jmcneill static void
    744  1.1  jmcneill genet_start(struct ifnet *ifp)
    745  1.1  jmcneill {
    746  1.1  jmcneill 	struct genet_softc *sc = ifp->if_softc;
    747  1.1  jmcneill 
    748  1.1  jmcneill 	GENET_LOCK(sc);
    749  1.1  jmcneill 	genet_start_locked(sc);
    750  1.1  jmcneill 	GENET_UNLOCK(sc);
    751  1.1  jmcneill }
    752  1.1  jmcneill 
    753  1.1  jmcneill int
    754  1.1  jmcneill genet_intr(void *arg)
    755  1.1  jmcneill {
    756  1.1  jmcneill 	struct genet_softc *sc = arg;
    757  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    758  1.1  jmcneill 	uint32_t val;
    759  1.1  jmcneill 
    760  1.1  jmcneill 	GENET_LOCK(sc);
    761  1.1  jmcneill 
    762  1.1  jmcneill 	val = RD4(sc, GENET_INTRL2_CPU_STAT);
    763  1.1  jmcneill 	val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);
    764  1.1  jmcneill 	WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
    765  1.1  jmcneill 
    766  1.1  jmcneill 	if (val & GENET_IRQ_RXDMA_DONE)
    767  1.1  jmcneill 		genet_rxintr(sc, GENET_DMA_DEFAULT_QUEUE);
    768  1.1  jmcneill 
    769  1.1  jmcneill 	if (val & GENET_IRQ_TXDMA_DONE) {
    770  1.1  jmcneill 		genet_txintr(sc, GENET_DMA_DEFAULT_QUEUE);
    771  1.1  jmcneill 		if_schedule_deferred_start(ifp);
    772  1.1  jmcneill 	}
    773  1.1  jmcneill 
    774  1.1  jmcneill 	GENET_UNLOCK(sc);
    775  1.1  jmcneill 
    776  1.1  jmcneill 	return 1;
    777  1.1  jmcneill }
    778  1.1  jmcneill 
    779  1.1  jmcneill static int
    780  1.1  jmcneill genet_ioctl(struct ifnet *ifp, u_long cmd, void *data)
    781  1.1  jmcneill {
    782  1.1  jmcneill 	struct genet_softc *sc = ifp->if_softc;
    783  1.1  jmcneill 	int error, s;
    784  1.1  jmcneill 
    785  1.1  jmcneill #ifndef GENET_MPSAFE
    786  1.1  jmcneill 	s = splnet();
    787  1.1  jmcneill #endif
    788  1.1  jmcneill 
    789  1.1  jmcneill 	switch (cmd) {
    790  1.1  jmcneill 	default:
    791  1.1  jmcneill #ifdef GENET_MPSAFE
    792  1.1  jmcneill 		s = splnet();
    793  1.1  jmcneill #endif
    794  1.1  jmcneill 		error = ether_ioctl(ifp, cmd, data);
    795  1.1  jmcneill #ifdef GENET_MPSAFE
    796  1.1  jmcneill 		splx(s);
    797  1.1  jmcneill #endif
    798  1.1  jmcneill 		if (error != ENETRESET)
    799  1.1  jmcneill 			break;
    800  1.1  jmcneill 
    801  1.1  jmcneill 		error = 0;
    802  1.1  jmcneill 
    803  1.1  jmcneill 		if (cmd == SIOCSIFCAP)
    804  1.1  jmcneill 			error = (*ifp->if_init)(ifp);
    805  1.1  jmcneill 		else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
    806  1.1  jmcneill 			;
    807  1.1  jmcneill 		else if ((ifp->if_flags & IFF_RUNNING) != 0) {
    808  1.1  jmcneill 			GENET_LOCK(sc);
    809  1.1  jmcneill 			genet_setup_rxfilter(sc);
    810  1.1  jmcneill 			GENET_UNLOCK(sc);
    811  1.1  jmcneill 		}
    812  1.1  jmcneill 		break;
    813  1.1  jmcneill 	}
    814  1.1  jmcneill 
    815  1.1  jmcneill #ifndef GENET_MPSAFE
    816  1.1  jmcneill 	splx(s);
    817  1.1  jmcneill #endif
    818  1.1  jmcneill 
    819  1.1  jmcneill 	return error;
    820  1.1  jmcneill }
    821  1.1  jmcneill 
    822  1.1  jmcneill static void
    823  1.1  jmcneill genet_get_eaddr(struct genet_softc *sc, uint8_t *eaddr)
    824  1.1  jmcneill {
    825  1.1  jmcneill 	prop_dictionary_t prop = device_properties(sc->sc_dev);
    826  1.1  jmcneill 	uint32_t maclo, machi;
    827  1.1  jmcneill 	prop_data_t eaprop;
    828  1.1  jmcneill 
    829  1.1  jmcneill 	eaprop = prop_dictionary_get(prop, "mac-address");
    830  1.1  jmcneill 	if (eaprop == NULL) {
    831  1.1  jmcneill 		/* Create one */
    832  1.1  jmcneill 		maclo = 0x00f2 | (cprng_strong32() & 0xffff0000);
    833  1.1  jmcneill 		machi = cprng_strong32() & 0xffff;
    834  1.1  jmcneill 
    835  1.1  jmcneill 		eaddr[0] = maclo & 0xff;
    836  1.1  jmcneill 		eaddr[1] = (maclo >> 8) & 0xff;
    837  1.1  jmcneill 		eaddr[2] = (maclo >> 16) & 0xff;
    838  1.1  jmcneill 		eaddr[3] = (maclo >> 24) & 0xff;
    839  1.1  jmcneill 		eaddr[4] = machi & 0xff;
    840  1.1  jmcneill 		eaddr[5] = (machi >> 8) & 0xff;
    841  1.1  jmcneill 	} else {
    842  1.1  jmcneill 		KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
    843  1.1  jmcneill 		KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
    844  1.1  jmcneill 		memcpy(eaddr, prop_data_data_nocopy(eaprop),
    845  1.1  jmcneill 		    ETHER_ADDR_LEN);
    846  1.1  jmcneill 	}
    847  1.1  jmcneill 
    848  1.1  jmcneill }
    849  1.1  jmcneill 
    850  1.1  jmcneill static int
    851  1.1  jmcneill genet_setup_dma(struct genet_softc *sc, int qid)
    852  1.1  jmcneill {
    853  1.1  jmcneill 	struct mbuf *m;
    854  1.1  jmcneill 	int error, i;
    855  1.1  jmcneill 
    856  1.1  jmcneill 	/* Setup TX ring */
    857  1.1  jmcneill 	sc->sc_tx.buf_tag = sc->sc_dmat;
    858  1.1  jmcneill 	for (i = 0; i < TX_DESC_COUNT; i++) {
    859  1.1  jmcneill 		error = bus_dmamap_create(sc->sc_tx.buf_tag, MCLBYTES,
    860  1.1  jmcneill 		    TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK,
    861  1.1  jmcneill 		    &sc->sc_tx.buf_map[i].map);
    862  1.1  jmcneill 		if (error != 0) {
    863  1.1  jmcneill 			device_printf(sc->sc_dev,
    864  1.1  jmcneill 			    "cannot create TX buffer map\n");
    865  1.1  jmcneill 			return error;
    866  1.1  jmcneill 		}
    867  1.1  jmcneill 	}
    868  1.1  jmcneill 
    869  1.1  jmcneill 	/* Setup RX ring */
    870  1.1  jmcneill 	sc->sc_rx.buf_tag = sc->sc_dmat;
    871  1.1  jmcneill 	for (i = 0; i < RX_DESC_COUNT; i++) {
    872  1.1  jmcneill 		error = bus_dmamap_create(sc->sc_rx.buf_tag, MCLBYTES,
    873  1.1  jmcneill 		    1, MCLBYTES, 0, BUS_DMA_WAITOK,
    874  1.1  jmcneill 		    &sc->sc_rx.buf_map[i].map);
    875  1.1  jmcneill 		if (error != 0) {
    876  1.1  jmcneill 			device_printf(sc->sc_dev,
    877  1.1  jmcneill 			    "cannot create RX buffer map\n");
    878  1.1  jmcneill 			return error;
    879  1.1  jmcneill 		}
    880  1.1  jmcneill 		if ((m = genet_alloc_mbufcl(sc)) == NULL) {
    881  1.1  jmcneill 			device_printf(sc->sc_dev, "cannot allocate RX mbuf\n");
    882  1.1  jmcneill 			return ENOMEM;
    883  1.1  jmcneill 		}
    884  1.1  jmcneill 		error = genet_setup_rxbuf(sc, i, m);
    885  1.1  jmcneill 		if (error != 0) {
    886  1.1  jmcneill 			device_printf(sc->sc_dev, "cannot create RX buffer\n");
    887  1.1  jmcneill 			return error;
    888  1.1  jmcneill 		}
    889  1.1  jmcneill 	}
    890  1.1  jmcneill 
    891  1.1  jmcneill 	return 0;
    892  1.1  jmcneill }
    893  1.1  jmcneill 
    894  1.1  jmcneill int
    895  1.1  jmcneill genet_attach(struct genet_softc *sc)
    896  1.1  jmcneill {
    897  1.1  jmcneill 	struct mii_data *mii = &sc->sc_mii;
    898  1.1  jmcneill 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    899  1.1  jmcneill 	uint8_t eaddr[ETHER_ADDR_LEN];
    900  1.1  jmcneill 	u_int maj, min;
    901  1.1  jmcneill 
    902  1.1  jmcneill 	const uint32_t rev = RD4(sc, GENET_SYS_REV_CTRL);
    903  1.1  jmcneill 	min = __SHIFTOUT(rev, SYS_REV_MINOR);
    904  1.1  jmcneill 	maj = __SHIFTOUT(rev, SYS_REV_MAJOR);
    905  1.1  jmcneill 	if (maj == 0)
    906  1.1  jmcneill 		maj++;
    907  1.1  jmcneill 	else if (maj == 5 || maj == 6)
    908  1.1  jmcneill 		maj--;
    909  1.1  jmcneill 
    910  1.1  jmcneill 	if (maj != 5) {
    911  1.1  jmcneill 		aprint_error(": GENETv%d.%d not supported\n", maj, min);
    912  1.1  jmcneill 		return ENXIO;
    913  1.1  jmcneill 	}
    914  1.1  jmcneill 
    915  1.1  jmcneill 	aprint_naive("\n");
    916  1.1  jmcneill 	aprint_normal(": GENETv%d.%d\n", maj, min);
    917  1.1  jmcneill 
    918  1.1  jmcneill 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET);
    919  1.1  jmcneill 	callout_init(&sc->sc_stat_ch, CALLOUT_FLAGS);
    920  1.1  jmcneill 	callout_setfunc(&sc->sc_stat_ch, genet_tick, sc);
    921  1.1  jmcneill 
    922  1.1  jmcneill 	genet_get_eaddr(sc, eaddr);
    923  1.1  jmcneill 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", ether_sprintf(eaddr));
    924  1.1  jmcneill 
    925  1.1  jmcneill 	/* Soft reset EMAC core */
    926  1.1  jmcneill 	genet_reset(sc);
    927  1.1  jmcneill 
    928  1.1  jmcneill 	/* Setup DMA descriptors */
    929  1.1  jmcneill 	if (genet_setup_dma(sc, GENET_DMA_DEFAULT_QUEUE) != 0) {
    930  1.1  jmcneill 		aprint_error_dev(sc->sc_dev, "failed to setup DMA descriptors\n");
    931  1.1  jmcneill 		return EINVAL;
    932  1.1  jmcneill 	}
    933  1.1  jmcneill 
    934  1.1  jmcneill 	/* Setup ethernet interface */
    935  1.1  jmcneill 	ifp->if_softc = sc;
    936  1.3  jmcneill 	snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev));
    937  1.1  jmcneill 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
    938  1.1  jmcneill #ifdef GENET_MPSAFE
    939  1.1  jmcneill 	ifp->if_extflags = IFEF_MPSAFE;
    940  1.1  jmcneill #endif
    941  1.1  jmcneill 	ifp->if_start = genet_start;
    942  1.1  jmcneill 	ifp->if_ioctl = genet_ioctl;
    943  1.1  jmcneill 	ifp->if_init = genet_init;
    944  1.1  jmcneill 	ifp->if_stop = genet_stop;
    945  1.1  jmcneill 	ifp->if_capabilities = 0;
    946  1.1  jmcneill 	ifp->if_capenable = ifp->if_capabilities;
    947  1.1  jmcneill 	IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
    948  1.1  jmcneill 	IFQ_SET_READY(&ifp->if_snd);
    949  1.1  jmcneill 
    950  1.1  jmcneill 	/* 802.1Q VLAN-sized frames are supported */
    951  1.1  jmcneill 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
    952  1.1  jmcneill 
    953  1.1  jmcneill 	/* Attach MII driver */
    954  1.1  jmcneill 	sc->sc_ec.ec_mii = mii;
    955  1.1  jmcneill 	ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
    956  1.1  jmcneill 	mii->mii_ifp = ifp;
    957  1.1  jmcneill 	mii->mii_readreg = genet_mii_readreg;
    958  1.1  jmcneill 	mii->mii_writereg = genet_mii_writereg;
    959  1.1  jmcneill 	mii->mii_statchg = genet_mii_statchg;
    960  1.1  jmcneill 	mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY,
    961  1.1  jmcneill 	    0);
    962  1.1  jmcneill 
    963  1.1  jmcneill 	if (LIST_EMPTY(&mii->mii_phys)) {
    964  1.1  jmcneill 		aprint_error_dev(sc->sc_dev, "no PHY found!\n");
    965  1.1  jmcneill 		return ENOENT;
    966  1.1  jmcneill 	}
    967  1.1  jmcneill 	ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
    968  1.1  jmcneill 
    969  1.1  jmcneill 	/* Attach interface */
    970  1.1  jmcneill 	if_attach(ifp);
    971  1.1  jmcneill 	if_deferred_start_init(ifp, NULL);
    972  1.1  jmcneill 
    973  1.1  jmcneill 	/* Attach ethernet interface */
    974  1.1  jmcneill 	ether_ifattach(ifp, eaddr);
    975  1.1  jmcneill 
    976  1.1  jmcneill 	return 0;
    977  1.1  jmcneill }
    978  1.1  jmcneill 
    979  1.1  jmcneill #ifdef DDB
    980  1.1  jmcneill void	genet_debug(void);
    981  1.1  jmcneill 
    982  1.1  jmcneill void
    983  1.1  jmcneill genet_debug(void)
    984  1.1  jmcneill {
    985  1.1  jmcneill 	device_t dev = device_find_by_xname("genet0");
    986  1.1  jmcneill 	if (dev == NULL)
    987  1.1  jmcneill 		return;
    988  1.1  jmcneill 
    989  1.1  jmcneill 	struct genet_softc * const sc = device_private(dev);
    990  1.1  jmcneill 	const int qid = GENET_DMA_DEFAULT_QUEUE;
    991  1.1  jmcneill 
    992  1.1  jmcneill 	printf("TX CIDX = %08x (soft)\n", sc->sc_tx.cidx);
    993  1.1  jmcneill 	printf("TX CIDX = %08x\n", RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)));
    994  1.1  jmcneill 	printf("TX PIDX = %08x (soft)\n", sc->sc_tx.pidx);
    995  1.1  jmcneill 	printf("TX PIDX = %08x\n", RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)));
    996  1.1  jmcneill 
    997  1.1  jmcneill 	printf("RX CIDX = %08x (soft)\n", sc->sc_rx.cidx);
    998  1.1  jmcneill 	printf("RX CIDX = %08x\n", RD4(sc, GENET_RX_DMA_CONS_INDEX(qid)));
    999  1.1  jmcneill 	printf("RX PIDX = %08x (soft)\n", sc->sc_rx.pidx);
   1000  1.1  jmcneill 	printf("RX PIDX = %08x\n", RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)));
   1001  1.1  jmcneill }
   1002  1.1  jmcneill #endif
   1003