Home | History | Annotate | Line # | Download | only in ic
bhareg.h revision 1.1 
      1 typedef u_int8_t physaddr[4];
      2 typedef u_int8_t physlen[4];
      3 #define	ltophys	_lto4l
      4 #define	phystol	_4ltol
      5 
      6 /*
      7  * I/O port offsets
      8  */
      9 #define	BHA_CTRL_PORT		0	/* control (wo) */
     10 #define	BHA_STAT_PORT		0	/* status (ro) */
     11 #define	BHA_CMD_PORT		1	/* command (wo) */
     12 #define	BHA_DATA_PORT		1	/* data (ro) */
     13 #define	BHA_INTR_PORT		2	/* interrupt status (ro) */
     14 
     15 /*
     16  * BHA_CTRL bits
     17  */
     18 #define BHA_CTRL_HRST		0x80	/* Hardware reset */
     19 #define BHA_CTRL_SRST		0x40	/* Software reset */
     20 #define BHA_CTRL_IRST		0x20	/* Interrupt reset */
     21 #define BHA_CTRL_SCRST		0x10	/* SCSI bus reset */
     22 
     23 /*
     24  * BHA_STAT bits
     25  */
     26 #define BHA_STAT_STST		0x80	/* Self test in Progress */
     27 #define BHA_STAT_DIAGF		0x40	/* Diagnostic Failure */
     28 #define BHA_STAT_INIT		0x20	/* Mbx Init required */
     29 #define BHA_STAT_IDLE		0x10	/* Host Adapter Idle */
     30 #define BHA_STAT_CDF		0x08	/* cmd/data out port full */
     31 #define BHA_STAT_DF		0x04	/* Data in port full */
     32 #define BHA_STAT_INVDCMD	0x01	/* Invalid command */
     33 
     34 /*
     35  * BHA_CMD opcodes
     36  */
     37 #define	BHA_NOP			0x00	/* No operation */
     38 #define BHA_MBX_INIT		0x01	/* Mbx initialization */
     39 #define BHA_START_SCSI		0x02	/* start scsi command */
     40 #define BHA_INQUIRE_REVISION	0x04	/* Adapter Inquiry */
     41 #define BHA_MBO_INTR_EN		0x05	/* Enable MBO available interrupt */
     42 #if 0
     43 #define BHA_SEL_TIMEOUT_SET	0x06	/* set selection time-out */
     44 #define BHA_BUS_ON_TIME_SET	0x07	/* set bus-on time */
     45 #define BHA_BUS_OFF_TIME_SET	0x08	/* set bus-off time */
     46 #define BHA_SPEED_SET		0x09	/* set transfer speed */
     47 #endif
     48 #define BHA_INQUIRE_DEVICES	0x0a	/* return installed devices 0-7 */
     49 #define BHA_INQUIRE_CONFIG	0x0b	/* return configuration data */
     50 #define BHA_TARGET_EN		0x0c	/* enable target mode */
     51 #define BHA_INQUIRE_SETUP	0x0d	/* return setup data */
     52 #define BHA_ECHO		0x1e	/* Echo command data */
     53 #define BHA_INQUIRE_DEVICES_2	0x23	/* return installed devices 8-15 */
     54 #define BHA_MBX_INIT_EXTENDED	0x81	/* Mbx initialization */
     55 #define BHA_INQUIRE_REVISION_3	0x84	/* Get 3rd firmware version byte */
     56 #define BHA_INQUIRE_REVISION_4	0x85	/* Get 4th firmware version byte */
     57 #define BHA_INQUIRE_MODEL	0x8b	/* Get hardware ID and revision */
     58 #define	BHA_INQUIRE_PERIOD	0x8c	/* Get synchronous period */
     59 #define BHA_INQUIRE_EXTENDED	0x8d	/* Adapter Setup Inquiry */
     60 #define	BHA_ROUND_ROBIN		0x8f	/* Enable/Disable(default) round robin */
     61 
     62 /*
     63  * BHA_INTR bits
     64  */
     65 #define BHA_INTR_ANYINTR	0x80	/* Any interrupt */
     66 #define BHA_INTR_SCRD		0x08	/* SCSI reset detected */
     67 #define BHA_INTR_HACC		0x04	/* Command complete */
     68 #define BHA_INTR_MBOA		0x02	/* MBX out empty */
     69 #define BHA_INTR_MBIF		0x01	/* MBX in full */
     70 
     71 struct bha_mbx_out {
     72 	physaddr ccb_addr;
     73 	u_char dummy[3];
     74 	u_char cmd;
     75 };
     76 
     77 struct bha_mbx_in {
     78 	physaddr ccb_addr;
     79 	u_char dummy[3];
     80 	u_char stat;
     81 };
     82 
     83 /*
     84  * mbo.cmd values
     85  */
     86 #define BHA_MBO_FREE	0x0	/* MBO entry is free */
     87 #define BHA_MBO_START	0x1	/* MBO activate entry */
     88 #define BHA_MBO_ABORT	0x2	/* MBO abort entry */
     89 
     90 /*
     91  * mbi.stat values
     92  */
     93 #define BHA_MBI_FREE	0x0	/* MBI entry is free */
     94 #define BHA_MBI_OK	0x1	/* completed without error */
     95 #define BHA_MBI_ABORT	0x2	/* aborted ccb */
     96 #define BHA_MBI_UNKNOWN	0x3	/* Tried to abort invalid CCB */
     97 #define BHA_MBI_ERROR	0x4	/* Completed with error */
     98 
     99 #if	defined(BIG_DMA)
    100 WARNING...THIS WON'T WORK(won't fit on 1 page)
    101 #if 0
    102 #define      BHA_NSEG 2048    /* Number of scatter gather segments - to much vm */
    103 #endif
    104 #define	BHA_NSEG	128
    105 #else
    106 #define	BHA_NSEG	33
    107 #endif /* BIG_DMA */
    108 
    109 struct bha_scat_gath {
    110 	physlen seg_len;
    111 	physaddr seg_addr;
    112 };
    113 
    114 struct bha_ccb {
    115 	u_char opcode;
    116 	u_char:3, data_in:1, data_out:1,:3;
    117 	u_char scsi_cmd_length;
    118 	u_char req_sense_length;
    119 	/*------------------------------------longword boundary */
    120 	physlen data_length;
    121 	/*------------------------------------longword boundary */
    122 	physaddr data_addr;
    123 	/*------------------------------------longword boundary */
    124 	u_char dummy1[2];
    125 	u_char host_stat;
    126 	u_char target_stat;
    127 	/*------------------------------------longword boundary */
    128 	u_char target;
    129 	u_char lun;
    130 	struct scsi_generic scsi_cmd;
    131 	u_char dummy2[1];
    132 	u_char link_id;
    133 	/*------------------------------------longword boundary */
    134 	physaddr link_addr;
    135 	/*------------------------------------longword boundary */
    136 	physaddr sense_ptr;
    137 /*-----end of HW fields-----------------------longword boundary */
    138 	struct scsi_sense_data scsi_sense;
    139 	/*------------------------------------longword boundary */
    140 	struct bha_scat_gath scat_gath[BHA_NSEG];
    141 	/*------------------------------------longword boundary */
    142 	TAILQ_ENTRY(bha_ccb) chain;
    143 	struct bha_ccb *nexthash;
    144 	long hashkey;
    145 	struct scsi_xfer *xs;		/* the scsi_xfer for this cmd */
    146 	int flags;
    147 #define	CCB_ALLOC	0x01
    148 #define	CCB_ABORT	0x02
    149 #ifdef BHADIAG
    150 #define	CCB_SENDING	0x04
    151 #endif
    152 	int timeout;
    153 };
    154 
    155 /*
    156  * opcode fields
    157  */
    158 #define BHA_INITIATOR_CCB	0x00	/* SCSI Initiator CCB */
    159 #define BHA_TARGET_CCB		0x01	/* SCSI Target CCB */
    160 #define BHA_INIT_SCAT_GATH_CCB	0x02	/* SCSI Initiator with scattter gather */
    161 #define BHA_RESET_CCB		0x81	/* SCSI Bus reset */
    162 
    163 /*
    164  * bha_ccb.host_stat values
    165  */
    166 #define BHA_OK		0x00	/* cmd ok */
    167 #define BHA_LINK_OK	0x0a	/* Link cmd ok */
    168 #define BHA_LINK_IT	0x0b	/* Link cmd ok + int */
    169 #define BHA_SEL_TIMEOUT	0x11	/* Selection time out */
    170 #define BHA_OVER_UNDER	0x12	/* Data over/under run */
    171 #define BHA_BUS_FREE	0x13	/* Bus dropped at unexpected time */
    172 #define BHA_INV_BUS	0x14	/* Invalid bus phase/sequence */
    173 #define BHA_BAD_MBO	0x15	/* Incorrect MBO cmd */
    174 #define BHA_BAD_CCB	0x16	/* Incorrect ccb opcode */
    175 #define BHA_BAD_LINK	0x17	/* Not same values of LUN for links */
    176 #define BHA_INV_TARGET	0x18	/* Invalid target direction */
    177 #define BHA_CCB_DUP	0x19	/* Duplicate CCB received */
    178 #define BHA_INV_CCB	0x1a	/* Invalid CCB or segment list */
    179 
    180 struct bha_extended_inquire {
    181 	struct {
    182 		u_char	opcode;
    183 		u_char	len;
    184 	} cmd;
    185 	struct {
    186 		u_char	bus_type;	/* Type of bus connected to */
    187 #define	BHA_BUS_TYPE_24BIT	'A'	/* ISA bus */
    188 #define	BHA_BUS_TYPE_32BIT	'E'	/* EISA/VLB/PCI bus */
    189 #define	BHA_BUS_TYPE_MCA	'M'	/* MicroChannel bus */
    190 		u_char	bios_address;	/* Address of adapter BIOS */
    191 		u_short	max_segment;	/* ? */
    192 	} reply;
    193 };
    194 
    195 struct bha_config {
    196 	struct {
    197 		u_char	opcode;
    198 	} cmd;
    199 	struct {
    200 		u_char  chan;
    201 		u_char  intr;
    202 		u_char  scsi_dev:3;
    203 		u_char	:5;
    204 	} reply;
    205 };
    206 
    207 struct bha_toggle {
    208 	struct {
    209 		u_char	opcode;
    210 		u_char	enable;
    211 	} cmd;
    212 };
    213 
    214 struct bha_mailbox {
    215 	struct {
    216 		u_char	opcode;
    217 		u_char	nmbx;
    218 		physaddr addr;
    219 	} cmd;
    220 };
    221 
    222 struct bha_model {
    223 	struct {
    224 		u_char	opcode;
    225 		u_char	len;
    226 	} cmd;
    227 	struct {
    228 		u_char	id[4];		/* i.e bt742a -> '7','4','2','A' */
    229 		u_char	version[2];	/* i.e Board Revision 'H' -> 'H', 0x00 */
    230 	} reply;
    231 };
    232 
    233 struct bha_revision {
    234 	struct {
    235 		u_char	opcode;
    236 	} cmd;
    237 	struct {
    238 		u_char  board_type;
    239 		u_char  custom_feature;
    240 		char    firm_revision;
    241 		u_char  firm_version;
    242 	} reply;
    243 };
    244 
    245 struct bha_digit {
    246 	struct {
    247 		u_char	opcode;
    248 	} cmd;
    249 	struct {
    250 		u_char  digit;
    251 	} reply;
    252 };
    253 
    254 struct bha_devices {
    255 	struct {
    256 		u_char	opcode;
    257 	} cmd;
    258 	struct {
    259 		u_char	junk[8];
    260 	} reply;
    261 };
    262 
    263 struct bha_setup {
    264 	struct {
    265 		u_char	opcode;
    266 		u_char	len;
    267 	} cmd;
    268 	struct {
    269 		u_char  sync_neg:1;
    270 		u_char  parity:1;
    271 		u_char	:6;
    272 		u_char  speed;
    273 		u_char  bus_on;
    274 		u_char  bus_off;
    275 		u_char  num_mbx;
    276 		u_char  mbx[3];		/*XXX */
    277 		/* doesn't make sense with 32bit addresses */
    278 		struct {
    279 			u_char  offset:4;
    280 			u_char  period:3;
    281 			u_char  valid:1;
    282 		} sync[8];
    283 		u_char  disc_sts;
    284 	} reply;
    285 };
    286 
    287 struct bha_period {
    288 	struct {
    289 		u_char	opcode;
    290 		u_char	len;
    291 	} cmd;
    292 	struct {
    293 		u_char	period[8];
    294 	} reply;
    295 };
    296 
    297 #define INT9	0x01
    298 #define INT10	0x02
    299 #define INT11	0x04
    300 #define INT12	0x08
    301 #define INT14	0x20
    302 #define INT15	0x40
    303 
    304 #define EISADMA	0x00
    305 #define CHAN0	0x01
    306 #define CHAN5	0x20
    307 #define CHAN6	0x40
    308 #define CHAN7	0x80
    309