bhareg.h revision 1.11
1 /* $NetBSD: bhareg.h,v 1.11 1998/02/06 23:06:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Originally written by Julian Elischer (julian (at) tfs.com) 71 * for TRW Financial Systems for use under the MACH(2.5) operating system. 72 * 73 * TRW Financial Systems, in accordance with their agreement with Carnegie 74 * Mellon University, makes this software available to CMU to distribute 75 * or use in any manner that they see fit as long as this message is kept with 76 * the software. For this reason TFS also grants any other persons or 77 * organisations permission to use or modify this software. 78 * 79 * TFS supplies this software to be publicly redistributed 80 * on the understanding that TFS is not responsible for the correct 81 * functioning of this software in any circumstances. 82 */ 83 84 typedef u_int8_t physaddr[4]; 85 typedef u_int8_t physlen[4]; 86 #define ltophys _lto4l 87 #define phystol _4ltol 88 89 /* 90 * I/O port offsets 91 */ 92 #define BHA_CTRL_PORT 0 /* control (wo) */ 93 #define BHA_STAT_PORT 0 /* status (ro) */ 94 #define BHA_CMD_PORT 1 /* command (wo) */ 95 #define BHA_DATA_PORT 1 /* data (ro) */ 96 #define BHA_INTR_PORT 2 /* interrupt status (ro) */ 97 #define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */ 98 99 /* 100 * BHA_CTRL bits 101 */ 102 #define BHA_CTRL_HRST 0x80 /* Hardware reset */ 103 #define BHA_CTRL_SRST 0x40 /* Software reset */ 104 #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ 105 #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 106 107 /* 108 * BHA_STAT bits 109 */ 110 #define BHA_STAT_STST 0x80 /* Self test in Progress */ 111 #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 112 #define BHA_STAT_INIT 0x20 /* Mbx Init required */ 113 #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 114 #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ 115 #define BHA_STAT_DF 0x04 /* Data in port full */ 116 #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ 117 118 /* 119 * BHA_CMD opcodes 120 */ 121 #define BHA_NOP 0x00 /* No operation */ 122 #define BHA_MBX_INIT 0x01 /* Mbx initialization */ 123 #define BHA_START_SCSI 0x02 /* start scsi command */ 124 #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 125 #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 126 #if 0 127 #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 128 #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 129 #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 130 #define BHA_SPEED_SET 0x09 /* set transfer speed */ 131 #endif 132 #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 133 #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 134 #define BHA_TARGET_EN 0x0c /* enable target mode */ 135 #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ 136 #define BHA_ECHO 0x1e /* Echo command data */ 137 #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 138 #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ 139 #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ 140 #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ 141 #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ 142 #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ 143 #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ 144 #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */ 145 #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */ 146 147 148 /* 149 * BHA_INTR bits 150 */ 151 #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ 152 #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ 153 #define BHA_INTR_HACC 0x04 /* Command complete */ 154 #define BHA_INTR_MBOA 0x02 /* MBX out empty */ 155 #define BHA_INTR_MBIF 0x01 /* MBX in full */ 156 157 struct bha_mbx_out { 158 physaddr ccb_addr; 159 u_char dummy[3]; 160 u_char cmd; 161 }; 162 163 struct bha_mbx_in { 164 physaddr ccb_addr; 165 u_char dummy[3]; 166 u_char stat; 167 }; 168 169 /* 170 * mbo.cmd values 171 */ 172 #define BHA_MBO_FREE 0x0 /* MBO entry is free */ 173 #define BHA_MBO_START 0x1 /* MBO activate entry */ 174 #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ 175 176 /* 177 * mbi.stat values 178 */ 179 #define BHA_MBI_FREE 0x0 /* MBI entry is free */ 180 #define BHA_MBI_OK 0x1 /* completed without error */ 181 #define BHA_MBI_ABORT 0x2 /* aborted ccb */ 182 #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 183 #define BHA_MBI_ERROR 0x4 /* Completed with error */ 184 185 #if defined(BIG_DMA) 186 WARNING...THIS WON'T WORK(won't fit on 1 page) 187 #if 0 188 #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ 189 #endif 190 #define BHA_NSEG 128 191 #else 192 #define BHA_NSEG 33 193 #endif /* BIG_DMA */ 194 195 struct bha_scat_gath { 196 physlen seg_len; 197 physaddr seg_addr; 198 }; 199 200 struct bha_ccb { 201 u_char opcode; 202 u_char:3, data_in:1, data_out:1,:3; 203 u_char scsi_cmd_length; 204 u_char req_sense_length; 205 /*------------------------------------longword boundary */ 206 physlen data_length; 207 /*------------------------------------longword boundary */ 208 physaddr data_addr; 209 /*------------------------------------longword boundary */ 210 u_char dummy1[2]; 211 u_char host_stat; 212 u_char target_stat; 213 /*------------------------------------longword boundary */ 214 u_char target; 215 u_char lun; 216 struct scsi_generic scsi_cmd; 217 u_char dummy2[1]; 218 u_char link_id; 219 /*------------------------------------longword boundary */ 220 physaddr link_addr; 221 /*------------------------------------longword boundary */ 222 physaddr sense_ptr; 223 /*-----end of HW fields-----------------------longword boundary */ 224 struct scsipi_sense_data scsi_sense; 225 /*------------------------------------longword boundary */ 226 struct bha_scat_gath scat_gath[BHA_NSEG]; 227 /*------------------------------------longword boundary */ 228 TAILQ_ENTRY(bha_ccb) chain; 229 struct bha_ccb *nexthash; 230 u_long hashkey; 231 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 232 int flags; 233 #define CCB_ALLOC 0x01 234 #define CCB_ABORT 0x02 235 #ifdef BHADIAG 236 #define CCB_SENDING 0x04 237 #endif 238 int timeout; 239 240 /* 241 * This DMA map maps the buffer involved in the transfer. 242 * Its contents are loaded into "scat_gath" above. 243 */ 244 bus_dmamap_t dmamap_xfer; 245 }; 246 247 /* 248 * opcode fields 249 */ 250 #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 251 #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 252 #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scattter gather */ 253 #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ 254 255 /* 256 * bha_ccb.host_stat values 257 */ 258 #define BHA_OK 0x00 /* cmd ok */ 259 #define BHA_LINK_OK 0x0a /* Link cmd ok */ 260 #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ 261 #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ 262 #define BHA_OVER_UNDER 0x12 /* Data over/under run */ 263 #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 264 #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 265 #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 266 #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 267 #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 268 #define BHA_INV_TARGET 0x18 /* Invalid target direction */ 269 #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ 270 #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 271 272 struct bha_extended_inquire { 273 struct { 274 u_char opcode; 275 u_char len; 276 } cmd; 277 struct { 278 u_char bus_type; /* Type of bus connected to */ 279 #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ 280 #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ 281 #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ 282 u_char bios_address; /* Address of adapter BIOS */ 283 u_short sg_limit; 284 u_char mbox_count; 285 u_char mbox_baseaddr[4]; /* packed/unaligned uint_32_t */ 286 u_char intrflags; 287 #define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */ 288 u_char firmware_level[3]; /* last 3 digits of firmware rev */ 289 u_char scsi_flags; /* supported SCSI features */ 290 #define BHA_SCSI_WIDE 0x01 291 #define BHA_SCSI_DIFFERENTIAL 0x02 292 #define BHA_SCSI_AUTOCONF 0x04 293 #define BHA_SCSI_ULTRA 0x08 294 #define BHA_SCSI_TERMINATION 0x10 295 } reply; 296 }; 297 298 struct bha_config { 299 struct { 300 u_char opcode; 301 } cmd; 302 struct { 303 u_char chan; 304 u_char intr; 305 u_char scsi_dev:3; 306 u_char :5; 307 } reply; 308 }; 309 310 struct bha_toggle { 311 struct { 312 u_char opcode; 313 u_char enable; 314 } cmd; 315 }; 316 317 struct bha_mailbox { 318 struct { 319 u_char opcode; 320 u_char nmbx; 321 physaddr addr; 322 } cmd; 323 }; 324 325 struct bha_model { 326 struct { 327 u_char opcode; 328 u_char len; 329 } cmd; 330 struct { 331 u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ 332 u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ 333 } reply; 334 }; 335 336 struct bha_revision { 337 struct { 338 u_char opcode; 339 } cmd; 340 struct { 341 u_char board_type; 342 u_char custom_feature; 343 char firm_revision; 344 u_char firm_version; 345 } reply; 346 }; 347 348 struct bha_digit { 349 struct { 350 u_char opcode; 351 } cmd; 352 struct { 353 u_char digit; 354 } reply; 355 }; 356 357 struct bha_devices { 358 struct { 359 u_char opcode; 360 } cmd; 361 struct { 362 u_char lun_map[8]; 363 } reply; 364 }; 365 366 struct bha_sync { 367 u_char offset:4; 368 u_char period:3; 369 u_char valid:1; 370 }; 371 372 struct bha_setup_reply { 373 u_char sync_neg:1; 374 u_char parity:1; 375 u_char :6; 376 u_char speed; 377 u_char bus_on; 378 u_char bus_off; 379 u_char num_mbx; 380 u_char mbx[3]; /*XXX */ 381 /* doesn't make sense with 32bit addresses */ 382 struct bha_sync sync[8]; 383 u_char disc_sts; 384 }; 385 386 /* additional reply data supplied by wide controlers */ 387 struct bus_setup_reply_wide { 388 u_char pad[5]; /* ??? */ 389 struct bha_sync sync[8]; 390 u_char disc_sts; 391 }; 392 393 struct bha_setup { 394 struct { 395 u_char opcode; 396 u_char len; 397 } cmd; 398 struct bha_setup_reply reply; 399 struct bus_setup_reply_wide reply_w; /* for wide controllers */ 400 }; 401 402 struct bha_period_reply { 403 u_char period[8]; 404 }; 405 406 struct bha_period { 407 struct { 408 u_char opcode; 409 u_char len; 410 } cmd; 411 struct bha_period_reply reply; 412 struct bha_period_reply reply_w; /* for wide controllers */ 413 }; 414 415 struct bha_isadisable { 416 struct { 417 u_char opcode; 418 u_char modifier; 419 } cmd; 420 }; 421 422 /* 423 * bha_isadisable.modifier parameters 424 */ 425 #define BHA_IOMODIFY_330 0x00 426 #define BHA_IOMODIFY_334 0x01 427 #define BHA_IOMODIFY_DISABLE1 0x06 428 #define BHA_IOMODIFY_DISABLE2 0x07 429 430 #define INT9 0x01 431 #define INT10 0x02 432 #define INT11 0x04 433 #define INT12 0x08 434 #define INT14 0x20 435 #define INT15 0x40 436 437 #define EISADMA 0x00 438 #define CHAN0 0x01 439 #define CHAN5 0x20 440 #define CHAN6 0x40 441 #define CHAN7 0x80 442
Indexes created Tue Sep 30 20:09:53 GMT 2025