bhareg.h revision 1.14
1 /* $NetBSD: bhareg.h,v 1.14 1999/12/23 00:15:12 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Originally written by Julian Elischer (julian (at) tfs.com) 42 * for TRW Financial Systems for use under the MACH(2.5) operating system. 43 * 44 * TRW Financial Systems, in accordance with their agreement with Carnegie 45 * Mellon University, makes this software available to CMU to distribute 46 * or use in any manner that they see fit as long as this message is kept with 47 * the software. For this reason TFS also grants any other persons or 48 * organisations permission to use or modify this software. 49 * 50 * TFS supplies this software to be publicly redistributed 51 * on the understanding that TFS is not responsible for the correct 52 * functioning of this software in any circumstances. 53 */ 54 55 typedef u_int8_t physaddr[4]; 56 typedef u_int8_t physlen[4]; 57 #define ltophys _lto4l 58 #define phystol _4ltol 59 60 /* 61 * I/O port offsets 62 */ 63 #define BHA_CTRL_PORT 0 /* control (wo) */ 64 #define BHA_STAT_PORT 0 /* status (ro) */ 65 #define BHA_CMD_PORT 1 /* command (wo) */ 66 #define BHA_DATA_PORT 1 /* data (ro) */ 67 #define BHA_INTR_PORT 2 /* interrupt status (ro) */ 68 #define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */ 69 70 /* 71 * BHA_CTRL bits 72 */ 73 #define BHA_CTRL_HRST 0x80 /* Hardware reset */ 74 #define BHA_CTRL_SRST 0x40 /* Software reset */ 75 #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ 76 #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 77 78 /* 79 * BHA_STAT bits 80 */ 81 #define BHA_STAT_STST 0x80 /* Self test in Progress */ 82 #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 83 #define BHA_STAT_INIT 0x20 /* Mbx Init required */ 84 #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 85 #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ 86 #define BHA_STAT_DF 0x04 /* Data in port full */ 87 #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ 88 89 /* 90 * BHA_CMD opcodes 91 */ 92 #define BHA_NOP 0x00 /* No operation */ 93 #define BHA_MBX_INIT 0x01 /* Mbx initialization */ 94 #define BHA_START_SCSI 0x02 /* start scsi command */ 95 #define BHA_EXECUTE_BIOS_CMD 0x03 /* execute BIOS command */ 96 #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 97 #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 98 #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 99 #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 100 #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 101 #define BHA_BUS_SPEED_SET 0x09 /* set bus transfer speed */ 102 #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 103 #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 104 #define BHA_TARGET_EN 0x0c /* enable target mode */ 105 #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ 106 #define BHA_WRITE_LRAM 0x1a /* write adapter local RAM */ 107 #define BHA_READ_LRAM 0x1b /* read adapter local RAM */ 108 #define BHA_WRITE_CHIP_FIFO 0x1c /* write bus master chip FIFO */ 109 #define BHA_READ_CHIP_FIFO 0x1d /* read bus master chip FIFO */ 110 #define BHA_ECHO 0x1f /* Echo command byte */ 111 #define BHA_ADAPTER_DIAGNOSTICS 0x20 /* host adapter diagnostics */ 112 #define BHA_SET_ADAPTER_OPTIONS 0x21 /* set adapter options */ 113 #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 114 #define BHA_INQUIRE_TARG_DEVS 0x24 /* inquire target devices */ 115 #define BHA_DISABLE_HAC_INTR 0x25 /* disable host adapter interrupt */ 116 #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ 117 #define BHA_EXECUTE_SCSI_CMD 0x83 /* execute SCSI command */ 118 #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ 119 #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ 120 #define BHA_INQUIRE_PCI_INFO 0x86 /* get PCI host adapter information */ 121 #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ 122 #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ 123 #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ 124 #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) 125 round robin */ 126 #define BHA_STORE_LRAM 0x90 /* store host adapter local RAM */ 127 #define BHA_FETCH_LRAM 0x91 /* fetch host adapter local RAM */ 128 #define BHA_SAVE_TO_EEPROM 0x92 /* store local RAM data in EEPROM */ 129 #define BHA_UPLOAD_AUTOSCSI 0x94 /* upload AutoSCSI code */ 130 #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */ 131 #define BHA_SET_CCB_FORMAT 0x96 /* set CCB format (legacy/wide lun) */ 132 #define BHA_WRITE_INQUIRY_BUF 0x9a /* write inquiry buffer */ 133 #define BHA_READ_INQUIRY_BUF 0x9b /* read inquiry buffer */ 134 #define BHA_FLASH_UP_DOWNLOAD 0xa7 /* flash upload/downlod */ 135 #define BHA_READ_SCAM_DATA 0xa8 /* read SCAM data */ 136 #define BHA_WRITE_SCAM_DATA 0xa9 /* write SCAM data */ 137 138 /* 139 * BHA_INTR bits 140 */ 141 #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ 142 #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ 143 #define BHA_INTR_HACC 0x04 /* Command complete */ 144 #define BHA_INTR_MBOA 0x02 /* MBX out empty */ 145 #define BHA_INTR_MBIF 0x01 /* MBX in full */ 146 147 struct bha_mbx_out { 148 physaddr ccb_addr; 149 u_int8_t reserved[3]; 150 u_int8_t cmd; 151 }; 152 153 struct bha_mbx_in { 154 physaddr ccb_addr; 155 u_int8_t host_stat; 156 u_int8_t target_stat; 157 u_int8_t reserved; 158 u_int8_t comp_stat; 159 }; 160 161 /* 162 * mbo.cmd values 163 */ 164 #define BHA_MBO_FREE 0x0 /* MBO entry is free */ 165 #define BHA_MBO_START 0x1 /* MBO activate entry */ 166 #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ 167 168 /* 169 * mbi.comp_stat values 170 */ 171 #define BHA_MBI_FREE 0x0 /* MBI entry is free */ 172 #define BHA_MBI_OK 0x1 /* completed without error */ 173 #define BHA_MBI_ABORT 0x2 /* aborted ccb */ 174 #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 175 #define BHA_MBI_ERROR 0x4 /* Completed with error */ 176 177 #if defined(BIG_DMA) 178 WARNING...THIS WON'T WORK(won't fit on 1 page) 179 #if 0 180 #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ 181 #endif 182 #define BHA_NSEG 128 183 #else 184 #define BHA_NSEG 33 185 #endif /* BIG_DMA */ 186 187 struct bha_scat_gath { 188 physlen seg_len; 189 physaddr seg_addr; 190 }; 191 192 struct bha_ccb { 193 u_int8_t opcode; 194 #if BYTE_ORDER == LITTLE_ENDIAN 195 u_int8_t :3, 196 data_in :1, 197 data_out :1, 198 wide_tag_enable :1, /* Wide Lun CCB format */ 199 wide_tag_type :2; /* Wide Lun CCB format */ 200 #else 201 u_int8_t wide_tag_type :2, /* Wide Lun CCB format */ 202 wide_tag_enable :1, /* Wide Lun CCB format */ 203 data_out :1, 204 data_in :1, 205 :3; 206 #endif 207 u_int8_t scsi_cmd_length; 208 u_int8_t req_sense_length; 209 /*------------------------------------longword boundary */ 210 physlen data_length; 211 /*------------------------------------longword boundary */ 212 physaddr data_addr; 213 /*------------------------------------longword boundary */ 214 u_int8_t reserved1[2]; 215 u_int8_t host_stat; 216 u_int8_t target_stat; 217 /*------------------------------------longword boundary */ 218 u_int8_t target; 219 #if BYTE_ORDER == LITTLE_ENDIAN 220 u_int8_t lun :5, 221 tag_enable :1, 222 tag_type :2; 223 #else 224 u_int8_t tag_type :2, 225 tag_enable :1, 226 lun :5; 227 #endif 228 u_int8_t scsi_cmd[12]; 229 u_int8_t reserved2[1]; 230 u_int8_t link_id; 231 /*------------------------------------longword boundary */ 232 physaddr link_addr; 233 /*------------------------------------longword boundary */ 234 physaddr sense_ptr; 235 /*-----end of HW fields-----------------------longword boundary */ 236 struct scsipi_sense_data scsi_sense; 237 /*------------------------------------longword boundary */ 238 struct bha_scat_gath scat_gath[BHA_NSEG]; 239 /*------------------------------------longword boundary */ 240 TAILQ_ENTRY(bha_ccb) chain; 241 struct bha_ccb *nexthash; 242 bus_addr_t hashkey; 243 244 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 245 246 int flags; 247 #define CCB_ALLOC 0x01 248 #define CCB_ABORT 0x02 249 #ifdef BHADIAG 250 #define CCB_SENDING 0x04 251 #endif 252 int timeout; 253 254 /* 255 * This DMA map maps the buffer involved in the transfer. 256 * Its contents are loaded into "scat_gath" above. 257 */ 258 bus_dmamap_t dmamap_xfer; 259 }; 260 261 /* 262 * opcode fields 263 */ 264 #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 265 #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 266 #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with S/G */ 267 #define BHA_INIT_RESID_CCB 0x03 /* SCSI Initiator w/ residual */ 268 #define BHA_INIT_RESID_SG_CCB 0x04 /* SCSI Initiator w/ residual and S/G */ 269 #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ 270 271 /* 272 * bha_ccb.host_stat values 273 */ 274 #define BHA_OK 0x00 /* cmd ok */ 275 #define BHA_LINK_OK 0x0a /* Link cmd ok */ 276 #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ 277 #define BHA_DATA_UNDRN 0x0c /* data underrun error */ 278 #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ 279 #define BHA_OVER_UNDER 0x12 /* Data over/under run */ 280 #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 281 #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 282 #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 283 #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 284 #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 285 #define BHA_INV_TARGET 0x18 /* Invalid target direction */ 286 #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ 287 #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 288 #define BHA_AUTOSENSE_FAILED 0x1b /* auto REQUEST SENSE failed */ 289 #define BHA_TAGGED_MSG_REJ 0x1c /* tagged queueing message rejected */ 290 #define BHA_UNSUP_MSG_RECVD 0x1d /* unsupported message received */ 291 #define BHA_HARDWARE_FAILURE 0x20 /* host adapter hardware failure */ 292 #define BHA_TARG_IGNORED_ATN 0x21 /* target ignored ATN signal */ 293 #define BHA_HA_SCSI_BUS_RESET 0x22 /* host adapter asserted RST */ 294 #define BHA_OTHER_SCSI_BUS_RESET 0x23 /* other device asserted RST */ 295 #define BHA_BAD_RECONNECT 0x24 /* target reconnected improperly */ 296 #define BHA_HA_BUS_DEVICE_RESET 0x25 /* host adapter performed BDR */ 297 #define BHA_ABORT_QUEUE 0x26 /* abort queue generated */ 298 #define BHA_SOFTWARE_FAILURE 0x27 /* host adapter software failure */ 299 #define BHA_HARDWARE_WATCHDOG 0x30 /* host adapter watchdog timer fired */ 300 #define BHA_SCSI_PARITY_ERROR 0x34 /* SCSI parity error detected */ 301 302 struct bha_extended_inquire { 303 struct { 304 u_char opcode; 305 u_char len; 306 } cmd; 307 struct { 308 u_char bus_type; /* Type of bus connected to */ 309 #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ 310 #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ 311 #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ 312 u_char bios_address; /* Address of adapter BIOS */ 313 u_short sg_limit; 314 u_char mbox_count; 315 u_char mbox_baseaddr[4]; /* packed/unaligned u_int32_t */ 316 u_char intrflags; 317 #define BHA_INTR_FASTEISA 0x04 318 #define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */ 319 u_char firmware_level[3]; /* last 3 digits of firmware rev */ 320 u_char scsi_flags; /* supported SCSI features */ 321 #define BHA_SCSI_WIDE 0x01 /* host adapter is wide */ 322 #define BHA_SCSI_DIFFERENTIAL 0x02 /* host adapter is differential */ 323 #define BHA_SCSI_SCAM 0x04 /* host adapter supports SCAM */ 324 #define BHA_SCSI_ULTRA 0x08 /* host adapter supports Ultra */ 325 #define BHA_SCSI_TERMINATION 0x10 /* host adapter supports smart 326 termination */ 327 } reply; 328 }; 329 330 struct bha_config { 331 struct { 332 u_char opcode; 333 } cmd; 334 struct { 335 u_char chan; 336 u_char intr; 337 #if BYTE_ORDER == LITTLE_ENDIAN 338 u_char scsi_dev :3, 339 :5; 340 #else 341 u_char :5, 342 scsi_dev :3; 343 #endif 344 } reply; 345 }; 346 347 struct bha_toggle { 348 struct { 349 u_char opcode; 350 u_char enable; 351 } cmd; 352 }; 353 354 struct bha_mailbox { 355 struct { 356 u_char opcode; 357 u_char nmbx; 358 physaddr addr; 359 } cmd; 360 }; 361 362 struct bha_model { 363 struct { 364 u_char opcode; 365 u_char len; 366 } cmd; 367 struct { 368 u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ 369 u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ 370 } reply; 371 }; 372 373 struct bha_revision { 374 struct { 375 u_char opcode; 376 } cmd; 377 struct { 378 u_char board_type; 379 u_char custom_feature; 380 char firm_revision; 381 u_char firm_version; 382 } reply; 383 }; 384 385 struct bha_digit { 386 struct { 387 u_char opcode; 388 } cmd; 389 struct { 390 u_char digit; 391 } reply; 392 }; 393 394 struct bha_devices { 395 struct { 396 u_char opcode; 397 } cmd; 398 struct { 399 u_char lun_map[8]; 400 } reply; 401 }; 402 403 struct bha_sync { 404 #if BYTE_ORDER == LITTLE_ENDIAN 405 u_char offset :4, 406 period :3, 407 valid :1; 408 #else 409 u_char valid :1, 410 period :3, 411 offset :4; 412 #endif 413 }; 414 415 struct bha_setup_reply { 416 #if BYTE_ORDER == LITTLE_ENDIAN 417 u_int8_t sync_neg :1, 418 parity :1, 419 :6; 420 #else 421 u_int8_t :6, 422 parity :1, 423 sync_neg :1; 424 #endif 425 u_int8_t speed; 426 u_int8_t bus_on; 427 u_int8_t bus_off; 428 u_int8_t num_mbx; 429 u_int8_t mbx[3]; /*XXX */ 430 /* doesn't make sense with 32bit addresses */ 431 struct bha_sync sync_low[8]; 432 u_int8_t low_disc_info; 433 }; 434 435 /* additional reply data supplied by wide controlers */ 436 struct bus_setup_reply_wide { 437 u_int8_t signature; 438 u_int8_t letter_d; 439 u_int8_t ha_type; 440 u_int8_t low_wide_allowed; 441 u_int8_t low_wide_active; 442 struct bha_sync sync_high[8]; 443 u_int8_t high_disc_info; 444 u_int8_t reserved; 445 u_int8_t high_wide_allowed; 446 u_int8_t high_wide_active; 447 }; 448 449 struct bha_setup { 450 struct { 451 u_char opcode; 452 u_char len; 453 } cmd; 454 struct bha_setup_reply reply; 455 struct bus_setup_reply_wide reply_w; /* for wide controllers */ 456 }; 457 458 struct bha_period_reply { 459 u_char period[8]; 460 }; 461 462 struct bha_period { 463 struct { 464 u_char opcode; 465 u_char len; 466 } cmd; 467 struct bha_period_reply reply; 468 struct bha_period_reply reply_w; /* for wide controllers */ 469 }; 470 471 struct bha_isadisable { 472 struct { 473 u_char opcode; 474 u_char modifier; 475 } cmd; 476 }; 477 478 /* 479 * bha_isadisable.modifier parameters 480 */ 481 #define BHA_IOMODIFY_330 0x00 482 #define BHA_IOMODIFY_334 0x01 483 #define BHA_IOMODIFY_DISABLE1 0x06 484 #define BHA_IOMODIFY_DISABLE2 0x07 485 486 #define INT9 0x01 487 #define INT10 0x02 488 #define INT11 0x04 489 #define INT12 0x08 490 #define INT14 0x20 491 #define INT15 0x40 492 493 #define EISADMA 0x00 494 #define CHAN0 0x01 495 #define CHAN5 0x20 496 #define CHAN6 0x40 497 #define CHAN7 0x80 498
Indexes created Mon Sep 29 21:09:56 GMT 2025