bhareg.h revision 1.15
1 /* $NetBSD: bhareg.h,v 1.15 2000/10/03 14:07:37 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Originally written by Julian Elischer (julian (at) tfs.com) 42 * for TRW Financial Systems for use under the MACH(2.5) operating system. 43 * 44 * TRW Financial Systems, in accordance with their agreement with Carnegie 45 * Mellon University, makes this software available to CMU to distribute 46 * or use in any manner that they see fit as long as this message is kept with 47 * the software. For this reason TFS also grants any other persons or 48 * organisations permission to use or modify this software. 49 * 50 * TFS supplies this software to be publicly redistributed 51 * on the understanding that TFS is not responsible for the correct 52 * functioning of this software in any circumstances. 53 */ 54 55 typedef u_int8_t physaddr[4]; 56 typedef u_int8_t physlen[4]; 57 #define ltophys _lto4l 58 #define phystol _4ltol 59 60 /* 61 * I/O port offsets 62 */ 63 #define BHA_CTRL_PORT 0 /* control (wo) */ 64 #define BHA_STAT_PORT 0 /* status (ro) */ 65 #define BHA_CMD_PORT 1 /* command (wo) */ 66 #define BHA_DATA_PORT 1 /* data (ro) */ 67 #define BHA_INTR_PORT 2 /* interrupt status (ro) */ 68 #define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */ 69 70 /* 71 * BHA_CTRL bits 72 */ 73 #define BHA_CTRL_HRST 0x80 /* Hardware reset */ 74 #define BHA_CTRL_SRST 0x40 /* Software reset */ 75 #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ 76 #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 77 78 /* 79 * BHA_STAT bits 80 */ 81 #define BHA_STAT_STST 0x80 /* Self test in Progress */ 82 #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 83 #define BHA_STAT_INIT 0x20 /* Mbx Init required */ 84 #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 85 #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ 86 #define BHA_STAT_DF 0x04 /* Data in port full */ 87 #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ 88 89 /* 90 * BHA_CMD opcodes 91 */ 92 #define BHA_NOP 0x00 /* No operation */ 93 #define BHA_MBX_INIT 0x01 /* Mbx initialization */ 94 #define BHA_START_SCSI 0x02 /* start scsi command */ 95 #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 96 #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 97 #if 0 98 #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 99 #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 100 #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 101 #define BHA_SPEED_SET 0x09 /* set transfer speed */ 102 #endif 103 #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 104 #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 105 #define BHA_TARGET_EN 0x0c /* enable target mode */ 106 #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ 107 #define BHA_ECHO 0x1e /* Echo command data */ 108 #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 109 #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ 110 #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ 111 #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ 112 #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ 113 #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ 114 #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ 115 #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */ 116 #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */ 117 118 119 /* 120 * BHA_INTR bits 121 */ 122 #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ 123 #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ 124 #define BHA_INTR_HACC 0x04 /* Command complete */ 125 #define BHA_INTR_MBOA 0x02 /* MBX out empty */ 126 #define BHA_INTR_MBIF 0x01 /* MBX in full */ 127 128 struct bha_mbx_out { 129 physaddr ccb_addr; 130 u_char dummy[3]; 131 u_char cmd; 132 }; 133 134 struct bha_mbx_in { 135 physaddr ccb_addr; 136 u_char dummy[3]; 137 u_char stat; 138 }; 139 140 /* 141 * mbo.cmd values 142 */ 143 #define BHA_MBO_FREE 0x0 /* MBO entry is free */ 144 #define BHA_MBO_START 0x1 /* MBO activate entry */ 145 #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ 146 147 /* 148 * mbi.stat values 149 */ 150 #define BHA_MBI_FREE 0x0 /* MBI entry is free */ 151 #define BHA_MBI_OK 0x1 /* completed without error */ 152 #define BHA_MBI_ABORT 0x2 /* aborted ccb */ 153 #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 154 #define BHA_MBI_ERROR 0x4 /* Completed with error */ 155 156 #if defined(BIG_DMA) 157 WARNING...THIS WON'T WORK(won't fit on 1 page) 158 #if 0 159 #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ 160 #endif 161 #define BHA_NSEG 128 162 #else 163 #define BHA_NSEG 33 164 #endif /* BIG_DMA */ 165 166 struct bha_scat_gath { 167 physlen seg_len; 168 physaddr seg_addr; 169 }; 170 171 struct bha_ccb { 172 u_int8_t opcode; 173 #if BYTE_ORDER == LITTLE_ENDIAN 174 u_int8_t :3, 175 data_in :1, 176 data_out :1, 177 wide_tag_enable :1, /* Wide Lun CCB format */ 178 wide_tag_type :2; /* Wide Lun CCB format */ 179 #else 180 u_int8_t wide_tag_type :2, /* Wide Lun CCB format */ 181 wide_tag_enable :1, /* Wide Lun CCB format */ 182 data_out :1, 183 data_in :1, 184 :3; 185 #endif 186 u_int8_t scsi_cmd_length; 187 u_int8_t req_sense_length; 188 /*------------------------------------longword boundary */ 189 physlen data_length; 190 /*------------------------------------longword boundary */ 191 physaddr data_addr; 192 /*------------------------------------longword boundary */ 193 u_char dummy1[2]; 194 u_char host_stat; 195 u_char target_stat; 196 /*------------------------------------longword boundary */ 197 u_int8_t target; 198 #if BYTE_ORDER == LITTLE_ENDIAN 199 u_int8_t lun :5, 200 tag_enable :1, 201 tag_type :2; 202 #else 203 u_int8_t tag_type :2, 204 tag_enable :1, 205 lun :5; 206 #endif 207 u_int8_t scsi_cmd[12]; 208 u_int8_t reserved2[1]; 209 u_int8_t link_id; 210 /*------------------------------------longword boundary */ 211 physaddr link_addr; 212 /*------------------------------------longword boundary */ 213 physaddr sense_ptr; 214 /*-----end of HW fields-----------------------longword boundary */ 215 struct scsipi_sense_data scsi_sense; 216 /*------------------------------------longword boundary */ 217 struct bha_scat_gath scat_gath[BHA_NSEG]; 218 /*------------------------------------longword boundary */ 219 TAILQ_ENTRY(bha_ccb) chain; 220 struct bha_ccb *nexthash; 221 u_long hashkey; 222 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 223 int flags; 224 #define CCB_ALLOC 0x01 225 #define CCB_ABORT 0x02 226 #ifdef BHADIAG 227 #define CCB_SENDING 0x04 228 #endif 229 int timeout; 230 231 /* 232 * This DMA map maps the buffer involved in the transfer. 233 * Its contents are loaded into "scat_gath" above. 234 */ 235 bus_dmamap_t dmamap_xfer; 236 }; 237 238 /* 239 * opcode fields 240 */ 241 #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 242 #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 243 #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scattter gather */ 244 #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ 245 246 /* 247 * bha_ccb.host_stat values 248 */ 249 #define BHA_OK 0x00 /* cmd ok */ 250 #define BHA_LINK_OK 0x0a /* Link cmd ok */ 251 #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ 252 #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ 253 #define BHA_OVER_UNDER 0x12 /* Data over/under run */ 254 #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 255 #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 256 #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 257 #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 258 #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 259 #define BHA_INV_TARGET 0x18 /* Invalid target direction */ 260 #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ 261 #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 262 263 struct bha_extended_inquire { 264 struct { 265 u_char opcode; 266 u_char len; 267 } cmd; 268 struct { 269 u_char bus_type; /* Type of bus connected to */ 270 #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ 271 #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ 272 #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ 273 u_char bios_address; /* Address of adapter BIOS */ 274 u_short sg_limit; 275 u_char mbox_count; 276 u_char mbox_baseaddr[4]; /* packed/unaligned uint_32_t */ 277 u_char intrflags; 278 #define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */ 279 u_char firmware_level[3]; /* last 3 digits of firmware rev */ 280 u_char scsi_flags; /* supported SCSI features */ 281 #define BHA_SCSI_WIDE 0x01 282 #define BHA_SCSI_DIFFERENTIAL 0x02 283 #define BHA_SCSI_AUTOCONF 0x04 284 #define BHA_SCSI_ULTRA 0x08 285 #define BHA_SCSI_TERMINATION 0x10 286 } reply; 287 }; 288 289 struct bha_config { 290 struct { 291 u_char opcode; 292 } cmd; 293 struct { 294 u_char chan; 295 u_char intr; 296 #if BYTE_ORDER == LITTLE_ENDIAN 297 u_char scsi_dev :3, 298 :5; 299 #else 300 u_char :5, 301 scsi_dev :3; 302 #endif 303 } reply; 304 }; 305 306 struct bha_toggle { 307 struct { 308 u_char opcode; 309 u_char enable; 310 } cmd; 311 }; 312 313 struct bha_mailbox { 314 struct { 315 u_char opcode; 316 u_char nmbx; 317 physaddr addr; 318 } cmd; 319 }; 320 321 struct bha_model { 322 struct { 323 u_char opcode; 324 u_char len; 325 } cmd; 326 struct { 327 u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ 328 u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ 329 } reply; 330 }; 331 332 struct bha_revision { 333 struct { 334 u_char opcode; 335 } cmd; 336 struct { 337 u_char board_type; 338 u_char custom_feature; 339 char firm_revision; 340 u_char firm_version; 341 } reply; 342 }; 343 344 struct bha_digit { 345 struct { 346 u_char opcode; 347 } cmd; 348 struct { 349 u_char digit; 350 } reply; 351 }; 352 353 struct bha_devices { 354 struct { 355 u_char opcode; 356 } cmd; 357 struct { 358 u_char lun_map[8]; 359 } reply; 360 }; 361 362 struct bha_sync { 363 #if BYTE_ORDER == LITTLE_ENDIAN 364 u_char offset :4, 365 period :3, 366 valid :1; 367 #else 368 u_char valid :1, 369 period :3, 370 offset :4; 371 #endif 372 }; 373 374 struct bha_setup_reply { 375 #if BYTE_ORDER == LITTLE_ENDIAN 376 u_int8_t sync_neg :1, 377 parity :1, 378 :6; 379 #else 380 u_int8_t :6, 381 parity :1, 382 sync_neg :1; 383 #endif 384 u_int8_t speed; 385 u_int8_t bus_on; 386 u_int8_t bus_off; 387 u_int8_t num_mbx; 388 u_int8_t mbx[3]; /*XXX */ 389 /* doesn't make sense with 32bit addresses */ 390 struct bha_sync sync[8]; 391 u_char disc_sts; 392 }; 393 394 /* additional reply data supplied by wide controlers */ 395 struct bus_setup_reply_wide { 396 u_char pad[5]; /* ??? */ 397 struct bha_sync sync[8]; 398 u_char disc_sts; 399 }; 400 401 struct bha_setup { 402 struct { 403 u_char opcode; 404 u_char len; 405 } cmd; 406 struct bha_setup_reply reply; 407 struct bus_setup_reply_wide reply_w; /* for wide controllers */ 408 }; 409 410 struct bha_period_reply { 411 u_char period[8]; 412 }; 413 414 struct bha_period { 415 struct { 416 u_char opcode; 417 u_char len; 418 } cmd; 419 struct bha_period_reply reply; 420 struct bha_period_reply reply_w; /* for wide controllers */ 421 }; 422 423 struct bha_isadisable { 424 struct { 425 u_char opcode; 426 u_char modifier; 427 } cmd; 428 }; 429 430 /* 431 * bha_isadisable.modifier parameters 432 */ 433 #define BHA_IOMODIFY_330 0x00 434 #define BHA_IOMODIFY_334 0x01 435 #define BHA_IOMODIFY_DISABLE1 0x06 436 #define BHA_IOMODIFY_DISABLE2 0x07 437 438 #define INT9 0x01 439 #define INT10 0x02 440 #define INT11 0x04 441 #define INT12 0x08 442 #define INT14 0x20 443 #define INT15 0x40 444 445 #define EISADMA 0x00 446 #define CHAN0 0x01 447 #define CHAN5 0x20 448 #define CHAN6 0x40 449 #define CHAN7 0x80 450
Indexes created Tue Oct 28 12:10:06 GMT 2025