bhareg.h revision 1.2
1 /* $NetBSD: bhareg.h,v 1.2 1996/09/01 00:54:36 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Originally written by Julian Elischer (julian (at) tfs.com) 34 * for TRW Financial Systems for use under the MACH(2.5) operating system. 35 * 36 * TRW Financial Systems, in accordance with their agreement with Carnegie 37 * Mellon University, makes this software available to CMU to distribute 38 * or use in any manner that they see fit as long as this message is kept with 39 * the software. For this reason TFS also grants any other persons or 40 * organisations permission to use or modify this software. 41 * 42 * TFS supplies this software to be publicly redistributed 43 * on the understanding that TFS is not responsible for the correct 44 * functioning of this software in any circumstances. 45 */ 46 47 typedef u_int8_t physaddr[4]; 48 typedef u_int8_t physlen[4]; 49 #define ltophys _lto4l 50 #define phystol _4ltol 51 52 /* 53 * I/O port offsets 54 */ 55 #define BHA_CTRL_PORT 0 /* control (wo) */ 56 #define BHA_STAT_PORT 0 /* status (ro) */ 57 #define BHA_CMD_PORT 1 /* command (wo) */ 58 #define BHA_DATA_PORT 1 /* data (ro) */ 59 #define BHA_INTR_PORT 2 /* interrupt status (ro) */ 60 61 /* 62 * BHA_CTRL bits 63 */ 64 #define BHA_CTRL_HRST 0x80 /* Hardware reset */ 65 #define BHA_CTRL_SRST 0x40 /* Software reset */ 66 #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ 67 #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 68 69 /* 70 * BHA_STAT bits 71 */ 72 #define BHA_STAT_STST 0x80 /* Self test in Progress */ 73 #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 74 #define BHA_STAT_INIT 0x20 /* Mbx Init required */ 75 #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 76 #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ 77 #define BHA_STAT_DF 0x04 /* Data in port full */ 78 #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ 79 80 /* 81 * BHA_CMD opcodes 82 */ 83 #define BHA_NOP 0x00 /* No operation */ 84 #define BHA_MBX_INIT 0x01 /* Mbx initialization */ 85 #define BHA_START_SCSI 0x02 /* start scsi command */ 86 #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 87 #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 88 #if 0 89 #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 90 #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 91 #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 92 #define BHA_SPEED_SET 0x09 /* set transfer speed */ 93 #endif 94 #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 95 #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 96 #define BHA_TARGET_EN 0x0c /* enable target mode */ 97 #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ 98 #define BHA_ECHO 0x1e /* Echo command data */ 99 #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 100 #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ 101 #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ 102 #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ 103 #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ 104 #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ 105 #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ 106 #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */ 107 108 /* 109 * BHA_INTR bits 110 */ 111 #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ 112 #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ 113 #define BHA_INTR_HACC 0x04 /* Command complete */ 114 #define BHA_INTR_MBOA 0x02 /* MBX out empty */ 115 #define BHA_INTR_MBIF 0x01 /* MBX in full */ 116 117 struct bha_mbx_out { 118 physaddr ccb_addr; 119 u_char dummy[3]; 120 u_char cmd; 121 }; 122 123 struct bha_mbx_in { 124 physaddr ccb_addr; 125 u_char dummy[3]; 126 u_char stat; 127 }; 128 129 /* 130 * mbo.cmd values 131 */ 132 #define BHA_MBO_FREE 0x0 /* MBO entry is free */ 133 #define BHA_MBO_START 0x1 /* MBO activate entry */ 134 #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ 135 136 /* 137 * mbi.stat values 138 */ 139 #define BHA_MBI_FREE 0x0 /* MBI entry is free */ 140 #define BHA_MBI_OK 0x1 /* completed without error */ 141 #define BHA_MBI_ABORT 0x2 /* aborted ccb */ 142 #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 143 #define BHA_MBI_ERROR 0x4 /* Completed with error */ 144 145 #if defined(BIG_DMA) 146 WARNING...THIS WON'T WORK(won't fit on 1 page) 147 #if 0 148 #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ 149 #endif 150 #define BHA_NSEG 128 151 #else 152 #define BHA_NSEG 33 153 #endif /* BIG_DMA */ 154 155 struct bha_scat_gath { 156 physlen seg_len; 157 physaddr seg_addr; 158 }; 159 160 struct bha_ccb { 161 u_char opcode; 162 u_char:3, data_in:1, data_out:1,:3; 163 u_char scsi_cmd_length; 164 u_char req_sense_length; 165 /*------------------------------------longword boundary */ 166 physlen data_length; 167 /*------------------------------------longword boundary */ 168 physaddr data_addr; 169 /*------------------------------------longword boundary */ 170 u_char dummy1[2]; 171 u_char host_stat; 172 u_char target_stat; 173 /*------------------------------------longword boundary */ 174 u_char target; 175 u_char lun; 176 struct scsi_generic scsi_cmd; 177 u_char dummy2[1]; 178 u_char link_id; 179 /*------------------------------------longword boundary */ 180 physaddr link_addr; 181 /*------------------------------------longword boundary */ 182 physaddr sense_ptr; 183 /*-----end of HW fields-----------------------longword boundary */ 184 struct scsi_sense_data scsi_sense; 185 /*------------------------------------longword boundary */ 186 struct bha_scat_gath scat_gath[BHA_NSEG]; 187 /*------------------------------------longword boundary */ 188 TAILQ_ENTRY(bha_ccb) chain; 189 struct bha_ccb *nexthash; 190 long hashkey; 191 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 192 int flags; 193 #define CCB_ALLOC 0x01 194 #define CCB_ABORT 0x02 195 #ifdef BHADIAG 196 #define CCB_SENDING 0x04 197 #endif 198 int timeout; 199 }; 200 201 /* 202 * opcode fields 203 */ 204 #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 205 #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 206 #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scattter gather */ 207 #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ 208 209 /* 210 * bha_ccb.host_stat values 211 */ 212 #define BHA_OK 0x00 /* cmd ok */ 213 #define BHA_LINK_OK 0x0a /* Link cmd ok */ 214 #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ 215 #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ 216 #define BHA_OVER_UNDER 0x12 /* Data over/under run */ 217 #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 218 #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 219 #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 220 #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 221 #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 222 #define BHA_INV_TARGET 0x18 /* Invalid target direction */ 223 #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ 224 #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 225 226 struct bha_extended_inquire { 227 struct { 228 u_char opcode; 229 u_char len; 230 } cmd; 231 struct { 232 u_char bus_type; /* Type of bus connected to */ 233 #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ 234 #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ 235 #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ 236 u_char bios_address; /* Address of adapter BIOS */ 237 u_short max_segment; /* ? */ 238 } reply; 239 }; 240 241 struct bha_config { 242 struct { 243 u_char opcode; 244 } cmd; 245 struct { 246 u_char chan; 247 u_char intr; 248 u_char scsi_dev:3; 249 u_char :5; 250 } reply; 251 }; 252 253 struct bha_toggle { 254 struct { 255 u_char opcode; 256 u_char enable; 257 } cmd; 258 }; 259 260 struct bha_mailbox { 261 struct { 262 u_char opcode; 263 u_char nmbx; 264 physaddr addr; 265 } cmd; 266 }; 267 268 struct bha_model { 269 struct { 270 u_char opcode; 271 u_char len; 272 } cmd; 273 struct { 274 u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ 275 u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ 276 } reply; 277 }; 278 279 struct bha_revision { 280 struct { 281 u_char opcode; 282 } cmd; 283 struct { 284 u_char board_type; 285 u_char custom_feature; 286 char firm_revision; 287 u_char firm_version; 288 } reply; 289 }; 290 291 struct bha_digit { 292 struct { 293 u_char opcode; 294 } cmd; 295 struct { 296 u_char digit; 297 } reply; 298 }; 299 300 struct bha_devices { 301 struct { 302 u_char opcode; 303 } cmd; 304 struct { 305 u_char junk[8]; 306 } reply; 307 }; 308 309 struct bha_setup { 310 struct { 311 u_char opcode; 312 u_char len; 313 } cmd; 314 struct { 315 u_char sync_neg:1; 316 u_char parity:1; 317 u_char :6; 318 u_char speed; 319 u_char bus_on; 320 u_char bus_off; 321 u_char num_mbx; 322 u_char mbx[3]; /*XXX */ 323 /* doesn't make sense with 32bit addresses */ 324 struct { 325 u_char offset:4; 326 u_char period:3; 327 u_char valid:1; 328 } sync[8]; 329 u_char disc_sts; 330 } reply; 331 }; 332 333 struct bha_period { 334 struct { 335 u_char opcode; 336 u_char len; 337 } cmd; 338 struct { 339 u_char period[8]; 340 } reply; 341 }; 342 343 #define INT9 0x01 344 #define INT10 0x02 345 #define INT11 0x04 346 #define INT12 0x08 347 #define INT14 0x20 348 #define INT15 0x40 349 350 #define EISADMA 0x00 351 #define CHAN0 0x01 352 #define CHAN5 0x20 353 #define CHAN6 0x40 354 #define CHAN7 0x80 355
Indexes created Mon Sep 29 15:09:53 GMT 2025