bhareg.h revision 1.3
1 /* $NetBSD: bhareg.h,v 1.3 1996/11/05 03:04:31 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Originally written by Julian Elischer (julian (at) tfs.com) 34 * for TRW Financial Systems for use under the MACH(2.5) operating system. 35 * 36 * TRW Financial Systems, in accordance with their agreement with Carnegie 37 * Mellon University, makes this software available to CMU to distribute 38 * or use in any manner that they see fit as long as this message is kept with 39 * the software. For this reason TFS also grants any other persons or 40 * organisations permission to use or modify this software. 41 * 42 * TFS supplies this software to be publicly redistributed 43 * on the understanding that TFS is not responsible for the correct 44 * functioning of this software in any circumstances. 45 */ 46 47 typedef u_int8_t physaddr[4]; 48 typedef u_int8_t physlen[4]; 49 #define ltophys _lto4l 50 #define phystol _4ltol 51 52 /* 53 * I/O port offsets 54 */ 55 #define BHA_CTRL_PORT 0 /* control (wo) */ 56 #define BHA_STAT_PORT 0 /* status (ro) */ 57 #define BHA_CMD_PORT 1 /* command (wo) */ 58 #define BHA_DATA_PORT 1 /* data (ro) */ 59 #define BHA_INTR_PORT 2 /* interrupt status (ro) */ 60 #define BHA_EXTGEOM_PORT 2 /* extended geometry (ro) */ 61 62 /* 63 * BHA_CTRL bits 64 */ 65 #define BHA_CTRL_HRST 0x80 /* Hardware reset */ 66 #define BHA_CTRL_SRST 0x40 /* Software reset */ 67 #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ 68 #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 69 70 /* 71 * BHA_STAT bits 72 */ 73 #define BHA_STAT_STST 0x80 /* Self test in Progress */ 74 #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 75 #define BHA_STAT_INIT 0x20 /* Mbx Init required */ 76 #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 77 #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ 78 #define BHA_STAT_DF 0x04 /* Data in port full */ 79 #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ 80 81 /* 82 * BHA_CMD opcodes 83 */ 84 #define BHA_NOP 0x00 /* No operation */ 85 #define BHA_MBX_INIT 0x01 /* Mbx initialization */ 86 #define BHA_START_SCSI 0x02 /* start scsi command */ 87 #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 88 #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 89 #if 0 90 #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 91 #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 92 #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 93 #define BHA_SPEED_SET 0x09 /* set transfer speed */ 94 #endif 95 #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 96 #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 97 #define BHA_TARGET_EN 0x0c /* enable target mode */ 98 #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ 99 #define BHA_ECHO 0x1e /* Echo command data */ 100 #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 101 #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ 102 #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ 103 #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ 104 #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ 105 #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ 106 #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ 107 #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */ 108 #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */ 109 110 111 /* 112 * BHA_INTR bits 113 */ 114 #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ 115 #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ 116 #define BHA_INTR_HACC 0x04 /* Command complete */ 117 #define BHA_INTR_MBOA 0x02 /* MBX out empty */ 118 #define BHA_INTR_MBIF 0x01 /* MBX in full */ 119 120 struct bha_mbx_out { 121 physaddr ccb_addr; 122 u_char dummy[3]; 123 u_char cmd; 124 }; 125 126 struct bha_mbx_in { 127 physaddr ccb_addr; 128 u_char dummy[3]; 129 u_char stat; 130 }; 131 132 /* 133 * mbo.cmd values 134 */ 135 #define BHA_MBO_FREE 0x0 /* MBO entry is free */ 136 #define BHA_MBO_START 0x1 /* MBO activate entry */ 137 #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ 138 139 /* 140 * mbi.stat values 141 */ 142 #define BHA_MBI_FREE 0x0 /* MBI entry is free */ 143 #define BHA_MBI_OK 0x1 /* completed without error */ 144 #define BHA_MBI_ABORT 0x2 /* aborted ccb */ 145 #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 146 #define BHA_MBI_ERROR 0x4 /* Completed with error */ 147 148 #if defined(BIG_DMA) 149 WARNING...THIS WON'T WORK(won't fit on 1 page) 150 #if 0 151 #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ 152 #endif 153 #define BHA_NSEG 128 154 #else 155 #define BHA_NSEG 33 156 #endif /* BIG_DMA */ 157 158 struct bha_scat_gath { 159 physlen seg_len; 160 physaddr seg_addr; 161 }; 162 163 struct bha_ccb { 164 u_char opcode; 165 u_char:3, data_in:1, data_out:1,:3; 166 u_char scsi_cmd_length; 167 u_char req_sense_length; 168 /*------------------------------------longword boundary */ 169 physlen data_length; 170 /*------------------------------------longword boundary */ 171 physaddr data_addr; 172 /*------------------------------------longword boundary */ 173 u_char dummy1[2]; 174 u_char host_stat; 175 u_char target_stat; 176 /*------------------------------------longword boundary */ 177 u_char target; 178 u_char lun; 179 struct scsi_generic scsi_cmd; 180 u_char dummy2[1]; 181 u_char link_id; 182 /*------------------------------------longword boundary */ 183 physaddr link_addr; 184 /*------------------------------------longword boundary */ 185 physaddr sense_ptr; 186 /*-----end of HW fields-----------------------longword boundary */ 187 struct scsi_sense_data scsi_sense; 188 /*------------------------------------longword boundary */ 189 struct bha_scat_gath scat_gath[BHA_NSEG]; 190 /*------------------------------------longword boundary */ 191 TAILQ_ENTRY(bha_ccb) chain; 192 struct bha_ccb *nexthash; 193 long hashkey; 194 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 195 int flags; 196 #define CCB_ALLOC 0x01 197 #define CCB_ABORT 0x02 198 #ifdef BHADIAG 199 #define CCB_SENDING 0x04 200 #endif 201 int timeout; 202 }; 203 204 /* 205 * opcode fields 206 */ 207 #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 208 #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 209 #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scattter gather */ 210 #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ 211 212 /* 213 * bha_ccb.host_stat values 214 */ 215 #define BHA_OK 0x00 /* cmd ok */ 216 #define BHA_LINK_OK 0x0a /* Link cmd ok */ 217 #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ 218 #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ 219 #define BHA_OVER_UNDER 0x12 /* Data over/under run */ 220 #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 221 #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 222 #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 223 #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 224 #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 225 #define BHA_INV_TARGET 0x18 /* Invalid target direction */ 226 #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ 227 #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 228 229 struct bha_extended_inquire { 230 struct { 231 u_char opcode; 232 u_char len; 233 } cmd; 234 struct { 235 u_char bus_type; /* Type of bus connected to */ 236 #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ 237 #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ 238 #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ 239 u_char bios_address; /* Address of adapter BIOS */ 240 u_short max_segment; /* ? */ 241 } reply; 242 }; 243 244 struct bha_config { 245 struct { 246 u_char opcode; 247 } cmd; 248 struct { 249 u_char chan; 250 u_char intr; 251 u_char scsi_dev:3; 252 u_char :5; 253 } reply; 254 }; 255 256 struct bha_toggle { 257 struct { 258 u_char opcode; 259 u_char enable; 260 } cmd; 261 }; 262 263 struct bha_mailbox { 264 struct { 265 u_char opcode; 266 u_char nmbx; 267 physaddr addr; 268 } cmd; 269 }; 270 271 struct bha_model { 272 struct { 273 u_char opcode; 274 u_char len; 275 } cmd; 276 struct { 277 u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ 278 u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ 279 } reply; 280 }; 281 282 struct bha_revision { 283 struct { 284 u_char opcode; 285 } cmd; 286 struct { 287 u_char board_type; 288 u_char custom_feature; 289 char firm_revision; 290 u_char firm_version; 291 } reply; 292 }; 293 294 struct bha_digit { 295 struct { 296 u_char opcode; 297 } cmd; 298 struct { 299 u_char digit; 300 } reply; 301 }; 302 303 struct bha_devices { 304 struct { 305 u_char opcode; 306 } cmd; 307 struct { 308 u_char junk[8]; 309 } reply; 310 }; 311 312 struct bha_setup { 313 struct { 314 u_char opcode; 315 u_char len; 316 } cmd; 317 struct { 318 u_char sync_neg:1; 319 u_char parity:1; 320 u_char :6; 321 u_char speed; 322 u_char bus_on; 323 u_char bus_off; 324 u_char num_mbx; 325 u_char mbx[3]; /*XXX */ 326 /* doesn't make sense with 32bit addresses */ 327 struct { 328 u_char offset:4; 329 u_char period:3; 330 u_char valid:1; 331 } sync[8]; 332 u_char disc_sts; 333 } reply; 334 }; 335 336 struct bha_period { 337 struct { 338 u_char opcode; 339 u_char len; 340 } cmd; 341 struct { 342 u_char period[8]; 343 } reply; 344 }; 345 346 struct bha_isadisable { 347 struct { 348 u_char opcode; 349 u_char modifier; 350 } cmd; 351 }; 352 353 /* 354 * bha_isadisable.modifier parameters 355 */ 356 #define BHA_IOMODIFY_330 0x00 357 #define BHA_IOMODIFY_334 0x01 358 #define BHA_IOMODIFY_DISABLE1 0x06 359 #define BHA_IOMODIFY_DISABLE2 0x07 360 361 #define INT9 0x01 362 #define INT10 0x02 363 #define INT11 0x04 364 #define INT12 0x08 365 #define INT14 0x20 366 #define INT15 0x40 367 368 #define EISADMA 0x00 369 #define CHAN0 0x01 370 #define CHAN5 0x20 371 #define CHAN6 0x40 372 #define CHAN7 0x80 373
Indexes created Mon Sep 29 21:09:56 GMT 2025