bq4802reg.h revision 1.1
11.1Sjdc/*	$NetBSD: bq4802reg.h,v 1.1 2026/02/01 11:45:10 jdc Exp $	*/
21.1Sjdc
31.1Sjdc/*-
41.1Sjdc * Copyright (c) 2026 The NetBSD Foundation, Inc.
51.1Sjdc * All rights reserved.
61.1Sjdc *
71.1Sjdc * This code is derived from software contributed to The NetBSD Foundation
81.1Sjdc * by Julian Coleman.
91.1Sjdc *
101.1Sjdc * Redistribution and use in source and binary forms, with or without
111.1Sjdc * modification, are permitted provided that the following conditions
121.1Sjdc * are met:
131.1Sjdc * 1. Redistributions of source code must retain the above copyright
141.1Sjdc *    notice, this list of conditions and the following disclaimer.
151.1Sjdc * 2. Redistributions in binary form must reproduce the above copyright
161.1Sjdc *    notice, this list of conditions and the following disclaimer in the
171.1Sjdc *    documentation and/or other materials provided with the distribution.
181.1Sjdc *
191.1Sjdc * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
201.1Sjdc * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
211.1Sjdc * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
221.1Sjdc * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
231.1Sjdc * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
241.1Sjdc * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
251.1Sjdc * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
261.1Sjdc * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
271.1Sjdc * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
281.1Sjdc * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
291.1Sjdc * POSSIBILITY OF SUCH DAMAGE.
301.1Sjdc */
311.1Sjdc
321.1Sjdc
331.1Sjdc/*
341.1Sjdc * Registers and register values taken from the Texas Instruments
351.1Sjdc * bq4802Y/bq4802LY data sheet 2002.
361.1Sjdc */
371.1Sjdc
381.1Sjdc#define	BQ4802_SEC		0x00	/* Seconds */
391.1Sjdc#define	BQ4802_SEC_ALM		0x01	/* Seconds alarm */
401.1Sjdc#define	BQ4802_MIN		0x02	/* Minutes */
411.1Sjdc#define	BQ4802_MIN_ALM		0x03	/* Minutes alarm */
421.1Sjdc#define	BQ4802_HOUR		0x04	/* Hours */
431.1Sjdc#define	BQ4802_HOUR_ALM		0x05	/* Hours alarm */
441.1Sjdc#define	BQ4802_DAY		0x06	/* Day */
451.1Sjdc#define	BQ4802_DAY_ALM		0x07	/* Day alarm */
461.1Sjdc#define	BQ4802_WDAY		0x08	/* Day of week */
471.1Sjdc#define	BQ4802_MONTH		0x09	/* Month */
481.1Sjdc#define	BQ4802_YEAR		0x0a	/* Year */
491.1Sjdc#define	BQ4802_RATES		0x0b	/* Rates */
501.1Sjdc#define	BQ4802_ENABLES		0x0c	/* Enables */
511.1Sjdc#define	BQ4802_FLAGS		0x0d	/* Flags */
521.1Sjdc#define	BQ4802_CTRL		0x0e	/* Control */
531.1Sjdc#define	BQ4802_CENT		0x0f	/* Century */
541.1Sjdc
551.1Sjdc/* Seconds and Seconds alarm (00-59) */
561.1Sjdc#define	BQ4802_SECS_1		0x0f	/* 1-second digit */
571.1Sjdc#define	BQ4802_SECS_10		0x70	/* 10-second digit */
581.1Sjdc#define	BQ4802_SECS_ALM0	0x40	/* seconds alarm mask 0 */
591.1Sjdc#define	BQ4802_SECS_ALM1	0x80	/* seconds alarm mask 1 */
601.1Sjdc
611.1Sjdc/* Minutes and Minutes alarm (00-59) */
621.1Sjdc#define	BQ4802_MINS_1		0x0f	/* 1-minute digit */
631.1Sjdc#define	BQ4802_MINS_10		0x70	/* 10-minute digit */
641.1Sjdc#define	BQ4802_MINS_ALM0	0x40	/* minutes alarm mask 0 */
651.1Sjdc#define	BQ4802_MINS_ALM1	0x80	/* minutes alarm mask 1 */
661.1Sjdc
671.1Sjdc/* Hours and Hours alarm (01-24 or 01-12 AM / 81-92 PM) */
681.1Sjdc#define	BQ4802_HOURS_1		0x0f	/* 1-hour digit */
691.1Sjdc#define	BQ4802_HOURS_10		0x30	/* 10-hour digit */
701.1Sjdc#define	BQ4802_HOURS_AM		0x00	/* AM/PM bit */
711.1Sjdc#define	BQ4802_HOURS_PM		0x80	/* AM/PM bit */
721.1Sjdc#define	BQ4802_HOURS_ALM0	0x40	/* hours alarm mask 0 */
731.1Sjdc#define	BQ4802_HOURS_ALM1	0x80	/* hours alarm mask 1 */
741.1Sjdc
751.1Sjdc/* Days and Days alarm (01-31) */
761.1Sjdc#define	BQ4802_DAYS_1		0x0f	/* 1-day digit */
771.1Sjdc#define	BQ4802_DAYS_10		0x30	/* 10-day digit */
781.1Sjdc#define	BQ4802_DAYS_ALM0	0x40	/* days alarm mask 0 */
791.1Sjdc#define	BQ4802_DAYS_ALM1	0x80	/* days alarm mask 1 */
801.1Sjdc
811.1Sjdc/* Day of week (01-07) */
821.1Sjdc#define	BQ4802_WDAYS_1		0x07	/* day of week digit */
831.1Sjdc
841.1Sjdc/* Month (01-12) */
851.1Sjdc#define	BQ4802_MONTHS_1		0x0f	/* 1-month digit */
861.1Sjdc#define	BQ4802_MONTHS_10	0x30	/* 10-month digit */
871.1Sjdc
881.1Sjdc/* Year (00-99) */
891.1Sjdc#define	BQ4802_YEARS_1		0x0f	/* 1-year digit */
901.1Sjdc#define	BQ4802_YEARS_10		0xf0	/* 10-year digit */
911.1Sjdc
921.1Sjdc/* Century (00-99) */
931.1Sjdc#define	BQ4802_CENTS_1		0x0f	/* 1-century digit */
941.1Sjdc#define	BQ4802_CENTS_10		0xf0	/* 10-century digit */
951.1Sjdc
961.1Sjdc/* Rates */
971.1Sjdc#define	BQ4802_RATE_RS0	0x01	/* RS0 */
981.1Sjdc#define	BQ4802_RATE_RS1	0x02	/* RS1 */
991.1Sjdc#define	BQ4802_RATE_RS2	0x04	/* RS2 */
1001.1Sjdc#define	BQ4802_RATE_RS3	0x08	/* RS3 */
1011.1Sjdc#define	BQ4802_RATE_WD0	0x10	/* WD0 */
1021.1Sjdc#define	BQ4802_RATE_WD1	0x20	/* WD1 */
1031.1Sjdc#define	BQ4802_RATE_WD2	0x40	/* WD2 */
1041.1Sjdc
1051.1Sjdc/* Enables */
1061.1Sjdc#define	BQ4802_EN_ABE	0x01	/* Alarm enable in battery-backup mode */
1071.1Sjdc#define	BQ4802_EN_PWRIE	0x02	/* Power-fail interrupt enable */
1081.1Sjdc#define	BQ4802_EN_PIE	0x04	/* Periodic interrupt enable */
1091.1Sjdc#define	BQ4802_EN_AIE	0x08	/* Alarm interrupt enable */
1101.1Sjdc
1111.1Sjdc/* Flags */
1121.1Sjdc#define	BQ4802_FLG_BVF	0x01	/* Battery-valid flag */
1131.1Sjdc#define	BQ4802_FLG_PWRF	0x02	/* Power-fail interrupt flag */
1141.1Sjdc#define	BQ4802_FLG_PF	0x04	/* Periodic interrupt flag */
1151.1Sjdc#define	BQ4802_FLG_AF	0x08	/* Alarm interrupt flag */
1161.1Sjdc
1171.1Sjdc/* Control */
1181.1Sjdc#define	BQ4802_CTRL_DSE	0x01	/* Daylight savings enable */
1191.1Sjdc#define	BQ4802_CTRL_24	0x02	/* 1 for 24-hour, 0 for 12-hour */
1201.1Sjdc#define	BQ4802_CTRL_STP	0x04	/* Stop when in battery-backup mode */
1211.1Sjdc#define	BQ4802_CTRL_UTI	0x08	/* Update transfer inhibit */
1221.1Sjdc
1231.1Sjdc/* Max number of registers we need to read/write for the TOD. */
1241.1Sjdc#define	BQ4802_NREGS	0x10
1251.1Sjdctypedef uint8_t bq4802_regs[BQ4802_NREGS];	/* sparse */
1261.1Sjdcstatic int bq4802_tods[BQ4802_NREGS] =		/* TOD registers */
1271.1Sjdc    { 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1 };
1281.1Sjdc
1291.1Sjdc/* Register read and write functions -- machine-dependent. */
1301.1Sjdcuint8_t bq4802_read(void *, uint8_t);
1311.1Sjdcvoid bq4802_write(void *, uint8_t, uint8_t);
1321.1Sjdc
1331.1Sjdc/*
1341.1Sjdc * Get all of the TOD registers.
1351.1Sjdc * Called at splclock(), and with the RTC set up.
1361.1Sjdc */
1371.1Sjdc#define	BQ4802_GETTOD(sc, regs)						\
1381.1Sjdc	do {								\
1391.1Sjdc		int i;							\
1401.1Sjdc		uint8_t ctrl;						\
1411.1Sjdc									\
1421.1Sjdc		/* disable register updates */				\
1431.1Sjdc		ctrl = bq4802_read(sc, BQ4802_CTRL);			\
1441.1Sjdc		bq4802_write(sc, BQ4802_CTRL, ctrl | BQ4802_CTRL_UTI);	\
1451.1Sjdc									\
1461.1Sjdc		/* read the TOD registers */				\
1471.1Sjdc		for (i = 0; i < BQ4802_NREGS; i++) 			\
1481.1Sjdc			if (bq4802_tods[i])				\
1491.1Sjdc				(*regs)[i] = bq4802_read(sc, i);	\
1501.1Sjdc									\
1511.1Sjdc		/* re-enable register updates */			\
1521.1Sjdc		bq4802_write(sc, BQ4802_CTRL, ctrl);			\
1531.1Sjdc	} while (0);
1541.1Sjdc
1551.1Sjdc/*
1561.1Sjdc * Set all of the TOD registers.
1571.1Sjdc * Called at splclock(), and with the RTC set up.
1581.1Sjdc */
1591.1Sjdc#define	BQ4802_SETTOD(sc, regs)						\
1601.1Sjdc	do {								\
1611.1Sjdc		int i;							\
1621.1Sjdc		uint8_t ctrl;						\
1631.1Sjdc									\
1641.1Sjdc		/* disable register updates */				\
1651.1Sjdc		ctrl = bq4802_read(sc, BQ4802_CTRL);			\
1661.1Sjdc		bq4802_write(sc, BQ4802_CTRL, ctrl | BQ4802_CTRL_UTI);	\
1671.1Sjdc									\
1681.1Sjdc		/* write the TOD registers */				\
1691.1Sjdc		for (i = 0; i < BQ4802_NREGS; i++) 			\
1701.1Sjdc			if (bq4802_tods[i])				\
1711.1Sjdc				bq4802_write(sc, i, (*regs)[i]);	\
1721.1Sjdc									\
1731.1Sjdc		/* re-enable register updates */			\
1741.1Sjdc		bq4802_write(sc, BQ4802_CTRL, ctrl);			\
1751.1Sjdc	} while (0);
176