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      1  1.12  andvar /*	$NetBSD: cacreg.h,v 1.12 2022/11/01 19:24:30 andvar Exp $	*/
      2   1.1      ad 
      3   1.1      ad /*-
      4   1.1      ad  * Copyright (c) 2000 The NetBSD Foundation, Inc.
      5   1.1      ad  * All rights reserved.
      6   1.1      ad  *
      7   1.1      ad  * This code is derived from software contributed to The NetBSD Foundation
      8   1.3      ad  * by Andrew Doran.
      9   1.1      ad  *
     10   1.1      ad  * Redistribution and use in source and binary forms, with or without
     11   1.1      ad  * modification, are permitted provided that the following conditions
     12   1.1      ad  * are met:
     13   1.1      ad  * 1. Redistributions of source code must retain the above copyright
     14   1.1      ad  *    notice, this list of conditions and the following disclaimer.
     15   1.1      ad  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1      ad  *    notice, this list of conditions and the following disclaimer in the
     17   1.1      ad  *    documentation and/or other materials provided with the distribution.
     18   1.1      ad  *
     19   1.1      ad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1      ad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1      ad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1      ad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1      ad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1      ad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1      ad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1      ad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1      ad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1      ad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1      ad  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1      ad  */
     31   1.1      ad 
     32   1.1      ad /*-
     33   1.1      ad  * Copyright (c) 1999 Jonathan Lemon
     34   1.1      ad  * All rights reserved.
     35   1.1      ad  *
     36   1.1      ad  * Redistribution and use in source and binary forms, with or without
     37   1.1      ad  * modification, are permitted provided that the following conditions
     38   1.1      ad  * are met:
     39   1.1      ad  * 1. Redistributions of source code must retain the above copyright
     40   1.1      ad  *    notice, this list of conditions and the following disclaimer.
     41   1.1      ad  * 2. Redistributions in binary form must reproduce the above copyright
     42   1.1      ad  *    notice, this list of conditions and the following disclaimer in the
     43   1.1      ad  *    documentation and/or other materials provided with the distribution.
     44   1.1      ad  *
     45   1.1      ad  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     46   1.1      ad  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     47   1.1      ad  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     48   1.1      ad  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     49   1.1      ad  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     50   1.1      ad  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     51   1.1      ad  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     52   1.1      ad  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     53   1.1      ad  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     54   1.1      ad  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     55   1.1      ad  * SUCH DAMAGE.
     56   1.1      ad  */
     57   1.1      ad 
     58   1.1      ad #ifndef _IC_CACREG_H_
     59   1.4      ad #define	_IC_CACREG_H_
     60   1.1      ad 
     61   1.1      ad /* Board register offsets */
     62   1.4      ad #define	CAC_REG_CMD_FIFO		0x04
     63   1.4      ad #define	CAC_REG_DONE_FIFO		0x08
     64   1.4      ad #define	CAC_REG_INTR_MASK		0x0C
     65   1.4      ad #define	CAC_REG_STATUS			0x10
     66   1.4      ad #define	CAC_REG_INTR_PENDING		0x14
     67   1.4      ad 
     68   1.4      ad #define	CAC_42REG_CMD_FIFO		0x40
     69   1.4      ad #define	CAC_42REG_DONE_FIFO		0x44
     70   1.4      ad #define	CAC_42REG_INTR_MASK		0x34
     71   1.4      ad #define	CAC_42REG_STATUS		0x30
     72   1.5      ad 
     73   1.5      ad #define	CAC_42_EXTINT			0x08
     74   1.4      ad 
     75   1.4      ad #define	CAC_EISAREG_INTR_MASK		0x01
     76   1.4      ad #define	CAC_EISAREG_LOCAL_MASK		0x04
     77   1.4      ad #define	CAC_EISAREG_LOCAL_DOORBELL	0x05
     78   1.4      ad #define	CAC_EISAREG_SYSTEM_MASK		0x06
     79   1.4      ad #define	CAC_EISAREG_SYSTEM_DOORBELL	0x07
     80   1.4      ad #define	CAC_EISAREG_LIST_ADDR		0x08
     81   1.4      ad #define	CAC_EISAREG_LIST_LEN		0x0c
     82   1.4      ad #define	CAC_EISAREG_TAG			0x0f
     83   1.4      ad #define	CAC_EISAREG_COMPLETE_ADDR	0x10
     84   1.4      ad #define	CAC_EISAREG_LIST_STATUS		0x16
     85   1.4      ad 
     86   1.4      ad /* EISA channel control */
     87   1.4      ad #define	CAC_EISA_CHANNEL_BUSY		0x01
     88   1.4      ad #define	CAC_EISA_CHANNEL_CLEAR		0x02
     89   1.1      ad 
     90   1.1      ad /* Interrupt mask values */
     91   1.4      ad #define	CAC_INTR_DISABLE		0x00
     92   1.4      ad #define	CAC_INTR_ENABLE			0x01
     93   1.1      ad 
     94   1.1      ad /* Command types */
     95   1.1      ad #define	CAC_CMD_GET_LOG_DRV_INFO	0x10
     96   1.1      ad #define	CAC_CMD_GET_CTRL_INFO		0x11
     97   1.1      ad #define	CAC_CMD_SENSE_DRV_STATUS	0x12
     98   1.1      ad #define	CAC_CMD_START_RECOVERY		0x13
     99   1.1      ad #define	CAC_CMD_GET_PHYS_DRV_INFO	0x15
    100   1.1      ad #define	CAC_CMD_BLINK_DRV_LEDS		0x16
    101   1.1      ad #define	CAC_CMD_SENSE_DRV_LEDS		0x17
    102   1.1      ad #define	CAC_CMD_GET_LOG_DRV_EXT		0x18
    103   1.1      ad #define	CAC_CMD_GET_CTRL_INFO		0x11
    104   1.4      ad #define	CAC_CMD_READ			0x20
    105   1.4      ad #define	CAC_CMD_WRITE			0x30
    106   1.4      ad #define	CAC_CMD_WRITE_MEDIA		0x31
    107   1.4      ad #define	CAC_CMD_GET_CONFIG		0x50
    108   1.4      ad #define	CAC_CMD_SET_CONFIG		0x51
    109   1.4      ad #define	CAC_CMD_START_FIRMWARE		0x99
    110   1.4      ad #define	CAC_CMD_FLUSH_CACHE		0xc2
    111   1.1      ad 
    112   1.1      ad /* Return status codes */
    113   1.4      ad #define	CAC_RET_SOFT_ERROR		0x02
    114   1.4      ad #define	CAC_RET_HARD_ERROR		0x04
    115   1.8      ad #define	CAC_RET_INVAL_BLOCK		0x10
    116   1.4      ad #define	CAC_RET_CMD_REJECTED		0x14
    117   1.1      ad 
    118   1.1      ad struct cac_drive_info {
    119   1.2      ad 	u_int16_t	secsize;
    120   1.2      ad 	u_int32_t	secperunit;
    121   1.2      ad 	u_int16_t	ncylinders;
    122   1.2      ad 	u_int8_t	nheads;
    123   1.2      ad 	u_int8_t	signature;
    124   1.2      ad 	u_int8_t	psectors;
    125   1.2      ad 	u_int16_t	wprecomp;
    126   1.2      ad 	u_int8_t	max_acc;
    127   1.2      ad 	u_int8_t	control;
    128   1.2      ad 	u_int16_t	pcylinders;
    129   1.2      ad 	u_int8_t	ptracks;
    130   1.2      ad 	u_int16_t	landing_zone;
    131   1.2      ad 	u_int8_t	nsectors;
    132   1.2      ad 	u_int8_t	checksum;
    133   1.2      ad 	u_int8_t	mirror;
    134   1.9   perry } __packed;
    135   1.1      ad 
    136   1.1      ad struct cac_controller_info {
    137   1.2      ad 	u_int8_t	num_drvs;
    138   1.2      ad 	u_int32_t	signature;
    139   1.2      ad 	u_int8_t	firm_rev[4];
    140   1.4      ad 	u_int8_t	rom_rev[4];
    141   1.4      ad 	u_int8_t	hw_rev;
    142   1.4      ad 	u_int32_t	bb_rev;
    143   1.4      ad 	u_int32_t	drv_present_map;
    144   1.4      ad 	u_int32_t	ext_drv_map;
    145   1.4      ad 	u_int32_t	board_id;
    146   1.4      ad 	u_int8_t	cfg_error;
    147   1.4      ad 	u_int32_t	non_disk_bits;
    148   1.4      ad 	u_int8_t	bad_ram_addr;
    149   1.4      ad 	u_int8_t	cpu_rev;
    150   1.4      ad 	u_int8_t	pdpi_rev;
    151   1.4      ad 	u_int8_t	epic_rev;
    152   1.4      ad 	u_int8_t	wcxc_rev;
    153   1.4      ad 	u_int8_t	marketing_rev;
    154   1.4      ad 	u_int8_t	ctlr_flags;
    155   1.4      ad 	u_int8_t	host_flags;
    156   1.4      ad 	u_int8_t	expand_dis;
    157   1.4      ad 	u_int8_t	scsi_chips;
    158   1.4      ad 	u_int32_t	max_req_blocks;
    159   1.4      ad 	u_int32_t	ctlr_clock;
    160   1.4      ad 	u_int8_t	drvs_per_bus;
    161   1.4      ad 	u_int16_t	big_drv_present_map[8];
    162   1.4      ad 	u_int16_t	big_ext_drv_map[8];
    163   1.4      ad 	u_int16_t	big_non_disk_map[8];
    164   1.4      ad 	u_int16_t	task_flags;
    165   1.4      ad 	u_int8_t	icl_bus;
    166   1.4      ad 	u_int8_t	red_modes;
    167   1.4      ad 	u_int8_t	cur_red_mode;
    168   1.4      ad 	u_int8_t	red_ctlr_stat;
    169   1.4      ad 	u_int8_t	red_fail_reason;
    170   1.4      ad 	u_int8_t	reserved[403];
    171   1.9   perry } __packed;
    172   1.1      ad 
    173  1.10  mhitch struct cac_drive_status {
    174  1.10  mhitch 	u_int8_t	stat;
    175  1.10  mhitch #define	CAC_LD_OK	0
    176  1.10  mhitch #define	CAC_LD_FAILED	1
    177  1.10  mhitch #define	CAC_LD_UNCONF	2
    178  1.10  mhitch #define	CAC_LD_DEGRAD	3
    179  1.10  mhitch #define	CAC_LD_RBLDRD	4	/* ready for rebuild */
    180  1.10  mhitch #define	CAC_LD_REBLD	5
    181  1.10  mhitch #define	CAC_LD_PDINV	6	/* wrong phys drive replaced */
    182  1.10  mhitch #define	CAC_LD_PDUNC	7	/* phys drive is not connected proper */
    183  1.10  mhitch #define	CAC_LD_EXPND	10	/* expanding */
    184  1.10  mhitch #define	CAC_LD_NORDY	11	/* volume is not ready */
    185  1.10  mhitch #define	CAC_LD_QEXPND	12	/* queued for expansion */
    186  1.10  mhitch 	u_int8_t	failed[4];	/* failed map */
    187  1.10  mhitch 	u_int8_t	res0[416];
    188  1.10  mhitch 	u_int8_t	prog[4];	/* blocks left to rebuild/expand */
    189  1.10  mhitch 	u_int8_t	rebuild;	/* drive that is rebuilding */
    190  1.10  mhitch 	u_int16_t	remapcnt[32];	/* count of re3mapped blocks for pds */
    191  1.10  mhitch 	u_int8_t	replaced[4];	/* replaced drives map */
    192  1.10  mhitch 	u_int8_t	spare[4];	/* used spares map */
    193  1.10  mhitch 	u_int8_t	sparestat;	/* spare status */
    194  1.10  mhitch #define	CAC_LD_CONF	0x01	/* spare configured */
    195  1.10  mhitch #define	CAC_LD_RBLD	0x02	/* spare is used and rebuilding */
    196  1.10  mhitch #define	CAC_LD_DONE	0x04	/* spare rebuild done */
    197  1.10  mhitch #define	CAC_LD_FAIL	0x08	/* at least one spare drive has failed */
    198  1.10  mhitch #define	CAC_LD_USED	0x10	/* at least one spare drive is used */
    199  1.10  mhitch #define	CAC_LD_AVAIL	0x20	/* at least one spare is available */
    200  1.10  mhitch 	u_int8_t	sparemap[32];	/* spare->pd replacement map */
    201  1.10  mhitch 	u_int8_t	replok[4];	/* replaced failed map */
    202  1.10  mhitch 	u_int8_t	readyok;	/* ready to become ok */
    203  1.10  mhitch 	u_int8_t	memfail;	/* cache mem failure */
    204  1.10  mhitch 	u_int8_t	expfail;	/* expansion failure */
    205  1.10  mhitch 	u_int8_t	rebldfail;	/* rebuild failure */
    206  1.12  andvar #define	CAC_LD_RBLD_READ	0x01	/* read failed */
    207  1.10  mhitch #define	CAC_LD_RBLD_WRITE	0x02	/* write fail */
    208  1.10  mhitch 	u_int8_t	bigfailed[16];	/* bigmap vers of same of the above */
    209  1.10  mhitch 	u_int8_t	bigremapcnt[256];
    210  1.10  mhitch 	u_int8_t	bigreplaced[16];
    211  1.10  mhitch 	u_int8_t	bigspare[16];
    212  1.10  mhitch 	u_int8_t	bigsparemap[128];
    213  1.10  mhitch 	u_int8_t	bigreplok[16];
    214  1.10  mhitch 	u_int8_t	bigrebuild;	/* big-number rebuilding driveno */
    215  1.10  mhitch } __packed;
    216  1.10  mhitch 
    217  1.10  mhitch struct cac_blink {
    218  1.10  mhitch 	u_int32_t	duration;	/* x100ms */
    219  1.10  mhitch 	u_int32_t	elapsed;	/* only for sense */
    220  1.10  mhitch 	u_int8_t	pdtab[256];
    221  1.10  mhitch #define	CAC_BLINK_ALL	1
    222  1.10  mhitch #define	CAC_BLINK_TIMED 2
    223  1.10  mhitch 	u_int8_t	res[248];
    224  1.10  mhitch } __packed;
    225  1.10  mhitch 
    226   1.1      ad struct cac_hdr {
    227   1.1      ad 	u_int8_t	drive;		/* logical drive */
    228   1.1      ad 	u_int8_t	priority;	/* block priority */
    229   1.1      ad 	u_int16_t	size;		/* size of request, in words */
    230   1.9   perry } __packed;
    231   1.1      ad 
    232   1.1      ad struct cac_req {
    233   1.1      ad 	u_int16_t	next;		/* offset of next request */
    234   1.1      ad 	u_int8_t	command;	/* command */
    235   1.1      ad 	u_int8_t	error;		/* return error code */
    236   1.1      ad 	u_int32_t	blkno;		/* block number */
    237   1.1      ad 	u_int16_t	bcount;		/* block count */
    238   1.1      ad 	u_int8_t	sgcount;	/* number of scatter/gather entries */
    239   1.1      ad 	u_int8_t	reserved;	/* reserved */
    240   1.9   perry } __packed;
    241   1.1      ad 
    242   1.1      ad struct cac_sgb {
    243   1.1      ad 	u_int32_t	length;		/* length of S/G segment */
    244   1.1      ad 	u_int32_t	addr;		/* physical address of block */
    245   1.9   perry } __packed;
    246   1.6   perry 
    247   1.1      ad #endif	/* !_IC_CACREG_H_ */
    248