cacreg.h revision 1.10
1 /* $NetBSD: cacreg.h,v 1.10 2008/03/14 03:30:19 mhitch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Jonathan Lemon 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 #ifndef _IC_CACREG_H_ 66 #define _IC_CACREG_H_ 67 68 /* Board register offsets */ 69 #define CAC_REG_CMD_FIFO 0x04 70 #define CAC_REG_DONE_FIFO 0x08 71 #define CAC_REG_INTR_MASK 0x0C 72 #define CAC_REG_STATUS 0x10 73 #define CAC_REG_INTR_PENDING 0x14 74 75 #define CAC_42REG_CMD_FIFO 0x40 76 #define CAC_42REG_DONE_FIFO 0x44 77 #define CAC_42REG_INTR_MASK 0x34 78 #define CAC_42REG_STATUS 0x30 79 80 #define CAC_42_EXTINT 0x08 81 82 #define CAC_EISAREG_INTR_MASK 0x01 83 #define CAC_EISAREG_LOCAL_MASK 0x04 84 #define CAC_EISAREG_LOCAL_DOORBELL 0x05 85 #define CAC_EISAREG_SYSTEM_MASK 0x06 86 #define CAC_EISAREG_SYSTEM_DOORBELL 0x07 87 #define CAC_EISAREG_LIST_ADDR 0x08 88 #define CAC_EISAREG_LIST_LEN 0x0c 89 #define CAC_EISAREG_TAG 0x0f 90 #define CAC_EISAREG_COMPLETE_ADDR 0x10 91 #define CAC_EISAREG_LIST_STATUS 0x16 92 93 /* EISA channel control */ 94 #define CAC_EISA_CHANNEL_BUSY 0x01 95 #define CAC_EISA_CHANNEL_CLEAR 0x02 96 97 /* Interrupt mask values */ 98 #define CAC_INTR_DISABLE 0x00 99 #define CAC_INTR_ENABLE 0x01 100 101 /* Command types */ 102 #define CAC_CMD_GET_LOG_DRV_INFO 0x10 103 #define CAC_CMD_GET_CTRL_INFO 0x11 104 #define CAC_CMD_SENSE_DRV_STATUS 0x12 105 #define CAC_CMD_START_RECOVERY 0x13 106 #define CAC_CMD_GET_PHYS_DRV_INFO 0x15 107 #define CAC_CMD_BLINK_DRV_LEDS 0x16 108 #define CAC_CMD_SENSE_DRV_LEDS 0x17 109 #define CAC_CMD_GET_LOG_DRV_EXT 0x18 110 #define CAC_CMD_GET_CTRL_INFO 0x11 111 #define CAC_CMD_READ 0x20 112 #define CAC_CMD_WRITE 0x30 113 #define CAC_CMD_WRITE_MEDIA 0x31 114 #define CAC_CMD_GET_CONFIG 0x50 115 #define CAC_CMD_SET_CONFIG 0x51 116 #define CAC_CMD_START_FIRMWARE 0x99 117 #define CAC_CMD_FLUSH_CACHE 0xc2 118 119 /* Return status codes */ 120 #define CAC_RET_SOFT_ERROR 0x02 121 #define CAC_RET_HARD_ERROR 0x04 122 #define CAC_RET_INVAL_BLOCK 0x10 123 #define CAC_RET_CMD_REJECTED 0x14 124 125 struct cac_drive_info { 126 u_int16_t secsize; 127 u_int32_t secperunit; 128 u_int16_t ncylinders; 129 u_int8_t nheads; 130 u_int8_t signature; 131 u_int8_t psectors; 132 u_int16_t wprecomp; 133 u_int8_t max_acc; 134 u_int8_t control; 135 u_int16_t pcylinders; 136 u_int8_t ptracks; 137 u_int16_t landing_zone; 138 u_int8_t nsectors; 139 u_int8_t checksum; 140 u_int8_t mirror; 141 } __packed; 142 143 struct cac_controller_info { 144 u_int8_t num_drvs; 145 u_int32_t signature; 146 u_int8_t firm_rev[4]; 147 u_int8_t rom_rev[4]; 148 u_int8_t hw_rev; 149 u_int32_t bb_rev; 150 u_int32_t drv_present_map; 151 u_int32_t ext_drv_map; 152 u_int32_t board_id; 153 u_int8_t cfg_error; 154 u_int32_t non_disk_bits; 155 u_int8_t bad_ram_addr; 156 u_int8_t cpu_rev; 157 u_int8_t pdpi_rev; 158 u_int8_t epic_rev; 159 u_int8_t wcxc_rev; 160 u_int8_t marketing_rev; 161 u_int8_t ctlr_flags; 162 u_int8_t host_flags; 163 u_int8_t expand_dis; 164 u_int8_t scsi_chips; 165 u_int32_t max_req_blocks; 166 u_int32_t ctlr_clock; 167 u_int8_t drvs_per_bus; 168 u_int16_t big_drv_present_map[8]; 169 u_int16_t big_ext_drv_map[8]; 170 u_int16_t big_non_disk_map[8]; 171 u_int16_t task_flags; 172 u_int8_t icl_bus; 173 u_int8_t red_modes; 174 u_int8_t cur_red_mode; 175 u_int8_t red_ctlr_stat; 176 u_int8_t red_fail_reason; 177 u_int8_t reserved[403]; 178 } __packed; 179 180 struct cac_drive_status { 181 u_int8_t stat; 182 #define CAC_LD_OK 0 183 #define CAC_LD_FAILED 1 184 #define CAC_LD_UNCONF 2 185 #define CAC_LD_DEGRAD 3 186 #define CAC_LD_RBLDRD 4 /* ready for rebuild */ 187 #define CAC_LD_REBLD 5 188 #define CAC_LD_PDINV 6 /* wrong phys drive replaced */ 189 #define CAC_LD_PDUNC 7 /* phys drive is not connected proper */ 190 #define CAC_LD_EXPND 10 /* expanding */ 191 #define CAC_LD_NORDY 11 /* volume is not ready */ 192 #define CAC_LD_QEXPND 12 /* queued for expansion */ 193 u_int8_t failed[4]; /* failed map */ 194 u_int8_t res0[416]; 195 u_int8_t prog[4]; /* blocks left to rebuild/expand */ 196 u_int8_t rebuild; /* drive that is rebuilding */ 197 u_int16_t remapcnt[32]; /* count of re3mapped blocks for pds */ 198 u_int8_t replaced[4]; /* replaced drives map */ 199 u_int8_t spare[4]; /* used spares map */ 200 u_int8_t sparestat; /* spare status */ 201 #define CAC_LD_CONF 0x01 /* spare configured */ 202 #define CAC_LD_RBLD 0x02 /* spare is used and rebuilding */ 203 #define CAC_LD_DONE 0x04 /* spare rebuild done */ 204 #define CAC_LD_FAIL 0x08 /* at least one spare drive has failed */ 205 #define CAC_LD_USED 0x10 /* at least one spare drive is used */ 206 #define CAC_LD_AVAIL 0x20 /* at least one spare is available */ 207 u_int8_t sparemap[32]; /* spare->pd replacement map */ 208 u_int8_t replok[4]; /* replaced failed map */ 209 u_int8_t readyok; /* ready to become ok */ 210 u_int8_t memfail; /* cache mem failure */ 211 u_int8_t expfail; /* expansion failure */ 212 u_int8_t rebldfail; /* rebuild failure */ 213 #define CAC_LD_RBLD_READ 0x01 /* read faild */ 214 #define CAC_LD_RBLD_WRITE 0x02 /* write fail */ 215 u_int8_t bigfailed[16]; /* bigmap vers of same of the above */ 216 u_int8_t bigremapcnt[256]; 217 u_int8_t bigreplaced[16]; 218 u_int8_t bigspare[16]; 219 u_int8_t bigsparemap[128]; 220 u_int8_t bigreplok[16]; 221 u_int8_t bigrebuild; /* big-number rebuilding driveno */ 222 } __packed; 223 224 struct cac_blink { 225 u_int32_t duration; /* x100ms */ 226 u_int32_t elapsed; /* only for sense */ 227 u_int8_t pdtab[256]; 228 #define CAC_BLINK_ALL 1 229 #define CAC_BLINK_TIMED 2 230 u_int8_t res[248]; 231 } __packed; 232 233 struct cac_hdr { 234 u_int8_t drive; /* logical drive */ 235 u_int8_t priority; /* block priority */ 236 u_int16_t size; /* size of request, in words */ 237 } __packed; 238 239 struct cac_req { 240 u_int16_t next; /* offset of next request */ 241 u_int8_t command; /* command */ 242 u_int8_t error; /* return error code */ 243 u_int32_t blkno; /* block number */ 244 u_int16_t bcount; /* block count */ 245 u_int8_t sgcount; /* number of scatter/gather entries */ 246 u_int8_t reserved; /* reserved */ 247 } __packed; 248 249 struct cac_sgb { 250 u_int32_t length; /* length of S/G segment */ 251 u_int32_t addr; /* physical address of block */ 252 } __packed; 253 254 #endif /* !_IC_CACREG_H_ */ 255
Indexes created Mon Sep 29 03:10:08 GMT 2025