cissreg.h revision 1.2.4.1
1 1.2.4.1 haad /* $NetBSD: cissreg.h,v 1.2.4.1 2008/10/19 22:16:26 haad Exp $ */ 2 1.1 he /* $OpenBSD: cissreg.h,v 1.4 2005/12/13 15:55:59 brad Exp $ */ 3 1.1 he 4 1.1 he /* 5 1.1 he * Copyright (c) 2005 Michael Shalayeff 6 1.1 he * All rights reserved. 7 1.1 he * 8 1.1 he * Permission to use, copy, modify, and distribute this software for any 9 1.1 he * purpose with or without fee is hereby granted, provided that the above 10 1.1 he * copyright notice and this permission notice appear in all copies. 11 1.1 he * 12 1.1 he * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.1 he * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.1 he * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.1 he * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.1 he * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 17 1.1 he * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 18 1.1 he * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.1 he */ 20 1.1 he 21 1.2 mhitch #define CISS_BIGBIT 0x80 /* texas radio and the big beat! */ 22 1.2 mhitch 23 1.1 he #define CISS_IDB 0x20 24 1.1 he #define CISS_IDB_CFG 0x01 25 1.1 he #define CISS_ISR 0x30 26 1.1 he #define CISS_IMR 0x34 27 1.1 he #define CISS_READYENAB 4 28 1.1 he #define CISS_READYENA 8 29 1.1 he #define CISS_INQ 0x40 30 1.1 he #define CISS_OUTQ 0x44 31 1.1 he #define CISS_CFG_BAR 0xb4 32 1.1 he #define CISS_CFG_OFF 0xb8 33 1.1 he 34 1.1 he #define CISS_DRVMAP_SIZE (128 / 8) 35 1.1 he 36 1.1 he #define CISS_CMD_CTRL_GET 0x26 37 1.1 he #define CISS_CMD_CTRL_SET 0x27 38 1.1 he /* sub-commands for GET/SET */ 39 1.1 he #define CISS_CMS_CTRL_LDID 0x10 40 1.1 he #define CISS_CMS_CTRL_CTRL 0x11 41 1.1 he #define CISS_CMS_CTRL_LDSTAT 0x12 42 1.1 he #define CISS_CMS_CTRL_PDID 0x15 43 1.1 he #define CISS_CMS_CTRL_PDBLINK 0x16 44 1.1 he #define CISS_CMS_CTRL_PDBLSENS 0x17 45 1.2 mhitch #define CISS_CMS_CTRL_LDIDEXT 0x18 46 1.2 mhitch #define CISS_CMS_CTRL_REDSTAT 0x82 47 1.1 he #define CISS_CMS_CTRL_FLUSH 0xc2 48 1.1 he #define CISS_CMS_CTRL_ACCEPT 0xe0 49 1.1 he 50 1.2 mhitch #define CISS_CMD_READ 0xc0 51 1.2 mhitch #define CISS_CMD_READ_EVENT 0xd0 52 1.2 mhitch #define CISS_EVENT_RECENT 0x08 /* ignore previous events */ 53 1.2 mhitch #define CISS_EVENT_RSTOLD 0x04 /* start w/ the oldest one */ 54 1.2 mhitch #define CISS_EVENT_ORDER 0x02 /* keep the order */ 55 1.2 mhitch #define CISS_EVENT_SYNC 0x01 /* sync mode: wait till new come */ 56 1.1 he #define CISS_CMD_LDMAP 0xc2 57 1.1 he #define CISS_CMD_PDMAP 0xc3 58 1.1 he 59 1.2 mhitch #define ciss_bitset(d, v) ((v)[(d) >> 3] & (1 << ((d) & 7))) 60 1.2 mhitch 61 1.1 he struct ciss_softc; 62 1.1 he 63 1.1 he struct ciss_config { 64 1.1 he u_int32_t signature; 65 1.1 he #define CISS_SIGNATURE (*(const u_int32_t *)"CISS") 66 1.1 he u_int32_t version; 67 1.1 he u_int32_t methods; 68 1.1 he #define CISS_METH_READY 0x0001 69 1.1 he #define CISS_METH_SIMPL 0x0002 70 1.1 he #define CISS_METH_PERF 0x0004 71 1.1 he #define CISS_METH_EMQ 0x0008 72 1.1 he u_int32_t amethod; 73 1.1 he u_int32_t rmethod; 74 1.1 he u_int32_t paddr_lim; 75 1.1 he u_int32_t int_delay; 76 1.1 he u_int32_t int_count; 77 1.1 he u_int32_t maxcmd; 78 1.1 he u_int32_t scsibus; 79 1.1 he #define CISS_BUS_U2 0x0001 80 1.1 he #define CISS_BUS_U3 0x0002 81 1.1 he #define CISS_BUS_FC1 0x0100 82 1.1 he #define CISS_BUS_FC2 0x0200 83 1.1 he u_int32_t troff; 84 1.1 he u_int8_t hostname[16]; 85 1.1 he u_int32_t heartbeat; 86 1.1 he u_int32_t driverf; 87 1.1 he #define CISS_DRV_UATT 0x0001 88 1.1 he #define CISS_DRV_QINI 0x0002 89 1.1 he #define CISS_DRV_LCKINT 0x0004 90 1.1 he #define CISS_DRV_QTAGS 0x0008 91 1.1 he #define CISS_DRV_ALPHA 0x0010 92 1.1 he #define CISS_DRV_LUNS 0x0020 93 1.1 he #define CISS_DRV_MSGRQ 0x0080 94 1.1 he #define CISS_DRV_DBRD 0x0100 95 1.1 he #define CISS_DRV_PRF 0x0200 96 1.1 he u_int32_t maxsg; 97 1.1 he } __packed; 98 1.1 he 99 1.1 he struct ciss_inquiry { 100 1.1 he u_int8_t numld; 101 1.1 he u_int8_t sign[4]; 102 1.1 he u_int8_t fw_running[4]; 103 1.1 he u_int8_t fw_stored[4]; 104 1.1 he u_int8_t hw_rev; 105 1.1 he u_int8_t resv0[12]; 106 1.1 he u_int16_t pci_vendor; 107 1.1 he u_int16_t pci_product; 108 1.1 he u_int8_t resv1[10]; 109 1.1 he u_int8_t market_rev; 110 1.1 he u_int8_t flags; 111 1.1 he #define CISS_INQ_WIDE 0x08 112 1.1 he #define CISS_INQ_BIGMAP 0x80 113 1.1 he #define CISS_INQ_BITS "\020\04WIDE\010BIGMAP" 114 1.1 he u_int8_t resv2[2]; 115 1.1 he u_int8_t nscsi_bus; 116 1.1 he u_int8_t resv3[4]; 117 1.1 he u_int8_t clk[4]; /* unaligned dumbness */ 118 1.1 he u_int8_t buswidth; 119 1.1 he u_int8_t disks[CISS_DRVMAP_SIZE]; 120 1.1 he u_int8_t extdisks[CISS_DRVMAP_SIZE]; 121 1.1 he u_int8_t nondisks[CISS_DRVMAP_SIZE]; 122 1.1 he } __packed; 123 1.1 he 124 1.1 he struct ciss_ldmap { 125 1.1 he u_int32_t size; 126 1.1 he u_int32_t resv; 127 1.1 he struct { 128 1.1 he u_int32_t tgt; 129 1.1 he u_int32_t tgt2; 130 1.1 he } map[1]; 131 1.1 he } __packed; 132 1.1 he 133 1.1 he struct ciss_flush { 134 1.1 he u_int16_t flush; 135 1.1 he #define CISS_FLUSH_ENABLE 0 136 1.1 he #define CISS_FLUSH_DISABLE 1 137 1.1 he u_int16_t resv[255]; 138 1.1 he } __packed; 139 1.1 he 140 1.2 mhitch struct ciss_blink { 141 1.2 mhitch u_int32_t duration; /* x100ms */ 142 1.2 mhitch u_int32_t elapsed; /* only for sense */ 143 1.2 mhitch u_int8_t pdtab[256]; 144 1.2 mhitch #define CISS_BLINK_ALL 1 145 1.2 mhitch #define CISS_BLINK_TIMED 2 146 1.2 mhitch u_int8_t res[248]; 147 1.2 mhitch } __packed; 148 1.2 mhitch 149 1.2 mhitch struct ciss_ldid { 150 1.2 mhitch u_int16_t blksize; 151 1.2 mhitch u_int16_t nblocks[2]; /* UNALIGNED! */ 152 1.2 mhitch u_int8_t params[16]; 153 1.2 mhitch u_int8_t type; 154 1.2 mhitch #define CISS_LD_RAID0 0 155 1.2 mhitch #define CISS_LD_RAID4 1 156 1.2 mhitch #define CISS_LD_RAID1 2 157 1.2 mhitch #define CISS_LD_RAID5 3 158 1.2 mhitch #define CISS_LD_RAID51 4 159 1.2 mhitch #define CISS_LD_RAIDADG 5 160 1.2 mhitch u_int8_t res0; 161 1.2 mhitch u_int8_t bios_dis; 162 1.2 mhitch u_int8_t res1; 163 1.2 mhitch u_int32_t id; 164 1.2 mhitch u_int8_t label[64]; 165 1.2 mhitch u_int64_t nbigblocks; 166 1.2 mhitch u_int8_t res2[410]; 167 1.2 mhitch } __packed; 168 1.2 mhitch 169 1.2 mhitch struct ciss_ldstat { 170 1.2 mhitch u_int8_t stat; 171 1.2 mhitch #define CISS_LD_OK 0 172 1.2 mhitch #define CISS_LD_FAILED 1 173 1.2 mhitch #define CISS_LD_UNCONF 2 174 1.2 mhitch #define CISS_LD_DEGRAD 3 175 1.2 mhitch #define CISS_LD_RBLDRD 4 /* ready for rebuild */ 176 1.2 mhitch #define CISS_LD_REBLD 5 177 1.2 mhitch #define CISS_LD_PDINV 6 /* wrong phys drive replaced */ 178 1.2 mhitch #define CISS_LD_PDUNC 7 /* phys drive is not connected proper */ 179 1.2 mhitch #define CISS_LD_EXPND 10 /* expanding */ 180 1.2 mhitch #define CISS_LD_NORDY 11 /* volume is not ready */ 181 1.2 mhitch #define CISS_LD_QEXPND 12 /* queued for expansion */ 182 1.2 mhitch u_int8_t failed[4]; /* failed map */ 183 1.2 mhitch u_int8_t res0[416]; 184 1.2 mhitch u_int8_t prog[4]; /* blocks left to rebuild/expand */ 185 1.2 mhitch u_int8_t rebuild; /* drive that is rebuilding */ 186 1.2 mhitch u_int16_t remapcnt[32]; /* count of remapped blocks for pds */ 187 1.2 mhitch u_int8_t replaced[4]; /* replaced drives map */ 188 1.2 mhitch u_int8_t spare[4]; /* used spares map */ 189 1.2 mhitch u_int8_t sparestat; /* spare status */ 190 1.2 mhitch #define CISS_LD_CONF 0x01 /* spare configured */ 191 1.2 mhitch #define CISS_LD_RBLD 0x02 /* spare is used and rebuilding */ 192 1.2 mhitch #define CISS_LD_DONE 0x04 /* spare rebuild done */ 193 1.2 mhitch #define CISS_LD_FAIL 0x08 /* at least one spare drive has failed */ 194 1.2 mhitch #define CISS_LD_USED 0x10 /* at least one spare drive is used */ 195 1.2 mhitch #define CISS_LD_AVAIL 0x20 /* at least one spare is available */ 196 1.2 mhitch u_int8_t sparemap[32]; /* spare->pd replacement map */ 197 1.2 mhitch u_int8_t replok[4]; /* replaced failed map */ 198 1.2 mhitch u_int8_t readyok; /* ready to become ok */ 199 1.2 mhitch u_int8_t memfail; /* cache mem failure */ 200 1.2 mhitch u_int8_t expfail; /* expansion failure */ 201 1.2 mhitch u_int8_t rebldfail; /* rebuild failure */ 202 1.2 mhitch #define CISS_LD_RBLD_READ 0x01 /* read faild */ 203 1.2 mhitch #define CISS_LD_RBLD_WRITE 0x02 /* write fail */ 204 1.2 mhitch u_int8_t bigfailed[16]; /* bigmap vers of same of the above */ 205 1.2 mhitch u_int8_t bigremapcnt[256]; 206 1.2 mhitch u_int8_t bigreplaced[16]; 207 1.2 mhitch u_int8_t bigspare[16]; 208 1.2 mhitch u_int8_t bigsparemap[128]; 209 1.2 mhitch u_int8_t bigreplok[16]; 210 1.2 mhitch u_int8_t bigrebuild; /* big-number rebuilding driveno */ 211 1.2 mhitch } __packed; 212 1.2 mhitch 213 1.2 mhitch struct ciss_pdid { 214 1.2 mhitch u_int8_t bus; 215 1.2 mhitch u_int8_t target; 216 1.2 mhitch u_int16_t blksz; 217 1.2 mhitch u_int32_t nblocks; 218 1.2 mhitch u_int32_t resblks; 219 1.2 mhitch u_int8_t model[40]; 220 1.2 mhitch u_int8_t serial[40]; 221 1.2 mhitch u_int8_t revision[8]; 222 1.2 mhitch u_int8_t bits; 223 1.2 mhitch u_int8_t res0[2]; 224 1.2 mhitch u_int8_t present; 225 1.2 mhitch #define CISS_PD_PRESENT 0x01 226 1.2 mhitch #define CISS_PD_NONDSK 0x02 227 1.2 mhitch #define CISS_PD_WIDE 0x04 228 1.2 mhitch #define CISS_PD_SYNC 0x08 229 1.2 mhitch #define CISS_PD_NARROW 0x10 230 1.2 mhitch #define CISS_PD_W2NARR 0x20 /* wide downgrade to narrow */ 231 1.2 mhitch #define CISS_PD_ULTRA 0x40 232 1.2 mhitch #define CISS_PD_ULTRA2 0x80 233 1.2 mhitch u_int8_t config; 234 1.2 mhitch #define CISS_PD_SMART 0x01 235 1.2 mhitch #define CISS_PD_SMERRR 0x02 236 1.2 mhitch #define CISS_PD_SMERRE 0x04 237 1.2 mhitch #define CISS_PD_SMERRD 0x08 238 1.2 mhitch #define CISS_PD_EXT 0x10 239 1.2 mhitch #define CISS_PD_CONF 0x20 240 1.2 mhitch #define CISS_PD_SPARE 0x40 241 1.2 mhitch #define CISS_PD_CASAVE 0x80 242 1.2 mhitch u_int8_t res1; 243 1.2 mhitch u_int8_t cache; 244 1.2 mhitch #define CISS_PD_CACHE 0x01 245 1.2 mhitch #define CISS_PD_CASAFE 0x01 246 1.2 mhitch u_int8_t res2[5]; 247 1.2 mhitch u_int8_t connector[2]; 248 1.2 mhitch u_int8_t res3; 249 1.2 mhitch u_int8_t bay; 250 1.2 mhitch u_int16_t rpm; 251 1.2 mhitch u_int8_t type; 252 1.2 mhitch u_int8_t res4[393]; 253 1.2 mhitch } __packed; 254 1.2 mhitch 255 1.2 mhitch struct ciss_event { 256 1.2 mhitch u_int32_t reltime; /* time since controller boot */ 257 1.2 mhitch u_int16_t event; 258 1.2 mhitch #define CISS_EVCLS_PROTO 0 259 1.2 mhitch #define CISS_EVCLS_PLUG 1 260 1.2 mhitch #define CISS_EVCLS_HW 2 261 1.2 mhitch #define CISS_EVCLS_ENV 3 262 1.2 mhitch #define CISS_EVCLS_PD 4 /* ciss_evpdchg in details */ 263 1.2 mhitch #define CISS_EVCLS_LD 5 264 1.2 mhitch #define CISS_EVCLS_CTRL 6 265 1.2 mhitch #define CISS_EVCLS_CISS 8 /* funky errors */ 266 1.2 mhitch #define CISS_EVCLS_RESV 9 267 1.2 mhitch u_int16_t subevent; 268 1.2 mhitch #define CISS_EVPROTO_STAT 0 269 1.2 mhitch #define CISS_EVPROTO_ERR 1 270 1.2 mhitch #define CISS_EVPLUG_PDCHG 0 /* ciss_evpdchg */ 271 1.2 mhitch #define CISS_EVPLUG_POWER 1 /* ciss_evpschg */ 272 1.2 mhitch #define CISS_EVPLUG_FAN 2 /* ciss_evfanchg */ 273 1.2 mhitch #define CISS_EVPLUG_UPS 3 /* ciss_evupschg */ 274 1.2 mhitch #define CISS_EVPLUG_CTRL 4 /* ciss_evctrlchg: ctrl removed? (; */ 275 1.2 mhitch #define CISS_EVHW_CABLES 0 276 1.2 mhitch #define CISS_EVHW_MEMORY 1 277 1.2 mhitch #define CISS_EVHW_FAN 2 /* detail as in CISS_EVPLUG_FAN */ 278 1.2 mhitch #define CISS_EVHW_VRM 3 279 1.2 mhitch #define CISS_EVENV_TEMP 0 /* ciss_evtempchg */ 280 1.2 mhitch #define CISS_EVENV_PS 1 281 1.2 mhitch #define CISS_EVENV_CHASSIS 2 282 1.2 mhitch #define CISS_EVENV_AC 3 283 1.2 mhitch #define CISS_EVPD_STAT 0 284 1.2 mhitch #define CISS_EVLD_STAT 0 285 1.2 mhitch #define CISS_EVLD_ERR 1 286 1.2 mhitch #define CISS_EVLD_CHECK 2 /* surface check */ 287 1.2 mhitch #define CISS_EVCTRL_STAT 0 288 1.2 mhitch u_int16_t detail; 289 1.2 mhitch #define CISS_EVSTAT_NONE 0 290 1.2 mhitch #define CISS_EVSTAT_DISABLE 1 291 1.2 mhitch #define CISS_EVSTAT_TMO 2 /* async event poll timeout */ 292 1.2 mhitch #define CISS_EVERR_OVERFLOW 0 /* event queue overflow */ 293 1.2 mhitch #define CISS_EVPLUG_REMOVE 0 294 1.2 mhitch #define CISS_EVPLUG_INSERT 1 295 1.2 mhitch #define CISS_EVFAN_FAULT 0 296 1.2 mhitch #define CISS_EVFAN_DEGRADED 1 297 1.2 mhitch #define CISS_EVFAN_OK 2 298 1.2 mhitch #define CISS_EVVRM_REMOVE 0 299 1.2 mhitch #define CISS_EVVRM_INSERT 1 300 1.2 mhitch #define CISS_EVVRM_FAILED 2 301 1.2 mhitch #define CISS_EVVRM_OK 3 302 1.2 mhitch #define CISS_EVTEMP_LIMEX 0 /* limit exceeded */ 303 1.2 mhitch #define CISS_EVTEMP_WARN 1 304 1.2 mhitch #define CISS_EVTEMP_OK 2 305 1.2 mhitch #define CISS_EVPS_FAIL 0 306 1.2 mhitch #define CISS_EVPS_OK 2 307 1.2 mhitch #define CISS_EVCHAS_OPEN 0 308 1.2 mhitch #define CISS_EVCHAS_CLOSE 2 309 1.2 mhitch #define CISS_EVAC_FAIL 0 310 1.2 mhitch #define CISS_EVAC_BATTLOW 1 311 1.2 mhitch #define CISS_EVPDSTAT_FAIL 0 312 1.2 mhitch #define CISS_EVLDSTAT_CHG 0 /* ciss_evldchg */ 313 1.2 mhitch #define CISS_EVLDSTAT_EXMEDIA 1 /* untolerant cfg got drive replaced */ 314 1.2 mhitch #define CISS_EVLDSTAT_RERDERR 2 /* ciss_evldrblderr */ 315 1.2 mhitch #define CISS_EVLDSTAT_REWRERR 3 /* ciss_evldrblderr */ 316 1.2 mhitch #define CISS_EVLDERR_FATAL 0 /* ciss_evlderr */ 317 1.2 mhitch #define CISS_EVCHECK_DONE 0 /* details have onle 16bit ld num */ 318 1.2 mhitch #define CISS_EVCTRLSTAT_CHG 0 /* ciss_evctrlstat */ 319 1.2 mhitch u_int8_t data[64]; 320 1.2 mhitch u_int8_t msg[80]; 321 1.2 mhitch u_int32_t tag; 322 1.2 mhitch u_int16_t monday; 323 1.2 mhitch u_int16_t year; 324 1.2 mhitch u_int32_t time; 325 1.2 mhitch u_int16_t presec; /* time for events before boot */ 326 1.2 mhitch u_int8_t device[8]; 327 1.2 mhitch u_int8_t resv[336]; 328 1.2 mhitch } __packed; 329 1.2 mhitch 330 1.2 mhitch struct ciss_evpdchg { /* details pointer */ 331 1.2 mhitch u_int16_t pd; 332 1.2 mhitch u_int8_t flag; /* 1 for configured */ 333 1.2 mhitch u_int8_t spare; 334 1.2 mhitch u_int8_t bigpd; /* big number of the pd */ 335 1.2 mhitch u_int8_t baynum; 336 1.2 mhitch } __packed; 337 1.2 mhitch 338 1.2 mhitch struct ciss_evpschg { /* details pointer */ 339 1.2 mhitch u_int16_t port; 340 1.2 mhitch u_int16_t psid; 341 1.2 mhitch u_int16_t box; 342 1.2 mhitch } __packed; 343 1.2 mhitch 344 1.2 mhitch struct ciss_evfanchg { /* details pointer */ 345 1.2 mhitch u_int16_t port; 346 1.2 mhitch u_int16_t fanid; 347 1.2 mhitch u_int16_t box; 348 1.2 mhitch } __packed; 349 1.2 mhitch 350 1.2 mhitch struct ciss_evupschg { /* details pointer */ 351 1.2 mhitch u_int16_t port; 352 1.2 mhitch u_int16_t upsid; 353 1.2 mhitch } __packed; 354 1.2 mhitch 355 1.2 mhitch struct ciss_evctrlchg { /* details pointer */ 356 1.2 mhitch u_int16_t slot; 357 1.2 mhitch } __packed; 358 1.2 mhitch 359 1.2 mhitch struct ciss_evtempchg { /* details pointer */ 360 1.2 mhitch u_int16_t port; 361 1.2 mhitch u_int16_t sensid; 362 1.2 mhitch u_int16_t box; 363 1.2 mhitch } __packed; 364 1.2 mhitch 365 1.2 mhitch struct ciss_evldchg { /* details pointer */ 366 1.2 mhitch u_int16_t ld; 367 1.2 mhitch u_int8_t prevstat; /* same as ldstat->state */ 368 1.2 mhitch u_int8_t newstat; /* same as ldstat->state */ 369 1.2 mhitch u_int8_t sparestat; 370 1.2 mhitch } __packed; 371 1.2 mhitch 372 1.2 mhitch struct ciss_evldrblderr { /* details pointer */ 373 1.2 mhitch u_int16_t ld; 374 1.2 mhitch u_int8_t replace; 375 1.2 mhitch u_int8_t errpd; 376 1.2 mhitch u_int8_t bigreplace; 377 1.2 mhitch u_int8_t bigerrpd; 378 1.2 mhitch } __packed; 379 1.2 mhitch 380 1.2 mhitch struct ciss_evlderr { /* details pointer */ 381 1.2 mhitch u_int16_t ld; 382 1.2 mhitch u_int16_t blkno[2]; /* unaligned; if >2tb see big later */ 383 1.2 mhitch u_int16_t count; 384 1.2 mhitch u_int8_t ldcmd; 385 1.2 mhitch u_int8_t bus; 386 1.2 mhitch u_int8_t target; 387 1.2 mhitch u_int8_t bigblkno[8]; /* unaligned */ 388 1.2 mhitch } __packed; 389 1.2 mhitch 390 1.2 mhitch struct ciss_evctrlstat { /* details pointer */ 391 1.2 mhitch u_int8_t prefctrl; 392 1.2 mhitch u_int8_t currmode; 393 1.2 mhitch u_int8_t redctrl; 394 1.2 mhitch u_int8_t redfail; 395 1.2 mhitch u_int8_t prevctrl; 396 1.2 mhitch u_int8_t prevmode; 397 1.2 mhitch u_int8_t prevred; 398 1.2 mhitch u_int8_t prevfail; 399 1.2 mhitch } __packed; 400 1.2 mhitch 401 1.1 he struct ciss_cmd { 402 1.1 he u_int8_t resv0; /* 00 */ 403 1.1 he u_int8_t sgin; /* 01: #sg in the cmd */ 404 1.1 he u_int16_t sglen; /* 02: #sg total */ 405 1.1 he u_int32_t id; /* 04: cmd id << 2 and status bits */ 406 1.1 he #define CISS_CMD_ERR 0x02 407 1.1 he u_int32_t id_hi; /* 08: not used */ 408 1.1 he u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */ 409 1.1 he #define CISS_CMD_MODE_PERIPH 0x00000000 410 1.1 he #define CISS_CMD_MODE_LD 0x40000000 411 1.1 he #define CISS_CMD_TGT_MASK 0x40ffffff 412 1.1 he #define CISS_CMD_BUS_MASK 0x3f000000 413 1.1 he #define CISS_CMD_BUS_SHIFT 24 414 1.1 he u_int32_t tgt2; /* 10: scsi-3 address bytes */ 415 1.1 he 416 1.1 he u_int8_t cdblen; /* 14: valid length of cdb */ 417 1.1 he u_int8_t flags; /* 15 */ 418 1.1 he #define CISS_CDB_CMD 0x00 419 1.1 he #define CISS_CDB_MSG 0x01 420 1.1 he #define CISS_CDB_NOTAG 0x00 421 1.1 he #define CISS_CDB_SIMPL 0x20 422 1.1 he #define CISS_CDB_QHEAD 0x28 423 1.1 he #define CISS_CDB_ORDR 0x30 424 1.1 he #define CISS_CDB_AUTO 0x38 425 1.1 he #define CISS_CDB_IN 0x80 426 1.1 he #define CISS_CDB_OUT 0x40 427 1.1 he u_int16_t tmo; /* 16: timeout in seconds */ 428 1.2.4.1 haad #define CISS_MAX_CDB 16 429 1.1 he u_int8_t cdb[16];/* 18 */ 430 1.1 he 431 1.1 he u_int64_t err_pa; /* 28: pa(struct ciss_error *) */ 432 1.1 he u_int32_t err_len;/* 30 */ 433 1.1 he 434 1.1 he struct { /* 34 */ 435 1.1 he u_int32_t addr_lo; 436 1.1 he u_int32_t addr_hi; 437 1.1 he u_int32_t len; 438 1.1 he u_int32_t flags; 439 1.1 he #define CISS_SG_EXT 0x0001 440 1.1 he } sgl[1]; 441 1.1 he } __packed; 442 1.1 he 443 1.1 he struct ciss_error { 444 1.1 he u_int8_t scsi_stat; /* SCSI_OK etc */ 445 1.1 he u_int8_t senselen; 446 1.1 he u_int16_t cmd_stat; 447 1.1 he #define CISS_ERR_OK 0 448 1.1 he #define CISS_ERR_TGTST 1 /* target status */ 449 1.1 he #define CISS_ERR_UNRUN 2 450 1.1 he #define CISS_ERR_OVRUN 3 451 1.1 he #define CISS_ERR_INVCMD 4 452 1.1 he #define CISS_ERR_PROTE 5 453 1.1 he #define CISS_ERR_HWERR 6 454 1.1 he #define CISS_ERR_CLOSS 7 455 1.1 he #define CISS_ERR_ABRT 8 456 1.1 he #define CISS_ERR_FABRT 9 457 1.1 he #define CISS_ERR_UABRT 10 458 1.1 he #define CISS_ERR_TMO 11 459 1.1 he #define CISS_ERR_NABRT 12 460 1.1 he u_int32_t resid; 461 1.1 he u_int8_t err_type[4]; 462 1.1 he u_int32_t err_info; 463 1.1 he u_int8_t sense[32]; 464 1.1 he } __packed; 465 1.1 he 466 1.1 he struct ciss_ccb { 467 1.1 he TAILQ_ENTRY(ciss_ccb) ccb_link; 468 1.1 he struct ciss_softc *ccb_sc; 469 1.1 he paddr_t ccb_cmdpa; 470 1.1 he enum { 471 1.1 he CISS_CCB_FREE = 0x01, 472 1.1 he CISS_CCB_READY = 0x02, 473 1.1 he CISS_CCB_ONQ = 0x04, 474 1.1 he CISS_CCB_PREQ = 0x08, 475 1.1 he CISS_CCB_POLL = 0x10, 476 1.1 he CISS_CCB_FAIL = 0x80 477 1.1 he #define CISS_CCB_BITS "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL" 478 1.1 he } ccb_state; 479 1.1 he 480 1.1 he struct scsipi_xfer *ccb_xs; 481 1.1 he size_t ccb_len; 482 1.1 he void *ccb_data; 483 1.1 he bus_dmamap_t ccb_dmamap; 484 1.1 he 485 1.1 he struct ciss_error ccb_err; 486 1.1 he struct ciss_cmd ccb_cmd; /* followed by sgl */ 487 1.1 he }; 488 1.1 he 489 1.1 he typedef TAILQ_HEAD(ciss_queue_head, ciss_ccb) ciss_queue_head; 490 1.1 he 491
Indexes created Sat Oct 25 07:10:08 GMT 2025