cissreg.h revision 1.3.28.1
1 1.3.28.1 yamt /* $NetBSD: cissreg.h,v 1.3.28.1 2014/05/22 11:40:22 yamt Exp $ */ 2 1.3.28.1 yamt /* $OpenBSD: cissreg.h,v 1.11 2010/06/03 01:02:13 dlg Exp $ */ 3 1.1 he 4 1.1 he /* 5 1.3.28.1 yamt * Copyright (c) 2005,2006 Michael Shalayeff 6 1.1 he * All rights reserved. 7 1.1 he * 8 1.1 he * Permission to use, copy, modify, and distribute this software for any 9 1.1 he * purpose with or without fee is hereby granted, provided that the above 10 1.1 he * copyright notice and this permission notice appear in all copies. 11 1.1 he * 12 1.1 he * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.1 he * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.1 he * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.1 he * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.1 he * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 17 1.1 he * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 18 1.1 he * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.1 he */ 20 1.1 he 21 1.2 mhitch #define CISS_BIGBIT 0x80 /* texas radio and the big beat! */ 22 1.2 mhitch 23 1.1 he #define CISS_IDB 0x20 24 1.1 he #define CISS_IDB_CFG 0x01 25 1.1 he #define CISS_ISR 0x30 26 1.1 he #define CISS_IMR 0x34 27 1.1 he #define CISS_READYENAB 4 28 1.1 he #define CISS_READYENA 8 29 1.1 he #define CISS_INQ 0x40 30 1.1 he #define CISS_OUTQ 0x44 31 1.1 he #define CISS_CFG_BAR 0xb4 32 1.1 he #define CISS_CFG_OFF 0xb8 33 1.1 he 34 1.3.28.1 yamt /* 64bit FIFO mode input/output post queues */ 35 1.3.28.1 yamt #define CISS_INQ64_LO 0xc0 36 1.3.28.1 yamt #define CISS_INQ64_HI 0xc4 37 1.3.28.1 yamt #define CISS_OUTQ64_LO 0xc8 38 1.3.28.1 yamt #define CISS_OUTQ64_HI 0xcc 39 1.3.28.1 yamt 40 1.1 he #define CISS_DRVMAP_SIZE (128 / 8) 41 1.1 he 42 1.1 he #define CISS_CMD_CTRL_GET 0x26 43 1.1 he #define CISS_CMD_CTRL_SET 0x27 44 1.1 he /* sub-commands for GET/SET */ 45 1.1 he #define CISS_CMS_CTRL_LDID 0x10 46 1.1 he #define CISS_CMS_CTRL_CTRL 0x11 47 1.1 he #define CISS_CMS_CTRL_LDSTAT 0x12 48 1.1 he #define CISS_CMS_CTRL_PDID 0x15 49 1.1 he #define CISS_CMS_CTRL_PDBLINK 0x16 50 1.1 he #define CISS_CMS_CTRL_PDBLSENS 0x17 51 1.2 mhitch #define CISS_CMS_CTRL_LDIDEXT 0x18 52 1.2 mhitch #define CISS_CMS_CTRL_REDSTAT 0x82 53 1.1 he #define CISS_CMS_CTRL_FLUSH 0xc2 54 1.1 he #define CISS_CMS_CTRL_ACCEPT 0xe0 55 1.1 he 56 1.2 mhitch #define CISS_CMD_READ 0xc0 57 1.2 mhitch #define CISS_CMD_READ_EVENT 0xd0 58 1.2 mhitch #define CISS_EVENT_RECENT 0x08 /* ignore previous events */ 59 1.2 mhitch #define CISS_EVENT_RSTOLD 0x04 /* start w/ the oldest one */ 60 1.2 mhitch #define CISS_EVENT_ORDER 0x02 /* keep the order */ 61 1.2 mhitch #define CISS_EVENT_SYNC 0x01 /* sync mode: wait till new come */ 62 1.1 he #define CISS_CMD_LDMAP 0xc2 63 1.1 he #define CISS_CMD_PDMAP 0xc3 64 1.1 he 65 1.2 mhitch #define ciss_bitset(d, v) ((v)[(d) >> 3] & (1 << ((d) & 7))) 66 1.2 mhitch 67 1.1 he struct ciss_softc; 68 1.1 he 69 1.1 he struct ciss_config { 70 1.1 he u_int32_t signature; 71 1.1 he #define CISS_SIGNATURE (*(const u_int32_t *)"CISS") 72 1.1 he u_int32_t version; 73 1.1 he u_int32_t methods; 74 1.3.28.1 yamt #define CISS_METH_READY 0x00000001 /* indicate to accept commands */ 75 1.3.28.1 yamt #define CISS_METH_SIMPL 0x00000002 /* simple mode */ 76 1.3.28.1 yamt #define CISS_METH_PERF 0x00000004 /* performant mode */ 77 1.3.28.1 yamt #define CISS_METH_EMQ 0x00000008 /* MEMQ method */ 78 1.3.28.1 yamt #define CISS_METH_BIT63 0x08000000 /* address bit 63 is valid */ 79 1.3.28.1 yamt #define CISS_METH_FIFO64_RRO 0x10000000 /* 64bit FIFO reverse read order */ 80 1.3.28.1 yamt #define CISS_METH_SHORT_TAG 0x20000000 /* short 4 byte tag support */ 81 1.3.28.1 yamt #define CISS_METH_MSIX 0x40000000 /* directed MSI-X support */ 82 1.3.28.1 yamt #define CISS_METH_FIFO64 0x80000000 /* 64bit FIFO support */ 83 1.1 he u_int32_t amethod; 84 1.1 he u_int32_t rmethod; 85 1.1 he u_int32_t paddr_lim; 86 1.1 he u_int32_t int_delay; 87 1.1 he u_int32_t int_count; 88 1.1 he u_int32_t maxcmd; 89 1.1 he u_int32_t scsibus; 90 1.1 he #define CISS_BUS_U2 0x0001 91 1.1 he #define CISS_BUS_U3 0x0002 92 1.1 he #define CISS_BUS_FC1 0x0100 93 1.1 he #define CISS_BUS_FC2 0x0200 94 1.1 he u_int32_t troff; 95 1.1 he u_int8_t hostname[16]; 96 1.1 he u_int32_t heartbeat; 97 1.1 he u_int32_t driverf; 98 1.1 he #define CISS_DRV_UATT 0x0001 99 1.1 he #define CISS_DRV_QINI 0x0002 100 1.1 he #define CISS_DRV_LCKINT 0x0004 101 1.1 he #define CISS_DRV_QTAGS 0x0008 102 1.1 he #define CISS_DRV_ALPHA 0x0010 103 1.1 he #define CISS_DRV_LUNS 0x0020 104 1.1 he #define CISS_DRV_MSGRQ 0x0080 105 1.1 he #define CISS_DRV_DBRD 0x0100 106 1.1 he #define CISS_DRV_PRF 0x0200 107 1.1 he u_int32_t maxsg; 108 1.1 he } __packed; 109 1.1 he 110 1.1 he struct ciss_inquiry { 111 1.1 he u_int8_t numld; 112 1.1 he u_int8_t sign[4]; 113 1.1 he u_int8_t fw_running[4]; 114 1.1 he u_int8_t fw_stored[4]; 115 1.1 he u_int8_t hw_rev; 116 1.1 he u_int8_t resv0[12]; 117 1.1 he u_int16_t pci_vendor; 118 1.1 he u_int16_t pci_product; 119 1.1 he u_int8_t resv1[10]; 120 1.1 he u_int8_t market_rev; 121 1.1 he u_int8_t flags; 122 1.1 he #define CISS_INQ_WIDE 0x08 123 1.1 he #define CISS_INQ_BIGMAP 0x80 124 1.1 he #define CISS_INQ_BITS "\020\04WIDE\010BIGMAP" 125 1.1 he u_int8_t resv2[2]; 126 1.1 he u_int8_t nscsi_bus; 127 1.1 he u_int8_t resv3[4]; 128 1.1 he u_int8_t clk[4]; /* unaligned dumbness */ 129 1.1 he u_int8_t buswidth; 130 1.1 he u_int8_t disks[CISS_DRVMAP_SIZE]; 131 1.1 he u_int8_t extdisks[CISS_DRVMAP_SIZE]; 132 1.1 he u_int8_t nondisks[CISS_DRVMAP_SIZE]; 133 1.1 he } __packed; 134 1.1 he 135 1.1 he struct ciss_ldmap { 136 1.1 he u_int32_t size; 137 1.1 he u_int32_t resv; 138 1.1 he struct { 139 1.1 he u_int32_t tgt; 140 1.1 he u_int32_t tgt2; 141 1.1 he } map[1]; 142 1.1 he } __packed; 143 1.1 he 144 1.1 he struct ciss_flush { 145 1.1 he u_int16_t flush; 146 1.1 he #define CISS_FLUSH_ENABLE 0 147 1.1 he #define CISS_FLUSH_DISABLE 1 148 1.1 he u_int16_t resv[255]; 149 1.1 he } __packed; 150 1.1 he 151 1.2 mhitch struct ciss_blink { 152 1.2 mhitch u_int32_t duration; /* x100ms */ 153 1.2 mhitch u_int32_t elapsed; /* only for sense */ 154 1.2 mhitch u_int8_t pdtab[256]; 155 1.2 mhitch #define CISS_BLINK_ALL 1 156 1.2 mhitch #define CISS_BLINK_TIMED 2 157 1.2 mhitch u_int8_t res[248]; 158 1.2 mhitch } __packed; 159 1.2 mhitch 160 1.2 mhitch struct ciss_ldid { 161 1.2 mhitch u_int16_t blksize; 162 1.2 mhitch u_int16_t nblocks[2]; /* UNALIGNED! */ 163 1.2 mhitch u_int8_t params[16]; 164 1.2 mhitch u_int8_t type; 165 1.2 mhitch #define CISS_LD_RAID0 0 166 1.2 mhitch #define CISS_LD_RAID4 1 167 1.2 mhitch #define CISS_LD_RAID1 2 168 1.2 mhitch #define CISS_LD_RAID5 3 169 1.2 mhitch #define CISS_LD_RAID51 4 170 1.2 mhitch #define CISS_LD_RAIDADG 5 171 1.2 mhitch u_int8_t res0; 172 1.2 mhitch u_int8_t bios_dis; 173 1.2 mhitch u_int8_t res1; 174 1.2 mhitch u_int32_t id; 175 1.2 mhitch u_int8_t label[64]; 176 1.2 mhitch u_int64_t nbigblocks; 177 1.2 mhitch u_int8_t res2[410]; 178 1.2 mhitch } __packed; 179 1.2 mhitch 180 1.2 mhitch struct ciss_ldstat { 181 1.2 mhitch u_int8_t stat; 182 1.2 mhitch #define CISS_LD_OK 0 183 1.2 mhitch #define CISS_LD_FAILED 1 184 1.2 mhitch #define CISS_LD_UNCONF 2 185 1.2 mhitch #define CISS_LD_DEGRAD 3 186 1.2 mhitch #define CISS_LD_RBLDRD 4 /* ready for rebuild */ 187 1.2 mhitch #define CISS_LD_REBLD 5 188 1.2 mhitch #define CISS_LD_PDINV 6 /* wrong phys drive replaced */ 189 1.2 mhitch #define CISS_LD_PDUNC 7 /* phys drive is not connected proper */ 190 1.2 mhitch #define CISS_LD_EXPND 10 /* expanding */ 191 1.2 mhitch #define CISS_LD_NORDY 11 /* volume is not ready */ 192 1.2 mhitch #define CISS_LD_QEXPND 12 /* queued for expansion */ 193 1.2 mhitch u_int8_t failed[4]; /* failed map */ 194 1.2 mhitch u_int8_t res0[416]; 195 1.2 mhitch u_int8_t prog[4]; /* blocks left to rebuild/expand */ 196 1.2 mhitch u_int8_t rebuild; /* drive that is rebuilding */ 197 1.2 mhitch u_int16_t remapcnt[32]; /* count of remapped blocks for pds */ 198 1.2 mhitch u_int8_t replaced[4]; /* replaced drives map */ 199 1.2 mhitch u_int8_t spare[4]; /* used spares map */ 200 1.2 mhitch u_int8_t sparestat; /* spare status */ 201 1.2 mhitch #define CISS_LD_CONF 0x01 /* spare configured */ 202 1.2 mhitch #define CISS_LD_RBLD 0x02 /* spare is used and rebuilding */ 203 1.2 mhitch #define CISS_LD_DONE 0x04 /* spare rebuild done */ 204 1.2 mhitch #define CISS_LD_FAIL 0x08 /* at least one spare drive has failed */ 205 1.2 mhitch #define CISS_LD_USED 0x10 /* at least one spare drive is used */ 206 1.2 mhitch #define CISS_LD_AVAIL 0x20 /* at least one spare is available */ 207 1.2 mhitch u_int8_t sparemap[32]; /* spare->pd replacement map */ 208 1.2 mhitch u_int8_t replok[4]; /* replaced failed map */ 209 1.2 mhitch u_int8_t readyok; /* ready to become ok */ 210 1.2 mhitch u_int8_t memfail; /* cache mem failure */ 211 1.2 mhitch u_int8_t expfail; /* expansion failure */ 212 1.2 mhitch u_int8_t rebldfail; /* rebuild failure */ 213 1.2 mhitch #define CISS_LD_RBLD_READ 0x01 /* read faild */ 214 1.2 mhitch #define CISS_LD_RBLD_WRITE 0x02 /* write fail */ 215 1.2 mhitch u_int8_t bigfailed[16]; /* bigmap vers of same of the above */ 216 1.2 mhitch u_int8_t bigremapcnt[256]; 217 1.2 mhitch u_int8_t bigreplaced[16]; 218 1.2 mhitch u_int8_t bigspare[16]; 219 1.2 mhitch u_int8_t bigsparemap[128]; 220 1.2 mhitch u_int8_t bigreplok[16]; 221 1.2 mhitch u_int8_t bigrebuild; /* big-number rebuilding driveno */ 222 1.2 mhitch } __packed; 223 1.2 mhitch 224 1.2 mhitch struct ciss_pdid { 225 1.2 mhitch u_int8_t bus; 226 1.2 mhitch u_int8_t target; 227 1.2 mhitch u_int16_t blksz; 228 1.2 mhitch u_int32_t nblocks; 229 1.2 mhitch u_int32_t resblks; 230 1.2 mhitch u_int8_t model[40]; 231 1.2 mhitch u_int8_t serial[40]; 232 1.2 mhitch u_int8_t revision[8]; 233 1.2 mhitch u_int8_t bits; 234 1.2 mhitch u_int8_t res0[2]; 235 1.2 mhitch u_int8_t present; 236 1.2 mhitch #define CISS_PD_PRESENT 0x01 237 1.2 mhitch #define CISS_PD_NONDSK 0x02 238 1.2 mhitch #define CISS_PD_WIDE 0x04 239 1.2 mhitch #define CISS_PD_SYNC 0x08 240 1.2 mhitch #define CISS_PD_NARROW 0x10 241 1.2 mhitch #define CISS_PD_W2NARR 0x20 /* wide downgrade to narrow */ 242 1.2 mhitch #define CISS_PD_ULTRA 0x40 243 1.2 mhitch #define CISS_PD_ULTRA2 0x80 244 1.2 mhitch u_int8_t config; 245 1.2 mhitch #define CISS_PD_SMART 0x01 246 1.2 mhitch #define CISS_PD_SMERRR 0x02 247 1.2 mhitch #define CISS_PD_SMERRE 0x04 248 1.2 mhitch #define CISS_PD_SMERRD 0x08 249 1.2 mhitch #define CISS_PD_EXT 0x10 250 1.2 mhitch #define CISS_PD_CONF 0x20 251 1.2 mhitch #define CISS_PD_SPARE 0x40 252 1.2 mhitch #define CISS_PD_CASAVE 0x80 253 1.2 mhitch u_int8_t res1; 254 1.2 mhitch u_int8_t cache; 255 1.2 mhitch #define CISS_PD_CACHE 0x01 256 1.2 mhitch #define CISS_PD_CASAFE 0x01 257 1.2 mhitch u_int8_t res2[5]; 258 1.2 mhitch u_int8_t connector[2]; 259 1.2 mhitch u_int8_t res3; 260 1.2 mhitch u_int8_t bay; 261 1.2 mhitch u_int16_t rpm; 262 1.2 mhitch u_int8_t type; 263 1.2 mhitch u_int8_t res4[393]; 264 1.2 mhitch } __packed; 265 1.2 mhitch 266 1.2 mhitch struct ciss_event { 267 1.2 mhitch u_int32_t reltime; /* time since controller boot */ 268 1.2 mhitch u_int16_t event; 269 1.2 mhitch #define CISS_EVCLS_PROTO 0 270 1.2 mhitch #define CISS_EVCLS_PLUG 1 271 1.2 mhitch #define CISS_EVCLS_HW 2 272 1.2 mhitch #define CISS_EVCLS_ENV 3 273 1.2 mhitch #define CISS_EVCLS_PD 4 /* ciss_evpdchg in details */ 274 1.2 mhitch #define CISS_EVCLS_LD 5 275 1.2 mhitch #define CISS_EVCLS_CTRL 6 276 1.2 mhitch #define CISS_EVCLS_CISS 8 /* funky errors */ 277 1.2 mhitch #define CISS_EVCLS_RESV 9 278 1.2 mhitch u_int16_t subevent; 279 1.2 mhitch #define CISS_EVPROTO_STAT 0 280 1.2 mhitch #define CISS_EVPROTO_ERR 1 281 1.2 mhitch #define CISS_EVPLUG_PDCHG 0 /* ciss_evpdchg */ 282 1.2 mhitch #define CISS_EVPLUG_POWER 1 /* ciss_evpschg */ 283 1.2 mhitch #define CISS_EVPLUG_FAN 2 /* ciss_evfanchg */ 284 1.2 mhitch #define CISS_EVPLUG_UPS 3 /* ciss_evupschg */ 285 1.2 mhitch #define CISS_EVPLUG_CTRL 4 /* ciss_evctrlchg: ctrl removed? (; */ 286 1.2 mhitch #define CISS_EVHW_CABLES 0 287 1.2 mhitch #define CISS_EVHW_MEMORY 1 288 1.2 mhitch #define CISS_EVHW_FAN 2 /* detail as in CISS_EVPLUG_FAN */ 289 1.2 mhitch #define CISS_EVHW_VRM 3 290 1.2 mhitch #define CISS_EVENV_TEMP 0 /* ciss_evtempchg */ 291 1.2 mhitch #define CISS_EVENV_PS 1 292 1.2 mhitch #define CISS_EVENV_CHASSIS 2 293 1.2 mhitch #define CISS_EVENV_AC 3 294 1.2 mhitch #define CISS_EVPD_STAT 0 295 1.2 mhitch #define CISS_EVLD_STAT 0 296 1.2 mhitch #define CISS_EVLD_ERR 1 297 1.2 mhitch #define CISS_EVLD_CHECK 2 /* surface check */ 298 1.2 mhitch #define CISS_EVCTRL_STAT 0 299 1.2 mhitch u_int16_t detail; 300 1.2 mhitch #define CISS_EVSTAT_NONE 0 301 1.2 mhitch #define CISS_EVSTAT_DISABLE 1 302 1.2 mhitch #define CISS_EVSTAT_TMO 2 /* async event poll timeout */ 303 1.2 mhitch #define CISS_EVERR_OVERFLOW 0 /* event queue overflow */ 304 1.2 mhitch #define CISS_EVPLUG_REMOVE 0 305 1.2 mhitch #define CISS_EVPLUG_INSERT 1 306 1.2 mhitch #define CISS_EVFAN_FAULT 0 307 1.2 mhitch #define CISS_EVFAN_DEGRADED 1 308 1.2 mhitch #define CISS_EVFAN_OK 2 309 1.2 mhitch #define CISS_EVVRM_REMOVE 0 310 1.2 mhitch #define CISS_EVVRM_INSERT 1 311 1.2 mhitch #define CISS_EVVRM_FAILED 2 312 1.2 mhitch #define CISS_EVVRM_OK 3 313 1.2 mhitch #define CISS_EVTEMP_LIMEX 0 /* limit exceeded */ 314 1.2 mhitch #define CISS_EVTEMP_WARN 1 315 1.2 mhitch #define CISS_EVTEMP_OK 2 316 1.2 mhitch #define CISS_EVPS_FAIL 0 317 1.2 mhitch #define CISS_EVPS_OK 2 318 1.2 mhitch #define CISS_EVCHAS_OPEN 0 319 1.2 mhitch #define CISS_EVCHAS_CLOSE 2 320 1.2 mhitch #define CISS_EVAC_FAIL 0 321 1.2 mhitch #define CISS_EVAC_BATTLOW 1 322 1.2 mhitch #define CISS_EVPDSTAT_FAIL 0 323 1.2 mhitch #define CISS_EVLDSTAT_CHG 0 /* ciss_evldchg */ 324 1.2 mhitch #define CISS_EVLDSTAT_EXMEDIA 1 /* untolerant cfg got drive replaced */ 325 1.2 mhitch #define CISS_EVLDSTAT_RERDERR 2 /* ciss_evldrblderr */ 326 1.2 mhitch #define CISS_EVLDSTAT_REWRERR 3 /* ciss_evldrblderr */ 327 1.2 mhitch #define CISS_EVLDERR_FATAL 0 /* ciss_evlderr */ 328 1.2 mhitch #define CISS_EVCHECK_DONE 0 /* details have onle 16bit ld num */ 329 1.2 mhitch #define CISS_EVCTRLSTAT_CHG 0 /* ciss_evctrlstat */ 330 1.2 mhitch u_int8_t data[64]; 331 1.2 mhitch u_int8_t msg[80]; 332 1.2 mhitch u_int32_t tag; 333 1.2 mhitch u_int16_t monday; 334 1.2 mhitch u_int16_t year; 335 1.2 mhitch u_int32_t time; 336 1.2 mhitch u_int16_t presec; /* time for events before boot */ 337 1.2 mhitch u_int8_t device[8]; 338 1.2 mhitch u_int8_t resv[336]; 339 1.2 mhitch } __packed; 340 1.2 mhitch 341 1.2 mhitch struct ciss_evpdchg { /* details pointer */ 342 1.2 mhitch u_int16_t pd; 343 1.2 mhitch u_int8_t flag; /* 1 for configured */ 344 1.2 mhitch u_int8_t spare; 345 1.2 mhitch u_int8_t bigpd; /* big number of the pd */ 346 1.2 mhitch u_int8_t baynum; 347 1.2 mhitch } __packed; 348 1.2 mhitch 349 1.2 mhitch struct ciss_evpschg { /* details pointer */ 350 1.2 mhitch u_int16_t port; 351 1.2 mhitch u_int16_t psid; 352 1.2 mhitch u_int16_t box; 353 1.2 mhitch } __packed; 354 1.2 mhitch 355 1.2 mhitch struct ciss_evfanchg { /* details pointer */ 356 1.2 mhitch u_int16_t port; 357 1.2 mhitch u_int16_t fanid; 358 1.2 mhitch u_int16_t box; 359 1.2 mhitch } __packed; 360 1.2 mhitch 361 1.2 mhitch struct ciss_evupschg { /* details pointer */ 362 1.2 mhitch u_int16_t port; 363 1.2 mhitch u_int16_t upsid; 364 1.2 mhitch } __packed; 365 1.2 mhitch 366 1.2 mhitch struct ciss_evctrlchg { /* details pointer */ 367 1.2 mhitch u_int16_t slot; 368 1.2 mhitch } __packed; 369 1.2 mhitch 370 1.2 mhitch struct ciss_evtempchg { /* details pointer */ 371 1.2 mhitch u_int16_t port; 372 1.2 mhitch u_int16_t sensid; 373 1.2 mhitch u_int16_t box; 374 1.2 mhitch } __packed; 375 1.2 mhitch 376 1.2 mhitch struct ciss_evldchg { /* details pointer */ 377 1.2 mhitch u_int16_t ld; 378 1.2 mhitch u_int8_t prevstat; /* same as ldstat->state */ 379 1.2 mhitch u_int8_t newstat; /* same as ldstat->state */ 380 1.2 mhitch u_int8_t sparestat; 381 1.2 mhitch } __packed; 382 1.2 mhitch 383 1.2 mhitch struct ciss_evldrblderr { /* details pointer */ 384 1.2 mhitch u_int16_t ld; 385 1.2 mhitch u_int8_t replace; 386 1.2 mhitch u_int8_t errpd; 387 1.2 mhitch u_int8_t bigreplace; 388 1.2 mhitch u_int8_t bigerrpd; 389 1.2 mhitch } __packed; 390 1.2 mhitch 391 1.2 mhitch struct ciss_evlderr { /* details pointer */ 392 1.2 mhitch u_int16_t ld; 393 1.2 mhitch u_int16_t blkno[2]; /* unaligned; if >2tb see big later */ 394 1.2 mhitch u_int16_t count; 395 1.2 mhitch u_int8_t ldcmd; 396 1.2 mhitch u_int8_t bus; 397 1.2 mhitch u_int8_t target; 398 1.2 mhitch u_int8_t bigblkno[8]; /* unaligned */ 399 1.2 mhitch } __packed; 400 1.2 mhitch 401 1.2 mhitch struct ciss_evctrlstat { /* details pointer */ 402 1.2 mhitch u_int8_t prefctrl; 403 1.2 mhitch u_int8_t currmode; 404 1.2 mhitch u_int8_t redctrl; 405 1.2 mhitch u_int8_t redfail; 406 1.2 mhitch u_int8_t prevctrl; 407 1.2 mhitch u_int8_t prevmode; 408 1.2 mhitch u_int8_t prevred; 409 1.2 mhitch u_int8_t prevfail; 410 1.2 mhitch } __packed; 411 1.2 mhitch 412 1.1 he struct ciss_cmd { 413 1.1 he u_int8_t resv0; /* 00 */ 414 1.1 he u_int8_t sgin; /* 01: #sg in the cmd */ 415 1.1 he u_int16_t sglen; /* 02: #sg total */ 416 1.1 he u_int32_t id; /* 04: cmd id << 2 and status bits */ 417 1.1 he #define CISS_CMD_ERR 0x02 418 1.1 he u_int32_t id_hi; /* 08: not used */ 419 1.1 he u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */ 420 1.1 he #define CISS_CMD_MODE_PERIPH 0x00000000 421 1.1 he #define CISS_CMD_MODE_LD 0x40000000 422 1.1 he #define CISS_CMD_TGT_MASK 0x40ffffff 423 1.1 he #define CISS_CMD_BUS_MASK 0x3f000000 424 1.1 he #define CISS_CMD_BUS_SHIFT 24 425 1.1 he u_int32_t tgt2; /* 10: scsi-3 address bytes */ 426 1.1 he 427 1.1 he u_int8_t cdblen; /* 14: valid length of cdb */ 428 1.1 he u_int8_t flags; /* 15 */ 429 1.1 he #define CISS_CDB_CMD 0x00 430 1.1 he #define CISS_CDB_MSG 0x01 431 1.1 he #define CISS_CDB_NOTAG 0x00 432 1.1 he #define CISS_CDB_SIMPL 0x20 433 1.1 he #define CISS_CDB_QHEAD 0x28 434 1.1 he #define CISS_CDB_ORDR 0x30 435 1.1 he #define CISS_CDB_AUTO 0x38 436 1.1 he #define CISS_CDB_IN 0x80 437 1.1 he #define CISS_CDB_OUT 0x40 438 1.1 he u_int16_t tmo; /* 16: timeout in seconds */ 439 1.3 bouyer #define CISS_MAX_CDB 16 440 1.1 he u_int8_t cdb[16];/* 18 */ 441 1.1 he 442 1.1 he u_int64_t err_pa; /* 28: pa(struct ciss_error *) */ 443 1.1 he u_int32_t err_len;/* 30 */ 444 1.1 he 445 1.1 he struct { /* 34 */ 446 1.1 he u_int32_t addr_lo; 447 1.1 he u_int32_t addr_hi; 448 1.1 he u_int32_t len; 449 1.1 he u_int32_t flags; 450 1.1 he #define CISS_SG_EXT 0x0001 451 1.1 he } sgl[1]; 452 1.1 he } __packed; 453 1.1 he 454 1.1 he struct ciss_error { 455 1.1 he u_int8_t scsi_stat; /* SCSI_OK etc */ 456 1.1 he u_int8_t senselen; 457 1.1 he u_int16_t cmd_stat; 458 1.1 he #define CISS_ERR_OK 0 459 1.1 he #define CISS_ERR_TGTST 1 /* target status */ 460 1.1 he #define CISS_ERR_UNRUN 2 461 1.1 he #define CISS_ERR_OVRUN 3 462 1.1 he #define CISS_ERR_INVCMD 4 463 1.1 he #define CISS_ERR_PROTE 5 464 1.1 he #define CISS_ERR_HWERR 6 465 1.1 he #define CISS_ERR_CLOSS 7 466 1.1 he #define CISS_ERR_ABRT 8 467 1.1 he #define CISS_ERR_FABRT 9 468 1.1 he #define CISS_ERR_UABRT 10 469 1.1 he #define CISS_ERR_TMO 11 470 1.1 he #define CISS_ERR_NABRT 12 471 1.1 he u_int32_t resid; 472 1.1 he u_int8_t err_type[4]; 473 1.1 he u_int32_t err_info; 474 1.1 he u_int8_t sense[32]; 475 1.1 he } __packed; 476 1.1 he 477 1.1 he struct ciss_ccb { 478 1.1 he TAILQ_ENTRY(ciss_ccb) ccb_link; 479 1.1 he struct ciss_softc *ccb_sc; 480 1.1 he paddr_t ccb_cmdpa; 481 1.1 he enum { 482 1.1 he CISS_CCB_FREE = 0x01, 483 1.1 he CISS_CCB_READY = 0x02, 484 1.1 he CISS_CCB_ONQ = 0x04, 485 1.1 he CISS_CCB_PREQ = 0x08, 486 1.1 he CISS_CCB_POLL = 0x10, 487 1.1 he CISS_CCB_FAIL = 0x80 488 1.1 he #define CISS_CCB_BITS "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL" 489 1.1 he } ccb_state; 490 1.1 he 491 1.1 he struct scsipi_xfer *ccb_xs; 492 1.1 he size_t ccb_len; 493 1.1 he void *ccb_data; 494 1.1 he bus_dmamap_t ccb_dmamap; 495 1.1 he 496 1.1 he struct ciss_error ccb_err; 497 1.1 he struct ciss_cmd ccb_cmd; /* followed by sgl */ 498 1.1 he }; 499 1.1 he 500 1.1 he typedef TAILQ_HEAD(ciss_queue_head, ciss_ccb) ciss_queue_head; 501 1.1 he 502
Indexes created Sat Oct 25 16:10:12 GMT 2025