clmpcc.c revision 1.10.4.2 1 /* $NetBSD: clmpcc.c,v 1.10.4.2 2000/07/29 17:23:16 scw Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Steve C. Woodford.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller.
41 */
42
43 #include "opt_ddb.h"
44
45 #include <sys/types.h>
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/ioctl.h>
49 #include <sys/select.h>
50 #include <sys/tty.h>
51 #include <sys/proc.h>
52 #include <sys/user.h>
53 #include <sys/conf.h>
54 #include <sys/file.h>
55 #include <sys/uio.h>
56 #include <sys/kernel.h>
57 #include <sys/syslog.h>
58 #include <sys/device.h>
59 #include <sys/malloc.h>
60
61 #include <machine/bus.h>
62 #include <machine/intr.h>
63 #include <machine/param.h>
64
65 #include <dev/ic/clmpccreg.h>
66 #include <dev/ic/clmpccvar.h>
67 #include <dev/cons.h>
68
69
70 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH)
71 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive."
72 #endif
73
74
75 static int clmpcc_init __P((struct clmpcc_softc *sc));
76 static void clmpcc_shutdown __P((struct clmpcc_chan *));
77 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t,
78 int *, int *));
79 static int clmpcc_param __P((struct tty *, struct termios *));
80 static void clmpcc_set_params __P((struct clmpcc_chan *));
81 static void clmpcc_start __P((struct tty *));
82 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int));
83
84
85 cdev_decl(clmpcc);
86
87 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc)
88 #define CLMPCCCHAN(x) (minor(x) & 0x00003)
89 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000)
90
91 /*
92 * These should be in a header file somewhere...
93 */
94 #define ISSET(v, f) (((v) & (f)) != 0)
95 #define ISCLR(v, f) (((v) & (f)) == 0)
96 #define SET(v, f) (v) |= (f)
97 #define CLR(v, f) (v) &= ~(f)
98
99
100 extern struct cfdriver clmpcc_cd;
101
102
103 /*
104 * Make this an option variable one can patch.
105 */
106 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE;
107
108
109 /*
110 * Things needed when the device is used as a console
111 */
112 static struct clmpcc_softc *cons_sc = NULL;
113 static int cons_chan;
114 static int cons_rate;
115
116 static int clmpcc_common_getc __P((struct clmpcc_softc *, int));
117 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int));
118 int clmpcccngetc __P((dev_t));
119 void clmpcccnputc __P((dev_t, int));
120
121
122 /*
123 * Convenience functions, inlined for speed
124 */
125 #define integrate static inline
126 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int));
127 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int));
128 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int));
129 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int));
130 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *,
131 u_int));
132 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int));
133 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int));
134 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *));
135
136 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR)
137 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v)
138 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v)
139 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR)
140 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v)
141
142
143 integrate u_int8_t
144 clmpcc_rdreg(sc, offset)
145 struct clmpcc_softc *sc;
146 u_int offset;
147 {
148 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
149 offset ^= sc->sc_byteswap;
150 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
151 offset ^= CLMPCC_BYTESWAP_HIGH;
152 #endif
153 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
154 }
155
156 integrate void
157 clmpcc_wrreg(sc, offset, val)
158 struct clmpcc_softc *sc;
159 u_int offset;
160 u_int val;
161 {
162 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
163 offset ^= sc->sc_byteswap;
164 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
165 offset ^= CLMPCC_BYTESWAP_HIGH;
166 #endif
167 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
168 }
169
170 integrate u_int8_t
171 clmpcc_rdreg_odd(sc, offset)
172 struct clmpcc_softc *sc;
173 u_int offset;
174 {
175 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
176 offset ^= (sc->sc_byteswap & 2);
177 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
178 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
179 #endif
180 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
181 }
182
183 integrate void
184 clmpcc_wrreg_odd(sc, offset, val)
185 struct clmpcc_softc *sc;
186 u_int offset;
187 u_int val;
188 {
189 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
190 offset ^= (sc->sc_byteswap & 2);
191 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
192 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
193 #endif
194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
195 }
196
197 integrate void
198 clmpcc_wrtx_multi(sc, buff, count)
199 struct clmpcc_softc *sc;
200 u_int8_t *buff;
201 u_int count;
202 {
203 u_int offset = CLMPCC_REG_TDR;
204
205 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
206 offset ^= (sc->sc_byteswap & 2);
207 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
208 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
209 #endif
210 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count);
211 }
212
213 integrate u_int8_t
214 clmpcc_select_channel(sc, new_chan)
215 struct clmpcc_softc *sc;
216 u_int new_chan;
217 {
218 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR);
219
220 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan);
221
222 return old_chan;
223 }
224
225 integrate void
226 clmpcc_channel_cmd(sc, chan, cmd)
227 struct clmpcc_softc *sc;
228 int chan;
229 int cmd;
230 {
231 int i;
232
233 for (i = 5000; i; i--) {
234 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 )
235 break;
236 delay(1);
237 }
238
239 if ( i == 0 )
240 printf("%s: channel %d command timeout (idle)\n",
241 sc->sc_dev.dv_xname, chan);
242
243 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd);
244 }
245
246 integrate void
247 clmpcc_enable_transmitter(ch)
248 struct clmpcc_chan *ch;
249 {
250 u_int old;
251 int s;
252
253 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
254
255 s = splserial();
256 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
257 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY);
258 SET(ch->ch_tty->t_state, TS_BUSY);
259 splx(s);
260
261 clmpcc_select_channel(ch->ch_sc, old);
262 }
263
264 static int
265 clmpcc_speed(sc, speed, cor, bpr)
266 struct clmpcc_softc *sc;
267 speed_t speed;
268 int *cor, *bpr;
269 {
270 int c, co, br;
271
272 for (co = 0, c = 8; c <= 2048; co++, c *= 4) {
273 br = ((sc->sc_clk / c) / speed) - 1;
274 if ( br < 0x100 ) {
275 *cor = co;
276 *bpr = br;
277 return 0;
278 }
279 }
280
281 return -1;
282 }
283
284 void
285 clmpcc_attach(sc)
286 struct clmpcc_softc *sc;
287 {
288 struct clmpcc_chan *ch;
289 struct tty *tp;
290 int chan;
291
292 if ( cons_sc != NULL &&
293 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh )
294 cons_sc = sc;
295
296 /* Initialise the chip */
297 clmpcc_init(sc);
298
299 printf(": Cirrus Logic CD240%c Serial Controller\n",
300 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1');
301
302 #ifndef __GENERIC_SOFT_INTERRUPTS
303 sc->sc_soft_running = 0;
304 #else
305 sc->sc_softintr_cookie =
306 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc);
307 #ifdef DEBUG
308 if (sc->sc_softintr_cookie == NULL)
309 panic("clmpcc_attach: softintr_establish");
310 #endif
311 #endif
312 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans));
313
314 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
315 ch = &sc->sc_chans[chan];
316
317 ch->ch_sc = sc;
318 ch->ch_car = chan;
319
320 tp = ttymalloc();
321 tp->t_oproc = clmpcc_start;
322 tp->t_param = clmpcc_param;
323
324 ch->ch_tty = tp;
325
326 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT);
327 if ( ch->ch_ibuf == NULL ) {
328 printf("%s(%d): unable to allocate ring buffer\n",
329 sc->sc_dev.dv_xname, chan);
330 return;
331 }
332
333 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]);
334 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
335
336 tty_attach(tp);
337 }
338
339 printf("%s: %d channels available", sc->sc_dev.dv_xname,
340 CLMPCC_NUM_CHANS);
341 if ( cons_sc == sc ) {
342 printf(", console on channel %d.\n", cons_chan);
343 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE);
344 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR);
345 } else
346 printf(".\n");
347 }
348
349 static int
350 clmpcc_init(sc)
351 struct clmpcc_softc *sc;
352 {
353 u_int tcor, tbpr;
354 u_int rcor, rbpr;
355 u_int msvr_rts, msvr_dtr;
356 u_int ccr;
357 int is_console;
358 int i;
359
360 /*
361 * All we're really concerned about here is putting the chip
362 * into a quiescent state so that it won't do anything until
363 * clmpccopen() is called. (Except the console channel.)
364 */
365
366 /*
367 * If the chip is acting as console, set all channels to the supplied
368 * console baud rate. Otherwise, plump for 9600.
369 */
370 if ( cons_sc &&
371 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) {
372 clmpcc_speed(sc, cons_rate, &tcor, &tbpr);
373 clmpcc_speed(sc, cons_rate, &rcor, &rbpr);
374 is_console = 1;
375 } else {
376 clmpcc_speed(sc, 9600, &tcor, &tbpr);
377 clmpcc_speed(sc, 9600, &rcor, &rbpr);
378 is_console = 0;
379 }
380
381 /* Allow any pending output to be sent */
382 delay(10000);
383
384 /* Send the Reset All command to channel 0 (resets all channels!) */
385 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL);
386
387 delay(1000);
388
389 /*
390 * The chip will set it's firmware revision register to a non-zero
391 * value to indicate completion of reset.
392 */
393 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--)
394 delay(1);
395
396 if ( i == 0 ) {
397 /*
398 * Watch out... If this chip is console, the message
399 * probably won't be sent since we just reset it!
400 */
401 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname);
402 return -1;
403 }
404
405 for (i = 0; i < CLMPCC_NUM_CHANS; i++) {
406 clmpcc_select_channel(sc, i);
407
408 /* All interrupts are disabled to begin with */
409 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0);
410
411 /* Make sure the channel interrupts on the correct vectors */
412 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base);
413 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr);
414 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr);
415 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr);
416
417 /* Receive timer prescaler set to 1ms */
418 clmpcc_wrreg(sc, CLMPCC_REG_TPR,
419 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1));
420
421 /* We support Async mode only */
422 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC);
423
424 /* Set the required baud rate */
425 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor));
426 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr);
427 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor));
428 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr);
429
430 /* Always default to 8N1 (XXX what about console?) */
431 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS |
432 CLMPCC_COR1_NO_PARITY |
433 CLMPCC_COR1_IGNORE_PAR);
434
435 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0);
436
437 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1);
438
439 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd |
440 CLMPCC_COR4_CDzd |
441 CLMPCC_COR4_CTSzd);
442
443 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod |
444 CLMPCC_COR5_CDod |
445 CLMPCC_COR5_CTSod |
446 CLMPCC_COR5_FLOW_NORM);
447
448 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0);
449 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0);
450
451 /* Set the receive FIFO timeout */
452 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT);
453 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0);
454
455 /* At this point, we set up the console differently */
456 if ( is_console && i == cons_chan ) {
457 msvr_rts = CLMPCC_MSVR_RTS;
458 msvr_dtr = CLMPCC_MSVR_DTR;
459 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN;
460 } else {
461 msvr_rts = 0;
462 msvr_dtr = 0;
463 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS;
464 }
465
466 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts);
467 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr);
468 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr);
469 delay(100);
470 }
471
472 return 0;
473 }
474
475 static void
476 clmpcc_shutdown(ch)
477 struct clmpcc_chan *ch;
478 {
479 int oldch;
480
481 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
482
483 /* Turn off interrupts. */
484 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0);
485
486 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
487 /* Disable the transmitter and receiver */
488 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS |
489 CLMPCC_CCR_T0_TX_DIS);
490
491 /* Drop RTS and DTR */
492 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
493 }
494
495 clmpcc_select_channel(ch->ch_sc, oldch);
496 }
497
498 int
499 clmpccopen(dev, flag, mode, p)
500 dev_t dev;
501 int flag, mode;
502 struct proc *p;
503 {
504 struct clmpcc_softc *sc;
505 struct clmpcc_chan *ch;
506 struct tty *tp;
507 int oldch;
508 int error;
509 int unit;
510
511 if ( (unit = CLMPCCUNIT(dev)) >= clmpcc_cd.cd_ndevs ||
512 (sc = clmpcc_cd.cd_devs[unit]) == NULL ) {
513 return ENXIO;
514 }
515
516 ch = &sc->sc_chans[CLMPCCCHAN(dev)];
517
518 tp = ch->ch_tty;
519
520 if ( ISSET(tp->t_state, TS_ISOPEN) &&
521 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 )
522 return EBUSY;
523
524 /*
525 * Do the following iff this is a first open.
526 */
527 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
528
529 ttychars(tp);
530
531 tp->t_dev = dev;
532 tp->t_iflag = TTYDEF_IFLAG;
533 tp->t_oflag = TTYDEF_OFLAG;
534 tp->t_lflag = TTYDEF_LFLAG;
535 tp->t_cflag = TTYDEF_CFLAG;
536 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED;
537
538 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) )
539 SET(tp->t_cflag, CLOCAL);
540 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) )
541 SET(tp->t_cflag, CRTSCTS);
542 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) )
543 SET(tp->t_cflag, MDMBUF);
544
545 /*
546 * Override some settings if the channel is being
547 * used as the console.
548 */
549 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
550 tp->t_ospeed = tp->t_ispeed = cons_rate;
551 SET(tp->t_cflag, CLOCAL);
552 CLR(tp->t_cflag, CRTSCTS);
553 CLR(tp->t_cflag, HUPCL);
554 }
555
556 ch->ch_control = 0;
557
558 clmpcc_param(tp, &tp->t_termios);
559 ttsetwater(tp);
560
561 /* Clear the input ring */
562 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
563
564 /* Select the channel */
565 oldch = clmpcc_select_channel(sc, ch->ch_car);
566
567 /* Reset it */
568 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR |
569 CLMPCC_CCR_T0_RX_EN |
570 CLMPCC_CCR_T0_TX_EN);
571
572 /* Enable receiver and modem change interrupts. */
573 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM |
574 CLMPCC_IER_RET |
575 CLMPCC_IER_RX_FIFO);
576
577 /* Raise RTS and DTR */
578 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
579
580 clmpcc_select_channel(sc, oldch);
581 } else
582 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 )
583 return EBUSY;
584
585 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK));
586 if (error)
587 goto bad;
588
589 error = (*linesw[tp->t_line].l_open)(dev, tp);
590 if (error)
591 goto bad;
592
593 return 0;
594
595 bad:
596 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
597 /*
598 * We failed to open the device, and nobody else had it opened.
599 * Clean up the state as appropriate.
600 */
601 clmpcc_shutdown(ch);
602 }
603
604 return error;
605 }
606
607 int
608 clmpccclose(dev, flag, mode, p)
609 dev_t dev;
610 int flag, mode;
611 struct proc *p;
612 {
613 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)];
614 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
615 struct tty *tp = ch->ch_tty;
616 int s;
617
618 if ( ISCLR(tp->t_state, TS_ISOPEN) )
619 return 0;
620
621 (*linesw[tp->t_line].l_close)(tp, flag);
622
623 s = spltty();
624
625 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
626 /*
627 * Although we got a last close, the device may still be in
628 * use; e.g. if this was the dialout node, and there are still
629 * processes waiting for carrier on the non-dialout node.
630 */
631 clmpcc_shutdown(ch);
632 }
633
634 ttyclose(tp);
635
636 splx(s);
637
638 return 0;
639 }
640
641 int
642 clmpccread(dev, uio, flag)
643 dev_t dev;
644 struct uio *uio;
645 int flag;
646 {
647 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)];
648 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
649
650 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
651 }
652
653 int
654 clmpccwrite(dev, uio, flag)
655 dev_t dev;
656 struct uio *uio;
657 int flag;
658 {
659 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)];
660 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
661
662 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
663 }
664
665 struct tty *
666 clmpcctty(dev)
667 dev_t dev;
668 {
669 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)];
670
671 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty);
672 }
673
674 int
675 clmpccioctl(dev, cmd, data, flag, p)
676 dev_t dev;
677 u_long cmd;
678 caddr_t data;
679 int flag;
680 struct proc *p;
681 {
682 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(dev)];
683 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
684 struct tty *tp = ch->ch_tty;
685 int error;
686
687 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
688 if (error >= 0)
689 return error;
690
691 error = ttioctl(tp, cmd, data, flag, p);
692 if (error >= 0)
693 return error;
694
695 error = 0;
696
697 switch (cmd) {
698 case TIOCSBRK:
699 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK);
700 clmpcc_enable_transmitter(ch);
701 break;
702
703 case TIOCCBRK:
704 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK);
705 clmpcc_enable_transmitter(ch);
706 break;
707
708 case TIOCSDTR:
709 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS);
710 break;
711
712 case TIOCCDTR:
713 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC);
714 break;
715
716 case TIOCMSET:
717 clmpcc_modem_control(ch, *((int *)data), DMSET);
718 break;
719
720 case TIOCMBIS:
721 clmpcc_modem_control(ch, *((int *)data), DMBIS);
722 break;
723
724 case TIOCMBIC:
725 clmpcc_modem_control(ch, *((int *)data), DMBIC);
726 break;
727
728 case TIOCMGET:
729 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET);
730 break;
731
732 case TIOCGFLAGS:
733 *((int *)data) = ch->ch_openflags;
734 break;
735
736 case TIOCSFLAGS:
737 error = suser(p->p_ucred, &p->p_acflag);
738 if ( error )
739 break;
740 ch->ch_openflags = *((int *)data) &
741 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
742 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
743 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) )
744 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR);
745 break;
746
747 default:
748 error = ENOTTY;
749 break;
750 }
751
752 return error;
753 }
754
755 int
756 clmpcc_modem_control(ch, bits, howto)
757 struct clmpcc_chan *ch;
758 int bits;
759 int howto;
760 {
761 struct clmpcc_softc *sc = ch->ch_sc;
762 struct tty *tp = ch->ch_tty;
763 int oldch;
764 int msvr;
765 int rbits = 0;
766
767 oldch = clmpcc_select_channel(sc, ch->ch_car);
768
769 switch ( howto ) {
770 case DMGET:
771 msvr = clmpcc_rd_msvr(sc);
772
773 if ( sc->sc_swaprtsdtr ) {
774 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0;
775 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0;
776 } else {
777 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0;
778 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0;
779 }
780
781 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0;
782 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0;
783 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0;
784 break;
785
786 case DMSET:
787 if ( sc->sc_swaprtsdtr ) {
788 if ( ISCLR(tp->t_cflag, CRTSCTS) )
789 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
790 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0);
791 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
792 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0);
793 } else {
794 if ( ISCLR(tp->t_cflag, CRTSCTS) )
795 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
796 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0);
797 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
798 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0);
799 }
800 break;
801
802 case DMBIS:
803 if ( sc->sc_swaprtsdtr ) {
804 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
805 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
806 if ( ISSET(bits, TIOCM_DTR) )
807 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
808 } else {
809 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
810 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
811 if ( ISSET(bits, TIOCM_DTR) )
812 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
813 }
814 break;
815
816 case DMBIC:
817 if ( sc->sc_swaprtsdtr ) {
818 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
819 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
820 if ( ISCLR(bits, TIOCM_DTR) )
821 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
822 } else {
823 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
824 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
825 if ( ISCLR(bits, TIOCM_DTR) )
826 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
827 }
828 break;
829 }
830
831 clmpcc_select_channel(sc, oldch);
832
833 return rbits;
834 }
835
836 static int
837 clmpcc_param(tp, t)
838 struct tty *tp;
839 struct termios *t;
840 {
841 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)];
842 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
843 u_char cor;
844 u_char oldch;
845 int oclk, obpr;
846 int iclk, ibpr;
847 int s;
848
849 /* Check requested parameters. */
850 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 )
851 return EINVAL;
852
853 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 )
854 return EINVAL;
855
856 /*
857 * For the console, always force CLOCAL and !HUPCL, so that the port
858 * is always active.
859 */
860 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) ||
861 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
862 SET(t->c_cflag, CLOCAL);
863 CLR(t->c_cflag, HUPCL);
864 }
865
866 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
867
868 /* If ospeed it zero, hangup the line */
869 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS);
870
871 if ( t->c_ospeed ) {
872 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk);
873 ch->ch_tbpr = obpr;
874 } else {
875 ch->ch_tcor = 0;
876 ch->ch_tbpr = 0;
877 }
878
879 if ( t->c_ispeed ) {
880 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk);
881 ch->ch_rbpr = ibpr;
882 } else {
883 ch->ch_rcor = 0;
884 ch->ch_rbpr = 0;
885 }
886
887 /* Work out value to use for COR1 */
888 cor = 0;
889 if ( ISSET(t->c_cflag, PARENB) ) {
890 cor |= CLMPCC_COR1_NORM_PARITY;
891 if ( ISSET(t->c_cflag, PARODD) )
892 cor |= CLMPCC_COR1_ODD_PARITY;
893 }
894
895 if ( ISCLR(t->c_cflag, INPCK) )
896 cor |= CLMPCC_COR1_IGNORE_PAR;
897
898 switch ( t->c_cflag & CSIZE ) {
899 case CS5:
900 cor |= CLMPCC_COR1_CHAR_5BITS;
901 break;
902
903 case CS6:
904 cor |= CLMPCC_COR1_CHAR_6BITS;
905 break;
906
907 case CS7:
908 cor |= CLMPCC_COR1_CHAR_7BITS;
909 break;
910
911 case CS8:
912 cor |= CLMPCC_COR1_CHAR_8BITS;
913 break;
914 }
915
916 ch->ch_cor1 = cor;
917
918 /*
919 * The only interesting bit in COR2 is 'CTS Automatic Enable'
920 * when hardware flow control is in effect.
921 */
922 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0;
923
924 /* COR3 needs to be set to the number of stop bits... */
925 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 :
926 CLMPCC_COR3_STOP_1;
927
928 /*
929 * COR4 contains the FIFO threshold setting.
930 * We adjust the threshold depending on the input speed...
931 */
932 if ( t->c_ispeed <= 1200 )
933 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW;
934 else if ( t->c_ispeed <= 19200 )
935 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED;
936 else
937 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH;
938
939 /*
940 * If chip is used with CTS and DTR swapped, we can enable
941 * automatic hardware flow control.
942 */
943 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) )
944 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM;
945 else
946 ch->ch_cor5 = 0;
947
948 s = splserial();
949 oldch = clmpcc_select_channel(sc, ch->ch_car);
950
951 /*
952 * COR2 needs to be set immediately otherwise we might never get
953 * a Tx EMPTY interrupt to change the other parameters.
954 */
955 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 )
956 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
957
958 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) )
959 clmpcc_set_params(ch);
960 else
961 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
962
963 clmpcc_select_channel(sc, oldch);
964
965 splx(s);
966
967 return 0;
968 }
969
970 static void
971 clmpcc_set_params(ch)
972 struct clmpcc_chan *ch;
973 {
974 struct clmpcc_softc *sc = ch->ch_sc;
975 u_char r1;
976 u_char r2;
977
978 if ( ch->ch_tcor || ch->ch_tbpr ) {
979 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR);
980 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR);
981 /* Only write Tx rate if it really has changed */
982 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) {
983 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor);
984 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr);
985 }
986 }
987
988 if ( ch->ch_rcor || ch->ch_rbpr ) {
989 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR);
990 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR);
991 /* Only write Rx rate if it really has changed */
992 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) {
993 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor);
994 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr);
995 }
996 }
997
998 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) {
999 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1);
1000 /* Any change to COR1 requires an INIT command */
1001 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1002 }
1003
1004 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 )
1005 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3);
1006
1007 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1008 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) {
1009 /*
1010 * Note: If the FIFO has changed, we always set it to
1011 * zero here and disable the Receive Timeout interrupt.
1012 * It's up to the Rx Interrupt handler to pick the
1013 * appropriate moment to write the new FIFO length.
1014 */
1015 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK);
1016 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1017 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET);
1018 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1019 }
1020
1021 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5);
1022 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) {
1023 r1 &= ~CLMPCC_COR5_FLOW_MASK;
1024 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5);
1025 }
1026 }
1027
1028 static void
1029 clmpcc_start(tp)
1030 struct tty *tp;
1031 {
1032 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)];
1033 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1034 u_int oldch;
1035 int s;
1036
1037 s = spltty();
1038
1039 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1040 if ( tp->t_outq.c_cc <= tp->t_lowat ) {
1041 if ( ISSET(tp->t_state, TS_ASLEEP) ) {
1042 CLR(tp->t_state, TS_ASLEEP);
1043 wakeup(&tp->t_outq);
1044 }
1045 selwakeup(&tp->t_wsel);
1046 }
1047
1048 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1049 CLMPCC_FLG_END_BREAK) ||
1050 tp->t_outq.c_cc > 0 ) {
1051
1052 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1053 CLMPCC_FLG_END_BREAK) ) {
1054 ch->ch_obuf_addr = tp->t_outq.c_cf;
1055 ch->ch_obuf_size = ndqb(&tp->t_outq, 0);
1056 }
1057
1058 /* Enable TX empty interrupts */
1059 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
1060 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
1061 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) |
1062 CLMPCC_IER_TX_EMPTY);
1063 clmpcc_select_channel(ch->ch_sc, oldch);
1064 SET(tp->t_state, TS_BUSY);
1065 }
1066 }
1067
1068 splx(s);
1069 }
1070
1071 /*
1072 * Stop output on a line.
1073 */
1074 void
1075 clmpccstop(tp, flag)
1076 struct tty *tp;
1077 int flag;
1078 {
1079 struct clmpcc_softc *sc = clmpcc_cd.cd_devs[CLMPCCUNIT(tp->t_dev)];
1080 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1081 int s;
1082
1083 s = splserial();
1084
1085 if ( ISSET(tp->t_state, TS_BUSY) ) {
1086 if ( ISCLR(tp->t_state, TS_TTSTOP) )
1087 SET(tp->t_state, TS_FLUSH);
1088 ch->ch_obuf_size = 0;
1089 }
1090 splx(s);
1091 }
1092
1093 /*
1094 * RX interrupt routine
1095 */
1096 int
1097 clmpcc_rxintr(arg)
1098 void *arg;
1099 {
1100 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1101 struct clmpcc_chan *ch;
1102 u_int8_t *put, *end, rxd;
1103 u_char errstat;
1104 u_char fc, tc;
1105 u_char risr;
1106 u_char rir;
1107 #ifdef DDB
1108 int saw_break = 0;
1109 #endif
1110
1111 /* Receive interrupt active? */
1112 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1113
1114 /*
1115 * If we're using auto-vectored interrupts, we have to
1116 * verify if the chip is generating the interrupt.
1117 */
1118 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 )
1119 return 0;
1120
1121 /* Get pointer to interrupting channel's data structure */
1122 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK];
1123
1124 /* Get the interrupt status register */
1125 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl);
1126 if ( risr & CLMPCC_RISR_TIMEOUT ) {
1127 u_char reg;
1128 /*
1129 * Set the FIFO threshold to zero, and disable
1130 * further receive timeout interrupts.
1131 */
1132 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1133 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK);
1134 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1135 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET);
1136 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1137 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1138 return 1;
1139 }
1140
1141 /* How many bytes are waiting in the FIFO? */
1142 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK;
1143
1144 #ifdef DDB
1145 /*
1146 * Allow BREAK on the console to drop to the debugger.
1147 */
1148 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) &&
1149 risr & CLMPCC_RISR_BREAK ) {
1150 saw_break = 1;
1151 }
1152 #endif
1153
1154 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) {
1155 /* Just get rid of the data */
1156 while ( fc-- )
1157 (void) clmpcc_rd_rxdata(sc);
1158 goto rx_done;
1159 }
1160
1161 put = ch->ch_ibuf_wr;
1162 end = ch->ch_ibuf_end;
1163
1164 /*
1165 * Note: The chip is completely hosed WRT these error
1166 * conditions; there seems to be no way to associate
1167 * the error with the correct character in the FIFO.
1168 * We compromise by tagging the first character we read
1169 * with the error. Not perfect, but there's no other way.
1170 */
1171 errstat = 0;
1172 if ( risr & CLMPCC_RISR_PARITY )
1173 errstat |= TTY_PE;
1174 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) )
1175 errstat |= TTY_FE;
1176
1177 /*
1178 * As long as there are characters in the FIFO, and we
1179 * have space for them...
1180 */
1181 while ( fc > 0 ) {
1182
1183 *put++ = rxd = clmpcc_rd_rxdata(sc);
1184 *put++ = errstat;
1185
1186 if ( put >= end )
1187 put = ch->ch_ibuf;
1188
1189 if ( put == ch->ch_ibuf_rd ) {
1190 put -= 2;
1191 if ( put < ch->ch_ibuf )
1192 put = end - 2;
1193 }
1194
1195 errstat = 0;
1196 fc--;
1197 }
1198
1199 ch->ch_ibuf_wr = put;
1200
1201 #if 0
1202 if ( sc->sc_swaprtsdtr == 0 &&
1203 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) {
1204 /*
1205 * If RTS/DTR are not physically swapped, we have to
1206 * do hardware flow control manually
1207 */
1208 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0);
1209 }
1210 #endif
1211
1212 rx_done:
1213 if ( fc != tc ) {
1214 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) {
1215 u_char reg;
1216 /*
1217 * Set the FIFO threshold to the preset value,
1218 * and enable receive timeout interrupts.
1219 */
1220 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1221 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4;
1222 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg);
1223 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1224 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET);
1225 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1226 }
1227
1228 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1229 #ifndef __GENERIC_SOFT_INTERRUPTS
1230 if ( sc->sc_soft_running == 0 ) {
1231 sc->sc_soft_running = 1;
1232 (sc->sc_softhook)(sc);
1233 }
1234 #else
1235 softintr_schedule(sc->sc_softintr_cookie);
1236 #endif
1237 } else
1238 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1239
1240 #ifdef DDB
1241 /*
1242 * Only =after= we write REOIR is it safe to drop to the debugger.
1243 */
1244 if ( saw_break )
1245 Debugger();
1246 #endif
1247
1248 return 1;
1249 }
1250
1251 /*
1252 * Tx interrupt routine
1253 */
1254 int
1255 clmpcc_txintr(arg)
1256 void *arg;
1257 {
1258 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1259 struct clmpcc_chan *ch;
1260 struct tty *tp;
1261 u_char ftc, oftc;
1262 u_char tir, teoir;
1263 int etcmode = 0;
1264
1265 /* Tx interrupt active? */
1266 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR);
1267
1268 /*
1269 * If we're using auto-vectored interrupts, we have to
1270 * verify if the chip is generating the interrupt.
1271 */
1272 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 )
1273 return 0;
1274
1275 /* Get pointer to interrupting channel's data structure */
1276 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK];
1277 tp = ch->ch_tty;
1278
1279 /* Dummy read of the interrupt status register */
1280 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR);
1281
1282 /* Make sure embedded transmit commands are disabled */
1283 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
1284
1285 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC);
1286
1287 /* Handle a delayed parameter change */
1288 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) {
1289 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
1290 clmpcc_set_params(ch);
1291 }
1292
1293 if ( ch->ch_obuf_size > 0 ) {
1294 u_int n = min(ch->ch_obuf_size, ftc);
1295
1296 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n);
1297
1298 ftc -= n;
1299 ch->ch_obuf_size -= n;
1300 ch->ch_obuf_addr += n;
1301
1302 } else {
1303 /*
1304 * Check if we should start/stop a break
1305 */
1306 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) {
1307 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK);
1308 /* Enable embedded transmit commands */
1309 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1310 ch->ch_cor2 | CLMPCC_COR2_ETC);
1311 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1312 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK);
1313 ftc -= 2;
1314 etcmode = 1;
1315 }
1316
1317 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) {
1318 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK);
1319 /* Enable embedded transmit commands */
1320 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1321 ch->ch_cor2 | CLMPCC_COR2_ETC);
1322 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1323 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK);
1324 ftc -= 2;
1325 etcmode = 1;
1326 }
1327 }
1328
1329 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1330
1331 if ( ftc != oftc ) {
1332 /*
1333 * Enable/disable the Tx FIFO threshold interrupt
1334 * according to how much data is in the FIFO.
1335 * However, always disable the FIFO threshold if
1336 * we've left the channel in 'Embedded Transmit
1337 * Command' mode.
1338 */
1339 if ( etcmode || ftc >= ch->ch_cor4 )
1340 tir &= ~CLMPCC_IER_TX_FIFO;
1341 else
1342 tir |= CLMPCC_IER_TX_FIFO;
1343 teoir = 0;
1344 } else {
1345 /*
1346 * No data was sent.
1347 * Disable transmit interrupt.
1348 */
1349 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO);
1350 teoir = CLMPCC_TEOIR_NO_TRANS;
1351
1352 /*
1353 * Request Tx processing in the soft interrupt handler
1354 */
1355 ch->ch_tx_done = 1;
1356 #ifndef __GENERIC_SOFT_INTERRUPTS
1357 if ( sc->sc_soft_running == 0 ) {
1358 sc->sc_soft_running = 1;
1359 (sc->sc_softhook)(sc);
1360 }
1361 #else
1362 softintr_schedule(sc->sc_softintr_cookie);
1363 #endif
1364 }
1365
1366 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir);
1367 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir);
1368
1369 return 1;
1370 }
1371
1372 /*
1373 * Modem change interrupt routine
1374 */
1375 int
1376 clmpcc_mdintr(arg)
1377 void *arg;
1378 {
1379 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1380 u_char mir;
1381
1382 /* Modem status interrupt active? */
1383 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR);
1384
1385 /*
1386 * If we're using auto-vectored interrupts, we have to
1387 * verify if the chip is generating the interrupt.
1388 */
1389 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 )
1390 return 0;
1391
1392 /* Dummy read of the interrupt status register */
1393 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR);
1394
1395 /* Retrieve current status of modem lines. */
1396 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |=
1397 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1398
1399 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0);
1400
1401 #ifndef __GENERIC_SOFT_INTERRUPTS
1402 if ( sc->sc_soft_running == 0 ) {
1403 sc->sc_soft_running = 1;
1404 (sc->sc_softhook)(sc);
1405 }
1406 #else
1407 softintr_schedule(sc->sc_softintr_cookie);
1408 #endif
1409
1410 return 1;
1411 }
1412
1413 void
1414 clmpcc_softintr(arg)
1415 void *arg;
1416 {
1417 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1418 struct clmpcc_chan *ch;
1419 struct tty *tp;
1420 int (*rint) __P((int, struct tty *));
1421 u_char *get;
1422 u_char reg;
1423 u_int c;
1424 int chan;
1425
1426 #ifndef __GENERIC_SOFT_INTERRUPTS
1427 sc->sc_soft_running = 0;
1428 #endif
1429
1430 /* Handle Modem state changes too... */
1431
1432 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
1433 ch = &sc->sc_chans[chan];
1434 tp = ch->ch_tty;
1435
1436 get = ch->ch_ibuf_rd;
1437 rint = linesw[tp->t_line].l_rint;
1438
1439 /* Squirt buffered incoming data into the tty layer */
1440 while ( get != ch->ch_ibuf_wr ) {
1441 c = get[0];
1442 c |= ((u_int)get[1]) << 8;
1443 if ( (rint)(c, tp) == -1 ) {
1444 ch->ch_ibuf_rd = ch->ch_ibuf_wr;
1445 break;
1446 }
1447
1448 get += 2;
1449 if ( get == ch->ch_ibuf_end )
1450 get = ch->ch_ibuf;
1451
1452 ch->ch_ibuf_rd = get;
1453 }
1454
1455 /*
1456 * Is the transmitter idle and in need of attention?
1457 */
1458 if ( ch->ch_tx_done ) {
1459 ch->ch_tx_done = 0;
1460
1461 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) {
1462 clmpcc_channel_cmd(sc, ch->ch_car,
1463 CLMPCC_CCR_T0_INIT |
1464 CLMPCC_CCR_T0_RX_EN |
1465 CLMPCC_CCR_T0_TX_EN);
1466 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1467
1468 /*
1469 * Allow time for the channel to initialise.
1470 * (Empirically derived duration; there must
1471 * be another way to determine the command
1472 * has completed without busy-waiting...)
1473 */
1474 delay(800);
1475
1476 /*
1477 * Update the tty layer's idea of the carrier
1478 * bit, in case we changed CLOCAL or MDMBUF.
1479 * We don't hang up here; we only do that by
1480 * explicit request.
1481 */
1482 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1483 (*linesw[tp->t_line].l_modem)(tp, reg != 0);
1484 }
1485
1486 CLR(tp->t_state, TS_BUSY);
1487 if ( ISSET(tp->t_state, TS_FLUSH) )
1488 CLR(tp->t_state, TS_FLUSH);
1489 else
1490 ndflush(&tp->t_outq,
1491 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf));
1492
1493 (*linesw[tp->t_line].l_start)(tp);
1494 }
1495 }
1496 }
1497
1498
1499 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1500 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1501 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1502 /*
1503 * Following are all routines needed for a cd240x channel to act as console
1504 */
1505 int
1506 clmpcc_cnattach(sc, chan, rate)
1507 struct clmpcc_softc *sc;
1508 int chan;
1509 int rate;
1510 {
1511 cons_sc = sc;
1512 cons_chan = chan;
1513 cons_rate = rate;
1514
1515 return 0;
1516 }
1517
1518 /*
1519 * The following functions are polled getc and putc routines, for console use.
1520 */
1521 static int
1522 clmpcc_common_getc(sc, chan)
1523 struct clmpcc_softc *sc;
1524 int chan;
1525 {
1526 u_char old_chan;
1527 u_char old_ier;
1528 u_char ch, rir, risr;
1529 int s;
1530
1531 s = splhigh();
1532
1533 /* Save the currently active channel */
1534 old_chan = clmpcc_select_channel(sc, chan);
1535
1536 /*
1537 * We have to put the channel into RX interrupt mode before
1538 * trying to read the Rx data register. So save the previous
1539 * interrupt mode.
1540 */
1541 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1542 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO);
1543
1544 /* Loop until we get a character */
1545 for (;;) {
1546 /*
1547 * The REN bit will be set in the Receive Interrupt Register
1548 * when the CD240x has a character to process. Remember,
1549 * the RACT bit won't be set until we generate an interrupt
1550 * acknowledge cycle via the MD front-end.
1551 */
1552 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1553 if ( (rir & CLMPCC_RIR_REN) == 0 )
1554 continue;
1555
1556 /* Acknowledge the request */
1557 if ( sc->sc_iackhook )
1558 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX);
1559
1560 /*
1561 * Determine if the interrupt is for the required channel
1562 * and if valid data is available.
1563 */
1564 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1565 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR);
1566 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan ||
1567 risr != 0 ) {
1568 /* Rx error, or BREAK */
1569 clmpcc_wrreg(sc, CLMPCC_REG_REOIR,
1570 CLMPCC_REOIR_NO_TRANS);
1571 } else {
1572 /* Dummy read of the FIFO count register */
1573 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC);
1574
1575 /* Fetch the received character */
1576 ch = clmpcc_rd_rxdata(sc);
1577
1578 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1579 break;
1580 }
1581 }
1582
1583 /* Restore the original IER and CAR register contents */
1584 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier);
1585 clmpcc_select_channel(sc, old_chan);
1586
1587 splx(s);
1588 return ch;
1589 }
1590
1591
1592 static void
1593 clmpcc_common_putc(sc, chan, c)
1594 struct clmpcc_softc *sc;
1595 int chan;
1596 int c;
1597 {
1598 u_char old_chan;
1599 int s = splhigh();
1600
1601 /* Save the currently active channel */
1602 old_chan = clmpcc_select_channel(sc, chan);
1603
1604 /*
1605 * Since we can only access the Tx Data register from within
1606 * the interrupt handler, the easiest way to get console data
1607 * onto the wire is using one of the Special Transmit Character
1608 * registers.
1609 */
1610 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c);
1611 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) |
1612 CLMPCC_STCR_SND_SPC);
1613
1614 /* Wait until the "Send Special Character" command is accepted */
1615 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 )
1616 ;
1617
1618 /* Restore the previous channel selected */
1619 clmpcc_select_channel(sc, old_chan);
1620
1621 splx(s);
1622 }
1623
1624 int
1625 clmpcccngetc(dev)
1626 dev_t dev;
1627 {
1628 return clmpcc_common_getc(cons_sc, cons_chan);
1629 }
1630
1631 /*
1632 * Console kernel output character routine.
1633 */
1634 void
1635 clmpcccnputc(dev, c)
1636 dev_t dev;
1637 int c;
1638 {
1639 if ( c == '\n' )
1640 clmpcc_common_putc(cons_sc, cons_chan, '\r');
1641
1642 clmpcc_common_putc(cons_sc, cons_chan, c);
1643 }
1644