clmpcc.c revision 1.29 1 /* $NetBSD: clmpcc.c,v 1.29 2006/07/21 16:48:48 ad Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Steve C. Woodford.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller.
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.29 2006/07/21 16:48:48 ad Exp $");
45
46 #include "opt_ddb.h"
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/ioctl.h>
51 #include <sys/select.h>
52 #include <sys/tty.h>
53 #include <sys/proc.h>
54 #include <sys/user.h>
55 #include <sys/conf.h>
56 #include <sys/file.h>
57 #include <sys/uio.h>
58 #include <sys/kernel.h>
59 #include <sys/syslog.h>
60 #include <sys/device.h>
61 #include <sys/malloc.h>
62 #include <sys/kauth.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66 #include <machine/param.h>
67
68 #include <dev/ic/clmpccreg.h>
69 #include <dev/ic/clmpccvar.h>
70 #include <dev/cons.h>
71
72
73 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH)
74 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive."
75 #endif
76
77
78 static int clmpcc_init(struct clmpcc_softc *sc);
79 static void clmpcc_shutdown(struct clmpcc_chan *);
80 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *);
81 static int clmpcc_param(struct tty *, struct termios *);
82 static void clmpcc_set_params(struct clmpcc_chan *);
83 static void clmpcc_start(struct tty *);
84 static int clmpcc_modem_control(struct clmpcc_chan *, int, int);
85
86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc)
87 #define CLMPCCCHAN(x) (minor(x) & 0x00003)
88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000)
89
90 /*
91 * These should be in a header file somewhere...
92 */
93 #define ISCLR(v, f) (((v) & (f)) == 0)
94
95 extern struct cfdriver clmpcc_cd;
96
97 dev_type_open(clmpccopen);
98 dev_type_close(clmpccclose);
99 dev_type_read(clmpccread);
100 dev_type_write(clmpccwrite);
101 dev_type_ioctl(clmpccioctl);
102 dev_type_stop(clmpccstop);
103 dev_type_tty(clmpcctty);
104 dev_type_poll(clmpccpoll);
105
106 const struct cdevsw clmpcc_cdevsw = {
107 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl,
108 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY
109 };
110
111 /*
112 * Make this an option variable one can patch.
113 */
114 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE;
115
116
117 /*
118 * Things needed when the device is used as a console
119 */
120 static struct clmpcc_softc *cons_sc = NULL;
121 static int cons_chan;
122 static int cons_rate;
123
124 static int clmpcc_common_getc(struct clmpcc_softc *, int);
125 static void clmpcc_common_putc(struct clmpcc_softc *, int, int);
126 int clmpcccngetc(dev_t);
127 void clmpcccnputc(dev_t, int);
128
129
130 /*
131 * Convenience functions, inlined for speed
132 */
133 #define integrate static inline
134 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int);
135 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int);
136 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int);
137 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int);
138 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *,
139 u_int);
140 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int);
141 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int);
142 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *);
143
144 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR)
145 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v)
146 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v)
147 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR)
148 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v)
149
150
151 integrate u_int8_t
152 clmpcc_rdreg(sc, offset)
153 struct clmpcc_softc *sc;
154 u_int offset;
155 {
156 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
157 offset ^= sc->sc_byteswap;
158 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
159 offset ^= CLMPCC_BYTESWAP_HIGH;
160 #endif
161 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
162 }
163
164 integrate void
165 clmpcc_wrreg(sc, offset, val)
166 struct clmpcc_softc *sc;
167 u_int offset;
168 u_int val;
169 {
170 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
171 offset ^= sc->sc_byteswap;
172 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
173 offset ^= CLMPCC_BYTESWAP_HIGH;
174 #endif
175 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
176 }
177
178 integrate u_int8_t
179 clmpcc_rdreg_odd(sc, offset)
180 struct clmpcc_softc *sc;
181 u_int offset;
182 {
183 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
184 offset ^= (sc->sc_byteswap & 2);
185 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
186 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
187 #endif
188 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
189 }
190
191 integrate void
192 clmpcc_wrreg_odd(sc, offset, val)
193 struct clmpcc_softc *sc;
194 u_int offset;
195 u_int val;
196 {
197 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
198 offset ^= (sc->sc_byteswap & 2);
199 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
200 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
201 #endif
202 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
203 }
204
205 integrate void
206 clmpcc_wrtx_multi(sc, buff, count)
207 struct clmpcc_softc *sc;
208 u_int8_t *buff;
209 u_int count;
210 {
211 u_int offset = CLMPCC_REG_TDR;
212
213 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
214 offset ^= (sc->sc_byteswap & 2);
215 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
216 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
217 #endif
218 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count);
219 }
220
221 integrate u_int8_t
222 clmpcc_select_channel(sc, new_chan)
223 struct clmpcc_softc *sc;
224 u_int new_chan;
225 {
226 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR);
227
228 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan);
229
230 return old_chan;
231 }
232
233 integrate void
234 clmpcc_channel_cmd(sc, chan, cmd)
235 struct clmpcc_softc *sc;
236 int chan;
237 int cmd;
238 {
239 int i;
240
241 for (i = 5000; i; i--) {
242 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 )
243 break;
244 delay(1);
245 }
246
247 if ( i == 0 )
248 printf("%s: channel %d command timeout (idle)\n",
249 sc->sc_dev.dv_xname, chan);
250
251 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd);
252 }
253
254 integrate void
255 clmpcc_enable_transmitter(ch)
256 struct clmpcc_chan *ch;
257 {
258 u_int old;
259 int s;
260
261 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
262
263 s = splserial();
264 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
265 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY);
266 SET(ch->ch_tty->t_state, TS_BUSY);
267 splx(s);
268
269 clmpcc_select_channel(ch->ch_sc, old);
270 }
271
272 static int
273 clmpcc_speed(sc, speed, cor, bpr)
274 struct clmpcc_softc *sc;
275 speed_t speed;
276 int *cor, *bpr;
277 {
278 int c, co, br;
279
280 for (co = 0, c = 8; c <= 2048; co++, c *= 4) {
281 br = ((sc->sc_clk / c) / speed) - 1;
282 if ( br < 0x100 ) {
283 *cor = co;
284 *bpr = br;
285 return 0;
286 }
287 }
288
289 return -1;
290 }
291
292 void
293 clmpcc_attach(sc)
294 struct clmpcc_softc *sc;
295 {
296 struct clmpcc_chan *ch;
297 struct tty *tp;
298 int chan;
299
300 if ( cons_sc != NULL &&
301 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh )
302 cons_sc = sc;
303
304 /* Initialise the chip */
305 clmpcc_init(sc);
306
307 printf(": Cirrus Logic CD240%c Serial Controller\n",
308 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1');
309
310 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
311 sc->sc_soft_running = 0;
312 #else
313 sc->sc_softintr_cookie =
314 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc);
315 #ifdef DEBUG
316 if (sc->sc_softintr_cookie == NULL)
317 panic("clmpcc_attach: softintr_establish");
318 #endif
319 #endif
320 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans));
321
322 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
323 ch = &sc->sc_chans[chan];
324
325 ch->ch_sc = sc;
326 ch->ch_car = chan;
327
328 tp = ttymalloc();
329 tp->t_oproc = clmpcc_start;
330 tp->t_param = clmpcc_param;
331
332 ch->ch_tty = tp;
333
334 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT);
335 if ( ch->ch_ibuf == NULL ) {
336 printf("%s(%d): unable to allocate ring buffer\n",
337 sc->sc_dev.dv_xname, chan);
338 return;
339 }
340
341 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]);
342 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
343
344 tty_attach(tp);
345 }
346
347 printf("%s: %d channels available", sc->sc_dev.dv_xname,
348 CLMPCC_NUM_CHANS);
349 if ( cons_sc == sc ) {
350 printf(", console on channel %d.\n", cons_chan);
351 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE);
352 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR);
353 } else
354 printf(".\n");
355 }
356
357 static int
358 clmpcc_init(sc)
359 struct clmpcc_softc *sc;
360 {
361 u_int tcor, tbpr;
362 u_int rcor, rbpr;
363 u_int msvr_rts, msvr_dtr;
364 u_int ccr;
365 int is_console;
366 int i;
367
368 /*
369 * All we're really concerned about here is putting the chip
370 * into a quiescent state so that it won't do anything until
371 * clmpccopen() is called. (Except the console channel.)
372 */
373
374 /*
375 * If the chip is acting as console, set all channels to the supplied
376 * console baud rate. Otherwise, plump for 9600.
377 */
378 if ( cons_sc &&
379 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) {
380 clmpcc_speed(sc, cons_rate, &tcor, &tbpr);
381 clmpcc_speed(sc, cons_rate, &rcor, &rbpr);
382 is_console = 1;
383 } else {
384 clmpcc_speed(sc, 9600, &tcor, &tbpr);
385 clmpcc_speed(sc, 9600, &rcor, &rbpr);
386 is_console = 0;
387 }
388
389 /* Allow any pending output to be sent */
390 delay(10000);
391
392 /* Send the Reset All command to channel 0 (resets all channels!) */
393 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL);
394
395 delay(1000);
396
397 /*
398 * The chip will set it's firmware revision register to a non-zero
399 * value to indicate completion of reset.
400 */
401 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--)
402 delay(1);
403
404 if ( i == 0 ) {
405 /*
406 * Watch out... If this chip is console, the message
407 * probably won't be sent since we just reset it!
408 */
409 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname);
410 return -1;
411 }
412
413 for (i = 0; i < CLMPCC_NUM_CHANS; i++) {
414 clmpcc_select_channel(sc, i);
415
416 /* All interrupts are disabled to begin with */
417 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0);
418
419 /* Make sure the channel interrupts on the correct vectors */
420 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base);
421 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr);
422 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr);
423 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr);
424
425 /* Receive timer prescaler set to 1ms */
426 clmpcc_wrreg(sc, CLMPCC_REG_TPR,
427 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1));
428
429 /* We support Async mode only */
430 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC);
431
432 /* Set the required baud rate */
433 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor));
434 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr);
435 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor));
436 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr);
437
438 /* Always default to 8N1 (XXX what about console?) */
439 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS |
440 CLMPCC_COR1_NO_PARITY |
441 CLMPCC_COR1_IGNORE_PAR);
442
443 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0);
444
445 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1);
446
447 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd |
448 CLMPCC_COR4_CDzd |
449 CLMPCC_COR4_CTSzd);
450
451 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod |
452 CLMPCC_COR5_CDod |
453 CLMPCC_COR5_CTSod |
454 CLMPCC_COR5_FLOW_NORM);
455
456 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0);
457 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0);
458
459 /* Set the receive FIFO timeout */
460 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT);
461 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0);
462
463 /* At this point, we set up the console differently */
464 if ( is_console && i == cons_chan ) {
465 msvr_rts = CLMPCC_MSVR_RTS;
466 msvr_dtr = CLMPCC_MSVR_DTR;
467 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN;
468 } else {
469 msvr_rts = 0;
470 msvr_dtr = 0;
471 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS;
472 }
473
474 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts);
475 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr);
476 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr);
477 delay(100);
478 }
479
480 return 0;
481 }
482
483 static void
484 clmpcc_shutdown(ch)
485 struct clmpcc_chan *ch;
486 {
487 int oldch;
488
489 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
490
491 /* Turn off interrupts. */
492 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0);
493
494 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
495 /* Disable the transmitter and receiver */
496 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS |
497 CLMPCC_CCR_T0_TX_DIS);
498
499 /* Drop RTS and DTR */
500 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
501 }
502
503 clmpcc_select_channel(ch->ch_sc, oldch);
504 }
505
506 int
507 clmpccopen(dev, flag, mode, l)
508 dev_t dev;
509 int flag, mode;
510 struct lwp *l;
511 {
512 struct clmpcc_softc *sc;
513 struct clmpcc_chan *ch;
514 struct tty *tp;
515 int oldch;
516 int error;
517
518 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
519 if (sc == NULL)
520 return (ENXIO);
521
522 ch = &sc->sc_chans[CLMPCCCHAN(dev)];
523
524 tp = ch->ch_tty;
525
526 if ( ISSET(tp->t_state, TS_ISOPEN) &&
527 ISSET(tp->t_state, TS_XCLUDE) &&
528 kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER,
529 &l->l_acflag) != 0 )
530 return EBUSY;
531
532 /*
533 * Do the following iff this is a first open.
534 */
535 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
536
537 ttychars(tp);
538
539 tp->t_dev = dev;
540 tp->t_iflag = TTYDEF_IFLAG;
541 tp->t_oflag = TTYDEF_OFLAG;
542 tp->t_lflag = TTYDEF_LFLAG;
543 tp->t_cflag = TTYDEF_CFLAG;
544 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED;
545
546 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) )
547 SET(tp->t_cflag, CLOCAL);
548 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) )
549 SET(tp->t_cflag, CRTSCTS);
550 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) )
551 SET(tp->t_cflag, MDMBUF);
552
553 /*
554 * Override some settings if the channel is being
555 * used as the console.
556 */
557 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
558 tp->t_ospeed = tp->t_ispeed = cons_rate;
559 SET(tp->t_cflag, CLOCAL);
560 CLR(tp->t_cflag, CRTSCTS);
561 CLR(tp->t_cflag, HUPCL);
562 }
563
564 ch->ch_control = 0;
565
566 clmpcc_param(tp, &tp->t_termios);
567 ttsetwater(tp);
568
569 /* Clear the input ring */
570 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
571
572 /* Select the channel */
573 oldch = clmpcc_select_channel(sc, ch->ch_car);
574
575 /* Reset it */
576 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR |
577 CLMPCC_CCR_T0_RX_EN |
578 CLMPCC_CCR_T0_TX_EN);
579
580 /* Enable receiver and modem change interrupts. */
581 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM |
582 CLMPCC_IER_RET |
583 CLMPCC_IER_RX_FIFO);
584
585 /* Raise RTS and DTR */
586 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
587
588 clmpcc_select_channel(sc, oldch);
589 }
590
591 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK));
592 if (error)
593 goto bad;
594
595 error = (*tp->t_linesw->l_open)(dev, tp);
596 if (error)
597 goto bad;
598
599 return 0;
600
601 bad:
602 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
603 /*
604 * We failed to open the device, and nobody else had it opened.
605 * Clean up the state as appropriate.
606 */
607 clmpcc_shutdown(ch);
608 }
609
610 return error;
611 }
612
613 int
614 clmpccclose(dev, flag, mode, l)
615 dev_t dev;
616 int flag, mode;
617 struct lwp *l;
618 {
619 struct clmpcc_softc *sc =
620 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
621 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
622 struct tty *tp = ch->ch_tty;
623 int s;
624
625 if ( ISCLR(tp->t_state, TS_ISOPEN) )
626 return 0;
627
628 (*tp->t_linesw->l_close)(tp, flag);
629
630 s = spltty();
631
632 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
633 /*
634 * Although we got a last close, the device may still be in
635 * use; e.g. if this was the dialout node, and there are still
636 * processes waiting for carrier on the non-dialout node.
637 */
638 clmpcc_shutdown(ch);
639 }
640
641 ttyclose(tp);
642
643 splx(s);
644
645 return 0;
646 }
647
648 int
649 clmpccread(dev, uio, flag)
650 dev_t dev;
651 struct uio *uio;
652 int flag;
653 {
654 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
655 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
656
657 return ((*tp->t_linesw->l_read)(tp, uio, flag));
658 }
659
660 int
661 clmpccwrite(dev, uio, flag)
662 dev_t dev;
663 struct uio *uio;
664 int flag;
665 {
666 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
667 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
668
669 return ((*tp->t_linesw->l_write)(tp, uio, flag));
670 }
671
672 int
673 clmpccpoll(dev, events, l)
674 dev_t dev;
675 int events;
676 struct lwp *l;
677 {
678 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
679 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
680
681 return ((*tp->t_linesw->l_poll)(tp, events, l));
682 }
683
684 struct tty *
685 clmpcctty(dev)
686 dev_t dev;
687 {
688 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
689
690 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty);
691 }
692
693 int
694 clmpccioctl(dev, cmd, data, flag, l)
695 dev_t dev;
696 u_long cmd;
697 caddr_t data;
698 int flag;
699 struct lwp *l;
700 {
701 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
702 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
703 struct tty *tp = ch->ch_tty;
704 int error;
705
706 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
707 if (error != EPASSTHROUGH)
708 return error;
709
710 error = ttioctl(tp, cmd, data, flag, l);
711 if (error != EPASSTHROUGH)
712 return error;
713
714 error = 0;
715
716 switch (cmd) {
717 case TIOCSBRK:
718 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK);
719 clmpcc_enable_transmitter(ch);
720 break;
721
722 case TIOCCBRK:
723 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK);
724 clmpcc_enable_transmitter(ch);
725 break;
726
727 case TIOCSDTR:
728 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS);
729 break;
730
731 case TIOCCDTR:
732 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC);
733 break;
734
735 case TIOCMSET:
736 clmpcc_modem_control(ch, *((int *)data), DMSET);
737 break;
738
739 case TIOCMBIS:
740 clmpcc_modem_control(ch, *((int *)data), DMBIS);
741 break;
742
743 case TIOCMBIC:
744 clmpcc_modem_control(ch, *((int *)data), DMBIC);
745 break;
746
747 case TIOCMGET:
748 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET);
749 break;
750
751 case TIOCGFLAGS:
752 *((int *)data) = ch->ch_openflags;
753 break;
754
755 case TIOCSFLAGS:
756 error = kauth_authorize_generic(l->l_cred,
757 KAUTH_GENERIC_ISSUSER, &l->l_acflag);
758 if ( error )
759 break;
760 ch->ch_openflags = *((int *)data) &
761 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
762 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
763 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) )
764 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR);
765 break;
766
767 default:
768 error = EPASSTHROUGH;
769 break;
770 }
771
772 return error;
773 }
774
775 int
776 clmpcc_modem_control(ch, bits, howto)
777 struct clmpcc_chan *ch;
778 int bits;
779 int howto;
780 {
781 struct clmpcc_softc *sc = ch->ch_sc;
782 struct tty *tp = ch->ch_tty;
783 int oldch;
784 int msvr;
785 int rbits = 0;
786
787 oldch = clmpcc_select_channel(sc, ch->ch_car);
788
789 switch ( howto ) {
790 case DMGET:
791 msvr = clmpcc_rd_msvr(sc);
792
793 if ( sc->sc_swaprtsdtr ) {
794 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0;
795 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0;
796 } else {
797 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0;
798 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0;
799 }
800
801 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0;
802 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0;
803 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0;
804 break;
805
806 case DMSET:
807 if ( sc->sc_swaprtsdtr ) {
808 if ( ISCLR(tp->t_cflag, CRTSCTS) )
809 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
810 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0);
811 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
812 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0);
813 } else {
814 if ( ISCLR(tp->t_cflag, CRTSCTS) )
815 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
816 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0);
817 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
818 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0);
819 }
820 break;
821
822 case DMBIS:
823 if ( sc->sc_swaprtsdtr ) {
824 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
825 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
826 if ( ISSET(bits, TIOCM_DTR) )
827 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
828 } else {
829 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
830 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
831 if ( ISSET(bits, TIOCM_DTR) )
832 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
833 }
834 break;
835
836 case DMBIC:
837 if ( sc->sc_swaprtsdtr ) {
838 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
839 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
840 if ( ISCLR(bits, TIOCM_DTR) )
841 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
842 } else {
843 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
844 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
845 if ( ISCLR(bits, TIOCM_DTR) )
846 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
847 }
848 break;
849 }
850
851 clmpcc_select_channel(sc, oldch);
852
853 return rbits;
854 }
855
856 static int
857 clmpcc_param(tp, t)
858 struct tty *tp;
859 struct termios *t;
860 {
861 struct clmpcc_softc *sc =
862 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
863 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
864 u_char cor;
865 u_char oldch;
866 int oclk, obpr;
867 int iclk, ibpr;
868 int s;
869
870 /* Check requested parameters. */
871 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 )
872 return EINVAL;
873
874 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 )
875 return EINVAL;
876
877 /*
878 * For the console, always force CLOCAL and !HUPCL, so that the port
879 * is always active.
880 */
881 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) ||
882 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
883 SET(t->c_cflag, CLOCAL);
884 CLR(t->c_cflag, HUPCL);
885 }
886
887 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
888
889 /* If ospeed it zero, hangup the line */
890 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS);
891
892 if ( t->c_ospeed ) {
893 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk);
894 ch->ch_tbpr = obpr;
895 } else {
896 ch->ch_tcor = 0;
897 ch->ch_tbpr = 0;
898 }
899
900 if ( t->c_ispeed ) {
901 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk);
902 ch->ch_rbpr = ibpr;
903 } else {
904 ch->ch_rcor = 0;
905 ch->ch_rbpr = 0;
906 }
907
908 /* Work out value to use for COR1 */
909 cor = 0;
910 if ( ISSET(t->c_cflag, PARENB) ) {
911 cor |= CLMPCC_COR1_NORM_PARITY;
912 if ( ISSET(t->c_cflag, PARODD) )
913 cor |= CLMPCC_COR1_ODD_PARITY;
914 }
915
916 if ( ISCLR(t->c_cflag, INPCK) )
917 cor |= CLMPCC_COR1_IGNORE_PAR;
918
919 switch ( t->c_cflag & CSIZE ) {
920 case CS5:
921 cor |= CLMPCC_COR1_CHAR_5BITS;
922 break;
923
924 case CS6:
925 cor |= CLMPCC_COR1_CHAR_6BITS;
926 break;
927
928 case CS7:
929 cor |= CLMPCC_COR1_CHAR_7BITS;
930 break;
931
932 case CS8:
933 cor |= CLMPCC_COR1_CHAR_8BITS;
934 break;
935 }
936
937 ch->ch_cor1 = cor;
938
939 /*
940 * The only interesting bit in COR2 is 'CTS Automatic Enable'
941 * when hardware flow control is in effect.
942 */
943 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0;
944
945 /* COR3 needs to be set to the number of stop bits... */
946 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 :
947 CLMPCC_COR3_STOP_1;
948
949 /*
950 * COR4 contains the FIFO threshold setting.
951 * We adjust the threshold depending on the input speed...
952 */
953 if ( t->c_ispeed <= 1200 )
954 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW;
955 else if ( t->c_ispeed <= 19200 )
956 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED;
957 else
958 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH;
959
960 /*
961 * If chip is used with CTS and DTR swapped, we can enable
962 * automatic hardware flow control.
963 */
964 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) )
965 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM;
966 else
967 ch->ch_cor5 = 0;
968
969 s = splserial();
970 oldch = clmpcc_select_channel(sc, ch->ch_car);
971
972 /*
973 * COR2 needs to be set immediately otherwise we might never get
974 * a Tx EMPTY interrupt to change the other parameters.
975 */
976 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 )
977 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
978
979 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) )
980 clmpcc_set_params(ch);
981 else
982 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
983
984 clmpcc_select_channel(sc, oldch);
985
986 splx(s);
987
988 return 0;
989 }
990
991 static void
992 clmpcc_set_params(ch)
993 struct clmpcc_chan *ch;
994 {
995 struct clmpcc_softc *sc = ch->ch_sc;
996 u_char r1;
997 u_char r2;
998
999 if ( ch->ch_tcor || ch->ch_tbpr ) {
1000 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR);
1001 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR);
1002 /* Only write Tx rate if it really has changed */
1003 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) {
1004 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor);
1005 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr);
1006 }
1007 }
1008
1009 if ( ch->ch_rcor || ch->ch_rbpr ) {
1010 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR);
1011 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR);
1012 /* Only write Rx rate if it really has changed */
1013 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) {
1014 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor);
1015 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr);
1016 }
1017 }
1018
1019 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) {
1020 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1);
1021 /* Any change to COR1 requires an INIT command */
1022 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1023 }
1024
1025 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 )
1026 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3);
1027
1028 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1029 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) {
1030 /*
1031 * Note: If the FIFO has changed, we always set it to
1032 * zero here and disable the Receive Timeout interrupt.
1033 * It's up to the Rx Interrupt handler to pick the
1034 * appropriate moment to write the new FIFO length.
1035 */
1036 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK);
1037 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1038 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET);
1039 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1040 }
1041
1042 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5);
1043 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) {
1044 r1 &= ~CLMPCC_COR5_FLOW_MASK;
1045 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5);
1046 }
1047 }
1048
1049 static void
1050 clmpcc_start(tp)
1051 struct tty *tp;
1052 {
1053 struct clmpcc_softc *sc =
1054 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
1055 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1056 u_int oldch;
1057 int s;
1058
1059 s = spltty();
1060
1061 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1062 if ( tp->t_outq.c_cc <= tp->t_lowat ) {
1063 if ( ISSET(tp->t_state, TS_ASLEEP) ) {
1064 CLR(tp->t_state, TS_ASLEEP);
1065 wakeup(&tp->t_outq);
1066 }
1067 selwakeup(&tp->t_wsel);
1068 }
1069
1070 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1071 CLMPCC_FLG_END_BREAK) ||
1072 tp->t_outq.c_cc > 0 ) {
1073
1074 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1075 CLMPCC_FLG_END_BREAK) ) {
1076 ch->ch_obuf_addr = tp->t_outq.c_cf;
1077 ch->ch_obuf_size = ndqb(&tp->t_outq, 0);
1078 }
1079
1080 /* Enable TX empty interrupts */
1081 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
1082 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
1083 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) |
1084 CLMPCC_IER_TX_EMPTY);
1085 clmpcc_select_channel(ch->ch_sc, oldch);
1086 SET(tp->t_state, TS_BUSY);
1087 }
1088 }
1089
1090 splx(s);
1091 }
1092
1093 /*
1094 * Stop output on a line.
1095 */
1096 void
1097 clmpccstop(tp, flag)
1098 struct tty *tp;
1099 int flag;
1100 {
1101 struct clmpcc_softc *sc =
1102 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
1103 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1104 int s;
1105
1106 s = splserial();
1107
1108 if ( ISSET(tp->t_state, TS_BUSY) ) {
1109 if ( ISCLR(tp->t_state, TS_TTSTOP) )
1110 SET(tp->t_state, TS_FLUSH);
1111 ch->ch_obuf_size = 0;
1112 }
1113 splx(s);
1114 }
1115
1116 /*
1117 * RX interrupt routine
1118 */
1119 int
1120 clmpcc_rxintr(arg)
1121 void *arg;
1122 {
1123 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1124 struct clmpcc_chan *ch;
1125 u_int8_t *put, *end, rxd;
1126 u_char errstat;
1127 u_char fc, tc;
1128 u_char risr;
1129 u_char rir;
1130 #ifdef DDB
1131 int saw_break = 0;
1132 #endif
1133
1134 /* Receive interrupt active? */
1135 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1136
1137 /*
1138 * If we're using auto-vectored interrupts, we have to
1139 * verify if the chip is generating the interrupt.
1140 */
1141 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 )
1142 return 0;
1143
1144 /* Get pointer to interrupting channel's data structure */
1145 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK];
1146
1147 /* Get the interrupt status register */
1148 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl);
1149 if ( risr & CLMPCC_RISR_TIMEOUT ) {
1150 u_char reg;
1151 /*
1152 * Set the FIFO threshold to zero, and disable
1153 * further receive timeout interrupts.
1154 */
1155 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1156 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK);
1157 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1158 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET);
1159 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1160 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1161 return 1;
1162 }
1163
1164 /* How many bytes are waiting in the FIFO? */
1165 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK;
1166
1167 #ifdef DDB
1168 /*
1169 * Allow BREAK on the console to drop to the debugger.
1170 */
1171 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) &&
1172 risr & CLMPCC_RISR_BREAK ) {
1173 saw_break = 1;
1174 }
1175 #endif
1176
1177 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) {
1178 /* Just get rid of the data */
1179 while ( fc-- )
1180 (void) clmpcc_rd_rxdata(sc);
1181 goto rx_done;
1182 }
1183
1184 put = ch->ch_ibuf_wr;
1185 end = ch->ch_ibuf_end;
1186
1187 /*
1188 * Note: The chip is completely hosed WRT these error
1189 * conditions; there seems to be no way to associate
1190 * the error with the correct character in the FIFO.
1191 * We compromise by tagging the first character we read
1192 * with the error. Not perfect, but there's no other way.
1193 */
1194 errstat = 0;
1195 if ( risr & CLMPCC_RISR_PARITY )
1196 errstat |= TTY_PE;
1197 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) )
1198 errstat |= TTY_FE;
1199
1200 /*
1201 * As long as there are characters in the FIFO, and we
1202 * have space for them...
1203 */
1204 while ( fc > 0 ) {
1205
1206 *put++ = rxd = clmpcc_rd_rxdata(sc);
1207 *put++ = errstat;
1208
1209 if ( put >= end )
1210 put = ch->ch_ibuf;
1211
1212 if ( put == ch->ch_ibuf_rd ) {
1213 put -= 2;
1214 if ( put < ch->ch_ibuf )
1215 put = end - 2;
1216 }
1217
1218 errstat = 0;
1219 fc--;
1220 }
1221
1222 ch->ch_ibuf_wr = put;
1223
1224 #if 0
1225 if ( sc->sc_swaprtsdtr == 0 &&
1226 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) {
1227 /*
1228 * If RTS/DTR are not physically swapped, we have to
1229 * do hardware flow control manually
1230 */
1231 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0);
1232 }
1233 #endif
1234
1235 rx_done:
1236 if ( fc != tc ) {
1237 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) {
1238 u_char reg;
1239 /*
1240 * Set the FIFO threshold to the preset value,
1241 * and enable receive timeout interrupts.
1242 */
1243 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1244 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4;
1245 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg);
1246 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1247 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET);
1248 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1249 }
1250
1251 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1252 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1253 if ( sc->sc_soft_running == 0 ) {
1254 sc->sc_soft_running = 1;
1255 (sc->sc_softhook)(sc);
1256 }
1257 #else
1258 softintr_schedule(sc->sc_softintr_cookie);
1259 #endif
1260 } else
1261 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1262
1263 #ifdef DDB
1264 /*
1265 * Only =after= we write REOIR is it safe to drop to the debugger.
1266 */
1267 if ( saw_break )
1268 Debugger();
1269 #endif
1270
1271 return 1;
1272 }
1273
1274 /*
1275 * Tx interrupt routine
1276 */
1277 int
1278 clmpcc_txintr(arg)
1279 void *arg;
1280 {
1281 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1282 struct clmpcc_chan *ch;
1283 struct tty *tp;
1284 u_char ftc, oftc;
1285 u_char tir, teoir;
1286 int etcmode = 0;
1287
1288 /* Tx interrupt active? */
1289 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR);
1290
1291 /*
1292 * If we're using auto-vectored interrupts, we have to
1293 * verify if the chip is generating the interrupt.
1294 */
1295 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 )
1296 return 0;
1297
1298 /* Get pointer to interrupting channel's data structure */
1299 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK];
1300 tp = ch->ch_tty;
1301
1302 /* Dummy read of the interrupt status register */
1303 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR);
1304
1305 /* Make sure embedded transmit commands are disabled */
1306 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
1307
1308 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC);
1309
1310 /* Handle a delayed parameter change */
1311 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) {
1312 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
1313 clmpcc_set_params(ch);
1314 }
1315
1316 if ( ch->ch_obuf_size > 0 ) {
1317 u_int n = min(ch->ch_obuf_size, ftc);
1318
1319 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n);
1320
1321 ftc -= n;
1322 ch->ch_obuf_size -= n;
1323 ch->ch_obuf_addr += n;
1324
1325 } else {
1326 /*
1327 * Check if we should start/stop a break
1328 */
1329 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) {
1330 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK);
1331 /* Enable embedded transmit commands */
1332 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1333 ch->ch_cor2 | CLMPCC_COR2_ETC);
1334 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1335 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK);
1336 ftc -= 2;
1337 etcmode = 1;
1338 }
1339
1340 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) {
1341 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK);
1342 /* Enable embedded transmit commands */
1343 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1344 ch->ch_cor2 | CLMPCC_COR2_ETC);
1345 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1346 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK);
1347 ftc -= 2;
1348 etcmode = 1;
1349 }
1350 }
1351
1352 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1353
1354 if ( ftc != oftc ) {
1355 /*
1356 * Enable/disable the Tx FIFO threshold interrupt
1357 * according to how much data is in the FIFO.
1358 * However, always disable the FIFO threshold if
1359 * we've left the channel in 'Embedded Transmit
1360 * Command' mode.
1361 */
1362 if ( etcmode || ftc >= ch->ch_cor4 )
1363 tir &= ~CLMPCC_IER_TX_FIFO;
1364 else
1365 tir |= CLMPCC_IER_TX_FIFO;
1366 teoir = 0;
1367 } else {
1368 /*
1369 * No data was sent.
1370 * Disable transmit interrupt.
1371 */
1372 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO);
1373 teoir = CLMPCC_TEOIR_NO_TRANS;
1374
1375 /*
1376 * Request Tx processing in the soft interrupt handler
1377 */
1378 ch->ch_tx_done = 1;
1379 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1380 if ( sc->sc_soft_running == 0 ) {
1381 sc->sc_soft_running = 1;
1382 (sc->sc_softhook)(sc);
1383 }
1384 #else
1385 softintr_schedule(sc->sc_softintr_cookie);
1386 #endif
1387 }
1388
1389 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir);
1390 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir);
1391
1392 return 1;
1393 }
1394
1395 /*
1396 * Modem change interrupt routine
1397 */
1398 int
1399 clmpcc_mdintr(arg)
1400 void *arg;
1401 {
1402 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1403 u_char mir;
1404
1405 /* Modem status interrupt active? */
1406 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR);
1407
1408 /*
1409 * If we're using auto-vectored interrupts, we have to
1410 * verify if the chip is generating the interrupt.
1411 */
1412 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 )
1413 return 0;
1414
1415 /* Dummy read of the interrupt status register */
1416 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR);
1417
1418 /* Retrieve current status of modem lines. */
1419 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |=
1420 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1421
1422 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0);
1423
1424 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1425 if ( sc->sc_soft_running == 0 ) {
1426 sc->sc_soft_running = 1;
1427 (sc->sc_softhook)(sc);
1428 }
1429 #else
1430 softintr_schedule(sc->sc_softintr_cookie);
1431 #endif
1432
1433 return 1;
1434 }
1435
1436 void
1437 clmpcc_softintr(arg)
1438 void *arg;
1439 {
1440 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1441 struct clmpcc_chan *ch;
1442 struct tty *tp;
1443 int (*rint)(int, struct tty *);
1444 u_char *get;
1445 u_char reg;
1446 u_int c;
1447 int chan;
1448
1449 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1450 sc->sc_soft_running = 0;
1451 #endif
1452
1453 /* Handle Modem state changes too... */
1454
1455 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
1456 ch = &sc->sc_chans[chan];
1457 tp = ch->ch_tty;
1458
1459 get = ch->ch_ibuf_rd;
1460 rint = tp->t_linesw->l_rint;
1461
1462 /* Squirt buffered incoming data into the tty layer */
1463 while ( get != ch->ch_ibuf_wr ) {
1464 c = get[0];
1465 c |= ((u_int)get[1]) << 8;
1466 if ( (rint)(c, tp) == -1 ) {
1467 ch->ch_ibuf_rd = ch->ch_ibuf_wr;
1468 break;
1469 }
1470
1471 get += 2;
1472 if ( get == ch->ch_ibuf_end )
1473 get = ch->ch_ibuf;
1474
1475 ch->ch_ibuf_rd = get;
1476 }
1477
1478 /*
1479 * Is the transmitter idle and in need of attention?
1480 */
1481 if ( ch->ch_tx_done ) {
1482 ch->ch_tx_done = 0;
1483
1484 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) {
1485 clmpcc_channel_cmd(sc, ch->ch_car,
1486 CLMPCC_CCR_T0_INIT |
1487 CLMPCC_CCR_T0_RX_EN |
1488 CLMPCC_CCR_T0_TX_EN);
1489 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1490
1491 /*
1492 * Allow time for the channel to initialise.
1493 * (Empirically derived duration; there must
1494 * be another way to determine the command
1495 * has completed without busy-waiting...)
1496 */
1497 delay(800);
1498
1499 /*
1500 * Update the tty layer's idea of the carrier
1501 * bit, in case we changed CLOCAL or MDMBUF.
1502 * We don't hang up here; we only do that by
1503 * explicit request.
1504 */
1505 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1506 (*tp->t_linesw->l_modem)(tp, reg != 0);
1507 }
1508
1509 CLR(tp->t_state, TS_BUSY);
1510 if ( ISSET(tp->t_state, TS_FLUSH) )
1511 CLR(tp->t_state, TS_FLUSH);
1512 else
1513 ndflush(&tp->t_outq,
1514 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf));
1515
1516 (*tp->t_linesw->l_start)(tp);
1517 }
1518 }
1519 }
1520
1521
1522 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1523 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1524 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1525 /*
1526 * Following are all routines needed for a cd240x channel to act as console
1527 */
1528 int
1529 clmpcc_cnattach(sc, chan, rate)
1530 struct clmpcc_softc *sc;
1531 int chan;
1532 int rate;
1533 {
1534 cons_sc = sc;
1535 cons_chan = chan;
1536 cons_rate = rate;
1537
1538 return (clmpcc_init(sc));
1539 }
1540
1541 /*
1542 * The following functions are polled getc and putc routines, for console use.
1543 */
1544 static int
1545 clmpcc_common_getc(sc, chan)
1546 struct clmpcc_softc *sc;
1547 int chan;
1548 {
1549 u_char old_chan;
1550 u_char old_ier;
1551 u_char ch, rir, risr;
1552 int s;
1553
1554 s = splhigh();
1555
1556 /* Save the currently active channel */
1557 old_chan = clmpcc_select_channel(sc, chan);
1558
1559 /*
1560 * We have to put the channel into RX interrupt mode before
1561 * trying to read the Rx data register. So save the previous
1562 * interrupt mode.
1563 */
1564 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1565 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO);
1566
1567 /* Loop until we get a character */
1568 for (;;) {
1569 /*
1570 * The REN bit will be set in the Receive Interrupt Register
1571 * when the CD240x has a character to process. Remember,
1572 * the RACT bit won't be set until we generate an interrupt
1573 * acknowledge cycle via the MD front-end.
1574 */
1575 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1576 if ( (rir & CLMPCC_RIR_REN) == 0 )
1577 continue;
1578
1579 /* Acknowledge the request */
1580 if ( sc->sc_iackhook )
1581 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX);
1582
1583 /*
1584 * Determine if the interrupt is for the required channel
1585 * and if valid data is available.
1586 */
1587 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1588 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR);
1589 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan ||
1590 risr != 0 ) {
1591 /* Rx error, or BREAK */
1592 clmpcc_wrreg(sc, CLMPCC_REG_REOIR,
1593 CLMPCC_REOIR_NO_TRANS);
1594 } else {
1595 /* Dummy read of the FIFO count register */
1596 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC);
1597
1598 /* Fetch the received character */
1599 ch = clmpcc_rd_rxdata(sc);
1600
1601 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1602 break;
1603 }
1604 }
1605
1606 /* Restore the original IER and CAR register contents */
1607 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier);
1608 clmpcc_select_channel(sc, old_chan);
1609
1610 splx(s);
1611 return ch;
1612 }
1613
1614
1615 static void
1616 clmpcc_common_putc(sc, chan, c)
1617 struct clmpcc_softc *sc;
1618 int chan;
1619 int c;
1620 {
1621 u_char old_chan;
1622 int s = splhigh();
1623
1624 /* Save the currently active channel */
1625 old_chan = clmpcc_select_channel(sc, chan);
1626
1627 /*
1628 * Since we can only access the Tx Data register from within
1629 * the interrupt handler, the easiest way to get console data
1630 * onto the wire is using one of the Special Transmit Character
1631 * registers.
1632 */
1633 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c);
1634 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) |
1635 CLMPCC_STCR_SND_SPC);
1636
1637 /* Wait until the "Send Special Character" command is accepted */
1638 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 )
1639 ;
1640
1641 /* Restore the previous channel selected */
1642 clmpcc_select_channel(sc, old_chan);
1643
1644 splx(s);
1645 }
1646
1647 int
1648 clmpcccngetc(dev)
1649 dev_t dev;
1650 {
1651 return clmpcc_common_getc(cons_sc, cons_chan);
1652 }
1653
1654 /*
1655 * Console kernel output character routine.
1656 */
1657 void
1658 clmpcccnputc(dev, c)
1659 dev_t dev;
1660 int c;
1661 {
1662 if ( c == '\n' )
1663 clmpcc_common_putc(cons_sc, cons_chan, '\r');
1664
1665 clmpcc_common_putc(cons_sc, cons_chan, c);
1666 }
1667