1 1.13 chs /* $NetBSD: clmpccvar.h,v 1.13 2012/10/27 17:18:20 chs Exp $ */ 2 1.1 scw 3 1.1 scw /*- 4 1.1 scw * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.1 scw * All rights reserved. 6 1.1 scw * 7 1.1 scw * This code is derived from software contributed to The NetBSD Foundation 8 1.1 scw * by Steve C. Woodford. 9 1.1 scw * 10 1.1 scw * Redistribution and use in source and binary forms, with or without 11 1.1 scw * modification, are permitted provided that the following conditions 12 1.1 scw * are met: 13 1.1 scw * 1. Redistributions of source code must retain the above copyright 14 1.1 scw * notice, this list of conditions and the following disclaimer. 15 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 scw * notice, this list of conditions and the following disclaimer in the 17 1.1 scw * documentation and/or other materials provided with the distribution. 18 1.1 scw * 19 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 scw * POSSIBILITY OF SUCH DAMAGE. 30 1.1 scw */ 31 1.1 scw 32 1.1 scw #ifndef __clmpccvar_h 33 1.1 scw #define __clmpccvar_h 34 1.1 scw 35 1.1 scw 36 1.1 scw /* Buffer size for character buffer */ 37 1.1 scw #define CLMPCC_RING_SIZE 512 38 1.1 scw 39 1.1 scw /* How many channels per chip */ 40 1.1 scw #define CLMPCC_NUM_CHANS 4 41 1.1 scw 42 1.1 scw /* Reasons for calling the MD code's iack hook function */ 43 1.1 scw #define CLMPCC_IACK_MODEM 0 44 1.1 scw #define CLMPCC_IACK_RX 1 45 1.1 scw #define CLMPCC_IACK_TX 2 46 1.1 scw 47 1.1 scw 48 1.1 scw struct clmpcc_softc; 49 1.1 scw 50 1.1 scw /* 51 1.1 scw * Each channel is represented by one of the following structures 52 1.1 scw */ 53 1.1 scw struct clmpcc_chan { 54 1.1 scw struct tty *ch_tty; /* This channel's tty structure */ 55 1.1 scw struct clmpcc_softc *ch_sc; /* Pointer to chip's softc structure */ 56 1.2 scw u_char ch_car; /* Channel number (CD2400_REG_CAR) */ 57 1.8 wiz u_char ch_openflags; /* Persistent TIOC flags */ 58 1.3 scw volatile u_short ch_flags; /* Various channel-specific flags */ 59 1.2 scw #define CLMPCC_FLG_IS_CONSOLE 0x0001 /* Channel is system console */ 60 1.3 scw #define CLMPCC_FLG_START_BREAK 0x0002 61 1.3 scw #define CLMPCC_FLG_END_BREAK 0x0004 62 1.3 scw #define CLMPCC_FLG_FIFO_CLEAR 0x0008 63 1.3 scw #define CLMPCC_FLG_UPDATE_PARMS 0x0010 64 1.3 scw #define CLMPCC_FLG_NEED_INIT 0x0020 65 1.3 scw 66 1.3 scw u_char ch_tx_done; 67 1.1 scw 68 1.1 scw u_char ch_control; 69 1.2 scw 70 1.2 scw /* New port parameters wait here until written by the Tx ISR */ 71 1.2 scw u_char ch_tcor; 72 1.2 scw u_char ch_tbpr; 73 1.2 scw u_char ch_rcor; 74 1.2 scw u_char ch_rbpr; 75 1.2 scw u_char ch_cor1; 76 1.2 scw u_char ch_cor2; 77 1.2 scw u_char ch_cor3; 78 1.2 scw u_char ch_cor4; /* Current Rx Fifo threshold */ 79 1.2 scw u_char ch_cor5; 80 1.1 scw 81 1.1 scw u_int8_t *ch_ibuf; /* Start of input ring buffer */ 82 1.1 scw u_int8_t *ch_ibuf_end; /* End of input ring buffer */ 83 1.1 scw u_int8_t *ch_ibuf_rd; /* Input buffer tail (reader) */ 84 1.1 scw u_int8_t *ch_ibuf_wr; /* Input buffer head (writer) */ 85 1.3 scw 86 1.3 scw u_int8_t *ch_obuf_addr; /* Output buffer address */ 87 1.3 scw u_int ch_obuf_size; /* Output buffer size (in bytes) */ 88 1.1 scw }; 89 1.1 scw 90 1.1 scw 91 1.1 scw struct clmpcc_softc { 92 1.13 chs device_t sc_dev; 93 1.1 scw 94 1.1 scw /* 95 1.1 scw * The bus/MD-specific attachment code must initialise the 96 1.3 scw * following fields before calling 'clmpcc_attach_subr()'. 97 1.1 scw */ 98 1.1 scw bus_space_tag_t sc_iot; /* Tag for parent bus */ 99 1.1 scw bus_space_handle_t sc_ioh; /* Handle for chip's regs */ 100 1.1 scw void *sc_data; /* MD-specific data */ 101 1.1 scw int sc_clk; /* Clock-rate, in Hz */ 102 1.7 scw struct evcnt *sc_evcnt; /* Parent Event Counter (or NULL) */ 103 1.1 scw u_char sc_vector_base; /* Vector base reg, or 0 for auto */ 104 1.8 wiz u_char sc_rpilr; /* Receive Priority Interrupt Level */ 105 1.8 wiz u_char sc_tpilr; /* Transmit Priority Interrupt Level */ 106 1.8 wiz u_char sc_mpilr; /* Modem Priority Interrupt Level */ 107 1.1 scw int sc_swaprtsdtr; /* Non-zero if RTS and DTR swapped */ 108 1.1 scw u_int sc_byteswap; /* One of the following ... */ 109 1.1 scw #define CLMPCC_BYTESWAP_LOW 0x00 /* *byteswap pin is low */ 110 1.1 scw #define CLMPCC_BYTESWAP_HIGH 0x03 /* *byteswap pin is high */ 111 1.1 scw 112 1.5 scw void *sc_softintr_cookie; 113 1.1 scw 114 1.1 scw /* Called when an interrupt has to be acknowledged in polled mode. */ 115 1.9 perry void (*sc_iackhook)(struct clmpcc_softc *, int); 116 1.1 scw 117 1.1 scw /* 118 1.1 scw * No user-serviceable parts below 119 1.1 scw */ 120 1.1 scw struct clmpcc_chan sc_chans[CLMPCC_NUM_CHANS]; 121 1.1 scw }; 122 1.1 scw 123 1.9 perry extern void clmpcc_attach(struct clmpcc_softc *); 124 1.9 perry extern int clmpcc_cnattach(struct clmpcc_softc *, int, int); 125 1.9 perry extern int clmpcc_rxintr(void *); 126 1.9 perry extern int clmpcc_txintr(void *); 127 1.9 perry extern int clmpcc_mdintr(void *); 128 1.9 perry extern void clmpcc_softintr(void *); 129 1.1 scw 130 1.1 scw #endif /* __clmpccvar_h */ 131