com.c revision 1.234.2.4
1 /* $NetBSD: com.c,v 1.234.2.4 2007/09/03 14:34:26 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.234.2.4 2007/09/03 14:34:26 yamt Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 195 integrate void com_rxsoft(struct com_softc *, struct tty *); 196 integrate void com_txsoft(struct com_softc *, struct tty *); 197 integrate void com_stsoft(struct com_softc *, struct tty *); 198 integrate void com_schedrx(struct com_softc *); 199 void comdiag(void *); 200 201 extern struct cfdriver com_cd; 202 203 dev_type_open(comopen); 204 dev_type_close(comclose); 205 dev_type_read(comread); 206 dev_type_write(comwrite); 207 dev_type_ioctl(comioctl); 208 dev_type_stop(comstop); 209 dev_type_tty(comtty); 210 dev_type_poll(compoll); 211 212 const struct cdevsw com_cdevsw = { 213 comopen, comclose, comread, comwrite, comioctl, 214 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 215 }; 216 217 /* 218 * Make this an option variable one can patch. 219 * But be warned: this must be a power of 2! 220 */ 221 u_int com_rbuf_size = COM_RING_SIZE; 222 223 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 224 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 225 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 226 227 static struct com_regs comconsregs; 228 static int comconsattached; 229 static int comconsrate; 230 static tcflag_t comconscflag; 231 static struct cnm_state com_cnm_state; 232 233 #ifndef __HAVE_TIMECOUNTER 234 static int ppscap = 235 PPS_TSFMT_TSPEC | 236 PPS_CAPTUREASSERT | 237 PPS_CAPTURECLEAR | 238 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 239 #endif /* !__HAVE_TIMECOUNTER */ 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_16550 { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 256 257 const bus_size_t com_std_map[16] = COM_REG_16550; 258 #endif /* COM_REGMAP */ 259 260 #define COMUNIT_MASK 0x7ffff 261 #define COMDIALOUT_MASK 0x80000 262 263 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 264 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active(&(sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 275 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 276 277 /*ARGSUSED*/ 278 int 279 comspeed(long speed, long frequency, int type) 280 { 281 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 282 283 int x, err; 284 285 #if 0 286 if (speed == 0) 287 return (0); 288 #endif 289 if (speed <= 0) 290 return (-1); 291 x = divrnd(frequency / 16, speed); 292 if (x <= 0) 293 return (-1); 294 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 295 if (err < 0) 296 err = -err; 297 if (err > COM_TOLERANCE) 298 return (-1); 299 return (x); 300 301 #undef divrnd 302 } 303 304 #ifdef COM_DEBUG 305 int com_debug = 0; 306 307 void comstatus(struct com_softc *, const char *); 308 void 309 comstatus(struct com_softc *sc, const char *str) 310 { 311 struct tty *tp = sc->sc_tty; 312 313 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 314 sc->sc_dev.dv_xname, str, 315 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 316 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 317 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 318 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 319 sc->sc_tx_stopped ? '+' : '-'); 320 321 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 322 sc->sc_dev.dv_xname, str, 323 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 324 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 325 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 326 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 327 sc->sc_rx_flags); 328 } 329 #endif 330 331 int 332 com_probe_subr(struct com_regs *regs) 333 { 334 335 /* force access to id reg */ 336 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 337 CSR_WRITE_1(regs, COM_REG_IIR, 0); 338 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 339 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 340 return (0); 341 342 return (1); 343 } 344 345 int 346 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 347 { 348 struct com_regs regs; 349 350 regs.cr_iot = iot; 351 regs.cr_ioh = ioh; 352 #ifdef COM_REGMAP 353 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 354 #endif 355 356 return com_probe_subr(®s); 357 } 358 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 /* Turn on line break interrupt, set carrier. */ 363 sc->sc_ier = IER_ERXRDY; 364 if (sc->sc_type == COM_TYPE_PXA2x0) 365 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 366 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 367 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 368 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 369 } 370 371 void 372 com_attach_subr(struct com_softc *sc) 373 { 374 struct com_regs *regsp = &sc->sc_regs; 375 struct tty *tp; 376 #ifdef COM_16650 377 u_int8_t lcr; 378 #endif 379 const char *fifo_msg = NULL; 380 381 aprint_naive("\n"); 382 383 callout_init(&sc->sc_diag_callout, 0); 384 simple_lock_init(&sc->sc_lock); 385 386 /* Disable interrupts before configuring the device. */ 387 if (sc->sc_type == COM_TYPE_PXA2x0) 388 sc->sc_ier = IER_EUART; 389 else 390 sc->sc_ier = 0; 391 392 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 393 394 if (regsp->cr_iot == comconsregs.cr_iot && 395 regsp->cr_iobase == comconsregs.cr_iobase) { 396 comconsattached = 1; 397 398 /* Make sure the console is always "hardwired". */ 399 delay(10000); /* wait for output to finish */ 400 SET(sc->sc_hwflags, COM_HW_CONSOLE); 401 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 402 } 403 404 /* Probe for FIFO */ 405 switch (sc->sc_type) { 406 case COM_TYPE_HAYESP: 407 goto fifodone; 408 409 case COM_TYPE_AU1x00: 410 sc->sc_fifolen = 16; 411 fifo_msg = "Au1X00 UART, working fifo"; 412 SET(sc->sc_hwflags, COM_HW_FIFO); 413 goto fifodelay; 414 } 415 416 sc->sc_fifolen = 1; 417 /* look for a NS 16550AF UART with FIFOs */ 418 CSR_WRITE_1(regsp, COM_REG_FIFO, 419 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 420 delay(100); 421 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 422 == IIR_FIFO_MASK) 423 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 424 == FIFO_TRIGGER_14) { 425 SET(sc->sc_hwflags, COM_HW_FIFO); 426 427 #ifdef COM_16650 428 /* 429 * IIR changes into the EFR if LCR is set to LCR_EERS 430 * on 16650s. We also know IIR != 0 at this point. 431 * Write 0 into the EFR, and read it. If the result 432 * is 0, we have a 16650. 433 * 434 * Older 16650s were broken; the test to detect them 435 * is taken from the Linux driver. Apparently 436 * setting DLAB enable gives access to the EFR on 437 * these chips. 438 */ 439 lcr = CSR_READ_1(regsp, COM_REG_LCR); 440 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 441 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 442 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 443 CSR_WRITE_1(regsp, COM_REG_LCR, 444 lcr | LCR_DLAB); 445 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 446 CLR(sc->sc_hwflags, COM_HW_FIFO); 447 sc->sc_fifolen = 0; 448 } else { 449 SET(sc->sc_hwflags, COM_HW_FLOW); 450 sc->sc_fifolen = 32; 451 } 452 } else 453 #endif 454 sc->sc_fifolen = 16; 455 456 #ifdef COM_16650 457 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 458 if (sc->sc_fifolen == 0) 459 fifo_msg = "st16650, broken fifo"; 460 else if (sc->sc_fifolen == 32) 461 fifo_msg = "st16650a, working fifo"; 462 else 463 #endif 464 fifo_msg = "ns16550a, working fifo"; 465 } else 466 fifo_msg = "ns16550, broken fifo"; 467 else 468 fifo_msg = "ns8250 or ns16450, no fifo"; 469 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 470 fifodelay: 471 /* 472 * Some chips will clear down both Tx and Rx FIFOs when zero is 473 * written to com_fifo. If this chip is the console, writing zero 474 * results in some of the chip/FIFO description being lost, so delay 475 * printing it until now. 476 */ 477 delay(10); 478 aprint_normal(": %s\n", fifo_msg); 479 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 480 sc->sc_fifolen = 1; 481 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 482 } 483 484 fifodone: 485 486 tp = ttymalloc(); 487 tp->t_oproc = comstart; 488 tp->t_param = comparam; 489 tp->t_hwiflow = comhwiflow; 490 491 sc->sc_tty = tp; 492 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 493 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 494 sc->sc_rbavail = com_rbuf_size; 495 if (sc->sc_rbuf == NULL) { 496 aprint_error("%s: unable to allocate ring buffer\n", 497 sc->sc_dev.dv_xname); 498 return; 499 } 500 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 501 502 tty_attach(tp); 503 504 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 505 SET(sc->sc_mcr, MCR_IENABLE); 506 507 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 508 int maj; 509 510 /* locate the major number */ 511 maj = cdevsw_lookup_major(&com_cdevsw); 512 513 tp->t_dev = cn_tab->cn_dev = makedev(maj, 514 device_unit(&sc->sc_dev)); 515 516 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 517 } 518 519 #ifdef KGDB 520 /* 521 * Allow kgdb to "take over" this port. If this is 522 * not the console and is the kgdb device, it has 523 * exclusive use. If it's the console _and_ the 524 * kgdb device, it doesn't. 525 */ 526 if (regsp->cr_iot == comkgdbregs.cr_iot && 527 regsp->cr_iobase == comkgdbregs.cr_iobase) { 528 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 529 com_kgdb_attached = 1; 530 531 SET(sc->sc_hwflags, COM_HW_KGDB); 532 } 533 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 534 } 535 #endif 536 537 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 538 539 #if NRND > 0 && defined(RND_COM) 540 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 541 RND_TYPE_TTY, 0); 542 #endif 543 544 /* if there are no enable/disable functions, assume the device 545 is always enabled */ 546 if (!sc->enable) 547 sc->enabled = 1; 548 549 com_config(sc); 550 551 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 552 com_power, sc); 553 if (sc->sc_powerhook == NULL) 554 aprint_error("%s: WARNING: unable to establish power hook\n", 555 sc->sc_dev.dv_xname); 556 557 SET(sc->sc_hwflags, COM_HW_DEV_OK); 558 } 559 560 void 561 com_config(struct com_softc *sc) 562 { 563 struct com_regs *regsp = &sc->sc_regs; 564 565 /* Disable interrupts before configuring the device. */ 566 if (sc->sc_type == COM_TYPE_PXA2x0) 567 sc->sc_ier = IER_EUART; 568 else 569 sc->sc_ier = 0; 570 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 571 (void) CSR_READ_1(regsp, COM_REG_IIR); 572 573 #ifdef COM_HAYESP 574 /* Look for a Hayes ESP board. */ 575 if (sc->sc_type == COM_TYPE_HAYESP) { 576 577 /* Set 16550 compatibility mode */ 578 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 579 HAYESP_SETMODE); 580 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 581 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 582 HAYESP_MODE_SCALE); 583 584 /* Set RTS/CTS flow control */ 585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 586 HAYESP_SETFLOWTYPE); 587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 588 HAYESP_FLOW_RTS); 589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 590 HAYESP_FLOW_CTS); 591 592 /* Set flow control levels */ 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 594 HAYESP_SETRXFLOW); 595 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 596 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 598 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 600 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 603 } 604 #endif 605 606 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 607 com_enable_debugport(sc); 608 } 609 610 int 611 com_detach(struct device *self, int flags) 612 { 613 struct com_softc *sc = (struct com_softc *)self; 614 int maj, mn; 615 616 /* kill the power hook */ 617 if (sc->sc_powerhook != NULL) 618 powerhook_disestablish(sc->sc_powerhook); 619 620 /* locate the major number */ 621 maj = cdevsw_lookup_major(&com_cdevsw); 622 623 /* Nuke the vnodes for any open instances. */ 624 mn = device_unit(self); 625 vdevgone(maj, mn, mn, VCHR); 626 627 mn |= COMDIALOUT_MASK; 628 vdevgone(maj, mn, mn, VCHR); 629 630 if (sc->sc_rbuf == NULL) { 631 /* 632 * Ring buffer allocation failed in the com_attach_subr, 633 * only the tty is allocated, and nothing else. 634 */ 635 ttyfree(sc->sc_tty); 636 return 0; 637 } 638 639 /* Free the receive buffer. */ 640 free(sc->sc_rbuf, M_DEVBUF); 641 642 /* Detach and free the tty. */ 643 tty_detach(sc->sc_tty); 644 ttyfree(sc->sc_tty); 645 646 /* Unhook the soft interrupt handler. */ 647 softintr_disestablish(sc->sc_si); 648 649 #if NRND > 0 && defined(RND_COM) 650 /* Unhook the entropy source. */ 651 rnd_detach_source(&sc->rnd_source); 652 #endif 653 654 return (0); 655 } 656 657 int 658 com_activate(struct device *self, enum devact act) 659 { 660 struct com_softc *sc = (struct com_softc *)self; 661 int s, rv = 0; 662 663 s = splserial(); 664 COM_LOCK(sc); 665 switch (act) { 666 case DVACT_ACTIVATE: 667 rv = EOPNOTSUPP; 668 break; 669 670 case DVACT_DEACTIVATE: 671 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 672 rv = EBUSY; 673 break; 674 } 675 676 if (sc->disable != NULL && sc->enabled != 0) { 677 (*sc->disable)(sc); 678 sc->enabled = 0; 679 } 680 break; 681 } 682 683 COM_UNLOCK(sc); 684 splx(s); 685 return (rv); 686 } 687 688 void 689 com_shutdown(struct com_softc *sc) 690 { 691 struct tty *tp = sc->sc_tty; 692 int s; 693 694 s = splserial(); 695 COM_LOCK(sc); 696 697 /* If we were asserting flow control, then deassert it. */ 698 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 699 com_hwiflow(sc); 700 701 /* Clear any break condition set with TIOCSBRK. */ 702 com_break(sc, 0); 703 704 #ifndef __HAVE_TIMECOUNTER 705 /* Turn off PPS capture on last close. */ 706 sc->sc_ppsmask = 0; 707 sc->ppsparam.mode = 0; 708 #endif /* !__HAVE_TIMECOUNTER */ 709 710 /* 711 * Hang up if necessary. Wait a bit, so the other side has time to 712 * notice even if we immediately open the port again. 713 * Avoid tsleeping above splhigh(). 714 */ 715 if (ISSET(tp->t_cflag, HUPCL)) { 716 com_modem(sc, 0); 717 COM_UNLOCK(sc); 718 splx(s); 719 /* XXX tsleep will only timeout */ 720 (void) tsleep(sc, TTIPRI, ttclos, hz); 721 s = splserial(); 722 COM_LOCK(sc); 723 } 724 725 /* Turn off interrupts. */ 726 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 727 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 728 if (sc->sc_type == COM_TYPE_PXA2x0) 729 sc->sc_ier |= IER_ERXTOUT; 730 } else 731 sc->sc_ier = 0; 732 733 if (sc->sc_type == COM_TYPE_PXA2x0) 734 sc->sc_ier |= IER_EUART; 735 736 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 737 738 if (sc->disable) { 739 #ifdef DIAGNOSTIC 740 if (!sc->enabled) 741 panic("com_shutdown: not enabled?"); 742 #endif 743 (*sc->disable)(sc); 744 sc->enabled = 0; 745 } 746 COM_UNLOCK(sc); 747 splx(s); 748 } 749 750 int 751 comopen(dev_t dev, int flag, int mode, struct lwp *l) 752 { 753 struct com_softc *sc; 754 struct tty *tp; 755 int s, s2; 756 int error; 757 758 sc = device_lookup(&com_cd, COMUNIT(dev)); 759 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 760 sc->sc_rbuf == NULL) 761 return (ENXIO); 762 763 if (!device_is_active(&sc->sc_dev)) 764 return (ENXIO); 765 766 #ifdef KGDB 767 /* 768 * If this is the kgdb port, no other use is permitted. 769 */ 770 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 771 return (EBUSY); 772 #endif 773 774 tp = sc->sc_tty; 775 776 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 777 return (EBUSY); 778 779 s = spltty(); 780 781 /* 782 * Do the following iff this is a first open. 783 */ 784 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 785 struct termios t; 786 787 tp->t_dev = dev; 788 789 s2 = splserial(); 790 COM_LOCK(sc); 791 792 if (sc->enable) { 793 if ((*sc->enable)(sc)) { 794 COM_UNLOCK(sc); 795 splx(s2); 796 splx(s); 797 printf("%s: device enable failed\n", 798 sc->sc_dev.dv_xname); 799 return (EIO); 800 } 801 sc->enabled = 1; 802 com_config(sc); 803 } 804 805 /* Turn on interrupts. */ 806 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 807 if (sc->sc_type == COM_TYPE_PXA2x0) 808 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 809 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 810 811 /* Fetch the current modem control status, needed later. */ 812 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 813 814 /* Clear PPS capture state on first open. */ 815 #ifdef __HAVE_TIMECOUNTER 816 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 817 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 818 pps_init(&sc->sc_pps_state); 819 #else /* !__HAVE_TIMECOUNTER */ 820 sc->sc_ppsmask = 0; 821 sc->ppsparam.mode = 0; 822 #endif /* !__HAVE_TIMECOUNTER */ 823 824 COM_UNLOCK(sc); 825 splx(s2); 826 827 /* 828 * Initialize the termios status to the defaults. Add in the 829 * sticky bits from TIOCSFLAGS. 830 */ 831 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 832 t.c_ospeed = comconsrate; 833 t.c_cflag = comconscflag; 834 } else { 835 t.c_ospeed = TTYDEF_SPEED; 836 t.c_cflag = TTYDEF_CFLAG; 837 } 838 t.c_ispeed = t.c_ospeed; 839 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 840 SET(t.c_cflag, CLOCAL); 841 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 842 SET(t.c_cflag, CRTSCTS); 843 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 844 SET(t.c_cflag, MDMBUF); 845 /* Make sure comparam() will do something. */ 846 tp->t_ospeed = 0; 847 (void) comparam(tp, &t); 848 tp->t_iflag = TTYDEF_IFLAG; 849 tp->t_oflag = TTYDEF_OFLAG; 850 tp->t_lflag = TTYDEF_LFLAG; 851 ttychars(tp); 852 ttsetwater(tp); 853 854 s2 = splserial(); 855 COM_LOCK(sc); 856 857 /* 858 * Turn on DTR. We must always do this, even if carrier is not 859 * present, because otherwise we'd have to use TIOCSDTR 860 * immediately after setting CLOCAL, which applications do not 861 * expect. We always assert DTR while the device is open 862 * unless explicitly requested to deassert it. 863 */ 864 com_modem(sc, 1); 865 866 /* Clear the input ring, and unblock. */ 867 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 868 sc->sc_rbavail = com_rbuf_size; 869 com_iflush(sc); 870 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 871 com_hwiflow(sc); 872 873 #ifdef COM_DEBUG 874 if (com_debug) 875 comstatus(sc, "comopen "); 876 #endif 877 878 COM_UNLOCK(sc); 879 splx(s2); 880 } 881 882 splx(s); 883 884 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 885 if (error) 886 goto bad; 887 888 error = (*tp->t_linesw->l_open)(dev, tp); 889 if (error) 890 goto bad; 891 892 return (0); 893 894 bad: 895 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 896 /* 897 * We failed to open the device, and nobody else had it opened. 898 * Clean up the state as appropriate. 899 */ 900 com_shutdown(sc); 901 } 902 903 return (error); 904 } 905 906 int 907 comclose(dev_t dev, int flag, int mode, struct lwp *l) 908 { 909 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 910 struct tty *tp = sc->sc_tty; 911 912 /* XXX This is for cons.c. */ 913 if (!ISSET(tp->t_state, TS_ISOPEN)) 914 return (0); 915 916 (*tp->t_linesw->l_close)(tp, flag); 917 ttyclose(tp); 918 919 if (COM_ISALIVE(sc) == 0) 920 return (0); 921 922 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 923 /* 924 * Although we got a last close, the device may still be in 925 * use; e.g. if this was the dialout node, and there are still 926 * processes waiting for carrier on the non-dialout node. 927 */ 928 com_shutdown(sc); 929 } 930 931 return (0); 932 } 933 934 int 935 comread(dev_t dev, struct uio *uio, int flag) 936 { 937 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 938 struct tty *tp = sc->sc_tty; 939 940 if (COM_ISALIVE(sc) == 0) 941 return (EIO); 942 943 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 944 } 945 946 int 947 comwrite(dev_t dev, struct uio *uio, int flag) 948 { 949 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 950 struct tty *tp = sc->sc_tty; 951 952 if (COM_ISALIVE(sc) == 0) 953 return (EIO); 954 955 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 956 } 957 958 int 959 compoll(dev_t dev, int events, struct lwp *l) 960 { 961 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 962 struct tty *tp = sc->sc_tty; 963 964 if (COM_ISALIVE(sc) == 0) 965 return (POLLHUP); 966 967 return ((*tp->t_linesw->l_poll)(tp, events, l)); 968 } 969 970 struct tty * 971 comtty(dev_t dev) 972 { 973 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 974 struct tty *tp = sc->sc_tty; 975 976 return (tp); 977 } 978 979 int 980 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 981 { 982 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 983 struct tty *tp = sc->sc_tty; 984 int error; 985 int s; 986 987 if (COM_ISALIVE(sc) == 0) 988 return (EIO); 989 990 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 991 if (error != EPASSTHROUGH) 992 return (error); 993 994 error = ttioctl(tp, cmd, data, flag, l); 995 if (error != EPASSTHROUGH) 996 return (error); 997 998 error = 0; 999 switch (cmd) { 1000 case TIOCSFLAGS: 1001 error = kauth_authorize_device_tty(l->l_cred, 1002 KAUTH_DEVICE_TTY_PRIVSET, tp); 1003 break; 1004 default: 1005 /* nothing */ 1006 break; 1007 } 1008 if (error) { 1009 return error; 1010 } 1011 1012 s = splserial(); 1013 COM_LOCK(sc); 1014 1015 switch (cmd) { 1016 case TIOCSBRK: 1017 com_break(sc, 1); 1018 break; 1019 1020 case TIOCCBRK: 1021 com_break(sc, 0); 1022 break; 1023 1024 case TIOCSDTR: 1025 com_modem(sc, 1); 1026 break; 1027 1028 case TIOCCDTR: 1029 com_modem(sc, 0); 1030 break; 1031 1032 case TIOCGFLAGS: 1033 *(int *)data = sc->sc_swflags; 1034 break; 1035 1036 case TIOCSFLAGS: 1037 sc->sc_swflags = *(int *)data; 1038 break; 1039 1040 case TIOCMSET: 1041 case TIOCMBIS: 1042 case TIOCMBIC: 1043 tiocm_to_com(sc, cmd, *(int *)data); 1044 break; 1045 1046 case TIOCMGET: 1047 *(int *)data = com_to_tiocm(sc); 1048 break; 1049 1050 #ifdef __HAVE_TIMECOUNTER 1051 case PPS_IOC_CREATE: 1052 case PPS_IOC_DESTROY: 1053 case PPS_IOC_GETPARAMS: 1054 case PPS_IOC_SETPARAMS: 1055 case PPS_IOC_GETCAP: 1056 case PPS_IOC_FETCH: 1057 #ifdef PPS_SYNC 1058 case PPS_IOC_KCBIND: 1059 #endif 1060 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1061 break; 1062 #else /* !__HAVE_TIMECOUNTER */ 1063 case PPS_IOC_CREATE: 1064 break; 1065 1066 case PPS_IOC_DESTROY: 1067 break; 1068 1069 case PPS_IOC_GETPARAMS: { 1070 pps_params_t *pp; 1071 pp = (pps_params_t *)data; 1072 *pp = sc->ppsparam; 1073 break; 1074 } 1075 1076 case PPS_IOC_SETPARAMS: { 1077 pps_params_t *pp; 1078 int mode; 1079 pp = (pps_params_t *)data; 1080 if (pp->mode & ~ppscap) { 1081 error = EINVAL; 1082 break; 1083 } 1084 sc->ppsparam = *pp; 1085 /* 1086 * Compute msr masks from user-specified timestamp state. 1087 */ 1088 mode = sc->ppsparam.mode; 1089 switch (mode & PPS_CAPTUREBOTH) { 1090 case 0: 1091 sc->sc_ppsmask = 0; 1092 break; 1093 1094 case PPS_CAPTUREASSERT: 1095 sc->sc_ppsmask = MSR_DCD; 1096 sc->sc_ppsassert = MSR_DCD; 1097 sc->sc_ppsclear = -1; 1098 break; 1099 1100 case PPS_CAPTURECLEAR: 1101 sc->sc_ppsmask = MSR_DCD; 1102 sc->sc_ppsassert = -1; 1103 sc->sc_ppsclear = 0; 1104 break; 1105 1106 case PPS_CAPTUREBOTH: 1107 sc->sc_ppsmask = MSR_DCD; 1108 sc->sc_ppsassert = MSR_DCD; 1109 sc->sc_ppsclear = 0; 1110 break; 1111 1112 default: 1113 error = EINVAL; 1114 break; 1115 } 1116 break; 1117 } 1118 1119 case PPS_IOC_GETCAP: 1120 *(int*)data = ppscap; 1121 break; 1122 1123 case PPS_IOC_FETCH: { 1124 pps_info_t *pi; 1125 pi = (pps_info_t *)data; 1126 *pi = sc->ppsinfo; 1127 break; 1128 } 1129 1130 #ifdef PPS_SYNC 1131 case PPS_IOC_KCBIND: { 1132 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1133 1134 if (edge == 0) { 1135 /* 1136 * remove binding for this source; ignore 1137 * the request if this is not the current 1138 * hardpps source 1139 */ 1140 if (pps_kc_hardpps_source == sc) { 1141 pps_kc_hardpps_source = NULL; 1142 pps_kc_hardpps_mode = 0; 1143 } 1144 } else { 1145 /* 1146 * bind hardpps to this source, replacing any 1147 * previously specified source or edges 1148 */ 1149 pps_kc_hardpps_source = sc; 1150 pps_kc_hardpps_mode = edge; 1151 } 1152 break; 1153 } 1154 #endif /* PPS_SYNC */ 1155 #endif /* !__HAVE_TIMECOUNTER */ 1156 1157 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1158 #ifdef __HAVE_TIMECOUNTER 1159 #ifndef PPS_TRAILING_EDGE 1160 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1161 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1162 #else 1163 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1164 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1165 #endif 1166 #else /* !__HAVE_TIMECOUNTER */ 1167 /* 1168 * Some GPS clocks models use the falling rather than 1169 * rising edge as the on-the-second signal. 1170 * The old API has no way to specify PPS polarity. 1171 */ 1172 sc->sc_ppsmask = MSR_DCD; 1173 #ifndef PPS_TRAILING_EDGE 1174 sc->sc_ppsassert = MSR_DCD; 1175 sc->sc_ppsclear = -1; 1176 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1177 &sc->ppsinfo.assert_timestamp); 1178 #else 1179 sc->sc_ppsassert = -1; 1180 sc->sc_ppsclear = 0; 1181 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1182 &sc->ppsinfo.clear_timestamp); 1183 #endif 1184 #endif /* !__HAVE_TIMECOUNTER */ 1185 break; 1186 1187 default: 1188 error = EPASSTHROUGH; 1189 break; 1190 } 1191 1192 COM_UNLOCK(sc); 1193 splx(s); 1194 1195 #ifdef COM_DEBUG 1196 if (com_debug) 1197 comstatus(sc, "comioctl "); 1198 #endif 1199 1200 return (error); 1201 } 1202 1203 integrate void 1204 com_schedrx(struct com_softc *sc) 1205 { 1206 1207 sc->sc_rx_ready = 1; 1208 1209 /* Wake up the poller. */ 1210 softintr_schedule(sc->sc_si); 1211 } 1212 1213 void 1214 com_break(struct com_softc *sc, int onoff) 1215 { 1216 1217 if (onoff) 1218 SET(sc->sc_lcr, LCR_SBREAK); 1219 else 1220 CLR(sc->sc_lcr, LCR_SBREAK); 1221 1222 if (!sc->sc_heldchange) { 1223 if (sc->sc_tx_busy) { 1224 sc->sc_heldtbc = sc->sc_tbc; 1225 sc->sc_tbc = 0; 1226 sc->sc_heldchange = 1; 1227 } else 1228 com_loadchannelregs(sc); 1229 } 1230 } 1231 1232 void 1233 com_modem(struct com_softc *sc, int onoff) 1234 { 1235 1236 if (sc->sc_mcr_dtr == 0) 1237 return; 1238 1239 if (onoff) 1240 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1241 else 1242 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1243 1244 if (!sc->sc_heldchange) { 1245 if (sc->sc_tx_busy) { 1246 sc->sc_heldtbc = sc->sc_tbc; 1247 sc->sc_tbc = 0; 1248 sc->sc_heldchange = 1; 1249 } else 1250 com_loadchannelregs(sc); 1251 } 1252 } 1253 1254 void 1255 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1256 { 1257 u_char combits; 1258 1259 combits = 0; 1260 if (ISSET(ttybits, TIOCM_DTR)) 1261 SET(combits, MCR_DTR); 1262 if (ISSET(ttybits, TIOCM_RTS)) 1263 SET(combits, MCR_RTS); 1264 1265 switch (how) { 1266 case TIOCMBIC: 1267 CLR(sc->sc_mcr, combits); 1268 break; 1269 1270 case TIOCMBIS: 1271 SET(sc->sc_mcr, combits); 1272 break; 1273 1274 case TIOCMSET: 1275 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1276 SET(sc->sc_mcr, combits); 1277 break; 1278 } 1279 1280 if (!sc->sc_heldchange) { 1281 if (sc->sc_tx_busy) { 1282 sc->sc_heldtbc = sc->sc_tbc; 1283 sc->sc_tbc = 0; 1284 sc->sc_heldchange = 1; 1285 } else 1286 com_loadchannelregs(sc); 1287 } 1288 } 1289 1290 int 1291 com_to_tiocm(struct com_softc *sc) 1292 { 1293 u_char combits; 1294 int ttybits = 0; 1295 1296 combits = sc->sc_mcr; 1297 if (ISSET(combits, MCR_DTR)) 1298 SET(ttybits, TIOCM_DTR); 1299 if (ISSET(combits, MCR_RTS)) 1300 SET(ttybits, TIOCM_RTS); 1301 1302 combits = sc->sc_msr; 1303 if (ISSET(combits, MSR_DCD)) 1304 SET(ttybits, TIOCM_CD); 1305 if (ISSET(combits, MSR_CTS)) 1306 SET(ttybits, TIOCM_CTS); 1307 if (ISSET(combits, MSR_DSR)) 1308 SET(ttybits, TIOCM_DSR); 1309 if (ISSET(combits, MSR_RI | MSR_TERI)) 1310 SET(ttybits, TIOCM_RI); 1311 1312 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1313 SET(ttybits, TIOCM_LE); 1314 1315 return (ttybits); 1316 } 1317 1318 static u_char 1319 cflag2lcr(tcflag_t cflag) 1320 { 1321 u_char lcr = 0; 1322 1323 switch (ISSET(cflag, CSIZE)) { 1324 case CS5: 1325 SET(lcr, LCR_5BITS); 1326 break; 1327 case CS6: 1328 SET(lcr, LCR_6BITS); 1329 break; 1330 case CS7: 1331 SET(lcr, LCR_7BITS); 1332 break; 1333 case CS8: 1334 SET(lcr, LCR_8BITS); 1335 break; 1336 } 1337 if (ISSET(cflag, PARENB)) { 1338 SET(lcr, LCR_PENAB); 1339 if (!ISSET(cflag, PARODD)) 1340 SET(lcr, LCR_PEVEN); 1341 } 1342 if (ISSET(cflag, CSTOPB)) 1343 SET(lcr, LCR_STOPB); 1344 1345 return (lcr); 1346 } 1347 1348 int 1349 comparam(struct tty *tp, struct termios *t) 1350 { 1351 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1352 int ospeed; 1353 u_char lcr; 1354 int s; 1355 1356 if (COM_ISALIVE(sc) == 0) 1357 return (EIO); 1358 1359 #ifdef COM_HAYESP 1360 if (sc->sc_type == COM_TYPE_HAYESP) { 1361 int prescaler, speed; 1362 1363 /* 1364 * Calculate UART clock prescaler. It should be in 1365 * range of 0 .. 3. 1366 */ 1367 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1368 prescaler++, speed /= 2) 1369 if ((ospeed = comspeed(speed, sc->sc_frequency, 1370 sc->sc_type)) > 0) 1371 break; 1372 1373 if (prescaler == 4) 1374 return (EINVAL); 1375 sc->sc_prescaler = prescaler; 1376 } else 1377 #endif 1378 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1379 1380 /* Check requested parameters. */ 1381 if (ospeed < 0) 1382 return (EINVAL); 1383 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1384 return (EINVAL); 1385 1386 /* 1387 * For the console, always force CLOCAL and !HUPCL, so that the port 1388 * is always active. 1389 */ 1390 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1391 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1392 SET(t->c_cflag, CLOCAL); 1393 CLR(t->c_cflag, HUPCL); 1394 } 1395 1396 /* 1397 * If there were no changes, don't do anything. This avoids dropping 1398 * input and improves performance when all we did was frob things like 1399 * VMIN and VTIME. 1400 */ 1401 if (tp->t_ospeed == t->c_ospeed && 1402 tp->t_cflag == t->c_cflag) 1403 return (0); 1404 1405 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1406 1407 s = splserial(); 1408 COM_LOCK(sc); 1409 1410 sc->sc_lcr = lcr; 1411 1412 /* 1413 * If we're not in a mode that assumes a connection is present, then 1414 * ignore carrier changes. 1415 */ 1416 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1417 sc->sc_msr_dcd = 0; 1418 else 1419 sc->sc_msr_dcd = MSR_DCD; 1420 /* 1421 * Set the flow control pins depending on the current flow control 1422 * mode. 1423 */ 1424 if (ISSET(t->c_cflag, CRTSCTS)) { 1425 sc->sc_mcr_dtr = MCR_DTR; 1426 sc->sc_mcr_rts = MCR_RTS; 1427 sc->sc_msr_cts = MSR_CTS; 1428 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1429 } else if (ISSET(t->c_cflag, MDMBUF)) { 1430 /* 1431 * For DTR/DCD flow control, make sure we don't toggle DTR for 1432 * carrier detection. 1433 */ 1434 sc->sc_mcr_dtr = 0; 1435 sc->sc_mcr_rts = MCR_DTR; 1436 sc->sc_msr_cts = MSR_DCD; 1437 sc->sc_efr = 0; 1438 } else { 1439 /* 1440 * If no flow control, then always set RTS. This will make 1441 * the other side happy if it mistakenly thinks we're doing 1442 * RTS/CTS flow control. 1443 */ 1444 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1445 sc->sc_mcr_rts = 0; 1446 sc->sc_msr_cts = 0; 1447 sc->sc_efr = 0; 1448 if (ISSET(sc->sc_mcr, MCR_DTR)) 1449 SET(sc->sc_mcr, MCR_RTS); 1450 else 1451 CLR(sc->sc_mcr, MCR_RTS); 1452 } 1453 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1454 1455 #if 0 1456 if (ospeed == 0) 1457 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1458 else 1459 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1460 #endif 1461 1462 sc->sc_dlbl = ospeed; 1463 sc->sc_dlbh = ospeed >> 8; 1464 1465 /* 1466 * Set the FIFO threshold based on the receive speed. 1467 * 1468 * * If it's a low speed, it's probably a mouse or some other 1469 * interactive device, so set the threshold low. 1470 * * If it's a high speed, trim the trigger level down to prevent 1471 * overflows. 1472 * * Otherwise set it a bit higher. 1473 */ 1474 if (sc->sc_type == COM_TYPE_HAYESP) 1475 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1476 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1477 sc->sc_fifo = FIFO_ENABLE | 1478 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1479 else 1480 sc->sc_fifo = 0; 1481 1482 /* And copy to tty. */ 1483 tp->t_ispeed = t->c_ospeed; 1484 tp->t_ospeed = t->c_ospeed; 1485 tp->t_cflag = t->c_cflag; 1486 1487 if (!sc->sc_heldchange) { 1488 if (sc->sc_tx_busy) { 1489 sc->sc_heldtbc = sc->sc_tbc; 1490 sc->sc_tbc = 0; 1491 sc->sc_heldchange = 1; 1492 } else 1493 com_loadchannelregs(sc); 1494 } 1495 1496 if (!ISSET(t->c_cflag, CHWFLOW)) { 1497 /* Disable the high water mark. */ 1498 sc->sc_r_hiwat = 0; 1499 sc->sc_r_lowat = 0; 1500 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1501 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1502 com_schedrx(sc); 1503 } 1504 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1505 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1506 com_hwiflow(sc); 1507 } 1508 } else { 1509 sc->sc_r_hiwat = com_rbuf_hiwat; 1510 sc->sc_r_lowat = com_rbuf_lowat; 1511 } 1512 1513 COM_UNLOCK(sc); 1514 splx(s); 1515 1516 /* 1517 * Update the tty layer's idea of the carrier bit, in case we changed 1518 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1519 * explicit request. 1520 */ 1521 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1522 1523 #ifdef COM_DEBUG 1524 if (com_debug) 1525 comstatus(sc, "comparam "); 1526 #endif 1527 1528 if (!ISSET(t->c_cflag, CHWFLOW)) { 1529 if (sc->sc_tx_stopped) { 1530 sc->sc_tx_stopped = 0; 1531 comstart(tp); 1532 } 1533 } 1534 1535 return (0); 1536 } 1537 1538 void 1539 com_iflush(struct com_softc *sc) 1540 { 1541 struct com_regs *regsp = &sc->sc_regs; 1542 #ifdef DIAGNOSTIC 1543 int reg; 1544 #endif 1545 int timo; 1546 1547 #ifdef DIAGNOSTIC 1548 reg = 0xffff; 1549 #endif 1550 timo = 50000; 1551 /* flush any pending I/O */ 1552 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1553 && --timo) 1554 #ifdef DIAGNOSTIC 1555 reg = 1556 #else 1557 (void) 1558 #endif 1559 CSR_READ_1(regsp, COM_REG_RXDATA); 1560 #ifdef DIAGNOSTIC 1561 if (!timo) 1562 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1563 reg); 1564 #endif 1565 } 1566 1567 void 1568 com_loadchannelregs(struct com_softc *sc) 1569 { 1570 struct com_regs *regsp = &sc->sc_regs; 1571 1572 /* XXXXX necessary? */ 1573 com_iflush(sc); 1574 1575 if (sc->sc_type == COM_TYPE_PXA2x0) 1576 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1577 else 1578 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1579 1580 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1581 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1582 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1583 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1584 } 1585 } 1586 if (sc->sc_type == COM_TYPE_AU1x00) { 1587 /* alchemy has single separate 16-bit clock divisor register */ 1588 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1589 (sc->sc_dlbh << 8)); 1590 } else { 1591 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1592 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1593 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1594 } 1595 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1596 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1597 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1598 #ifdef COM_HAYESP 1599 if (sc->sc_type == COM_TYPE_HAYESP) { 1600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1601 HAYESP_SETPRESCALER); 1602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1603 sc->sc_prescaler); 1604 } 1605 #endif 1606 1607 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1608 } 1609 1610 int 1611 comhwiflow(struct tty *tp, int block) 1612 { 1613 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1614 int s; 1615 1616 if (COM_ISALIVE(sc) == 0) 1617 return (0); 1618 1619 if (sc->sc_mcr_rts == 0) 1620 return (0); 1621 1622 s = splserial(); 1623 COM_LOCK(sc); 1624 1625 if (block) { 1626 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1627 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1628 com_hwiflow(sc); 1629 } 1630 } else { 1631 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1632 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1633 com_schedrx(sc); 1634 } 1635 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1636 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1637 com_hwiflow(sc); 1638 } 1639 } 1640 1641 COM_UNLOCK(sc); 1642 splx(s); 1643 return (1); 1644 } 1645 1646 /* 1647 * (un)block input via hw flowcontrol 1648 */ 1649 void 1650 com_hwiflow(struct com_softc *sc) 1651 { 1652 struct com_regs *regsp= &sc->sc_regs; 1653 1654 if (sc->sc_mcr_rts == 0) 1655 return; 1656 1657 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1658 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1659 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1660 } else { 1661 SET(sc->sc_mcr, sc->sc_mcr_rts); 1662 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1663 } 1664 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1665 } 1666 1667 1668 void 1669 comstart(struct tty *tp) 1670 { 1671 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1672 struct com_regs *regsp = &sc->sc_regs; 1673 int s; 1674 1675 if (COM_ISALIVE(sc) == 0) 1676 return; 1677 1678 s = spltty(); 1679 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1680 goto out; 1681 if (sc->sc_tx_stopped) 1682 goto out; 1683 1684 if (tp->t_outq.c_cc <= tp->t_lowat) { 1685 if (ISSET(tp->t_state, TS_ASLEEP)) { 1686 CLR(tp->t_state, TS_ASLEEP); 1687 wakeup(&tp->t_outq); 1688 } 1689 selwakeup(&tp->t_wsel); 1690 if (tp->t_outq.c_cc == 0) 1691 goto out; 1692 } 1693 1694 /* Grab the first contiguous region of buffer space. */ 1695 { 1696 u_char *tba; 1697 int tbc; 1698 1699 tba = tp->t_outq.c_cf; 1700 tbc = ndqb(&tp->t_outq, 0); 1701 1702 (void)splserial(); 1703 COM_LOCK(sc); 1704 1705 sc->sc_tba = tba; 1706 sc->sc_tbc = tbc; 1707 } 1708 1709 SET(tp->t_state, TS_BUSY); 1710 sc->sc_tx_busy = 1; 1711 1712 /* Enable transmit completion interrupts if necessary. */ 1713 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1714 SET(sc->sc_ier, IER_ETXRDY); 1715 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1716 } 1717 1718 /* Output the first chunk of the contiguous buffer. */ 1719 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1720 u_int n; 1721 1722 n = sc->sc_tbc; 1723 if (n > sc->sc_fifolen) 1724 n = sc->sc_fifolen; 1725 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1726 sc->sc_tbc -= n; 1727 sc->sc_tba += n; 1728 } 1729 1730 COM_UNLOCK(sc); 1731 out: 1732 splx(s); 1733 return; 1734 } 1735 1736 /* 1737 * Stop output on a line. 1738 */ 1739 void 1740 comstop(struct tty *tp, int flag) 1741 { 1742 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1743 int s; 1744 1745 s = splserial(); 1746 COM_LOCK(sc); 1747 if (ISSET(tp->t_state, TS_BUSY)) { 1748 /* Stop transmitting at the next chunk. */ 1749 sc->sc_tbc = 0; 1750 sc->sc_heldtbc = 0; 1751 if (!ISSET(tp->t_state, TS_TTSTOP)) 1752 SET(tp->t_state, TS_FLUSH); 1753 } 1754 COM_UNLOCK(sc); 1755 splx(s); 1756 } 1757 1758 void 1759 comdiag(void *arg) 1760 { 1761 struct com_softc *sc = arg; 1762 int overflows, floods; 1763 int s; 1764 1765 s = splserial(); 1766 COM_LOCK(sc); 1767 overflows = sc->sc_overflows; 1768 sc->sc_overflows = 0; 1769 floods = sc->sc_floods; 1770 sc->sc_floods = 0; 1771 sc->sc_errors = 0; 1772 COM_UNLOCK(sc); 1773 splx(s); 1774 1775 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1776 sc->sc_dev.dv_xname, 1777 overflows, overflows == 1 ? "" : "s", 1778 floods, floods == 1 ? "" : "s"); 1779 } 1780 1781 integrate void 1782 com_rxsoft(struct com_softc *sc, struct tty *tp) 1783 { 1784 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1785 u_char *get, *end; 1786 u_int cc, scc; 1787 u_char lsr; 1788 int code; 1789 int s; 1790 1791 end = sc->sc_ebuf; 1792 get = sc->sc_rbget; 1793 scc = cc = com_rbuf_size - sc->sc_rbavail; 1794 1795 if (cc == com_rbuf_size) { 1796 sc->sc_floods++; 1797 if (sc->sc_errors++ == 0) 1798 callout_reset(&sc->sc_diag_callout, 60 * hz, 1799 comdiag, sc); 1800 } 1801 1802 /* If not yet open, drop the entire buffer content here */ 1803 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1804 get += cc << 1; 1805 if (get >= end) 1806 get -= com_rbuf_size << 1; 1807 cc = 0; 1808 } 1809 while (cc) { 1810 code = get[0]; 1811 lsr = get[1]; 1812 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1813 if (ISSET(lsr, LSR_OE)) { 1814 sc->sc_overflows++; 1815 if (sc->sc_errors++ == 0) 1816 callout_reset(&sc->sc_diag_callout, 1817 60 * hz, comdiag, sc); 1818 } 1819 if (ISSET(lsr, LSR_BI | LSR_FE)) 1820 SET(code, TTY_FE); 1821 if (ISSET(lsr, LSR_PE)) 1822 SET(code, TTY_PE); 1823 } 1824 if ((*rint)(code, tp) == -1) { 1825 /* 1826 * The line discipline's buffer is out of space. 1827 */ 1828 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1829 /* 1830 * We're either not using flow control, or the 1831 * line discipline didn't tell us to block for 1832 * some reason. Either way, we have no way to 1833 * know when there's more space available, so 1834 * just drop the rest of the data. 1835 */ 1836 get += cc << 1; 1837 if (get >= end) 1838 get -= com_rbuf_size << 1; 1839 cc = 0; 1840 } else { 1841 /* 1842 * Don't schedule any more receive processing 1843 * until the line discipline tells us there's 1844 * space available (through comhwiflow()). 1845 * Leave the rest of the data in the input 1846 * buffer. 1847 */ 1848 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1849 } 1850 break; 1851 } 1852 get += 2; 1853 if (get >= end) 1854 get = sc->sc_rbuf; 1855 cc--; 1856 } 1857 1858 if (cc != scc) { 1859 sc->sc_rbget = get; 1860 s = splserial(); 1861 COM_LOCK(sc); 1862 1863 cc = sc->sc_rbavail += scc - cc; 1864 /* Buffers should be ok again, release possible block. */ 1865 if (cc >= sc->sc_r_lowat) { 1866 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1867 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1868 SET(sc->sc_ier, IER_ERXRDY); 1869 #ifdef COM_PXA2X0 1870 if (sc->sc_type == COM_TYPE_PXA2x0) 1871 SET(sc->sc_ier, IER_ERXTOUT); 1872 #endif 1873 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1874 } 1875 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1876 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1877 com_hwiflow(sc); 1878 } 1879 } 1880 COM_UNLOCK(sc); 1881 splx(s); 1882 } 1883 } 1884 1885 integrate void 1886 com_txsoft(struct com_softc *sc, struct tty *tp) 1887 { 1888 1889 CLR(tp->t_state, TS_BUSY); 1890 if (ISSET(tp->t_state, TS_FLUSH)) 1891 CLR(tp->t_state, TS_FLUSH); 1892 else 1893 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1894 (*tp->t_linesw->l_start)(tp); 1895 } 1896 1897 integrate void 1898 com_stsoft(struct com_softc *sc, struct tty *tp) 1899 { 1900 u_char msr, delta; 1901 int s; 1902 1903 s = splserial(); 1904 COM_LOCK(sc); 1905 msr = sc->sc_msr; 1906 delta = sc->sc_msr_delta; 1907 sc->sc_msr_delta = 0; 1908 COM_UNLOCK(sc); 1909 splx(s); 1910 1911 if (ISSET(delta, sc->sc_msr_dcd)) { 1912 /* 1913 * Inform the tty layer that carrier detect changed. 1914 */ 1915 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1916 } 1917 1918 if (ISSET(delta, sc->sc_msr_cts)) { 1919 /* Block or unblock output according to flow control. */ 1920 if (ISSET(msr, sc->sc_msr_cts)) { 1921 sc->sc_tx_stopped = 0; 1922 (*tp->t_linesw->l_start)(tp); 1923 } else { 1924 sc->sc_tx_stopped = 1; 1925 } 1926 } 1927 1928 #ifdef COM_DEBUG 1929 if (com_debug) 1930 comstatus(sc, "com_stsoft"); 1931 #endif 1932 } 1933 1934 void 1935 comsoft(void *arg) 1936 { 1937 struct com_softc *sc = arg; 1938 struct tty *tp; 1939 1940 if (COM_ISALIVE(sc) == 0) 1941 return; 1942 1943 tp = sc->sc_tty; 1944 1945 if (sc->sc_rx_ready) { 1946 sc->sc_rx_ready = 0; 1947 com_rxsoft(sc, tp); 1948 } 1949 1950 if (sc->sc_st_check) { 1951 sc->sc_st_check = 0; 1952 com_stsoft(sc, tp); 1953 } 1954 1955 if (sc->sc_tx_done) { 1956 sc->sc_tx_done = 0; 1957 com_txsoft(sc, tp); 1958 } 1959 } 1960 1961 int 1962 comintr(void *arg) 1963 { 1964 struct com_softc *sc = arg; 1965 struct com_regs *regsp = &sc->sc_regs; 1966 1967 u_char *put, *end; 1968 u_int cc; 1969 u_char lsr, iir; 1970 1971 if (COM_ISALIVE(sc) == 0) 1972 return (0); 1973 1974 COM_LOCK(sc); 1975 iir = CSR_READ_1(regsp, COM_REG_IIR); 1976 if (ISSET(iir, IIR_NOPEND)) { 1977 COM_UNLOCK(sc); 1978 return (0); 1979 } 1980 1981 end = sc->sc_ebuf; 1982 put = sc->sc_rbput; 1983 cc = sc->sc_rbavail; 1984 1985 again: do { 1986 u_char msr, delta; 1987 1988 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1989 if (ISSET(lsr, LSR_BI)) { 1990 int cn_trapped = 0; 1991 1992 cn_check_magic(sc->sc_tty->t_dev, 1993 CNC_BREAK, com_cnm_state); 1994 if (cn_trapped) 1995 continue; 1996 #if defined(KGDB) && !defined(DDB) 1997 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1998 kgdb_connect(1); 1999 continue; 2000 } 2001 #endif 2002 } 2003 2004 if (ISSET(lsr, LSR_RCV_MASK) && 2005 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2006 while (cc > 0) { 2007 int cn_trapped = 0; 2008 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2009 put[1] = lsr; 2010 cn_check_magic(sc->sc_tty->t_dev, 2011 put[0], com_cnm_state); 2012 if (cn_trapped) 2013 goto next; 2014 put += 2; 2015 if (put >= end) 2016 put = sc->sc_rbuf; 2017 cc--; 2018 next: 2019 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2020 if (!ISSET(lsr, LSR_RCV_MASK)) 2021 break; 2022 } 2023 2024 /* 2025 * Current string of incoming characters ended because 2026 * no more data was available or we ran out of space. 2027 * Schedule a receive event if any data was received. 2028 * If we're out of space, turn off receive interrupts. 2029 */ 2030 sc->sc_rbput = put; 2031 sc->sc_rbavail = cc; 2032 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2033 sc->sc_rx_ready = 1; 2034 2035 /* 2036 * See if we are in danger of overflowing a buffer. If 2037 * so, use hardware flow control to ease the pressure. 2038 */ 2039 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2040 cc < sc->sc_r_hiwat) { 2041 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2042 com_hwiflow(sc); 2043 } 2044 2045 /* 2046 * If we're out of space, disable receive interrupts 2047 * until the queue has drained a bit. 2048 */ 2049 if (!cc) { 2050 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2051 #ifdef COM_PXA2X0 2052 if (sc->sc_type == COM_TYPE_PXA2x0) 2053 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2054 else 2055 #endif 2056 CLR(sc->sc_ier, IER_ERXRDY); 2057 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2058 } 2059 } else { 2060 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2061 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2062 continue; 2063 } 2064 } 2065 2066 msr = CSR_READ_1(regsp, COM_REG_MSR); 2067 delta = msr ^ sc->sc_msr; 2068 sc->sc_msr = msr; 2069 #ifdef __HAVE_TIMECOUNTER 2070 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2071 (delta & MSR_DCD)) { 2072 pps_capture(&sc->sc_pps_state); 2073 pps_event(&sc->sc_pps_state, 2074 (msr & MSR_DCD) ? 2075 PPS_CAPTUREASSERT : 2076 PPS_CAPTURECLEAR); 2077 } 2078 #else /* !__HAVE_TIMECOUNTER */ 2079 /* 2080 * Pulse-per-second (PSS) signals on edge of DCD? 2081 * Process these even if line discipline is ignoring DCD. 2082 */ 2083 if (delta & sc->sc_ppsmask) { 2084 struct timeval tv; 2085 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2086 /* XXX nanotime() */ 2087 microtime(&tv); 2088 TIMEVAL_TO_TIMESPEC(&tv, 2089 &sc->ppsinfo.assert_timestamp); 2090 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2091 timespecadd(&sc->ppsinfo.assert_timestamp, 2092 &sc->ppsparam.assert_offset, 2093 &sc->ppsinfo.assert_timestamp); 2094 } 2095 2096 #ifdef PPS_SYNC 2097 if (pps_kc_hardpps_source == sc && 2098 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2099 hardpps(&tv, tv.tv_usec); 2100 } 2101 #endif 2102 sc->ppsinfo.assert_sequence++; 2103 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2104 2105 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2106 /* XXX nanotime() */ 2107 microtime(&tv); 2108 TIMEVAL_TO_TIMESPEC(&tv, 2109 &sc->ppsinfo.clear_timestamp); 2110 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2111 timespecadd(&sc->ppsinfo.clear_timestamp, 2112 &sc->ppsparam.clear_offset, 2113 &sc->ppsinfo.clear_timestamp); 2114 } 2115 2116 #ifdef PPS_SYNC 2117 if (pps_kc_hardpps_source == sc && 2118 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2119 hardpps(&tv, tv.tv_usec); 2120 } 2121 #endif 2122 sc->ppsinfo.clear_sequence++; 2123 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2124 } 2125 } 2126 #endif /* !__HAVE_TIMECOUNTER */ 2127 2128 /* 2129 * Process normal status changes 2130 */ 2131 if (ISSET(delta, sc->sc_msr_mask)) { 2132 SET(sc->sc_msr_delta, delta); 2133 2134 /* 2135 * Stop output immediately if we lose the output 2136 * flow control signal or carrier detect. 2137 */ 2138 if (ISSET(~msr, sc->sc_msr_mask)) { 2139 sc->sc_tbc = 0; 2140 sc->sc_heldtbc = 0; 2141 #ifdef COM_DEBUG 2142 if (com_debug) 2143 comstatus(sc, "comintr "); 2144 #endif 2145 } 2146 2147 sc->sc_st_check = 1; 2148 } 2149 } while (!ISSET((iir = 2150 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2151 /* 2152 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2153 * by IIR read, so we can't do this way: `process all interrupts, 2154 * then do TX if possble'. 2155 */ 2156 (iir & IIR_IMASK) != IIR_TXRDY); 2157 2158 /* 2159 * Read LSR again, since there may be an interrupt between 2160 * the last LSR read and IIR read above. 2161 */ 2162 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2163 2164 /* 2165 * See if data can be transmitted as well. 2166 * Schedule tx done event if no data left 2167 * and tty was marked busy. 2168 */ 2169 if (ISSET(lsr, LSR_TXRDY)) { 2170 /* 2171 * If we've delayed a parameter change, do it now, and restart 2172 * output. 2173 */ 2174 if (sc->sc_heldchange) { 2175 com_loadchannelregs(sc); 2176 sc->sc_heldchange = 0; 2177 sc->sc_tbc = sc->sc_heldtbc; 2178 sc->sc_heldtbc = 0; 2179 } 2180 2181 /* Output the next chunk of the contiguous buffer, if any. */ 2182 if (sc->sc_tbc > 0) { 2183 u_int n; 2184 2185 n = sc->sc_tbc; 2186 if (n > sc->sc_fifolen) 2187 n = sc->sc_fifolen; 2188 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2189 sc->sc_tbc -= n; 2190 sc->sc_tba += n; 2191 } else { 2192 /* Disable transmit completion interrupts if necessary. */ 2193 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2194 CLR(sc->sc_ier, IER_ETXRDY); 2195 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2196 } 2197 if (sc->sc_tx_busy) { 2198 sc->sc_tx_busy = 0; 2199 sc->sc_tx_done = 1; 2200 } 2201 } 2202 } 2203 2204 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2205 goto again; 2206 2207 COM_UNLOCK(sc); 2208 2209 /* Wake up the poller. */ 2210 softintr_schedule(sc->sc_si); 2211 2212 #if NRND > 0 && defined(RND_COM) 2213 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2214 #endif 2215 2216 return (1); 2217 } 2218 2219 /* 2220 * The following functions are polled getc and putc routines, shared 2221 * by the console and kgdb glue. 2222 * 2223 * The read-ahead code is so that you can detect pending in-band 2224 * cn_magic in polled mode while doing output rather than having to 2225 * wait until the kernel decides it needs input. 2226 */ 2227 2228 #define MAX_READAHEAD 20 2229 static int com_readahead[MAX_READAHEAD]; 2230 static int com_readaheadcount = 0; 2231 2232 int 2233 com_common_getc(dev_t dev, struct com_regs *regsp) 2234 { 2235 int s = splserial(); 2236 u_char stat, c; 2237 2238 /* got a character from reading things earlier */ 2239 if (com_readaheadcount > 0) { 2240 int i; 2241 2242 c = com_readahead[0]; 2243 for (i = 1; i < com_readaheadcount; i++) { 2244 com_readahead[i-1] = com_readahead[i]; 2245 } 2246 com_readaheadcount--; 2247 splx(s); 2248 return (c); 2249 } 2250 2251 /* block until a character becomes available */ 2252 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2253 ; 2254 2255 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2256 stat = CSR_READ_1(regsp, COM_REG_IIR); 2257 { 2258 int cn_trapped = 0; /* unused */ 2259 #ifdef DDB 2260 extern int db_active; 2261 if (!db_active) 2262 #endif 2263 cn_check_magic(dev, c, com_cnm_state); 2264 } 2265 splx(s); 2266 return (c); 2267 } 2268 2269 void 2270 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2271 { 2272 int s = splserial(); 2273 int cin, stat, timo; 2274 2275 if (com_readaheadcount < MAX_READAHEAD 2276 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2277 int cn_trapped = 0; 2278 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2279 stat = CSR_READ_1(regsp, COM_REG_IIR); 2280 cn_check_magic(dev, cin, com_cnm_state); 2281 com_readahead[com_readaheadcount++] = cin; 2282 } 2283 2284 /* wait for any pending transmission to finish */ 2285 timo = 150000; 2286 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2287 continue; 2288 2289 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2290 COM_BARRIER(regsp, BR | BW); 2291 2292 splx(s); 2293 } 2294 2295 /* 2296 * Initialize UART for use as console or KGDB line. 2297 */ 2298 int 2299 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2300 tcflag_t cflag) 2301 { 2302 2303 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2304 ®sp->cr_ioh)) 2305 return (ENOMEM); /* ??? */ 2306 2307 rate = comspeed(rate, frequency, type); 2308 if (type != COM_TYPE_AU1x00) { 2309 /* no EFR on alchemy */ 2310 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2311 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2312 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2313 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2314 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2315 } else { 2316 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2317 } 2318 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2319 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2320 CSR_WRITE_1(regsp, COM_REG_FIFO, 2321 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2322 #ifdef COM_PXA2X0 2323 if (type == COM_TYPE_PXA2x0) 2324 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2325 else 2326 #endif 2327 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2328 2329 return (0); 2330 } 2331 2332 /* 2333 * Following are all routines needed for COM to act as console 2334 */ 2335 struct consdev comcons = { 2336 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2337 NODEV, CN_NORMAL 2338 }; 2339 2340 2341 int 2342 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2343 tcflag_t cflag) 2344 { 2345 int res; 2346 2347 comconsregs = *regsp; 2348 2349 res = cominit(&comconsregs, rate, frequency, type, cflag); 2350 if (res) 2351 return (res); 2352 2353 cn_tab = &comcons; 2354 cn_init_magic(&com_cnm_state); 2355 cn_set_magic("\047\001"); /* default magic is BREAK */ 2356 2357 comconsrate = rate; 2358 comconscflag = cflag; 2359 2360 return (0); 2361 } 2362 2363 int 2364 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2365 int type, tcflag_t cflag) 2366 { 2367 struct com_regs regs; 2368 2369 memset(®s, 0, sizeof regs); 2370 regs.cr_iot = iot; 2371 regs.cr_iobase = iobase; 2372 regs.cr_nports = COM_NPORTS; 2373 #ifdef COM_REGMAP 2374 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2375 #endif 2376 2377 return comcnattach1(®s, rate, frequency, type, cflag); 2378 } 2379 2380 int 2381 comcngetc(dev_t dev) 2382 { 2383 2384 return (com_common_getc(dev, &comconsregs)); 2385 } 2386 2387 /* 2388 * Console kernel output character routine. 2389 */ 2390 void 2391 comcnputc(dev_t dev, int c) 2392 { 2393 2394 com_common_putc(dev, &comconsregs, c); 2395 } 2396 2397 void 2398 comcnpollc(dev_t dev, int on) 2399 { 2400 2401 } 2402 2403 #ifdef KGDB 2404 int 2405 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2406 tcflag_t cflag) 2407 { 2408 int res; 2409 2410 if (regsp->cr_iot == comconsregs.cr_iot && 2411 regsp->cr_iobase == comconsregs.cr_iobase) { 2412 #if !defined(DDB) 2413 return (EBUSY); /* cannot share with console */ 2414 #else 2415 comkgdbregs = *regsp; 2416 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2417 #endif 2418 } else { 2419 comkgdbregs = *regsp; 2420 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2421 if (res) 2422 return (res); 2423 2424 /* 2425 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2426 * expects this to be initialized 2427 */ 2428 cn_init_magic(&com_cnm_state); 2429 cn_set_magic("\047\001"); 2430 } 2431 2432 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2433 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2434 2435 return (0); 2436 } 2437 2438 int 2439 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2440 int frequency, int type, tcflag_t cflag) 2441 { 2442 struct com_regs regs; 2443 2444 regs.cr_iot = iot; 2445 regs.cr_nports = COM_NPORTS; 2446 regs.cr_iobase = iobase; 2447 #ifdef COM_REGMAP 2448 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2449 #endif 2450 2451 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2452 } 2453 2454 /* ARGSUSED */ 2455 int 2456 com_kgdb_getc(void *arg) 2457 { 2458 2459 return (com_common_getc(NODEV, &comkgdbregs)); 2460 } 2461 2462 /* ARGSUSED */ 2463 void 2464 com_kgdb_putc(void *arg, int c) 2465 { 2466 2467 com_common_putc(NODEV, &comkgdbregs, c); 2468 } 2469 #endif /* KGDB */ 2470 2471 /* helper function to identify the com ports used by 2472 console or KGDB (and not yet autoconf attached) */ 2473 int 2474 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2475 { 2476 bus_space_handle_t help; 2477 2478 if (!comconsattached && 2479 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2480 help = comconsregs.cr_ioh; 2481 #ifdef KGDB 2482 else if (!com_kgdb_attached && 2483 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2484 help = comkgdbregs.cr_ioh; 2485 #endif 2486 else 2487 return (0); 2488 2489 if (ioh) 2490 *ioh = help; 2491 return (1); 2492 } 2493 2494 /* 2495 * this routine exists to serve as a shutdown hook for systems that 2496 * have firmware which doesn't interact properly with a com device in 2497 * FIFO mode. 2498 */ 2499 void 2500 com_cleanup(void *arg) 2501 { 2502 struct com_softc *sc = arg; 2503 2504 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2505 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2506 } 2507 2508 void 2509 com_power(int why, void *arg) 2510 { 2511 struct com_softc *sc = arg; 2512 int s; 2513 2514 s = splserial(); 2515 switch (why) { 2516 case PWR_SUSPEND: 2517 case PWR_STANDBY: 2518 /* XXX should we do something to stop the device? */ 2519 break; 2520 case PWR_RESUME: 2521 com_loadchannelregs(sc); 2522 break; 2523 case PWR_SOFTSUSPEND: 2524 case PWR_SOFTSTANDBY: 2525 case PWR_SOFTRESUME: 2526 break; 2527 } 2528 splx(s); 2529 } 2530
Indexes created Mon Oct 20 08:09:54 GMT 2025