com.c revision 1.234.2.8
1 /* $NetBSD: com.c,v 1.234.2.8 2008/02/04 09:23:23 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.234.2.8 2008/02/04 09:23:23 yamt Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 182 int com_common_getc(dev_t, struct com_regs *); 183 void com_common_putc(dev_t, struct com_regs *, int); 184 185 int cominit(struct com_regs *, int, int, int, tcflag_t); 186 187 int comcngetc(dev_t); 188 void comcnputc(dev_t, int); 189 void comcnpollc(dev_t, int); 190 191 #define integrate static inline 192 void comsoft(void *); 193 integrate void com_rxsoft(struct com_softc *, struct tty *); 194 integrate void com_txsoft(struct com_softc *, struct tty *); 195 integrate void com_stsoft(struct com_softc *, struct tty *); 196 integrate void com_schedrx(struct com_softc *); 197 void comdiag(void *); 198 199 extern struct cfdriver com_cd; 200 201 dev_type_open(comopen); 202 dev_type_close(comclose); 203 dev_type_read(comread); 204 dev_type_write(comwrite); 205 dev_type_ioctl(comioctl); 206 dev_type_stop(comstop); 207 dev_type_tty(comtty); 208 dev_type_poll(compoll); 209 210 const struct cdevsw com_cdevsw = { 211 comopen, comclose, comread, comwrite, comioctl, 212 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static struct com_regs comconsregs; 226 static int comconsattached; 227 static int comconsrate; 228 static tcflag_t comconscflag; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 #ifdef COM_REGMAP 242 /* initializer for typical 16550-ish hardware */ 243 #define COM_REG_16550 { \ 244 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 245 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 246 247 const bus_size_t com_std_map[16] = COM_REG_16550; 248 #endif /* COM_REGMAP */ 249 250 #define COMUNIT_MASK 0x7ffff 251 #define COMDIALOUT_MASK 0x80000 252 253 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 254 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 255 256 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 257 device_is_active(&(sc)->sc_dev)) 258 259 #define BR BUS_SPACE_BARRIER_READ 260 #define BW BUS_SPACE_BARRIER_WRITE 261 #define COM_BARRIER(r, f) \ 262 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 263 264 /*ARGSUSED*/ 265 int 266 comspeed(long speed, long frequency, int type) 267 { 268 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 269 270 int x, err; 271 272 #if 0 273 if (speed == 0) 274 return (0); 275 #endif 276 if (speed <= 0) 277 return (-1); 278 x = divrnd(frequency / 16, speed); 279 if (x <= 0) 280 return (-1); 281 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 282 if (err < 0) 283 err = -err; 284 if (err > COM_TOLERANCE) 285 return (-1); 286 return (x); 287 288 #undef divrnd 289 } 290 291 #ifdef COM_DEBUG 292 int com_debug = 0; 293 294 void comstatus(struct com_softc *, const char *); 295 void 296 comstatus(struct com_softc *sc, const char *str) 297 { 298 struct tty *tp = sc->sc_tty; 299 300 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 301 sc->sc_dev.dv_xname, str, 302 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 303 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 304 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 305 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 306 sc->sc_tx_stopped ? '+' : '-'); 307 308 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 309 sc->sc_dev.dv_xname, str, 310 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 312 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 314 sc->sc_rx_flags); 315 } 316 #endif 317 318 int 319 com_probe_subr(struct com_regs *regs) 320 { 321 322 /* force access to id reg */ 323 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 324 CSR_WRITE_1(regs, COM_REG_IIR, 0); 325 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 326 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 327 return (0); 328 329 return (1); 330 } 331 332 int 333 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 334 { 335 struct com_regs regs; 336 337 regs.cr_iot = iot; 338 regs.cr_ioh = ioh; 339 #ifdef COM_REGMAP 340 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 341 #endif 342 343 return com_probe_subr(®s); 344 } 345 346 /* 347 * No locking in this routine; it is only called during attach, 348 * or with the port already locked. 349 */ 350 static void 351 com_enable_debugport(struct com_softc *sc) 352 { 353 354 /* Turn on line break interrupt, set carrier. */ 355 sc->sc_ier = IER_ERXRDY; 356 if (sc->sc_type == COM_TYPE_PXA2x0) 357 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 358 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 359 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 360 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 361 } 362 363 void 364 com_attach_subr(struct com_softc *sc) 365 { 366 struct com_regs *regsp = &sc->sc_regs; 367 struct tty *tp; 368 #ifdef COM_16650 369 u_int8_t lcr; 370 #endif 371 const char *fifo_msg = NULL; 372 373 aprint_naive("\n"); 374 375 callout_init(&sc->sc_diag_callout, 0); 376 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 377 378 /* Disable interrupts before configuring the device. */ 379 if (sc->sc_type == COM_TYPE_PXA2x0) 380 sc->sc_ier = IER_EUART; 381 else 382 sc->sc_ier = 0; 383 384 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 385 386 if (regsp->cr_iot == comconsregs.cr_iot && 387 regsp->cr_iobase == comconsregs.cr_iobase) { 388 comconsattached = 1; 389 390 /* Make sure the console is always "hardwired". */ 391 delay(10000); /* wait for output to finish */ 392 SET(sc->sc_hwflags, COM_HW_CONSOLE); 393 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 394 } 395 396 /* Probe for FIFO */ 397 switch (sc->sc_type) { 398 case COM_TYPE_HAYESP: 399 goto fifodone; 400 401 case COM_TYPE_AU1x00: 402 sc->sc_fifolen = 16; 403 fifo_msg = "Au1X00 UART, working fifo"; 404 SET(sc->sc_hwflags, COM_HW_FIFO); 405 goto fifodelay; 406 } 407 408 sc->sc_fifolen = 1; 409 /* look for a NS 16550AF UART with FIFOs */ 410 CSR_WRITE_1(regsp, COM_REG_FIFO, 411 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 412 delay(100); 413 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 414 == IIR_FIFO_MASK) 415 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 416 == FIFO_TRIGGER_14) { 417 SET(sc->sc_hwflags, COM_HW_FIFO); 418 419 #ifdef COM_16650 420 /* 421 * IIR changes into the EFR if LCR is set to LCR_EERS 422 * on 16650s. We also know IIR != 0 at this point. 423 * Write 0 into the EFR, and read it. If the result 424 * is 0, we have a 16650. 425 * 426 * Older 16650s were broken; the test to detect them 427 * is taken from the Linux driver. Apparently 428 * setting DLAB enable gives access to the EFR on 429 * these chips. 430 */ 431 lcr = CSR_READ_1(regsp, COM_REG_LCR); 432 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 433 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 434 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 435 CSR_WRITE_1(regsp, COM_REG_LCR, 436 lcr | LCR_DLAB); 437 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 438 CLR(sc->sc_hwflags, COM_HW_FIFO); 439 sc->sc_fifolen = 0; 440 } else { 441 SET(sc->sc_hwflags, COM_HW_FLOW); 442 sc->sc_fifolen = 32; 443 } 444 } else 445 #endif 446 sc->sc_fifolen = 16; 447 448 #ifdef COM_16650 449 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 450 if (sc->sc_fifolen == 0) 451 fifo_msg = "st16650, broken fifo"; 452 else if (sc->sc_fifolen == 32) 453 fifo_msg = "st16650a, working fifo"; 454 else 455 #endif 456 fifo_msg = "ns16550a, working fifo"; 457 } else 458 fifo_msg = "ns16550, broken fifo"; 459 else 460 fifo_msg = "ns8250 or ns16450, no fifo"; 461 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 462 fifodelay: 463 /* 464 * Some chips will clear down both Tx and Rx FIFOs when zero is 465 * written to com_fifo. If this chip is the console, writing zero 466 * results in some of the chip/FIFO description being lost, so delay 467 * printing it until now. 468 */ 469 delay(10); 470 aprint_normal(": %s\n", fifo_msg); 471 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 472 sc->sc_fifolen = 1; 473 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 474 } 475 476 fifodone: 477 478 tp = ttymalloc(); 479 tp->t_oproc = comstart; 480 tp->t_param = comparam; 481 tp->t_hwiflow = comhwiflow; 482 483 sc->sc_tty = tp; 484 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 485 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 486 sc->sc_rbavail = com_rbuf_size; 487 if (sc->sc_rbuf == NULL) { 488 aprint_error("%s: unable to allocate ring buffer\n", 489 sc->sc_dev.dv_xname); 490 return; 491 } 492 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 493 494 tty_attach(tp); 495 496 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 497 SET(sc->sc_mcr, MCR_IENABLE); 498 499 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 500 int maj; 501 502 /* locate the major number */ 503 maj = cdevsw_lookup_major(&com_cdevsw); 504 505 tp->t_dev = cn_tab->cn_dev = makedev(maj, 506 device_unit(&sc->sc_dev)); 507 508 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 509 } 510 511 #ifdef KGDB 512 /* 513 * Allow kgdb to "take over" this port. If this is 514 * not the console and is the kgdb device, it has 515 * exclusive use. If it's the console _and_ the 516 * kgdb device, it doesn't. 517 */ 518 if (regsp->cr_iot == comkgdbregs.cr_iot && 519 regsp->cr_iobase == comkgdbregs.cr_iobase) { 520 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 521 com_kgdb_attached = 1; 522 523 SET(sc->sc_hwflags, COM_HW_KGDB); 524 } 525 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 526 } 527 #endif 528 529 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 530 531 #if NRND > 0 && defined(RND_COM) 532 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 533 RND_TYPE_TTY, 0); 534 #endif 535 536 /* if there are no enable/disable functions, assume the device 537 is always enabled */ 538 if (!sc->enable) 539 sc->enabled = 1; 540 541 com_config(sc); 542 543 SET(sc->sc_hwflags, COM_HW_DEV_OK); 544 } 545 546 void 547 com_config(struct com_softc *sc) 548 { 549 struct com_regs *regsp = &sc->sc_regs; 550 551 /* Disable interrupts before configuring the device. */ 552 if (sc->sc_type == COM_TYPE_PXA2x0) 553 sc->sc_ier = IER_EUART; 554 else 555 sc->sc_ier = 0; 556 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 557 (void) CSR_READ_1(regsp, COM_REG_IIR); 558 559 #ifdef COM_HAYESP 560 /* Look for a Hayes ESP board. */ 561 if (sc->sc_type == COM_TYPE_HAYESP) { 562 563 /* Set 16550 compatibility mode */ 564 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 565 HAYESP_SETMODE); 566 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 567 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 568 HAYESP_MODE_SCALE); 569 570 /* Set RTS/CTS flow control */ 571 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 572 HAYESP_SETFLOWTYPE); 573 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 574 HAYESP_FLOW_RTS); 575 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 576 HAYESP_FLOW_CTS); 577 578 /* Set flow control levels */ 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 580 HAYESP_SETRXFLOW); 581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 582 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 584 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 586 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 588 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 589 } 590 #endif 591 592 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 593 com_enable_debugport(sc); 594 } 595 596 int 597 com_detach(struct device *self, int flags) 598 { 599 struct com_softc *sc = (struct com_softc *)self; 600 int maj, mn; 601 602 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 603 return EBUSY; 604 605 /* locate the major number */ 606 maj = cdevsw_lookup_major(&com_cdevsw); 607 608 /* Nuke the vnodes for any open instances. */ 609 mn = device_unit(self); 610 vdevgone(maj, mn, mn, VCHR); 611 612 mn |= COMDIALOUT_MASK; 613 vdevgone(maj, mn, mn, VCHR); 614 615 if (sc->sc_rbuf == NULL) { 616 /* 617 * Ring buffer allocation failed in the com_attach_subr, 618 * only the tty is allocated, and nothing else. 619 */ 620 ttyfree(sc->sc_tty); 621 return 0; 622 } 623 624 /* Free the receive buffer. */ 625 free(sc->sc_rbuf, M_DEVBUF); 626 627 /* Detach and free the tty. */ 628 tty_detach(sc->sc_tty); 629 ttyfree(sc->sc_tty); 630 631 /* Unhook the soft interrupt handler. */ 632 softint_disestablish(sc->sc_si); 633 634 #if NRND > 0 && defined(RND_COM) 635 /* Unhook the entropy source. */ 636 rnd_detach_source(&sc->rnd_source); 637 #endif 638 639 /* Destroy the lock. */ 640 mutex_destroy(&sc->sc_lock); 641 642 return (0); 643 } 644 645 int 646 com_activate(struct device *self, enum devact act) 647 { 648 struct com_softc *sc = (struct com_softc *)self; 649 int rv = 0; 650 651 switch (act) { 652 case DVACT_ACTIVATE: 653 rv = EOPNOTSUPP; 654 break; 655 656 case DVACT_DEACTIVATE: 657 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 658 rv = EBUSY; 659 break; 660 } 661 662 if (sc->disable != NULL && sc->enabled != 0) { 663 (*sc->disable)(sc); 664 sc->enabled = 0; 665 } 666 break; 667 } 668 669 return (rv); 670 } 671 672 void 673 com_shutdown(struct com_softc *sc) 674 { 675 struct tty *tp = sc->sc_tty; 676 677 mutex_spin_enter(&sc->sc_lock); 678 679 /* If we were asserting flow control, then deassert it. */ 680 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 681 com_hwiflow(sc); 682 683 /* Clear any break condition set with TIOCSBRK. */ 684 com_break(sc, 0); 685 686 /* 687 * Hang up if necessary. Wait a bit, so the other side has time to 688 * notice even if we immediately open the port again. 689 * Avoid tsleeping above splhigh(). 690 */ 691 if (ISSET(tp->t_cflag, HUPCL)) { 692 com_modem(sc, 0); 693 mutex_spin_exit(&sc->sc_lock); 694 /* XXX will only timeout */ 695 (void) kpause(ttclos, false, hz, NULL); 696 mutex_spin_enter(&sc->sc_lock); 697 } 698 699 /* Turn off interrupts. */ 700 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 701 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 702 if (sc->sc_type == COM_TYPE_PXA2x0) 703 sc->sc_ier |= IER_ERXTOUT; 704 } else 705 sc->sc_ier = 0; 706 707 if (sc->sc_type == COM_TYPE_PXA2x0) 708 sc->sc_ier |= IER_EUART; 709 710 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 711 712 mutex_spin_exit(&sc->sc_lock); 713 714 if (sc->disable) { 715 #ifdef DIAGNOSTIC 716 if (!sc->enabled) 717 panic("com_shutdown: not enabled?"); 718 #endif 719 (*sc->disable)(sc); 720 sc->enabled = 0; 721 } 722 } 723 724 int 725 comopen(dev_t dev, int flag, int mode, struct lwp *l) 726 { 727 struct com_softc *sc; 728 struct tty *tp; 729 int s; 730 int error; 731 732 sc = device_lookup(&com_cd, COMUNIT(dev)); 733 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 734 sc->sc_rbuf == NULL) 735 return (ENXIO); 736 737 if (!device_is_active(&sc->sc_dev)) 738 return (ENXIO); 739 740 #ifdef KGDB 741 /* 742 * If this is the kgdb port, no other use is permitted. 743 */ 744 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 745 return (EBUSY); 746 #endif 747 748 tp = sc->sc_tty; 749 750 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 751 return (EBUSY); 752 753 s = spltty(); 754 755 /* 756 * Do the following iff this is a first open. 757 */ 758 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 759 struct termios t; 760 761 tp->t_dev = dev; 762 763 764 if (sc->enable) { 765 if ((*sc->enable)(sc)) { 766 splx(s); 767 printf("%s: device enable failed\n", 768 sc->sc_dev.dv_xname); 769 return (EIO); 770 } 771 mutex_spin_enter(&sc->sc_lock); 772 sc->enabled = 1; 773 com_config(sc); 774 } else { 775 mutex_spin_enter(&sc->sc_lock); 776 } 777 778 /* Turn on interrupts. */ 779 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 780 if (sc->sc_type == COM_TYPE_PXA2x0) 781 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 782 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 783 784 /* Fetch the current modem control status, needed later. */ 785 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 786 787 /* Clear PPS capture state on first open. */ 788 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 789 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 790 pps_init(&sc->sc_pps_state); 791 792 mutex_spin_exit(&sc->sc_lock); 793 794 /* 795 * Initialize the termios status to the defaults. Add in the 796 * sticky bits from TIOCSFLAGS. 797 */ 798 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 799 t.c_ospeed = comconsrate; 800 t.c_cflag = comconscflag; 801 } else { 802 t.c_ospeed = TTYDEF_SPEED; 803 t.c_cflag = TTYDEF_CFLAG; 804 } 805 t.c_ispeed = t.c_ospeed; 806 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 807 SET(t.c_cflag, CLOCAL); 808 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 809 SET(t.c_cflag, CRTSCTS); 810 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 811 SET(t.c_cflag, MDMBUF); 812 /* Make sure comparam() will do something. */ 813 tp->t_ospeed = 0; 814 (void) comparam(tp, &t); 815 tp->t_iflag = TTYDEF_IFLAG; 816 tp->t_oflag = TTYDEF_OFLAG; 817 tp->t_lflag = TTYDEF_LFLAG; 818 ttychars(tp); 819 ttsetwater(tp); 820 821 mutex_spin_enter(&sc->sc_lock); 822 823 /* 824 * Turn on DTR. We must always do this, even if carrier is not 825 * present, because otherwise we'd have to use TIOCSDTR 826 * immediately after setting CLOCAL, which applications do not 827 * expect. We always assert DTR while the device is open 828 * unless explicitly requested to deassert it. 829 */ 830 com_modem(sc, 1); 831 832 /* Clear the input ring, and unblock. */ 833 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 834 sc->sc_rbavail = com_rbuf_size; 835 com_iflush(sc); 836 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 837 com_hwiflow(sc); 838 839 #ifdef COM_DEBUG 840 if (com_debug) 841 comstatus(sc, "comopen "); 842 #endif 843 844 mutex_spin_exit(&sc->sc_lock); 845 } 846 847 splx(s); 848 849 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 850 if (error) 851 goto bad; 852 853 error = (*tp->t_linesw->l_open)(dev, tp); 854 if (error) 855 goto bad; 856 857 return (0); 858 859 bad: 860 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 861 /* 862 * We failed to open the device, and nobody else had it opened. 863 * Clean up the state as appropriate. 864 */ 865 com_shutdown(sc); 866 } 867 868 return (error); 869 } 870 871 int 872 comclose(dev_t dev, int flag, int mode, struct lwp *l) 873 { 874 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 875 struct tty *tp = sc->sc_tty; 876 877 /* XXX This is for cons.c. */ 878 if (!ISSET(tp->t_state, TS_ISOPEN)) 879 return (0); 880 881 (*tp->t_linesw->l_close)(tp, flag); 882 ttyclose(tp); 883 884 if (COM_ISALIVE(sc) == 0) 885 return (0); 886 887 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 888 /* 889 * Although we got a last close, the device may still be in 890 * use; e.g. if this was the dialout node, and there are still 891 * processes waiting for carrier on the non-dialout node. 892 */ 893 com_shutdown(sc); 894 } 895 896 return (0); 897 } 898 899 int 900 comread(dev_t dev, struct uio *uio, int flag) 901 { 902 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 903 struct tty *tp = sc->sc_tty; 904 905 if (COM_ISALIVE(sc) == 0) 906 return (EIO); 907 908 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 909 } 910 911 int 912 comwrite(dev_t dev, struct uio *uio, int flag) 913 { 914 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 915 struct tty *tp = sc->sc_tty; 916 917 if (COM_ISALIVE(sc) == 0) 918 return (EIO); 919 920 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 921 } 922 923 int 924 compoll(dev_t dev, int events, struct lwp *l) 925 { 926 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 927 struct tty *tp = sc->sc_tty; 928 929 if (COM_ISALIVE(sc) == 0) 930 return (POLLHUP); 931 932 return ((*tp->t_linesw->l_poll)(tp, events, l)); 933 } 934 935 struct tty * 936 comtty(dev_t dev) 937 { 938 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 939 struct tty *tp = sc->sc_tty; 940 941 return (tp); 942 } 943 944 int 945 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 946 { 947 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 948 struct tty *tp = sc->sc_tty; 949 int error; 950 951 if (COM_ISALIVE(sc) == 0) 952 return (EIO); 953 954 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 955 if (error != EPASSTHROUGH) 956 return (error); 957 958 error = ttioctl(tp, cmd, data, flag, l); 959 if (error != EPASSTHROUGH) 960 return (error); 961 962 error = 0; 963 switch (cmd) { 964 case TIOCSFLAGS: 965 error = kauth_authorize_device_tty(l->l_cred, 966 KAUTH_DEVICE_TTY_PRIVSET, tp); 967 break; 968 default: 969 /* nothing */ 970 break; 971 } 972 if (error) { 973 return error; 974 } 975 976 mutex_spin_enter(&sc->sc_lock); 977 978 switch (cmd) { 979 case TIOCSBRK: 980 com_break(sc, 1); 981 break; 982 983 case TIOCCBRK: 984 com_break(sc, 0); 985 break; 986 987 case TIOCSDTR: 988 com_modem(sc, 1); 989 break; 990 991 case TIOCCDTR: 992 com_modem(sc, 0); 993 break; 994 995 case TIOCGFLAGS: 996 *(int *)data = sc->sc_swflags; 997 break; 998 999 case TIOCSFLAGS: 1000 sc->sc_swflags = *(int *)data; 1001 break; 1002 1003 case TIOCMSET: 1004 case TIOCMBIS: 1005 case TIOCMBIC: 1006 tiocm_to_com(sc, cmd, *(int *)data); 1007 break; 1008 1009 case TIOCMGET: 1010 *(int *)data = com_to_tiocm(sc); 1011 break; 1012 1013 case PPS_IOC_CREATE: 1014 case PPS_IOC_DESTROY: 1015 case PPS_IOC_GETPARAMS: 1016 case PPS_IOC_SETPARAMS: 1017 case PPS_IOC_GETCAP: 1018 case PPS_IOC_FETCH: 1019 #ifdef PPS_SYNC 1020 case PPS_IOC_KCBIND: 1021 #endif 1022 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1023 break; 1024 1025 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1026 #ifndef PPS_TRAILING_EDGE 1027 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1028 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1029 #else 1030 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1031 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1032 #endif 1033 break; 1034 1035 default: 1036 error = EPASSTHROUGH; 1037 break; 1038 } 1039 1040 mutex_spin_exit(&sc->sc_lock); 1041 1042 #ifdef COM_DEBUG 1043 if (com_debug) 1044 comstatus(sc, "comioctl "); 1045 #endif 1046 1047 return (error); 1048 } 1049 1050 integrate void 1051 com_schedrx(struct com_softc *sc) 1052 { 1053 1054 sc->sc_rx_ready = 1; 1055 1056 /* Wake up the poller. */ 1057 softint_schedule(sc->sc_si); 1058 } 1059 1060 void 1061 com_break(struct com_softc *sc, int onoff) 1062 { 1063 1064 if (onoff) 1065 SET(sc->sc_lcr, LCR_SBREAK); 1066 else 1067 CLR(sc->sc_lcr, LCR_SBREAK); 1068 1069 if (!sc->sc_heldchange) { 1070 if (sc->sc_tx_busy) { 1071 sc->sc_heldtbc = sc->sc_tbc; 1072 sc->sc_tbc = 0; 1073 sc->sc_heldchange = 1; 1074 } else 1075 com_loadchannelregs(sc); 1076 } 1077 } 1078 1079 void 1080 com_modem(struct com_softc *sc, int onoff) 1081 { 1082 1083 if (sc->sc_mcr_dtr == 0) 1084 return; 1085 1086 if (onoff) 1087 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1088 else 1089 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1090 1091 if (!sc->sc_heldchange) { 1092 if (sc->sc_tx_busy) { 1093 sc->sc_heldtbc = sc->sc_tbc; 1094 sc->sc_tbc = 0; 1095 sc->sc_heldchange = 1; 1096 } else 1097 com_loadchannelregs(sc); 1098 } 1099 } 1100 1101 void 1102 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1103 { 1104 u_char combits; 1105 1106 combits = 0; 1107 if (ISSET(ttybits, TIOCM_DTR)) 1108 SET(combits, MCR_DTR); 1109 if (ISSET(ttybits, TIOCM_RTS)) 1110 SET(combits, MCR_RTS); 1111 1112 switch (how) { 1113 case TIOCMBIC: 1114 CLR(sc->sc_mcr, combits); 1115 break; 1116 1117 case TIOCMBIS: 1118 SET(sc->sc_mcr, combits); 1119 break; 1120 1121 case TIOCMSET: 1122 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1123 SET(sc->sc_mcr, combits); 1124 break; 1125 } 1126 1127 if (!sc->sc_heldchange) { 1128 if (sc->sc_tx_busy) { 1129 sc->sc_heldtbc = sc->sc_tbc; 1130 sc->sc_tbc = 0; 1131 sc->sc_heldchange = 1; 1132 } else 1133 com_loadchannelregs(sc); 1134 } 1135 } 1136 1137 int 1138 com_to_tiocm(struct com_softc *sc) 1139 { 1140 u_char combits; 1141 int ttybits = 0; 1142 1143 combits = sc->sc_mcr; 1144 if (ISSET(combits, MCR_DTR)) 1145 SET(ttybits, TIOCM_DTR); 1146 if (ISSET(combits, MCR_RTS)) 1147 SET(ttybits, TIOCM_RTS); 1148 1149 combits = sc->sc_msr; 1150 if (ISSET(combits, MSR_DCD)) 1151 SET(ttybits, TIOCM_CD); 1152 if (ISSET(combits, MSR_CTS)) 1153 SET(ttybits, TIOCM_CTS); 1154 if (ISSET(combits, MSR_DSR)) 1155 SET(ttybits, TIOCM_DSR); 1156 if (ISSET(combits, MSR_RI | MSR_TERI)) 1157 SET(ttybits, TIOCM_RI); 1158 1159 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1160 SET(ttybits, TIOCM_LE); 1161 1162 return (ttybits); 1163 } 1164 1165 static u_char 1166 cflag2lcr(tcflag_t cflag) 1167 { 1168 u_char lcr = 0; 1169 1170 switch (ISSET(cflag, CSIZE)) { 1171 case CS5: 1172 SET(lcr, LCR_5BITS); 1173 break; 1174 case CS6: 1175 SET(lcr, LCR_6BITS); 1176 break; 1177 case CS7: 1178 SET(lcr, LCR_7BITS); 1179 break; 1180 case CS8: 1181 SET(lcr, LCR_8BITS); 1182 break; 1183 } 1184 if (ISSET(cflag, PARENB)) { 1185 SET(lcr, LCR_PENAB); 1186 if (!ISSET(cflag, PARODD)) 1187 SET(lcr, LCR_PEVEN); 1188 } 1189 if (ISSET(cflag, CSTOPB)) 1190 SET(lcr, LCR_STOPB); 1191 1192 return (lcr); 1193 } 1194 1195 int 1196 comparam(struct tty *tp, struct termios *t) 1197 { 1198 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1199 int ospeed; 1200 u_char lcr; 1201 1202 if (COM_ISALIVE(sc) == 0) 1203 return (EIO); 1204 1205 #ifdef COM_HAYESP 1206 if (sc->sc_type == COM_TYPE_HAYESP) { 1207 int prescaler, speed; 1208 1209 /* 1210 * Calculate UART clock prescaler. It should be in 1211 * range of 0 .. 3. 1212 */ 1213 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1214 prescaler++, speed /= 2) 1215 if ((ospeed = comspeed(speed, sc->sc_frequency, 1216 sc->sc_type)) > 0) 1217 break; 1218 1219 if (prescaler == 4) 1220 return (EINVAL); 1221 sc->sc_prescaler = prescaler; 1222 } else 1223 #endif 1224 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1225 1226 /* Check requested parameters. */ 1227 if (ospeed < 0) 1228 return (EINVAL); 1229 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1230 return (EINVAL); 1231 1232 /* 1233 * For the console, always force CLOCAL and !HUPCL, so that the port 1234 * is always active. 1235 */ 1236 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1237 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1238 SET(t->c_cflag, CLOCAL); 1239 CLR(t->c_cflag, HUPCL); 1240 } 1241 1242 /* 1243 * If there were no changes, don't do anything. This avoids dropping 1244 * input and improves performance when all we did was frob things like 1245 * VMIN and VTIME. 1246 */ 1247 if (tp->t_ospeed == t->c_ospeed && 1248 tp->t_cflag == t->c_cflag) 1249 return (0); 1250 1251 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1252 1253 mutex_spin_enter(&sc->sc_lock); 1254 1255 sc->sc_lcr = lcr; 1256 1257 /* 1258 * If we're not in a mode that assumes a connection is present, then 1259 * ignore carrier changes. 1260 */ 1261 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1262 sc->sc_msr_dcd = 0; 1263 else 1264 sc->sc_msr_dcd = MSR_DCD; 1265 /* 1266 * Set the flow control pins depending on the current flow control 1267 * mode. 1268 */ 1269 if (ISSET(t->c_cflag, CRTSCTS)) { 1270 sc->sc_mcr_dtr = MCR_DTR; 1271 sc->sc_mcr_rts = MCR_RTS; 1272 sc->sc_msr_cts = MSR_CTS; 1273 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1274 } else if (ISSET(t->c_cflag, MDMBUF)) { 1275 /* 1276 * For DTR/DCD flow control, make sure we don't toggle DTR for 1277 * carrier detection. 1278 */ 1279 sc->sc_mcr_dtr = 0; 1280 sc->sc_mcr_rts = MCR_DTR; 1281 sc->sc_msr_cts = MSR_DCD; 1282 sc->sc_efr = 0; 1283 } else { 1284 /* 1285 * If no flow control, then always set RTS. This will make 1286 * the other side happy if it mistakenly thinks we're doing 1287 * RTS/CTS flow control. 1288 */ 1289 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1290 sc->sc_mcr_rts = 0; 1291 sc->sc_msr_cts = 0; 1292 sc->sc_efr = 0; 1293 if (ISSET(sc->sc_mcr, MCR_DTR)) 1294 SET(sc->sc_mcr, MCR_RTS); 1295 else 1296 CLR(sc->sc_mcr, MCR_RTS); 1297 } 1298 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1299 1300 #if 0 1301 if (ospeed == 0) 1302 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1303 else 1304 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1305 #endif 1306 1307 sc->sc_dlbl = ospeed; 1308 sc->sc_dlbh = ospeed >> 8; 1309 1310 /* 1311 * Set the FIFO threshold based on the receive speed. 1312 * 1313 * * If it's a low speed, it's probably a mouse or some other 1314 * interactive device, so set the threshold low. 1315 * * If it's a high speed, trim the trigger level down to prevent 1316 * overflows. 1317 * * Otherwise set it a bit higher. 1318 */ 1319 if (sc->sc_type == COM_TYPE_HAYESP) 1320 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1321 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1322 sc->sc_fifo = FIFO_ENABLE | 1323 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1324 else 1325 sc->sc_fifo = 0; 1326 1327 /* And copy to tty. */ 1328 tp->t_ispeed = t->c_ospeed; 1329 tp->t_ospeed = t->c_ospeed; 1330 tp->t_cflag = t->c_cflag; 1331 1332 if (!sc->sc_heldchange) { 1333 if (sc->sc_tx_busy) { 1334 sc->sc_heldtbc = sc->sc_tbc; 1335 sc->sc_tbc = 0; 1336 sc->sc_heldchange = 1; 1337 } else 1338 com_loadchannelregs(sc); 1339 } 1340 1341 if (!ISSET(t->c_cflag, CHWFLOW)) { 1342 /* Disable the high water mark. */ 1343 sc->sc_r_hiwat = 0; 1344 sc->sc_r_lowat = 0; 1345 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1346 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1347 com_schedrx(sc); 1348 } 1349 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1350 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1351 com_hwiflow(sc); 1352 } 1353 } else { 1354 sc->sc_r_hiwat = com_rbuf_hiwat; 1355 sc->sc_r_lowat = com_rbuf_lowat; 1356 } 1357 1358 mutex_spin_exit(&sc->sc_lock); 1359 1360 /* 1361 * Update the tty layer's idea of the carrier bit, in case we changed 1362 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1363 * explicit request. 1364 */ 1365 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1366 1367 #ifdef COM_DEBUG 1368 if (com_debug) 1369 comstatus(sc, "comparam "); 1370 #endif 1371 1372 if (!ISSET(t->c_cflag, CHWFLOW)) { 1373 if (sc->sc_tx_stopped) { 1374 sc->sc_tx_stopped = 0; 1375 comstart(tp); 1376 } 1377 } 1378 1379 return (0); 1380 } 1381 1382 void 1383 com_iflush(struct com_softc *sc) 1384 { 1385 struct com_regs *regsp = &sc->sc_regs; 1386 #ifdef DIAGNOSTIC 1387 int reg; 1388 #endif 1389 int timo; 1390 1391 #ifdef DIAGNOSTIC 1392 reg = 0xffff; 1393 #endif 1394 timo = 50000; 1395 /* flush any pending I/O */ 1396 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1397 && --timo) 1398 #ifdef DIAGNOSTIC 1399 reg = 1400 #else 1401 (void) 1402 #endif 1403 CSR_READ_1(regsp, COM_REG_RXDATA); 1404 #ifdef DIAGNOSTIC 1405 if (!timo) 1406 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1407 reg); 1408 #endif 1409 } 1410 1411 void 1412 com_loadchannelregs(struct com_softc *sc) 1413 { 1414 struct com_regs *regsp = &sc->sc_regs; 1415 1416 /* XXXXX necessary? */ 1417 com_iflush(sc); 1418 1419 if (sc->sc_type == COM_TYPE_PXA2x0) 1420 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1421 else 1422 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1423 1424 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1425 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1426 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1427 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1428 } 1429 } 1430 if (sc->sc_type == COM_TYPE_AU1x00) { 1431 /* alchemy has single separate 16-bit clock divisor register */ 1432 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1433 (sc->sc_dlbh << 8)); 1434 } else { 1435 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1436 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1437 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1438 } 1439 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1440 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1441 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1442 #ifdef COM_HAYESP 1443 if (sc->sc_type == COM_TYPE_HAYESP) { 1444 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1445 HAYESP_SETPRESCALER); 1446 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1447 sc->sc_prescaler); 1448 } 1449 #endif 1450 1451 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1452 } 1453 1454 int 1455 comhwiflow(struct tty *tp, int block) 1456 { 1457 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1458 1459 if (COM_ISALIVE(sc) == 0) 1460 return (0); 1461 1462 if (sc->sc_mcr_rts == 0) 1463 return (0); 1464 1465 mutex_spin_enter(&sc->sc_lock); 1466 1467 if (block) { 1468 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1469 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1470 com_hwiflow(sc); 1471 } 1472 } else { 1473 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1474 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1475 com_schedrx(sc); 1476 } 1477 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1478 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1479 com_hwiflow(sc); 1480 } 1481 } 1482 1483 mutex_spin_exit(&sc->sc_lock); 1484 return (1); 1485 } 1486 1487 /* 1488 * (un)block input via hw flowcontrol 1489 */ 1490 void 1491 com_hwiflow(struct com_softc *sc) 1492 { 1493 struct com_regs *regsp= &sc->sc_regs; 1494 1495 if (sc->sc_mcr_rts == 0) 1496 return; 1497 1498 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1499 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1500 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1501 } else { 1502 SET(sc->sc_mcr, sc->sc_mcr_rts); 1503 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1504 } 1505 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1506 } 1507 1508 1509 void 1510 comstart(struct tty *tp) 1511 { 1512 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1513 struct com_regs *regsp = &sc->sc_regs; 1514 int s; 1515 1516 if (COM_ISALIVE(sc) == 0) 1517 return; 1518 1519 s = spltty(); 1520 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1521 goto out; 1522 if (sc->sc_tx_stopped) 1523 goto out; 1524 if (!ttypull(tp)) 1525 goto out; 1526 1527 /* Grab the first contiguous region of buffer space. */ 1528 { 1529 u_char *tba; 1530 int tbc; 1531 1532 tba = tp->t_outq.c_cf; 1533 tbc = ndqb(&tp->t_outq, 0); 1534 1535 mutex_spin_enter(&sc->sc_lock); 1536 1537 sc->sc_tba = tba; 1538 sc->sc_tbc = tbc; 1539 } 1540 1541 SET(tp->t_state, TS_BUSY); 1542 sc->sc_tx_busy = 1; 1543 1544 /* Enable transmit completion interrupts if necessary. */ 1545 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1546 SET(sc->sc_ier, IER_ETXRDY); 1547 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1548 } 1549 1550 /* Output the first chunk of the contiguous buffer. */ 1551 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1552 u_int n; 1553 1554 n = sc->sc_tbc; 1555 if (n > sc->sc_fifolen) 1556 n = sc->sc_fifolen; 1557 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1558 sc->sc_tbc -= n; 1559 sc->sc_tba += n; 1560 } 1561 1562 mutex_spin_exit(&sc->sc_lock); 1563 out: 1564 splx(s); 1565 return; 1566 } 1567 1568 /* 1569 * Stop output on a line. 1570 */ 1571 void 1572 comstop(struct tty *tp, int flag) 1573 { 1574 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1575 1576 mutex_spin_enter(&sc->sc_lock); 1577 if (ISSET(tp->t_state, TS_BUSY)) { 1578 /* Stop transmitting at the next chunk. */ 1579 sc->sc_tbc = 0; 1580 sc->sc_heldtbc = 0; 1581 if (!ISSET(tp->t_state, TS_TTSTOP)) 1582 SET(tp->t_state, TS_FLUSH); 1583 } 1584 mutex_spin_exit(&sc->sc_lock); 1585 } 1586 1587 void 1588 comdiag(void *arg) 1589 { 1590 struct com_softc *sc = arg; 1591 int overflows, floods; 1592 1593 mutex_spin_enter(&sc->sc_lock); 1594 overflows = sc->sc_overflows; 1595 sc->sc_overflows = 0; 1596 floods = sc->sc_floods; 1597 sc->sc_floods = 0; 1598 sc->sc_errors = 0; 1599 mutex_spin_exit(&sc->sc_lock); 1600 1601 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1602 sc->sc_dev.dv_xname, 1603 overflows, overflows == 1 ? "" : "s", 1604 floods, floods == 1 ? "" : "s"); 1605 } 1606 1607 integrate void 1608 com_rxsoft(struct com_softc *sc, struct tty *tp) 1609 { 1610 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1611 u_char *get, *end; 1612 u_int cc, scc; 1613 u_char lsr; 1614 int code; 1615 1616 end = sc->sc_ebuf; 1617 get = sc->sc_rbget; 1618 scc = cc = com_rbuf_size - sc->sc_rbavail; 1619 1620 if (cc == com_rbuf_size) { 1621 sc->sc_floods++; 1622 if (sc->sc_errors++ == 0) 1623 callout_reset(&sc->sc_diag_callout, 60 * hz, 1624 comdiag, sc); 1625 } 1626 1627 /* If not yet open, drop the entire buffer content here */ 1628 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1629 get += cc << 1; 1630 if (get >= end) 1631 get -= com_rbuf_size << 1; 1632 cc = 0; 1633 } 1634 while (cc) { 1635 code = get[0]; 1636 lsr = get[1]; 1637 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1638 if (ISSET(lsr, LSR_OE)) { 1639 sc->sc_overflows++; 1640 if (sc->sc_errors++ == 0) 1641 callout_reset(&sc->sc_diag_callout, 1642 60 * hz, comdiag, sc); 1643 } 1644 if (ISSET(lsr, LSR_BI | LSR_FE)) 1645 SET(code, TTY_FE); 1646 if (ISSET(lsr, LSR_PE)) 1647 SET(code, TTY_PE); 1648 } 1649 if ((*rint)(code, tp) == -1) { 1650 /* 1651 * The line discipline's buffer is out of space. 1652 */ 1653 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1654 /* 1655 * We're either not using flow control, or the 1656 * line discipline didn't tell us to block for 1657 * some reason. Either way, we have no way to 1658 * know when there's more space available, so 1659 * just drop the rest of the data. 1660 */ 1661 get += cc << 1; 1662 if (get >= end) 1663 get -= com_rbuf_size << 1; 1664 cc = 0; 1665 } else { 1666 /* 1667 * Don't schedule any more receive processing 1668 * until the line discipline tells us there's 1669 * space available (through comhwiflow()). 1670 * Leave the rest of the data in the input 1671 * buffer. 1672 */ 1673 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1674 } 1675 break; 1676 } 1677 get += 2; 1678 if (get >= end) 1679 get = sc->sc_rbuf; 1680 cc--; 1681 } 1682 1683 if (cc != scc) { 1684 sc->sc_rbget = get; 1685 mutex_spin_enter(&sc->sc_lock); 1686 1687 cc = sc->sc_rbavail += scc - cc; 1688 /* Buffers should be ok again, release possible block. */ 1689 if (cc >= sc->sc_r_lowat) { 1690 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1691 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1692 SET(sc->sc_ier, IER_ERXRDY); 1693 #ifdef COM_PXA2X0 1694 if (sc->sc_type == COM_TYPE_PXA2x0) 1695 SET(sc->sc_ier, IER_ERXTOUT); 1696 #endif 1697 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1698 } 1699 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1700 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1701 com_hwiflow(sc); 1702 } 1703 } 1704 mutex_spin_exit(&sc->sc_lock); 1705 } 1706 } 1707 1708 integrate void 1709 com_txsoft(struct com_softc *sc, struct tty *tp) 1710 { 1711 1712 CLR(tp->t_state, TS_BUSY); 1713 if (ISSET(tp->t_state, TS_FLUSH)) 1714 CLR(tp->t_state, TS_FLUSH); 1715 else 1716 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1717 (*tp->t_linesw->l_start)(tp); 1718 } 1719 1720 integrate void 1721 com_stsoft(struct com_softc *sc, struct tty *tp) 1722 { 1723 u_char msr, delta; 1724 1725 mutex_spin_enter(&sc->sc_lock); 1726 msr = sc->sc_msr; 1727 delta = sc->sc_msr_delta; 1728 sc->sc_msr_delta = 0; 1729 mutex_spin_exit(&sc->sc_lock); 1730 1731 if (ISSET(delta, sc->sc_msr_dcd)) { 1732 /* 1733 * Inform the tty layer that carrier detect changed. 1734 */ 1735 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1736 } 1737 1738 if (ISSET(delta, sc->sc_msr_cts)) { 1739 /* Block or unblock output according to flow control. */ 1740 if (ISSET(msr, sc->sc_msr_cts)) { 1741 sc->sc_tx_stopped = 0; 1742 (*tp->t_linesw->l_start)(tp); 1743 } else { 1744 sc->sc_tx_stopped = 1; 1745 } 1746 } 1747 1748 #ifdef COM_DEBUG 1749 if (com_debug) 1750 comstatus(sc, "com_stsoft"); 1751 #endif 1752 } 1753 1754 void 1755 comsoft(void *arg) 1756 { 1757 struct com_softc *sc = arg; 1758 struct tty *tp; 1759 1760 if (COM_ISALIVE(sc) == 0) 1761 return; 1762 1763 tp = sc->sc_tty; 1764 1765 if (sc->sc_rx_ready) { 1766 sc->sc_rx_ready = 0; 1767 com_rxsoft(sc, tp); 1768 } 1769 1770 if (sc->sc_st_check) { 1771 sc->sc_st_check = 0; 1772 com_stsoft(sc, tp); 1773 } 1774 1775 if (sc->sc_tx_done) { 1776 sc->sc_tx_done = 0; 1777 com_txsoft(sc, tp); 1778 } 1779 } 1780 1781 int 1782 comintr(void *arg) 1783 { 1784 struct com_softc *sc = arg; 1785 struct com_regs *regsp = &sc->sc_regs; 1786 1787 u_char *put, *end; 1788 u_int cc; 1789 u_char lsr, iir; 1790 1791 if (COM_ISALIVE(sc) == 0) 1792 return (0); 1793 1794 mutex_spin_enter(&sc->sc_lock); 1795 iir = CSR_READ_1(regsp, COM_REG_IIR); 1796 if (ISSET(iir, IIR_NOPEND)) { 1797 mutex_spin_exit(&sc->sc_lock); 1798 return (0); 1799 } 1800 1801 end = sc->sc_ebuf; 1802 put = sc->sc_rbput; 1803 cc = sc->sc_rbavail; 1804 1805 again: do { 1806 u_char msr, delta; 1807 1808 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1809 if (ISSET(lsr, LSR_BI)) { 1810 int cn_trapped = 0; 1811 1812 cn_check_magic(sc->sc_tty->t_dev, 1813 CNC_BREAK, com_cnm_state); 1814 if (cn_trapped) 1815 continue; 1816 #if defined(KGDB) && !defined(DDB) 1817 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1818 kgdb_connect(1); 1819 continue; 1820 } 1821 #endif 1822 } 1823 1824 if (ISSET(lsr, LSR_RCV_MASK) && 1825 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1826 while (cc > 0) { 1827 int cn_trapped = 0; 1828 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1829 put[1] = lsr; 1830 cn_check_magic(sc->sc_tty->t_dev, 1831 put[0], com_cnm_state); 1832 if (cn_trapped) 1833 goto next; 1834 put += 2; 1835 if (put >= end) 1836 put = sc->sc_rbuf; 1837 cc--; 1838 next: 1839 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1840 if (!ISSET(lsr, LSR_RCV_MASK)) 1841 break; 1842 } 1843 1844 /* 1845 * Current string of incoming characters ended because 1846 * no more data was available or we ran out of space. 1847 * Schedule a receive event if any data was received. 1848 * If we're out of space, turn off receive interrupts. 1849 */ 1850 sc->sc_rbput = put; 1851 sc->sc_rbavail = cc; 1852 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1853 sc->sc_rx_ready = 1; 1854 1855 /* 1856 * See if we are in danger of overflowing a buffer. If 1857 * so, use hardware flow control to ease the pressure. 1858 */ 1859 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1860 cc < sc->sc_r_hiwat) { 1861 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1862 com_hwiflow(sc); 1863 } 1864 1865 /* 1866 * If we're out of space, disable receive interrupts 1867 * until the queue has drained a bit. 1868 */ 1869 if (!cc) { 1870 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1871 #ifdef COM_PXA2X0 1872 if (sc->sc_type == COM_TYPE_PXA2x0) 1873 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1874 else 1875 #endif 1876 CLR(sc->sc_ier, IER_ERXRDY); 1877 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1878 } 1879 } else { 1880 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1881 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1882 continue; 1883 } 1884 } 1885 1886 msr = CSR_READ_1(regsp, COM_REG_MSR); 1887 delta = msr ^ sc->sc_msr; 1888 sc->sc_msr = msr; 1889 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1890 (delta & MSR_DCD)) { 1891 pps_capture(&sc->sc_pps_state); 1892 pps_event(&sc->sc_pps_state, 1893 (msr & MSR_DCD) ? 1894 PPS_CAPTUREASSERT : 1895 PPS_CAPTURECLEAR); 1896 } 1897 1898 /* 1899 * Process normal status changes 1900 */ 1901 if (ISSET(delta, sc->sc_msr_mask)) { 1902 SET(sc->sc_msr_delta, delta); 1903 1904 /* 1905 * Stop output immediately if we lose the output 1906 * flow control signal or carrier detect. 1907 */ 1908 if (ISSET(~msr, sc->sc_msr_mask)) { 1909 sc->sc_tbc = 0; 1910 sc->sc_heldtbc = 0; 1911 #ifdef COM_DEBUG 1912 if (com_debug) 1913 comstatus(sc, "comintr "); 1914 #endif 1915 } 1916 1917 sc->sc_st_check = 1; 1918 } 1919 } while (!ISSET((iir = 1920 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 1921 /* 1922 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 1923 * by IIR read, so we can't do this way: `process all interrupts, 1924 * then do TX if possble'. 1925 */ 1926 (iir & IIR_IMASK) != IIR_TXRDY); 1927 1928 /* 1929 * Read LSR again, since there may be an interrupt between 1930 * the last LSR read and IIR read above. 1931 */ 1932 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1933 1934 /* 1935 * See if data can be transmitted as well. 1936 * Schedule tx done event if no data left 1937 * and tty was marked busy. 1938 */ 1939 if (ISSET(lsr, LSR_TXRDY)) { 1940 /* 1941 * If we've delayed a parameter change, do it now, and restart 1942 * output. 1943 */ 1944 if (sc->sc_heldchange) { 1945 com_loadchannelregs(sc); 1946 sc->sc_heldchange = 0; 1947 sc->sc_tbc = sc->sc_heldtbc; 1948 sc->sc_heldtbc = 0; 1949 } 1950 1951 /* Output the next chunk of the contiguous buffer, if any. */ 1952 if (sc->sc_tbc > 0) { 1953 u_int n; 1954 1955 n = sc->sc_tbc; 1956 if (n > sc->sc_fifolen) 1957 n = sc->sc_fifolen; 1958 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1959 sc->sc_tbc -= n; 1960 sc->sc_tba += n; 1961 } else { 1962 /* Disable transmit completion interrupts if necessary. */ 1963 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1964 CLR(sc->sc_ier, IER_ETXRDY); 1965 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1966 } 1967 if (sc->sc_tx_busy) { 1968 sc->sc_tx_busy = 0; 1969 sc->sc_tx_done = 1; 1970 } 1971 } 1972 } 1973 1974 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 1975 goto again; 1976 1977 mutex_spin_exit(&sc->sc_lock); 1978 1979 /* Wake up the poller. */ 1980 softint_schedule(sc->sc_si); 1981 1982 #if NRND > 0 && defined(RND_COM) 1983 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1984 #endif 1985 1986 return (1); 1987 } 1988 1989 /* 1990 * The following functions are polled getc and putc routines, shared 1991 * by the console and kgdb glue. 1992 * 1993 * The read-ahead code is so that you can detect pending in-band 1994 * cn_magic in polled mode while doing output rather than having to 1995 * wait until the kernel decides it needs input. 1996 */ 1997 1998 #define MAX_READAHEAD 20 1999 static int com_readahead[MAX_READAHEAD]; 2000 static int com_readaheadcount = 0; 2001 2002 int 2003 com_common_getc(dev_t dev, struct com_regs *regsp) 2004 { 2005 int s = splserial(); 2006 u_char stat, c; 2007 2008 /* got a character from reading things earlier */ 2009 if (com_readaheadcount > 0) { 2010 int i; 2011 2012 c = com_readahead[0]; 2013 for (i = 1; i < com_readaheadcount; i++) { 2014 com_readahead[i-1] = com_readahead[i]; 2015 } 2016 com_readaheadcount--; 2017 splx(s); 2018 return (c); 2019 } 2020 2021 /* block until a character becomes available */ 2022 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2023 ; 2024 2025 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2026 stat = CSR_READ_1(regsp, COM_REG_IIR); 2027 { 2028 int cn_trapped = 0; /* unused */ 2029 #ifdef DDB 2030 extern int db_active; 2031 if (!db_active) 2032 #endif 2033 cn_check_magic(dev, c, com_cnm_state); 2034 } 2035 splx(s); 2036 return (c); 2037 } 2038 2039 void 2040 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2041 { 2042 int s = splserial(); 2043 int cin, stat, timo; 2044 2045 if (com_readaheadcount < MAX_READAHEAD 2046 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2047 int cn_trapped = 0; 2048 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2049 stat = CSR_READ_1(regsp, COM_REG_IIR); 2050 cn_check_magic(dev, cin, com_cnm_state); 2051 com_readahead[com_readaheadcount++] = cin; 2052 } 2053 2054 /* wait for any pending transmission to finish */ 2055 timo = 150000; 2056 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2057 continue; 2058 2059 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2060 COM_BARRIER(regsp, BR | BW); 2061 2062 splx(s); 2063 } 2064 2065 /* 2066 * Initialize UART for use as console or KGDB line. 2067 */ 2068 int 2069 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2070 tcflag_t cflag) 2071 { 2072 2073 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2074 ®sp->cr_ioh)) 2075 return (ENOMEM); /* ??? */ 2076 2077 rate = comspeed(rate, frequency, type); 2078 if (type != COM_TYPE_AU1x00) { 2079 /* no EFR on alchemy */ 2080 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2081 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2082 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2083 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2084 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2085 } else { 2086 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2087 } 2088 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2089 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2090 CSR_WRITE_1(regsp, COM_REG_FIFO, 2091 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2092 #ifdef COM_PXA2X0 2093 if (type == COM_TYPE_PXA2x0) 2094 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2095 else 2096 #endif 2097 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2098 2099 return (0); 2100 } 2101 2102 /* 2103 * Following are all routines needed for COM to act as console 2104 */ 2105 struct consdev comcons = { 2106 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2107 NODEV, CN_NORMAL 2108 }; 2109 2110 2111 int 2112 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2113 tcflag_t cflag) 2114 { 2115 int res; 2116 2117 comconsregs = *regsp; 2118 2119 res = cominit(&comconsregs, rate, frequency, type, cflag); 2120 if (res) 2121 return (res); 2122 2123 cn_tab = &comcons; 2124 cn_init_magic(&com_cnm_state); 2125 cn_set_magic("\047\001"); /* default magic is BREAK */ 2126 2127 comconsrate = rate; 2128 comconscflag = cflag; 2129 2130 return (0); 2131 } 2132 2133 int 2134 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2135 int type, tcflag_t cflag) 2136 { 2137 struct com_regs regs; 2138 2139 memset(®s, 0, sizeof regs); 2140 regs.cr_iot = iot; 2141 regs.cr_iobase = iobase; 2142 regs.cr_nports = COM_NPORTS; 2143 #ifdef COM_REGMAP 2144 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2145 #endif 2146 2147 return comcnattach1(®s, rate, frequency, type, cflag); 2148 } 2149 2150 int 2151 comcngetc(dev_t dev) 2152 { 2153 2154 return (com_common_getc(dev, &comconsregs)); 2155 } 2156 2157 /* 2158 * Console kernel output character routine. 2159 */ 2160 void 2161 comcnputc(dev_t dev, int c) 2162 { 2163 2164 com_common_putc(dev, &comconsregs, c); 2165 } 2166 2167 void 2168 comcnpollc(dev_t dev, int on) 2169 { 2170 2171 } 2172 2173 #ifdef KGDB 2174 int 2175 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2176 tcflag_t cflag) 2177 { 2178 int res; 2179 2180 if (regsp->cr_iot == comconsregs.cr_iot && 2181 regsp->cr_iobase == comconsregs.cr_iobase) { 2182 #if !defined(DDB) 2183 return (EBUSY); /* cannot share with console */ 2184 #else 2185 comkgdbregs = *regsp; 2186 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2187 #endif 2188 } else { 2189 comkgdbregs = *regsp; 2190 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2191 if (res) 2192 return (res); 2193 2194 /* 2195 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2196 * expects this to be initialized 2197 */ 2198 cn_init_magic(&com_cnm_state); 2199 cn_set_magic("\047\001"); 2200 } 2201 2202 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2203 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2204 2205 return (0); 2206 } 2207 2208 int 2209 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2210 int frequency, int type, tcflag_t cflag) 2211 { 2212 struct com_regs regs; 2213 2214 regs.cr_iot = iot; 2215 regs.cr_nports = COM_NPORTS; 2216 regs.cr_iobase = iobase; 2217 #ifdef COM_REGMAP 2218 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2219 #endif 2220 2221 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2222 } 2223 2224 /* ARGSUSED */ 2225 int 2226 com_kgdb_getc(void *arg) 2227 { 2228 2229 return (com_common_getc(NODEV, &comkgdbregs)); 2230 } 2231 2232 /* ARGSUSED */ 2233 void 2234 com_kgdb_putc(void *arg, int c) 2235 { 2236 2237 com_common_putc(NODEV, &comkgdbregs, c); 2238 } 2239 #endif /* KGDB */ 2240 2241 /* helper function to identify the com ports used by 2242 console or KGDB (and not yet autoconf attached) */ 2243 int 2244 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2245 { 2246 bus_space_handle_t help; 2247 2248 if (!comconsattached && 2249 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2250 help = comconsregs.cr_ioh; 2251 #ifdef KGDB 2252 else if (!com_kgdb_attached && 2253 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2254 help = comkgdbregs.cr_ioh; 2255 #endif 2256 else 2257 return (0); 2258 2259 if (ioh) 2260 *ioh = help; 2261 return (1); 2262 } 2263 2264 /* 2265 * this routine exists to serve as a shutdown hook for systems that 2266 * have firmware which doesn't interact properly with a com device in 2267 * FIFO mode. 2268 */ 2269 void 2270 com_cleanup(void *arg) 2271 { 2272 struct com_softc *sc = arg; 2273 2274 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2275 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2276 } 2277 2278 bool 2279 com_resume(device_t dev) 2280 { 2281 struct com_softc *sc = device_private(dev); 2282 2283 mutex_spin_enter(&sc->sc_lock); 2284 com_loadchannelregs(sc); 2285 mutex_spin_exit(&sc->sc_lock); 2286 2287 return true; 2288 } 2289
Indexes created Mon Oct 20 08:09:54 GMT 2025