com.c revision 1.252
1 /* $NetBSD: com.c,v 1.252 2006/09/24 03:53:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.252 2006/09/24 03:53:08 jmcneill Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 194 void comsoft(void *); 195 #else 196 #ifndef __NO_SOFT_SERIAL_INTERRUPT 197 void comsoft(void); 198 #else 199 void comsoft(void *); 200 static struct callout comsoft_callout = CALLOUT_INITIALIZER; 201 #endif 202 #endif 203 integrate void com_rxsoft(struct com_softc *, struct tty *); 204 integrate void com_txsoft(struct com_softc *, struct tty *); 205 integrate void com_stsoft(struct com_softc *, struct tty *); 206 integrate void com_schedrx(struct com_softc *); 207 void comdiag(void *); 208 209 extern struct cfdriver com_cd; 210 211 dev_type_open(comopen); 212 dev_type_close(comclose); 213 dev_type_read(comread); 214 dev_type_write(comwrite); 215 dev_type_ioctl(comioctl); 216 dev_type_stop(comstop); 217 dev_type_tty(comtty); 218 dev_type_poll(compoll); 219 220 const struct cdevsw com_cdevsw = { 221 comopen, comclose, comread, comwrite, comioctl, 222 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 223 }; 224 225 /* 226 * Make this an option variable one can patch. 227 * But be warned: this must be a power of 2! 228 */ 229 u_int com_rbuf_size = COM_RING_SIZE; 230 231 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 232 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 233 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 234 235 static struct com_regs comconsregs; 236 static int comconsattached; 237 static int comconsrate; 238 static tcflag_t comconscflag; 239 static struct cnm_state com_cnm_state; 240 241 #ifndef __HAVE_TIMECOUNTER 242 static int ppscap = 243 PPS_TSFMT_TSPEC | 244 PPS_CAPTUREASSERT | 245 PPS_CAPTURECLEAR | 246 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 247 #endif /* !__HAVE_TIMECOUNTER */ 248 249 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 250 #ifdef __NO_SOFT_SERIAL_INTERRUPT 251 volatile int com_softintr_scheduled; 252 #endif 253 #endif 254 255 #ifdef KGDB 256 #include <sys/kgdb.h> 257 258 static struct com_regs comkgdbregs; 259 static int com_kgdb_attached; 260 261 int com_kgdb_getc(void *); 262 void com_kgdb_putc(void *, int); 263 #endif /* KGDB */ 264 265 #ifdef COM_REGMAP 266 /* initializer for typical 16550-ish hardware */ 267 #define COM_REG_16550 { \ 268 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 269 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 270 271 const bus_size_t com_std_map[16] = COM_REG_16550; 272 #endif /* COM_REGMAP */ 273 274 #define COMUNIT_MASK 0x7ffff 275 #define COMDIALOUT_MASK 0x80000 276 277 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 278 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 279 280 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 281 device_is_active(&(sc)->sc_dev)) 282 283 #define BR BUS_SPACE_BARRIER_READ 284 #define BW BUS_SPACE_BARRIER_WRITE 285 #define COM_BARRIER(r, f) \ 286 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 287 288 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 289 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 290 291 /*ARGSUSED*/ 292 int 293 comspeed(long speed, long frequency, int type) 294 { 295 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 296 297 int x, err; 298 299 #if 0 300 if (speed == 0) 301 return (0); 302 #endif 303 if (speed <= 0) 304 return (-1); 305 x = divrnd(frequency / 16, speed); 306 if (x <= 0) 307 return (-1); 308 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 309 if (err < 0) 310 err = -err; 311 if (err > COM_TOLERANCE) 312 return (-1); 313 return (x); 314 315 #undef divrnd 316 } 317 318 #ifdef COM_DEBUG 319 int com_debug = 0; 320 321 void comstatus(struct com_softc *, const char *); 322 void 323 comstatus(struct com_softc *sc, const char *str) 324 { 325 struct tty *tp = sc->sc_tty; 326 327 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 328 sc->sc_dev.dv_xname, str, 329 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 331 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 333 sc->sc_tx_stopped ? '+' : '-'); 334 335 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 sc->sc_dev.dv_xname, str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 static void 374 com_enable_debugport(struct com_softc *sc) 375 { 376 int s; 377 378 /* Turn on line break interrupt, set carrier. */ 379 s = splserial(); 380 COM_LOCK(sc); 381 sc->sc_ier = IER_ERXRDY; 382 if (sc->sc_type == COM_TYPE_PXA2x0) 383 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 384 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 385 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 386 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 387 COM_UNLOCK(sc); 388 splx(s); 389 } 390 391 void 392 com_attach_subr(struct com_softc *sc) 393 { 394 struct com_regs *regsp = &sc->sc_regs; 395 struct tty *tp; 396 #ifdef COM_16650 397 u_int8_t lcr; 398 #endif 399 const char *fifo_msg = NULL; 400 401 callout_init(&sc->sc_diag_callout); 402 simple_lock_init(&sc->sc_lock); 403 404 /* Disable interrupts before configuring the device. */ 405 if (sc->sc_type == COM_TYPE_PXA2x0) 406 sc->sc_ier = IER_EUART; 407 else 408 sc->sc_ier = 0; 409 410 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 411 412 if (regsp->cr_iot == comconsregs.cr_iot && 413 regsp->cr_iobase == comconsregs.cr_iobase) { 414 comconsattached = 1; 415 416 /* Make sure the console is always "hardwired". */ 417 delay(10000); /* wait for output to finish */ 418 SET(sc->sc_hwflags, COM_HW_CONSOLE); 419 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 420 } 421 422 /* Probe for FIFO */ 423 switch (sc->sc_type) { 424 case COM_TYPE_HAYESP: 425 goto fifodone; 426 427 case COM_TYPE_AU1x00: 428 sc->sc_fifolen = 16; 429 fifo_msg = "Au1X00 UART, working fifo"; 430 SET(sc->sc_hwflags, COM_HW_FIFO); 431 goto fifodelay; 432 } 433 434 sc->sc_fifolen = 1; 435 /* look for a NS 16550AF UART with FIFOs */ 436 CSR_WRITE_1(regsp, COM_REG_FIFO, 437 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 438 delay(100); 439 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 440 == IIR_FIFO_MASK) 441 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 442 == FIFO_TRIGGER_14) { 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 445 #ifdef COM_16650 446 /* 447 * IIR changes into the EFR if LCR is set to LCR_EERS 448 * on 16650s. We also know IIR != 0 at this point. 449 * Write 0 into the EFR, and read it. If the result 450 * is 0, we have a 16650. 451 * 452 * Older 16650s were broken; the test to detect them 453 * is taken from the Linux driver. Apparently 454 * setting DLAB enable gives access to the EFR on 455 * these chips. 456 */ 457 lcr = CSR_READ_1(regsp, COM_REG_LCR); 458 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 459 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 460 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 461 CSR_WRITE_1(regsp, COM_REG_LCR, 462 lcr | LCR_DLAB); 463 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 464 CLR(sc->sc_hwflags, COM_HW_FIFO); 465 sc->sc_fifolen = 0; 466 } else { 467 SET(sc->sc_hwflags, COM_HW_FLOW); 468 sc->sc_fifolen = 32; 469 } 470 } else 471 #endif 472 sc->sc_fifolen = 16; 473 474 #ifdef COM_16650 475 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 476 if (sc->sc_fifolen == 0) 477 fifo_msg = "st16650, broken fifo"; 478 else if (sc->sc_fifolen == 32) 479 fifo_msg = "st16650a, working fifo"; 480 else 481 #endif 482 fifo_msg = "ns16550a, working fifo"; 483 } else 484 fifo_msg = "ns16550, broken fifo"; 485 else 486 fifo_msg = "ns8250 or ns16450, no fifo"; 487 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 488 fifodelay: 489 /* 490 * Some chips will clear down both Tx and Rx FIFOs when zero is 491 * written to com_fifo. If this chip is the console, writing zero 492 * results in some of the chip/FIFO description being lost, so delay 493 * printing it until now. 494 */ 495 delay(10); 496 aprint_normal(": %s\n", fifo_msg); 497 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 498 sc->sc_fifolen = 1; 499 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 500 } 501 502 fifodone: 503 504 tp = ttymalloc(); 505 tp->t_oproc = comstart; 506 tp->t_param = comparam; 507 tp->t_hwiflow = comhwiflow; 508 509 sc->sc_tty = tp; 510 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 511 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 512 sc->sc_rbavail = com_rbuf_size; 513 if (sc->sc_rbuf == NULL) { 514 aprint_error("%s: unable to allocate ring buffer\n", 515 sc->sc_dev.dv_xname); 516 return; 517 } 518 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 519 520 tty_attach(tp); 521 522 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 523 SET(sc->sc_mcr, MCR_IENABLE); 524 525 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 526 int maj; 527 528 /* locate the major number */ 529 maj = cdevsw_lookup_major(&com_cdevsw); 530 531 tp->t_dev = cn_tab->cn_dev = makedev(maj, 532 device_unit(&sc->sc_dev)); 533 534 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 535 } 536 537 #ifdef KGDB 538 /* 539 * Allow kgdb to "take over" this port. If this is 540 * not the console and is the kgdb device, it has 541 * exclusive use. If it's the console _and_ the 542 * kgdb device, it doesn't. 543 */ 544 if (regsp->cr_iot == comkgdbregs.cr_iot && 545 regsp->cr_iobase == comkgdbregs.cr_iobase) { 546 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 547 com_kgdb_attached = 1; 548 549 SET(sc->sc_hwflags, COM_HW_KGDB); 550 } 551 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 552 } 553 #endif 554 555 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 556 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 557 #endif 558 559 #if NRND > 0 && defined(RND_COM) 560 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 561 RND_TYPE_TTY, 0); 562 #endif 563 564 /* if there are no enable/disable functions, assume the device 565 is always enabled */ 566 if (!sc->enable) 567 sc->enabled = 1; 568 569 com_config(sc); 570 571 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 572 com_power, sc); 573 if (sc->sc_powerhook == NULL) 574 printf("%s: WARNING: unable to establish power hook\n", 575 sc->sc_dev.dv_xname); 576 577 SET(sc->sc_hwflags, COM_HW_DEV_OK); 578 } 579 580 void 581 com_config(struct com_softc *sc) 582 { 583 struct com_regs *regsp = &sc->sc_regs; 584 585 /* Disable interrupts before configuring the device. */ 586 if (sc->sc_type == COM_TYPE_PXA2x0) 587 sc->sc_ier = IER_EUART; 588 else 589 sc->sc_ier = 0; 590 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 591 (void) CSR_READ_1(regsp, COM_REG_IIR); 592 593 #ifdef COM_HAYESP 594 /* Look for a Hayes ESP board. */ 595 if (sc->sc_type == COM_TYPE_HAYESP) { 596 597 /* Set 16550 compatibility mode */ 598 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 599 HAYESP_SETMODE); 600 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 602 HAYESP_MODE_SCALE); 603 604 /* Set RTS/CTS flow control */ 605 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 606 HAYESP_SETFLOWTYPE); 607 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 608 HAYESP_FLOW_RTS); 609 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_FLOW_CTS); 611 612 /* Set flow control levels */ 613 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 614 HAYESP_SETRXFLOW); 615 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 616 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 617 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 618 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 619 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 621 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 622 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 623 } 624 #endif 625 626 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 627 com_enable_debugport(sc); 628 } 629 630 int 631 com_detach(struct device *self, int flags) 632 { 633 struct com_softc *sc = (struct com_softc *)self; 634 int maj, mn; 635 636 /* kill the power hook */ 637 if (sc->sc_powerhook != NULL) 638 powerhook_disestablish(sc->sc_powerhook); 639 640 /* locate the major number */ 641 maj = cdevsw_lookup_major(&com_cdevsw); 642 643 /* Nuke the vnodes for any open instances. */ 644 mn = device_unit(self); 645 vdevgone(maj, mn, mn, VCHR); 646 647 mn |= COMDIALOUT_MASK; 648 vdevgone(maj, mn, mn, VCHR); 649 650 if (sc->sc_rbuf == NULL) { 651 /* 652 * Ring buffer allocation failed in the com_attach_subr, 653 * only the tty is allocated, and nothing else. 654 */ 655 ttyfree(sc->sc_tty); 656 return 0; 657 } 658 659 /* Free the receive buffer. */ 660 free(sc->sc_rbuf, M_DEVBUF); 661 662 /* Detach and free the tty. */ 663 tty_detach(sc->sc_tty); 664 ttyfree(sc->sc_tty); 665 666 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 667 /* Unhook the soft interrupt handler. */ 668 softintr_disestablish(sc->sc_si); 669 #endif 670 671 #if NRND > 0 && defined(RND_COM) 672 /* Unhook the entropy source. */ 673 rnd_detach_source(&sc->rnd_source); 674 #endif 675 676 return (0); 677 } 678 679 int 680 com_activate(struct device *self, enum devact act) 681 { 682 struct com_softc *sc = (struct com_softc *)self; 683 int s, rv = 0; 684 685 s = splserial(); 686 COM_LOCK(sc); 687 switch (act) { 688 case DVACT_ACTIVATE: 689 rv = EOPNOTSUPP; 690 break; 691 692 case DVACT_DEACTIVATE: 693 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 694 rv = EBUSY; 695 break; 696 } 697 698 if (sc->disable != NULL && sc->enabled != 0) { 699 (*sc->disable)(sc); 700 sc->enabled = 0; 701 } 702 break; 703 } 704 705 COM_UNLOCK(sc); 706 splx(s); 707 return (rv); 708 } 709 710 void 711 com_shutdown(struct com_softc *sc) 712 { 713 struct tty *tp = sc->sc_tty; 714 int s; 715 716 s = splserial(); 717 COM_LOCK(sc); 718 719 /* If we were asserting flow control, then deassert it. */ 720 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 721 com_hwiflow(sc); 722 723 /* Clear any break condition set with TIOCSBRK. */ 724 com_break(sc, 0); 725 726 #ifndef __HAVE_TIMECOUNTER 727 /* Turn off PPS capture on last close. */ 728 sc->sc_ppsmask = 0; 729 sc->ppsparam.mode = 0; 730 #endif /* !__HAVE_TIMECOUNTER */ 731 732 /* 733 * Hang up if necessary. Wait a bit, so the other side has time to 734 * notice even if we immediately open the port again. 735 * Avoid tsleeping above splhigh(). 736 */ 737 if (ISSET(tp->t_cflag, HUPCL)) { 738 com_modem(sc, 0); 739 COM_UNLOCK(sc); 740 splx(s); 741 /* XXX tsleep will only timeout */ 742 (void) tsleep(sc, TTIPRI, ttclos, hz); 743 s = splserial(); 744 COM_LOCK(sc); 745 } 746 747 /* Turn off interrupts. */ 748 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 749 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 750 if (sc->sc_type == COM_TYPE_PXA2x0) 751 sc->sc_ier |= IER_ERXTOUT; 752 } else 753 sc->sc_ier = 0; 754 755 if (sc->sc_type == COM_TYPE_PXA2x0) 756 sc->sc_ier |= IER_EUART; 757 758 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 759 760 if (sc->disable) { 761 #ifdef DIAGNOSTIC 762 if (!sc->enabled) 763 panic("com_shutdown: not enabled?"); 764 #endif 765 (*sc->disable)(sc); 766 sc->enabled = 0; 767 } 768 COM_UNLOCK(sc); 769 splx(s); 770 } 771 772 int 773 comopen(dev_t dev, int flag, int mode, struct lwp *l) 774 { 775 struct com_softc *sc; 776 struct tty *tp; 777 int s, s2; 778 int error; 779 780 sc = device_lookup(&com_cd, COMUNIT(dev)); 781 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 782 sc->sc_rbuf == NULL) 783 return (ENXIO); 784 785 if (!device_is_active(&sc->sc_dev)) 786 return (ENXIO); 787 788 #ifdef KGDB 789 /* 790 * If this is the kgdb port, no other use is permitted. 791 */ 792 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 793 return (EBUSY); 794 #endif 795 796 tp = sc->sc_tty; 797 798 if (ISSET(tp->t_state, TS_ISOPEN) && 799 ISSET(tp->t_state, TS_XCLUDE) && 800 kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 801 &l->l_acflag) != 0) 802 return (EBUSY); 803 804 s = spltty(); 805 806 /* 807 * Do the following iff this is a first open. 808 */ 809 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 810 struct termios t; 811 812 tp->t_dev = dev; 813 814 s2 = splserial(); 815 COM_LOCK(sc); 816 817 if (sc->enable) { 818 if ((*sc->enable)(sc)) { 819 COM_UNLOCK(sc); 820 splx(s2); 821 splx(s); 822 printf("%s: device enable failed\n", 823 sc->sc_dev.dv_xname); 824 return (EIO); 825 } 826 sc->enabled = 1; 827 com_config(sc); 828 } 829 830 /* Turn on interrupts. */ 831 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 832 if (sc->sc_type == COM_TYPE_PXA2x0) 833 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 834 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 835 836 /* Fetch the current modem control status, needed later. */ 837 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 838 839 /* Clear PPS capture state on first open. */ 840 #ifdef __HAVE_TIMECOUNTER 841 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 842 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 843 pps_init(&sc->sc_pps_state); 844 #else /* !__HAVE_TIMECOUNTER */ 845 sc->sc_ppsmask = 0; 846 sc->ppsparam.mode = 0; 847 #endif /* !__HAVE_TIMECOUNTER */ 848 849 COM_UNLOCK(sc); 850 splx(s2); 851 852 /* 853 * Initialize the termios status to the defaults. Add in the 854 * sticky bits from TIOCSFLAGS. 855 */ 856 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 857 t.c_ospeed = comconsrate; 858 t.c_cflag = comconscflag; 859 } else { 860 t.c_ospeed = TTYDEF_SPEED; 861 t.c_cflag = TTYDEF_CFLAG; 862 } 863 t.c_ispeed = t.c_ospeed; 864 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 865 SET(t.c_cflag, CLOCAL); 866 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 867 SET(t.c_cflag, CRTSCTS); 868 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 869 SET(t.c_cflag, MDMBUF); 870 /* Make sure comparam() will do something. */ 871 tp->t_ospeed = 0; 872 (void) comparam(tp, &t); 873 tp->t_iflag = TTYDEF_IFLAG; 874 tp->t_oflag = TTYDEF_OFLAG; 875 tp->t_lflag = TTYDEF_LFLAG; 876 ttychars(tp); 877 ttsetwater(tp); 878 879 s2 = splserial(); 880 COM_LOCK(sc); 881 882 /* 883 * Turn on DTR. We must always do this, even if carrier is not 884 * present, because otherwise we'd have to use TIOCSDTR 885 * immediately after setting CLOCAL, which applications do not 886 * expect. We always assert DTR while the device is open 887 * unless explicitly requested to deassert it. 888 */ 889 com_modem(sc, 1); 890 891 /* Clear the input ring, and unblock. */ 892 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 893 sc->sc_rbavail = com_rbuf_size; 894 com_iflush(sc); 895 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 896 com_hwiflow(sc); 897 898 #ifdef COM_DEBUG 899 if (com_debug) 900 comstatus(sc, "comopen "); 901 #endif 902 903 COM_UNLOCK(sc); 904 splx(s2); 905 } 906 907 splx(s); 908 909 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 910 if (error) 911 goto bad; 912 913 error = (*tp->t_linesw->l_open)(dev, tp); 914 if (error) 915 goto bad; 916 917 return (0); 918 919 bad: 920 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 921 /* 922 * We failed to open the device, and nobody else had it opened. 923 * Clean up the state as appropriate. 924 */ 925 com_shutdown(sc); 926 } 927 928 return (error); 929 } 930 931 int 932 comclose(dev_t dev, int flag, int mode, struct lwp *l) 933 { 934 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 935 struct tty *tp = sc->sc_tty; 936 937 /* XXX This is for cons.c. */ 938 if (!ISSET(tp->t_state, TS_ISOPEN)) 939 return (0); 940 941 (*tp->t_linesw->l_close)(tp, flag); 942 ttyclose(tp); 943 944 if (COM_ISALIVE(sc) == 0) 945 return (0); 946 947 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 948 /* 949 * Although we got a last close, the device may still be in 950 * use; e.g. if this was the dialout node, and there are still 951 * processes waiting for carrier on the non-dialout node. 952 */ 953 com_shutdown(sc); 954 } 955 956 return (0); 957 } 958 959 int 960 comread(dev_t dev, struct uio *uio, int flag) 961 { 962 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 963 struct tty *tp = sc->sc_tty; 964 965 if (COM_ISALIVE(sc) == 0) 966 return (EIO); 967 968 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 969 } 970 971 int 972 comwrite(dev_t dev, struct uio *uio, int flag) 973 { 974 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 975 struct tty *tp = sc->sc_tty; 976 977 if (COM_ISALIVE(sc) == 0) 978 return (EIO); 979 980 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 981 } 982 983 int 984 compoll(dev_t dev, int events, struct lwp *l) 985 { 986 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 987 struct tty *tp = sc->sc_tty; 988 989 if (COM_ISALIVE(sc) == 0) 990 return (POLLHUP); 991 992 return ((*tp->t_linesw->l_poll)(tp, events, l)); 993 } 994 995 struct tty * 996 comtty(dev_t dev) 997 { 998 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 999 struct tty *tp = sc->sc_tty; 1000 1001 return (tp); 1002 } 1003 1004 int 1005 comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 1006 { 1007 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 1008 struct tty *tp = sc->sc_tty; 1009 int error; 1010 int s; 1011 1012 if (COM_ISALIVE(sc) == 0) 1013 return (EIO); 1014 1015 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1016 if (error != EPASSTHROUGH) 1017 return (error); 1018 1019 error = ttioctl(tp, cmd, data, flag, l); 1020 if (error != EPASSTHROUGH) 1021 return (error); 1022 1023 error = 0; 1024 switch (cmd) { 1025 case TIOCSFLAGS: 1026 error = kauth_authorize_generic(l->l_cred, 1027 KAUTH_GENERIC_ISSUSER, &l->l_acflag); 1028 break; 1029 default: 1030 /* nothing */ 1031 break; 1032 } 1033 if (error) { 1034 return error; 1035 } 1036 1037 s = splserial(); 1038 COM_LOCK(sc); 1039 1040 switch (cmd) { 1041 case TIOCSBRK: 1042 com_break(sc, 1); 1043 break; 1044 1045 case TIOCCBRK: 1046 com_break(sc, 0); 1047 break; 1048 1049 case TIOCSDTR: 1050 com_modem(sc, 1); 1051 break; 1052 1053 case TIOCCDTR: 1054 com_modem(sc, 0); 1055 break; 1056 1057 case TIOCGFLAGS: 1058 *(int *)data = sc->sc_swflags; 1059 break; 1060 1061 case TIOCSFLAGS: 1062 sc->sc_swflags = *(int *)data; 1063 break; 1064 1065 case TIOCMSET: 1066 case TIOCMBIS: 1067 case TIOCMBIC: 1068 tiocm_to_com(sc, cmd, *(int *)data); 1069 break; 1070 1071 case TIOCMGET: 1072 *(int *)data = com_to_tiocm(sc); 1073 break; 1074 1075 #ifdef __HAVE_TIMECOUNTER 1076 case PPS_IOC_CREATE: 1077 case PPS_IOC_DESTROY: 1078 case PPS_IOC_GETPARAMS: 1079 case PPS_IOC_SETPARAMS: 1080 case PPS_IOC_GETCAP: 1081 case PPS_IOC_FETCH: 1082 #ifdef PPS_SYNC 1083 case PPS_IOC_KCBIND: 1084 #endif 1085 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1086 break; 1087 #else /* !__HAVE_TIMECOUNTER */ 1088 case PPS_IOC_CREATE: 1089 break; 1090 1091 case PPS_IOC_DESTROY: 1092 break; 1093 1094 case PPS_IOC_GETPARAMS: { 1095 pps_params_t *pp; 1096 pp = (pps_params_t *)data; 1097 *pp = sc->ppsparam; 1098 break; 1099 } 1100 1101 case PPS_IOC_SETPARAMS: { 1102 pps_params_t *pp; 1103 int mode; 1104 pp = (pps_params_t *)data; 1105 if (pp->mode & ~ppscap) { 1106 error = EINVAL; 1107 break; 1108 } 1109 sc->ppsparam = *pp; 1110 /* 1111 * Compute msr masks from user-specified timestamp state. 1112 */ 1113 mode = sc->ppsparam.mode; 1114 switch (mode & PPS_CAPTUREBOTH) { 1115 case 0: 1116 sc->sc_ppsmask = 0; 1117 break; 1118 1119 case PPS_CAPTUREASSERT: 1120 sc->sc_ppsmask = MSR_DCD; 1121 sc->sc_ppsassert = MSR_DCD; 1122 sc->sc_ppsclear = -1; 1123 break; 1124 1125 case PPS_CAPTURECLEAR: 1126 sc->sc_ppsmask = MSR_DCD; 1127 sc->sc_ppsassert = -1; 1128 sc->sc_ppsclear = 0; 1129 break; 1130 1131 case PPS_CAPTUREBOTH: 1132 sc->sc_ppsmask = MSR_DCD; 1133 sc->sc_ppsassert = MSR_DCD; 1134 sc->sc_ppsclear = 0; 1135 break; 1136 1137 default: 1138 error = EINVAL; 1139 break; 1140 } 1141 break; 1142 } 1143 1144 case PPS_IOC_GETCAP: 1145 *(int*)data = ppscap; 1146 break; 1147 1148 case PPS_IOC_FETCH: { 1149 pps_info_t *pi; 1150 pi = (pps_info_t *)data; 1151 *pi = sc->ppsinfo; 1152 break; 1153 } 1154 1155 #ifdef PPS_SYNC 1156 case PPS_IOC_KCBIND: { 1157 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1158 1159 if (edge == 0) { 1160 /* 1161 * remove binding for this source; ignore 1162 * the request if this is not the current 1163 * hardpps source 1164 */ 1165 if (pps_kc_hardpps_source == sc) { 1166 pps_kc_hardpps_source = NULL; 1167 pps_kc_hardpps_mode = 0; 1168 } 1169 } else { 1170 /* 1171 * bind hardpps to this source, replacing any 1172 * previously specified source or edges 1173 */ 1174 pps_kc_hardpps_source = sc; 1175 pps_kc_hardpps_mode = edge; 1176 } 1177 break; 1178 } 1179 #endif /* PPS_SYNC */ 1180 #endif /* !__HAVE_TIMECOUNTER */ 1181 1182 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1183 #ifdef __HAVE_TIMECOUNTER 1184 #ifndef PPS_TRAILING_EDGE 1185 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1186 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1187 #else 1188 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1189 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1190 #endif 1191 #else /* !__HAVE_TIMECOUNTER */ 1192 /* 1193 * Some GPS clocks models use the falling rather than 1194 * rising edge as the on-the-second signal. 1195 * The old API has no way to specify PPS polarity. 1196 */ 1197 sc->sc_ppsmask = MSR_DCD; 1198 #ifndef PPS_TRAILING_EDGE 1199 sc->sc_ppsassert = MSR_DCD; 1200 sc->sc_ppsclear = -1; 1201 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1202 &sc->ppsinfo.assert_timestamp); 1203 #else 1204 sc->sc_ppsassert = -1; 1205 sc->sc_ppsclear = 0; 1206 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1207 &sc->ppsinfo.clear_timestamp); 1208 #endif 1209 #endif /* !__HAVE_TIMECOUNTER */ 1210 break; 1211 1212 default: 1213 error = EPASSTHROUGH; 1214 break; 1215 } 1216 1217 COM_UNLOCK(sc); 1218 splx(s); 1219 1220 #ifdef COM_DEBUG 1221 if (com_debug) 1222 comstatus(sc, "comioctl "); 1223 #endif 1224 1225 return (error); 1226 } 1227 1228 integrate void 1229 com_schedrx(struct com_softc *sc) 1230 { 1231 1232 sc->sc_rx_ready = 1; 1233 1234 /* Wake up the poller. */ 1235 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1236 softintr_schedule(sc->sc_si); 1237 #else 1238 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1239 setsoftserial(); 1240 #else 1241 if (!com_softintr_scheduled) { 1242 com_softintr_scheduled = 1; 1243 callout_reset(&comsoft_callout, 1, comsoft, NULL); 1244 } 1245 #endif 1246 #endif 1247 } 1248 1249 void 1250 com_break(struct com_softc *sc, int onoff) 1251 { 1252 1253 if (onoff) 1254 SET(sc->sc_lcr, LCR_SBREAK); 1255 else 1256 CLR(sc->sc_lcr, LCR_SBREAK); 1257 1258 if (!sc->sc_heldchange) { 1259 if (sc->sc_tx_busy) { 1260 sc->sc_heldtbc = sc->sc_tbc; 1261 sc->sc_tbc = 0; 1262 sc->sc_heldchange = 1; 1263 } else 1264 com_loadchannelregs(sc); 1265 } 1266 } 1267 1268 void 1269 com_modem(struct com_softc *sc, int onoff) 1270 { 1271 1272 if (sc->sc_mcr_dtr == 0) 1273 return; 1274 1275 if (onoff) 1276 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1277 else 1278 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1279 1280 if (!sc->sc_heldchange) { 1281 if (sc->sc_tx_busy) { 1282 sc->sc_heldtbc = sc->sc_tbc; 1283 sc->sc_tbc = 0; 1284 sc->sc_heldchange = 1; 1285 } else 1286 com_loadchannelregs(sc); 1287 } 1288 } 1289 1290 void 1291 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1292 { 1293 u_char combits; 1294 1295 combits = 0; 1296 if (ISSET(ttybits, TIOCM_DTR)) 1297 SET(combits, MCR_DTR); 1298 if (ISSET(ttybits, TIOCM_RTS)) 1299 SET(combits, MCR_RTS); 1300 1301 switch (how) { 1302 case TIOCMBIC: 1303 CLR(sc->sc_mcr, combits); 1304 break; 1305 1306 case TIOCMBIS: 1307 SET(sc->sc_mcr, combits); 1308 break; 1309 1310 case TIOCMSET: 1311 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1312 SET(sc->sc_mcr, combits); 1313 break; 1314 } 1315 1316 if (!sc->sc_heldchange) { 1317 if (sc->sc_tx_busy) { 1318 sc->sc_heldtbc = sc->sc_tbc; 1319 sc->sc_tbc = 0; 1320 sc->sc_heldchange = 1; 1321 } else 1322 com_loadchannelregs(sc); 1323 } 1324 } 1325 1326 int 1327 com_to_tiocm(struct com_softc *sc) 1328 { 1329 u_char combits; 1330 int ttybits = 0; 1331 1332 combits = sc->sc_mcr; 1333 if (ISSET(combits, MCR_DTR)) 1334 SET(ttybits, TIOCM_DTR); 1335 if (ISSET(combits, MCR_RTS)) 1336 SET(ttybits, TIOCM_RTS); 1337 1338 combits = sc->sc_msr; 1339 if (ISSET(combits, MSR_DCD)) 1340 SET(ttybits, TIOCM_CD); 1341 if (ISSET(combits, MSR_CTS)) 1342 SET(ttybits, TIOCM_CTS); 1343 if (ISSET(combits, MSR_DSR)) 1344 SET(ttybits, TIOCM_DSR); 1345 if (ISSET(combits, MSR_RI | MSR_TERI)) 1346 SET(ttybits, TIOCM_RI); 1347 1348 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1349 SET(ttybits, TIOCM_LE); 1350 1351 return (ttybits); 1352 } 1353 1354 static u_char 1355 cflag2lcr(tcflag_t cflag) 1356 { 1357 u_char lcr = 0; 1358 1359 switch (ISSET(cflag, CSIZE)) { 1360 case CS5: 1361 SET(lcr, LCR_5BITS); 1362 break; 1363 case CS6: 1364 SET(lcr, LCR_6BITS); 1365 break; 1366 case CS7: 1367 SET(lcr, LCR_7BITS); 1368 break; 1369 case CS8: 1370 SET(lcr, LCR_8BITS); 1371 break; 1372 } 1373 if (ISSET(cflag, PARENB)) { 1374 SET(lcr, LCR_PENAB); 1375 if (!ISSET(cflag, PARODD)) 1376 SET(lcr, LCR_PEVEN); 1377 } 1378 if (ISSET(cflag, CSTOPB)) 1379 SET(lcr, LCR_STOPB); 1380 1381 return (lcr); 1382 } 1383 1384 int 1385 comparam(struct tty *tp, struct termios *t) 1386 { 1387 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1388 int ospeed; 1389 u_char lcr; 1390 int s; 1391 1392 if (COM_ISALIVE(sc) == 0) 1393 return (EIO); 1394 1395 #ifdef COM_HAYESP 1396 if (sc->sc_type == COM_TYPE_HAYESP) { 1397 int prescaler, speed; 1398 1399 /* 1400 * Calculate UART clock prescaler. It should be in 1401 * range of 0 .. 3. 1402 */ 1403 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1404 prescaler++, speed /= 2) 1405 if ((ospeed = comspeed(speed, sc->sc_frequency, 1406 sc->sc_type)) > 0) 1407 break; 1408 1409 if (prescaler == 4) 1410 return (EINVAL); 1411 sc->sc_prescaler = prescaler; 1412 } else 1413 #endif 1414 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1415 1416 /* Check requested parameters. */ 1417 if (ospeed < 0) 1418 return (EINVAL); 1419 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1420 return (EINVAL); 1421 1422 /* 1423 * For the console, always force CLOCAL and !HUPCL, so that the port 1424 * is always active. 1425 */ 1426 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1427 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1428 SET(t->c_cflag, CLOCAL); 1429 CLR(t->c_cflag, HUPCL); 1430 } 1431 1432 /* 1433 * If there were no changes, don't do anything. This avoids dropping 1434 * input and improves performance when all we did was frob things like 1435 * VMIN and VTIME. 1436 */ 1437 if (tp->t_ospeed == t->c_ospeed && 1438 tp->t_cflag == t->c_cflag) 1439 return (0); 1440 1441 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1442 1443 s = splserial(); 1444 COM_LOCK(sc); 1445 1446 sc->sc_lcr = lcr; 1447 1448 /* 1449 * If we're not in a mode that assumes a connection is present, then 1450 * ignore carrier changes. 1451 */ 1452 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1453 sc->sc_msr_dcd = 0; 1454 else 1455 sc->sc_msr_dcd = MSR_DCD; 1456 /* 1457 * Set the flow control pins depending on the current flow control 1458 * mode. 1459 */ 1460 if (ISSET(t->c_cflag, CRTSCTS)) { 1461 sc->sc_mcr_dtr = MCR_DTR; 1462 sc->sc_mcr_rts = MCR_RTS; 1463 sc->sc_msr_cts = MSR_CTS; 1464 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1465 } else if (ISSET(t->c_cflag, MDMBUF)) { 1466 /* 1467 * For DTR/DCD flow control, make sure we don't toggle DTR for 1468 * carrier detection. 1469 */ 1470 sc->sc_mcr_dtr = 0; 1471 sc->sc_mcr_rts = MCR_DTR; 1472 sc->sc_msr_cts = MSR_DCD; 1473 sc->sc_efr = 0; 1474 } else { 1475 /* 1476 * If no flow control, then always set RTS. This will make 1477 * the other side happy if it mistakenly thinks we're doing 1478 * RTS/CTS flow control. 1479 */ 1480 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1481 sc->sc_mcr_rts = 0; 1482 sc->sc_msr_cts = 0; 1483 sc->sc_efr = 0; 1484 if (ISSET(sc->sc_mcr, MCR_DTR)) 1485 SET(sc->sc_mcr, MCR_RTS); 1486 else 1487 CLR(sc->sc_mcr, MCR_RTS); 1488 } 1489 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1490 1491 #if 0 1492 if (ospeed == 0) 1493 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1494 else 1495 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1496 #endif 1497 1498 sc->sc_dlbl = ospeed; 1499 sc->sc_dlbh = ospeed >> 8; 1500 1501 /* 1502 * Set the FIFO threshold based on the receive speed. 1503 * 1504 * * If it's a low speed, it's probably a mouse or some other 1505 * interactive device, so set the threshold low. 1506 * * If it's a high speed, trim the trigger level down to prevent 1507 * overflows. 1508 * * Otherwise set it a bit higher. 1509 */ 1510 if (sc->sc_type == COM_TYPE_HAYESP) 1511 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1512 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1513 sc->sc_fifo = FIFO_ENABLE | 1514 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1515 else 1516 sc->sc_fifo = 0; 1517 1518 /* And copy to tty. */ 1519 tp->t_ispeed = t->c_ospeed; 1520 tp->t_ospeed = t->c_ospeed; 1521 tp->t_cflag = t->c_cflag; 1522 1523 if (!sc->sc_heldchange) { 1524 if (sc->sc_tx_busy) { 1525 sc->sc_heldtbc = sc->sc_tbc; 1526 sc->sc_tbc = 0; 1527 sc->sc_heldchange = 1; 1528 } else 1529 com_loadchannelregs(sc); 1530 } 1531 1532 if (!ISSET(t->c_cflag, CHWFLOW)) { 1533 /* Disable the high water mark. */ 1534 sc->sc_r_hiwat = 0; 1535 sc->sc_r_lowat = 0; 1536 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1537 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1538 com_schedrx(sc); 1539 } 1540 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1541 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1542 com_hwiflow(sc); 1543 } 1544 } else { 1545 sc->sc_r_hiwat = com_rbuf_hiwat; 1546 sc->sc_r_lowat = com_rbuf_lowat; 1547 } 1548 1549 COM_UNLOCK(sc); 1550 splx(s); 1551 1552 /* 1553 * Update the tty layer's idea of the carrier bit, in case we changed 1554 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1555 * explicit request. 1556 */ 1557 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1558 1559 #ifdef COM_DEBUG 1560 if (com_debug) 1561 comstatus(sc, "comparam "); 1562 #endif 1563 1564 if (!ISSET(t->c_cflag, CHWFLOW)) { 1565 if (sc->sc_tx_stopped) { 1566 sc->sc_tx_stopped = 0; 1567 comstart(tp); 1568 } 1569 } 1570 1571 return (0); 1572 } 1573 1574 void 1575 com_iflush(struct com_softc *sc) 1576 { 1577 struct com_regs *regsp = &sc->sc_regs; 1578 #ifdef DIAGNOSTIC 1579 int reg; 1580 #endif 1581 int timo; 1582 1583 #ifdef DIAGNOSTIC 1584 reg = 0xffff; 1585 #endif 1586 timo = 50000; 1587 /* flush any pending I/O */ 1588 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1589 && --timo) 1590 #ifdef DIAGNOSTIC 1591 reg = 1592 #else 1593 (void) 1594 #endif 1595 CSR_READ_1(regsp, COM_REG_RXDATA); 1596 #ifdef DIAGNOSTIC 1597 if (!timo) 1598 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1599 reg); 1600 #endif 1601 } 1602 1603 void 1604 com_loadchannelregs(struct com_softc *sc) 1605 { 1606 struct com_regs *regsp = &sc->sc_regs; 1607 1608 /* XXXXX necessary? */ 1609 com_iflush(sc); 1610 1611 if (sc->sc_type == COM_TYPE_PXA2x0) 1612 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1613 else 1614 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1615 1616 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1617 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1618 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1619 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1620 } 1621 } 1622 if (sc->sc_type == COM_TYPE_AU1x00) { 1623 /* alchemy has single separate 16-bit clock divisor register */ 1624 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1625 (sc->sc_dlbh << 8)); 1626 } else { 1627 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1628 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1629 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1630 } 1631 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1632 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1633 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1634 #ifdef COM_HAYESP 1635 if (sc->sc_type == COM_TYPE_HAYESP) { 1636 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 1637 HAYESP_SETPRESCALER); 1638 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 1639 sc->sc_prescaler); 1640 } 1641 #endif 1642 1643 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1644 } 1645 1646 int 1647 comhwiflow(struct tty *tp, int block) 1648 { 1649 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1650 int s; 1651 1652 if (COM_ISALIVE(sc) == 0) 1653 return (0); 1654 1655 if (sc->sc_mcr_rts == 0) 1656 return (0); 1657 1658 s = splserial(); 1659 COM_LOCK(sc); 1660 1661 if (block) { 1662 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1663 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1664 com_hwiflow(sc); 1665 } 1666 } else { 1667 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1668 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1669 com_schedrx(sc); 1670 } 1671 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1672 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1673 com_hwiflow(sc); 1674 } 1675 } 1676 1677 COM_UNLOCK(sc); 1678 splx(s); 1679 return (1); 1680 } 1681 1682 /* 1683 * (un)block input via hw flowcontrol 1684 */ 1685 void 1686 com_hwiflow(struct com_softc *sc) 1687 { 1688 struct com_regs *regsp= &sc->sc_regs; 1689 1690 if (sc->sc_mcr_rts == 0) 1691 return; 1692 1693 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1694 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1695 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1696 } else { 1697 SET(sc->sc_mcr, sc->sc_mcr_rts); 1698 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1699 } 1700 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1701 } 1702 1703 1704 void 1705 comstart(struct tty *tp) 1706 { 1707 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1708 struct com_regs *regsp = &sc->sc_regs; 1709 int s; 1710 1711 if (COM_ISALIVE(sc) == 0) 1712 return; 1713 1714 s = spltty(); 1715 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1716 goto out; 1717 if (sc->sc_tx_stopped) 1718 goto out; 1719 1720 if (tp->t_outq.c_cc <= tp->t_lowat) { 1721 if (ISSET(tp->t_state, TS_ASLEEP)) { 1722 CLR(tp->t_state, TS_ASLEEP); 1723 wakeup(&tp->t_outq); 1724 } 1725 selwakeup(&tp->t_wsel); 1726 if (tp->t_outq.c_cc == 0) 1727 goto out; 1728 } 1729 1730 /* Grab the first contiguous region of buffer space. */ 1731 { 1732 u_char *tba; 1733 int tbc; 1734 1735 tba = tp->t_outq.c_cf; 1736 tbc = ndqb(&tp->t_outq, 0); 1737 1738 (void)splserial(); 1739 COM_LOCK(sc); 1740 1741 sc->sc_tba = tba; 1742 sc->sc_tbc = tbc; 1743 } 1744 1745 SET(tp->t_state, TS_BUSY); 1746 sc->sc_tx_busy = 1; 1747 1748 /* Enable transmit completion interrupts if necessary. */ 1749 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1750 SET(sc->sc_ier, IER_ETXRDY); 1751 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1752 } 1753 1754 /* Output the first chunk of the contiguous buffer. */ 1755 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1756 u_int n; 1757 1758 n = sc->sc_tbc; 1759 if (n > sc->sc_fifolen) 1760 n = sc->sc_fifolen; 1761 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1762 sc->sc_tbc -= n; 1763 sc->sc_tba += n; 1764 } 1765 1766 COM_UNLOCK(sc); 1767 out: 1768 splx(s); 1769 return; 1770 } 1771 1772 /* 1773 * Stop output on a line. 1774 */ 1775 void 1776 comstop(struct tty *tp, int flag) 1777 { 1778 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1779 int s; 1780 1781 s = splserial(); 1782 COM_LOCK(sc); 1783 if (ISSET(tp->t_state, TS_BUSY)) { 1784 /* Stop transmitting at the next chunk. */ 1785 sc->sc_tbc = 0; 1786 sc->sc_heldtbc = 0; 1787 if (!ISSET(tp->t_state, TS_TTSTOP)) 1788 SET(tp->t_state, TS_FLUSH); 1789 } 1790 COM_UNLOCK(sc); 1791 splx(s); 1792 } 1793 1794 void 1795 comdiag(void *arg) 1796 { 1797 struct com_softc *sc = arg; 1798 int overflows, floods; 1799 int s; 1800 1801 s = splserial(); 1802 COM_LOCK(sc); 1803 overflows = sc->sc_overflows; 1804 sc->sc_overflows = 0; 1805 floods = sc->sc_floods; 1806 sc->sc_floods = 0; 1807 sc->sc_errors = 0; 1808 COM_UNLOCK(sc); 1809 splx(s); 1810 1811 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1812 sc->sc_dev.dv_xname, 1813 overflows, overflows == 1 ? "" : "s", 1814 floods, floods == 1 ? "" : "s"); 1815 } 1816 1817 integrate void 1818 com_rxsoft(struct com_softc *sc, struct tty *tp) 1819 { 1820 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1821 u_char *get, *end; 1822 u_int cc, scc; 1823 u_char lsr; 1824 int code; 1825 int s; 1826 1827 end = sc->sc_ebuf; 1828 get = sc->sc_rbget; 1829 scc = cc = com_rbuf_size - sc->sc_rbavail; 1830 1831 if (cc == com_rbuf_size) { 1832 sc->sc_floods++; 1833 if (sc->sc_errors++ == 0) 1834 callout_reset(&sc->sc_diag_callout, 60 * hz, 1835 comdiag, sc); 1836 } 1837 1838 /* If not yet open, drop the entire buffer content here */ 1839 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1840 get += cc << 1; 1841 if (get >= end) 1842 get -= com_rbuf_size << 1; 1843 cc = 0; 1844 } 1845 while (cc) { 1846 code = get[0]; 1847 lsr = get[1]; 1848 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1849 if (ISSET(lsr, LSR_OE)) { 1850 sc->sc_overflows++; 1851 if (sc->sc_errors++ == 0) 1852 callout_reset(&sc->sc_diag_callout, 1853 60 * hz, comdiag, sc); 1854 } 1855 if (ISSET(lsr, LSR_BI | LSR_FE)) 1856 SET(code, TTY_FE); 1857 if (ISSET(lsr, LSR_PE)) 1858 SET(code, TTY_PE); 1859 } 1860 if ((*rint)(code, tp) == -1) { 1861 /* 1862 * The line discipline's buffer is out of space. 1863 */ 1864 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1865 /* 1866 * We're either not using flow control, or the 1867 * line discipline didn't tell us to block for 1868 * some reason. Either way, we have no way to 1869 * know when there's more space available, so 1870 * just drop the rest of the data. 1871 */ 1872 get += cc << 1; 1873 if (get >= end) 1874 get -= com_rbuf_size << 1; 1875 cc = 0; 1876 } else { 1877 /* 1878 * Don't schedule any more receive processing 1879 * until the line discipline tells us there's 1880 * space available (through comhwiflow()). 1881 * Leave the rest of the data in the input 1882 * buffer. 1883 */ 1884 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1885 } 1886 break; 1887 } 1888 get += 2; 1889 if (get >= end) 1890 get = sc->sc_rbuf; 1891 cc--; 1892 } 1893 1894 if (cc != scc) { 1895 sc->sc_rbget = get; 1896 s = splserial(); 1897 COM_LOCK(sc); 1898 1899 cc = sc->sc_rbavail += scc - cc; 1900 /* Buffers should be ok again, release possible block. */ 1901 if (cc >= sc->sc_r_lowat) { 1902 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1903 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1904 SET(sc->sc_ier, IER_ERXRDY); 1905 #ifdef COM_PXA2X0 1906 if (sc->sc_type == COM_TYPE_PXA2x0) 1907 SET(sc->sc_ier, IER_ERXTOUT); 1908 #endif 1909 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1910 } 1911 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1912 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1913 com_hwiflow(sc); 1914 } 1915 } 1916 COM_UNLOCK(sc); 1917 splx(s); 1918 } 1919 } 1920 1921 integrate void 1922 com_txsoft(struct com_softc *sc, struct tty *tp) 1923 { 1924 1925 CLR(tp->t_state, TS_BUSY); 1926 if (ISSET(tp->t_state, TS_FLUSH)) 1927 CLR(tp->t_state, TS_FLUSH); 1928 else 1929 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1930 (*tp->t_linesw->l_start)(tp); 1931 } 1932 1933 integrate void 1934 com_stsoft(struct com_softc *sc, struct tty *tp) 1935 { 1936 u_char msr, delta; 1937 int s; 1938 1939 s = splserial(); 1940 COM_LOCK(sc); 1941 msr = sc->sc_msr; 1942 delta = sc->sc_msr_delta; 1943 sc->sc_msr_delta = 0; 1944 COM_UNLOCK(sc); 1945 splx(s); 1946 1947 if (ISSET(delta, sc->sc_msr_dcd)) { 1948 /* 1949 * Inform the tty layer that carrier detect changed. 1950 */ 1951 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1952 } 1953 1954 if (ISSET(delta, sc->sc_msr_cts)) { 1955 /* Block or unblock output according to flow control. */ 1956 if (ISSET(msr, sc->sc_msr_cts)) { 1957 sc->sc_tx_stopped = 0; 1958 (*tp->t_linesw->l_start)(tp); 1959 } else { 1960 sc->sc_tx_stopped = 1; 1961 } 1962 } 1963 1964 #ifdef COM_DEBUG 1965 if (com_debug) 1966 comstatus(sc, "com_stsoft"); 1967 #endif 1968 } 1969 1970 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1971 void 1972 comsoft(void *arg) 1973 { 1974 struct com_softc *sc = arg; 1975 struct tty *tp; 1976 1977 if (COM_ISALIVE(sc) == 0) 1978 return; 1979 1980 { 1981 #else 1982 void 1983 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1984 comsoft(void) 1985 #else 1986 comsoft(void *arg) 1987 #endif 1988 { 1989 struct com_softc *sc; 1990 struct tty *tp; 1991 int unit; 1992 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1993 int s; 1994 1995 s = splsoftserial(); 1996 com_softintr_scheduled = 0; 1997 #endif 1998 1999 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 2000 sc = device_lookup(&com_cd, unit); 2001 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK)) 2002 continue; 2003 2004 if (COM_ISALIVE(sc) == 0) 2005 continue; 2006 2007 tp = sc->sc_tty; 2008 if (tp == NULL) 2009 continue; 2010 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 2011 continue; 2012 #endif 2013 tp = sc->sc_tty; 2014 2015 if (sc->sc_rx_ready) { 2016 sc->sc_rx_ready = 0; 2017 com_rxsoft(sc, tp); 2018 } 2019 2020 if (sc->sc_st_check) { 2021 sc->sc_st_check = 0; 2022 com_stsoft(sc, tp); 2023 } 2024 2025 if (sc->sc_tx_done) { 2026 sc->sc_tx_done = 0; 2027 com_txsoft(sc, tp); 2028 } 2029 } 2030 2031 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 2032 #ifdef __NO_SOFT_SERIAL_INTERRUPT 2033 splx(s); 2034 #endif 2035 #endif 2036 } 2037 2038 #ifdef __ALIGN_BRACKET_LEVEL_FOR_CTAGS 2039 /* there has got to be a better way to do comsoft() */ 2040 }} 2041 #endif 2042 2043 int 2044 comintr(void *arg) 2045 { 2046 struct com_softc *sc = arg; 2047 struct com_regs *regsp = &sc->sc_regs; 2048 2049 u_char *put, *end; 2050 u_int cc; 2051 u_char lsr, iir; 2052 2053 if (COM_ISALIVE(sc) == 0) 2054 return (0); 2055 2056 COM_LOCK(sc); 2057 iir = CSR_READ_1(regsp, COM_REG_IIR); 2058 if (ISSET(iir, IIR_NOPEND)) { 2059 COM_UNLOCK(sc); 2060 return (0); 2061 } 2062 2063 end = sc->sc_ebuf; 2064 put = sc->sc_rbput; 2065 cc = sc->sc_rbavail; 2066 2067 again: do { 2068 u_char msr, delta; 2069 2070 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2071 if (ISSET(lsr, LSR_BI)) { 2072 int cn_trapped = 0; 2073 2074 cn_check_magic(sc->sc_tty->t_dev, 2075 CNC_BREAK, com_cnm_state); 2076 if (cn_trapped) 2077 continue; 2078 #if defined(KGDB) && !defined(DDB) 2079 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2080 kgdb_connect(1); 2081 continue; 2082 } 2083 #endif 2084 } 2085 2086 if (ISSET(lsr, LSR_RCV_MASK) && 2087 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2088 while (cc > 0) { 2089 int cn_trapped = 0; 2090 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2091 put[1] = lsr; 2092 cn_check_magic(sc->sc_tty->t_dev, 2093 put[0], com_cnm_state); 2094 if (cn_trapped) 2095 goto next; 2096 put += 2; 2097 if (put >= end) 2098 put = sc->sc_rbuf; 2099 cc--; 2100 next: 2101 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2102 if (!ISSET(lsr, LSR_RCV_MASK)) 2103 break; 2104 } 2105 2106 /* 2107 * Current string of incoming characters ended because 2108 * no more data was available or we ran out of space. 2109 * Schedule a receive event if any data was received. 2110 * If we're out of space, turn off receive interrupts. 2111 */ 2112 sc->sc_rbput = put; 2113 sc->sc_rbavail = cc; 2114 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2115 sc->sc_rx_ready = 1; 2116 2117 /* 2118 * See if we are in danger of overflowing a buffer. If 2119 * so, use hardware flow control to ease the pressure. 2120 */ 2121 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2122 cc < sc->sc_r_hiwat) { 2123 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2124 com_hwiflow(sc); 2125 } 2126 2127 /* 2128 * If we're out of space, disable receive interrupts 2129 * until the queue has drained a bit. 2130 */ 2131 if (!cc) { 2132 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2133 #ifdef COM_PXA2X0 2134 if (sc->sc_type == COM_TYPE_PXA2x0) 2135 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2136 else 2137 #endif 2138 CLR(sc->sc_ier, IER_ERXRDY); 2139 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2140 } 2141 } else { 2142 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2143 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2144 continue; 2145 } 2146 } 2147 2148 msr = CSR_READ_1(regsp, COM_REG_MSR); 2149 delta = msr ^ sc->sc_msr; 2150 sc->sc_msr = msr; 2151 #ifdef __HAVE_TIMECOUNTER 2152 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2153 (delta & MSR_DCD)) { 2154 pps_capture(&sc->sc_pps_state); 2155 pps_event(&sc->sc_pps_state, 2156 (msr & MSR_DCD) ? 2157 PPS_CAPTUREASSERT : 2158 PPS_CAPTURECLEAR); 2159 } 2160 #else /* !__HAVE_TIMECOUNTER */ 2161 /* 2162 * Pulse-per-second (PSS) signals on edge of DCD? 2163 * Process these even if line discipline is ignoring DCD. 2164 */ 2165 if (delta & sc->sc_ppsmask) { 2166 struct timeval tv; 2167 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2168 /* XXX nanotime() */ 2169 microtime(&tv); 2170 TIMEVAL_TO_TIMESPEC(&tv, 2171 &sc->ppsinfo.assert_timestamp); 2172 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2173 timespecadd(&sc->ppsinfo.assert_timestamp, 2174 &sc->ppsparam.assert_offset, 2175 &sc->ppsinfo.assert_timestamp); 2176 } 2177 2178 #ifdef PPS_SYNC 2179 if (pps_kc_hardpps_source == sc && 2180 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2181 hardpps(&tv, tv.tv_usec); 2182 } 2183 #endif 2184 sc->ppsinfo.assert_sequence++; 2185 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2186 2187 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2188 /* XXX nanotime() */ 2189 microtime(&tv); 2190 TIMEVAL_TO_TIMESPEC(&tv, 2191 &sc->ppsinfo.clear_timestamp); 2192 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2193 timespecadd(&sc->ppsinfo.clear_timestamp, 2194 &sc->ppsparam.clear_offset, 2195 &sc->ppsinfo.clear_timestamp); 2196 } 2197 2198 #ifdef PPS_SYNC 2199 if (pps_kc_hardpps_source == sc && 2200 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2201 hardpps(&tv, tv.tv_usec); 2202 } 2203 #endif 2204 sc->ppsinfo.clear_sequence++; 2205 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2206 } 2207 } 2208 #endif /* !__HAVE_TIMECOUNTER */ 2209 2210 /* 2211 * Process normal status changes 2212 */ 2213 if (ISSET(delta, sc->sc_msr_mask)) { 2214 SET(sc->sc_msr_delta, delta); 2215 2216 /* 2217 * Stop output immediately if we lose the output 2218 * flow control signal or carrier detect. 2219 */ 2220 if (ISSET(~msr, sc->sc_msr_mask)) { 2221 sc->sc_tbc = 0; 2222 sc->sc_heldtbc = 0; 2223 #ifdef COM_DEBUG 2224 if (com_debug) 2225 comstatus(sc, "comintr "); 2226 #endif 2227 } 2228 2229 sc->sc_st_check = 1; 2230 } 2231 } while (!ISSET((iir = 2232 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2233 /* 2234 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2235 * by IIR read, so we can't do this way: `process all interrupts, 2236 * then do TX if possble'. 2237 */ 2238 (iir & IIR_IMASK) != IIR_TXRDY); 2239 2240 /* 2241 * Read LSR again, since there may be an interrupt between 2242 * the last LSR read and IIR read above. 2243 */ 2244 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2245 2246 /* 2247 * See if data can be transmitted as well. 2248 * Schedule tx done event if no data left 2249 * and tty was marked busy. 2250 */ 2251 if (ISSET(lsr, LSR_TXRDY)) { 2252 /* 2253 * If we've delayed a parameter change, do it now, and restart 2254 * output. 2255 */ 2256 if (sc->sc_heldchange) { 2257 com_loadchannelregs(sc); 2258 sc->sc_heldchange = 0; 2259 sc->sc_tbc = sc->sc_heldtbc; 2260 sc->sc_heldtbc = 0; 2261 } 2262 2263 /* Output the next chunk of the contiguous buffer, if any. */ 2264 if (sc->sc_tbc > 0) { 2265 u_int n; 2266 2267 n = sc->sc_tbc; 2268 if (n > sc->sc_fifolen) 2269 n = sc->sc_fifolen; 2270 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2271 sc->sc_tbc -= n; 2272 sc->sc_tba += n; 2273 } else { 2274 /* Disable transmit completion interrupts if necessary. */ 2275 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2276 CLR(sc->sc_ier, IER_ETXRDY); 2277 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2278 } 2279 if (sc->sc_tx_busy) { 2280 sc->sc_tx_busy = 0; 2281 sc->sc_tx_done = 1; 2282 } 2283 } 2284 } 2285 2286 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2287 goto again; 2288 2289 COM_UNLOCK(sc); 2290 2291 /* Wake up the poller. */ 2292 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2293 softintr_schedule(sc->sc_si); 2294 #else 2295 #ifndef __NO_SOFT_SERIAL_INTERRUPT 2296 setsoftserial(); 2297 #else 2298 if (!com_softintr_scheduled) { 2299 com_softintr_scheduled = 1; 2300 callout_reset(&comsoft_callout, 1, comsoft, NULL); 2301 } 2302 #endif 2303 #endif 2304 2305 #if NRND > 0 && defined(RND_COM) 2306 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2307 #endif 2308 2309 return (1); 2310 } 2311 2312 /* 2313 * The following functions are polled getc and putc routines, shared 2314 * by the console and kgdb glue. 2315 * 2316 * The read-ahead code is so that you can detect pending in-band 2317 * cn_magic in polled mode while doing output rather than having to 2318 * wait until the kernel decides it needs input. 2319 */ 2320 2321 #define MAX_READAHEAD 20 2322 static int com_readahead[MAX_READAHEAD]; 2323 static int com_readaheadcount = 0; 2324 2325 int 2326 com_common_getc(dev_t dev, struct com_regs *regsp) 2327 { 2328 int s = splserial(); 2329 u_char stat, c; 2330 2331 /* got a character from reading things earlier */ 2332 if (com_readaheadcount > 0) { 2333 int i; 2334 2335 c = com_readahead[0]; 2336 for (i = 1; i < com_readaheadcount; i++) { 2337 com_readahead[i-1] = com_readahead[i]; 2338 } 2339 com_readaheadcount--; 2340 splx(s); 2341 return (c); 2342 } 2343 2344 /* block until a character becomes available */ 2345 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2346 ; 2347 2348 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2349 stat = CSR_READ_1(regsp, COM_REG_IIR); 2350 { 2351 int cn_trapped = 0; /* unused */ 2352 #ifdef DDB 2353 extern int db_active; 2354 if (!db_active) 2355 #endif 2356 cn_check_magic(dev, c, com_cnm_state); 2357 } 2358 splx(s); 2359 return (c); 2360 } 2361 2362 void 2363 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2364 { 2365 int s = splserial(); 2366 int cin, stat, timo; 2367 2368 if (com_readaheadcount < MAX_READAHEAD 2369 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2370 int cn_trapped = 0; 2371 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2372 stat = CSR_READ_1(regsp, COM_REG_IIR); 2373 cn_check_magic(dev, cin, com_cnm_state); 2374 com_readahead[com_readaheadcount++] = cin; 2375 } 2376 2377 /* wait for any pending transmission to finish */ 2378 timo = 150000; 2379 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2380 continue; 2381 2382 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2383 COM_BARRIER(regsp, BR | BW); 2384 2385 splx(s); 2386 } 2387 2388 /* 2389 * Initialize UART for use as console or KGDB line. 2390 */ 2391 int 2392 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2393 tcflag_t cflag) 2394 { 2395 2396 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2397 ®sp->cr_ioh)) 2398 return (ENOMEM); /* ??? */ 2399 2400 rate = comspeed(rate, frequency, type); 2401 if (type != COM_TYPE_AU1x00) { 2402 /* no EFR on alchemy */ 2403 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2404 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2405 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2406 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2407 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2408 } else { 2409 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2410 } 2411 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2412 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2413 CSR_WRITE_1(regsp, COM_REG_FIFO, 2414 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2415 #ifdef COM_PXA2X0 2416 if (type == COM_TYPE_PXA2x0) 2417 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2418 else 2419 #endif 2420 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2421 2422 return (0); 2423 } 2424 2425 /* 2426 * Following are all routines needed for COM to act as console 2427 */ 2428 struct consdev comcons = { 2429 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2430 NODEV, CN_NORMAL 2431 }; 2432 2433 2434 int 2435 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2436 tcflag_t cflag) 2437 { 2438 int res; 2439 2440 comconsregs = *regsp; 2441 2442 res = cominit(&comconsregs, rate, frequency, type, cflag); 2443 if (res) 2444 return (res); 2445 2446 cn_tab = &comcons; 2447 cn_init_magic(&com_cnm_state); 2448 cn_set_magic("\047\001"); /* default magic is BREAK */ 2449 2450 comconsrate = rate; 2451 comconscflag = cflag; 2452 2453 return (0); 2454 } 2455 2456 int 2457 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2458 int type, tcflag_t cflag) 2459 { 2460 struct com_regs regs; 2461 2462 memset(®s, 0, sizeof regs); 2463 regs.cr_iot = iot; 2464 regs.cr_iobase = iobase; 2465 regs.cr_nports = COM_NPORTS; 2466 #ifdef COM_REGMAP 2467 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2468 #endif 2469 2470 return comcnattach1(®s, rate, frequency, type, cflag); 2471 } 2472 2473 int 2474 comcngetc(dev_t dev) 2475 { 2476 2477 return (com_common_getc(dev, &comconsregs)); 2478 } 2479 2480 /* 2481 * Console kernel output character routine. 2482 */ 2483 void 2484 comcnputc(dev_t dev, int c) 2485 { 2486 2487 com_common_putc(dev, &comconsregs, c); 2488 } 2489 2490 void 2491 comcnpollc(dev_t dev, int on) 2492 { 2493 2494 } 2495 2496 #ifdef KGDB 2497 int 2498 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2499 tcflag_t cflag) 2500 { 2501 int res; 2502 2503 if (regsp->cr_iot == comconsregs.cr_iot && 2504 regsp->cr_iobase == comconsregs.cr_iobase) { 2505 #if !defined(DDB) 2506 return (EBUSY); /* cannot share with console */ 2507 #else 2508 comkgdbregs = *regsp; 2509 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2510 #endif 2511 } else { 2512 comkgdbregs = *regsp; 2513 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2514 if (res) 2515 return (res); 2516 2517 /* 2518 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2519 * expects this to be initialized 2520 */ 2521 cn_init_magic(&com_cnm_state); 2522 cn_set_magic("\047\001"); 2523 } 2524 2525 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2526 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2527 2528 return (0); 2529 } 2530 2531 int 2532 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2533 int frequency, int type, tcflag_t cflag) 2534 { 2535 struct com_regs regs; 2536 2537 regs.cr_iot = iot; 2538 regs.cr_nports = COM_NPORTS; 2539 regs.cr_iobase = iobase; 2540 #ifdef COM_REGMAP 2541 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2542 #endif 2543 2544 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2545 } 2546 2547 /* ARGSUSED */ 2548 int 2549 com_kgdb_getc(void *arg) 2550 { 2551 2552 return (com_common_getc(NODEV, &comkgdbregs)); 2553 } 2554 2555 /* ARGSUSED */ 2556 void 2557 com_kgdb_putc(void *arg, int c) 2558 { 2559 2560 com_common_putc(NODEV, &comkgdbregs, c); 2561 } 2562 #endif /* KGDB */ 2563 2564 /* helper function to identify the com ports used by 2565 console or KGDB (and not yet autoconf attached) */ 2566 int 2567 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2568 { 2569 bus_space_handle_t help; 2570 2571 if (!comconsattached && 2572 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2573 help = comconsregs.cr_ioh; 2574 #ifdef KGDB 2575 else if (!com_kgdb_attached && 2576 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2577 help = comkgdbregs.cr_ioh; 2578 #endif 2579 else 2580 return (0); 2581 2582 if (ioh) 2583 *ioh = help; 2584 return (1); 2585 } 2586 2587 /* 2588 * this routine exists to serve as a shutdown hook for systems that 2589 * have firmware which doesn't interact properly with a com device in 2590 * FIFO mode. 2591 */ 2592 void 2593 com_cleanup(void *arg) 2594 { 2595 struct com_softc *sc = arg; 2596 2597 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2598 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2599 } 2600 2601 void 2602 com_power(int why, void *arg) 2603 { 2604 struct com_softc *sc = arg; 2605 int s; 2606 2607 s = splserial(); 2608 switch (why) { 2609 case PWR_SUSPEND: 2610 case PWR_STANDBY: 2611 /* XXX should we do something to stop the device? */ 2612 break; 2613 case PWR_RESUME: 2614 com_loadchannelregs(sc); 2615 break; 2616 case PWR_SOFTSUSPEND: 2617 case PWR_SOFTSTANDBY: 2618 case PWR_SOFTRESUME: 2619 break; 2620 } 2621 splx(s); 2622 } 2623
Indexes created Fri Sep 26 20:09:58 GMT 2025