com.c revision 1.253
1 /* $NetBSD: com.c,v 1.253 2006/10/01 19:28:43 elad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.253 2006/10/01 19:28:43 elad Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 194 void comsoft(void *); 195 #else 196 #ifndef __NO_SOFT_SERIAL_INTERRUPT 197 void comsoft(void); 198 #else 199 void comsoft(void *); 200 static struct callout comsoft_callout = CALLOUT_INITIALIZER; 201 #endif 202 #endif 203 integrate void com_rxsoft(struct com_softc *, struct tty *); 204 integrate void com_txsoft(struct com_softc *, struct tty *); 205 integrate void com_stsoft(struct com_softc *, struct tty *); 206 integrate void com_schedrx(struct com_softc *); 207 void comdiag(void *); 208 209 extern struct cfdriver com_cd; 210 211 dev_type_open(comopen); 212 dev_type_close(comclose); 213 dev_type_read(comread); 214 dev_type_write(comwrite); 215 dev_type_ioctl(comioctl); 216 dev_type_stop(comstop); 217 dev_type_tty(comtty); 218 dev_type_poll(compoll); 219 220 const struct cdevsw com_cdevsw = { 221 comopen, comclose, comread, comwrite, comioctl, 222 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 223 }; 224 225 /* 226 * Make this an option variable one can patch. 227 * But be warned: this must be a power of 2! 228 */ 229 u_int com_rbuf_size = COM_RING_SIZE; 230 231 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 232 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 233 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 234 235 static struct com_regs comconsregs; 236 static int comconsattached; 237 static int comconsrate; 238 static tcflag_t comconscflag; 239 static struct cnm_state com_cnm_state; 240 241 #ifndef __HAVE_TIMECOUNTER 242 static int ppscap = 243 PPS_TSFMT_TSPEC | 244 PPS_CAPTUREASSERT | 245 PPS_CAPTURECLEAR | 246 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 247 #endif /* !__HAVE_TIMECOUNTER */ 248 249 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 250 #ifdef __NO_SOFT_SERIAL_INTERRUPT 251 volatile int com_softintr_scheduled; 252 #endif 253 #endif 254 255 #ifdef KGDB 256 #include <sys/kgdb.h> 257 258 static struct com_regs comkgdbregs; 259 static int com_kgdb_attached; 260 261 int com_kgdb_getc(void *); 262 void com_kgdb_putc(void *, int); 263 #endif /* KGDB */ 264 265 #ifdef COM_REGMAP 266 /* initializer for typical 16550-ish hardware */ 267 #define COM_REG_16550 { \ 268 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 269 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 270 271 const bus_size_t com_std_map[16] = COM_REG_16550; 272 #endif /* COM_REGMAP */ 273 274 #define COMUNIT_MASK 0x7ffff 275 #define COMDIALOUT_MASK 0x80000 276 277 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 278 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 279 280 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 281 device_is_active(&(sc)->sc_dev)) 282 283 #define BR BUS_SPACE_BARRIER_READ 284 #define BW BUS_SPACE_BARRIER_WRITE 285 #define COM_BARRIER(r, f) \ 286 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 287 288 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 289 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 290 291 /*ARGSUSED*/ 292 int 293 comspeed(long speed, long frequency, int type) 294 { 295 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 296 297 int x, err; 298 299 #if 0 300 if (speed == 0) 301 return (0); 302 #endif 303 if (speed <= 0) 304 return (-1); 305 x = divrnd(frequency / 16, speed); 306 if (x <= 0) 307 return (-1); 308 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 309 if (err < 0) 310 err = -err; 311 if (err > COM_TOLERANCE) 312 return (-1); 313 return (x); 314 315 #undef divrnd 316 } 317 318 #ifdef COM_DEBUG 319 int com_debug = 0; 320 321 void comstatus(struct com_softc *, const char *); 322 void 323 comstatus(struct com_softc *sc, const char *str) 324 { 325 struct tty *tp = sc->sc_tty; 326 327 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 328 sc->sc_dev.dv_xname, str, 329 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 331 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 333 sc->sc_tx_stopped ? '+' : '-'); 334 335 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 sc->sc_dev.dv_xname, str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 static void 374 com_enable_debugport(struct com_softc *sc) 375 { 376 int s; 377 378 /* Turn on line break interrupt, set carrier. */ 379 s = splserial(); 380 COM_LOCK(sc); 381 sc->sc_ier = IER_ERXRDY; 382 if (sc->sc_type == COM_TYPE_PXA2x0) 383 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 384 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 385 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 386 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 387 COM_UNLOCK(sc); 388 splx(s); 389 } 390 391 void 392 com_attach_subr(struct com_softc *sc) 393 { 394 struct com_regs *regsp = &sc->sc_regs; 395 struct tty *tp; 396 #ifdef COM_16650 397 u_int8_t lcr; 398 #endif 399 const char *fifo_msg = NULL; 400 401 callout_init(&sc->sc_diag_callout); 402 simple_lock_init(&sc->sc_lock); 403 404 /* Disable interrupts before configuring the device. */ 405 if (sc->sc_type == COM_TYPE_PXA2x0) 406 sc->sc_ier = IER_EUART; 407 else 408 sc->sc_ier = 0; 409 410 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 411 412 if (regsp->cr_iot == comconsregs.cr_iot && 413 regsp->cr_iobase == comconsregs.cr_iobase) { 414 comconsattached = 1; 415 416 /* Make sure the console is always "hardwired". */ 417 delay(10000); /* wait for output to finish */ 418 SET(sc->sc_hwflags, COM_HW_CONSOLE); 419 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 420 } 421 422 /* Probe for FIFO */ 423 switch (sc->sc_type) { 424 case COM_TYPE_HAYESP: 425 goto fifodone; 426 427 case COM_TYPE_AU1x00: 428 sc->sc_fifolen = 16; 429 fifo_msg = "Au1X00 UART, working fifo"; 430 SET(sc->sc_hwflags, COM_HW_FIFO); 431 goto fifodelay; 432 } 433 434 sc->sc_fifolen = 1; 435 /* look for a NS 16550AF UART with FIFOs */ 436 CSR_WRITE_1(regsp, COM_REG_FIFO, 437 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 438 delay(100); 439 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 440 == IIR_FIFO_MASK) 441 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 442 == FIFO_TRIGGER_14) { 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 445 #ifdef COM_16650 446 /* 447 * IIR changes into the EFR if LCR is set to LCR_EERS 448 * on 16650s. We also know IIR != 0 at this point. 449 * Write 0 into the EFR, and read it. If the result 450 * is 0, we have a 16650. 451 * 452 * Older 16650s were broken; the test to detect them 453 * is taken from the Linux driver. Apparently 454 * setting DLAB enable gives access to the EFR on 455 * these chips. 456 */ 457 lcr = CSR_READ_1(regsp, COM_REG_LCR); 458 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 459 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 460 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 461 CSR_WRITE_1(regsp, COM_REG_LCR, 462 lcr | LCR_DLAB); 463 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 464 CLR(sc->sc_hwflags, COM_HW_FIFO); 465 sc->sc_fifolen = 0; 466 } else { 467 SET(sc->sc_hwflags, COM_HW_FLOW); 468 sc->sc_fifolen = 32; 469 } 470 } else 471 #endif 472 sc->sc_fifolen = 16; 473 474 #ifdef COM_16650 475 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 476 if (sc->sc_fifolen == 0) 477 fifo_msg = "st16650, broken fifo"; 478 else if (sc->sc_fifolen == 32) 479 fifo_msg = "st16650a, working fifo"; 480 else 481 #endif 482 fifo_msg = "ns16550a, working fifo"; 483 } else 484 fifo_msg = "ns16550, broken fifo"; 485 else 486 fifo_msg = "ns8250 or ns16450, no fifo"; 487 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 488 fifodelay: 489 /* 490 * Some chips will clear down both Tx and Rx FIFOs when zero is 491 * written to com_fifo. If this chip is the console, writing zero 492 * results in some of the chip/FIFO description being lost, so delay 493 * printing it until now. 494 */ 495 delay(10); 496 aprint_normal(": %s\n", fifo_msg); 497 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 498 sc->sc_fifolen = 1; 499 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 500 } 501 502 fifodone: 503 504 tp = ttymalloc(); 505 tp->t_oproc = comstart; 506 tp->t_param = comparam; 507 tp->t_hwiflow = comhwiflow; 508 509 sc->sc_tty = tp; 510 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 511 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 512 sc->sc_rbavail = com_rbuf_size; 513 if (sc->sc_rbuf == NULL) { 514 aprint_error("%s: unable to allocate ring buffer\n", 515 sc->sc_dev.dv_xname); 516 return; 517 } 518 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 519 520 tty_attach(tp); 521 522 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 523 SET(sc->sc_mcr, MCR_IENABLE); 524 525 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 526 int maj; 527 528 /* locate the major number */ 529 maj = cdevsw_lookup_major(&com_cdevsw); 530 531 tp->t_dev = cn_tab->cn_dev = makedev(maj, 532 device_unit(&sc->sc_dev)); 533 534 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 535 } 536 537 #ifdef KGDB 538 /* 539 * Allow kgdb to "take over" this port. If this is 540 * not the console and is the kgdb device, it has 541 * exclusive use. If it's the console _and_ the 542 * kgdb device, it doesn't. 543 */ 544 if (regsp->cr_iot == comkgdbregs.cr_iot && 545 regsp->cr_iobase == comkgdbregs.cr_iobase) { 546 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 547 com_kgdb_attached = 1; 548 549 SET(sc->sc_hwflags, COM_HW_KGDB); 550 } 551 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 552 } 553 #endif 554 555 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 556 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 557 #endif 558 559 #if NRND > 0 && defined(RND_COM) 560 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 561 RND_TYPE_TTY, 0); 562 #endif 563 564 /* if there are no enable/disable functions, assume the device 565 is always enabled */ 566 if (!sc->enable) 567 sc->enabled = 1; 568 569 com_config(sc); 570 571 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 572 com_power, sc); 573 if (sc->sc_powerhook == NULL) 574 printf("%s: WARNING: unable to establish power hook\n", 575 sc->sc_dev.dv_xname); 576 577 SET(sc->sc_hwflags, COM_HW_DEV_OK); 578 } 579 580 void 581 com_config(struct com_softc *sc) 582 { 583 struct com_regs *regsp = &sc->sc_regs; 584 585 /* Disable interrupts before configuring the device. */ 586 if (sc->sc_type == COM_TYPE_PXA2x0) 587 sc->sc_ier = IER_EUART; 588 else 589 sc->sc_ier = 0; 590 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 591 (void) CSR_READ_1(regsp, COM_REG_IIR); 592 593 #ifdef COM_HAYESP 594 /* Look for a Hayes ESP board. */ 595 if (sc->sc_type == COM_TYPE_HAYESP) { 596 597 /* Set 16550 compatibility mode */ 598 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 599 HAYESP_SETMODE); 600 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 602 HAYESP_MODE_SCALE); 603 604 /* Set RTS/CTS flow control */ 605 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 606 HAYESP_SETFLOWTYPE); 607 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 608 HAYESP_FLOW_RTS); 609 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_FLOW_CTS); 611 612 /* Set flow control levels */ 613 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 614 HAYESP_SETRXFLOW); 615 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 616 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 617 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 618 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 619 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 621 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 622 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 623 } 624 #endif 625 626 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 627 com_enable_debugport(sc); 628 } 629 630 int 631 com_detach(struct device *self, int flags) 632 { 633 struct com_softc *sc = (struct com_softc *)self; 634 int maj, mn; 635 636 /* kill the power hook */ 637 if (sc->sc_powerhook != NULL) 638 powerhook_disestablish(sc->sc_powerhook); 639 640 /* locate the major number */ 641 maj = cdevsw_lookup_major(&com_cdevsw); 642 643 /* Nuke the vnodes for any open instances. */ 644 mn = device_unit(self); 645 vdevgone(maj, mn, mn, VCHR); 646 647 mn |= COMDIALOUT_MASK; 648 vdevgone(maj, mn, mn, VCHR); 649 650 if (sc->sc_rbuf == NULL) { 651 /* 652 * Ring buffer allocation failed in the com_attach_subr, 653 * only the tty is allocated, and nothing else. 654 */ 655 ttyfree(sc->sc_tty); 656 return 0; 657 } 658 659 /* Free the receive buffer. */ 660 free(sc->sc_rbuf, M_DEVBUF); 661 662 /* Detach and free the tty. */ 663 tty_detach(sc->sc_tty); 664 ttyfree(sc->sc_tty); 665 666 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 667 /* Unhook the soft interrupt handler. */ 668 softintr_disestablish(sc->sc_si); 669 #endif 670 671 #if NRND > 0 && defined(RND_COM) 672 /* Unhook the entropy source. */ 673 rnd_detach_source(&sc->rnd_source); 674 #endif 675 676 return (0); 677 } 678 679 int 680 com_activate(struct device *self, enum devact act) 681 { 682 struct com_softc *sc = (struct com_softc *)self; 683 int s, rv = 0; 684 685 s = splserial(); 686 COM_LOCK(sc); 687 switch (act) { 688 case DVACT_ACTIVATE: 689 rv = EOPNOTSUPP; 690 break; 691 692 case DVACT_DEACTIVATE: 693 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 694 rv = EBUSY; 695 break; 696 } 697 698 if (sc->disable != NULL && sc->enabled != 0) { 699 (*sc->disable)(sc); 700 sc->enabled = 0; 701 } 702 break; 703 } 704 705 COM_UNLOCK(sc); 706 splx(s); 707 return (rv); 708 } 709 710 void 711 com_shutdown(struct com_softc *sc) 712 { 713 struct tty *tp = sc->sc_tty; 714 int s; 715 716 s = splserial(); 717 COM_LOCK(sc); 718 719 /* If we were asserting flow control, then deassert it. */ 720 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 721 com_hwiflow(sc); 722 723 /* Clear any break condition set with TIOCSBRK. */ 724 com_break(sc, 0); 725 726 #ifndef __HAVE_TIMECOUNTER 727 /* Turn off PPS capture on last close. */ 728 sc->sc_ppsmask = 0; 729 sc->ppsparam.mode = 0; 730 #endif /* !__HAVE_TIMECOUNTER */ 731 732 /* 733 * Hang up if necessary. Wait a bit, so the other side has time to 734 * notice even if we immediately open the port again. 735 * Avoid tsleeping above splhigh(). 736 */ 737 if (ISSET(tp->t_cflag, HUPCL)) { 738 com_modem(sc, 0); 739 COM_UNLOCK(sc); 740 splx(s); 741 /* XXX tsleep will only timeout */ 742 (void) tsleep(sc, TTIPRI, ttclos, hz); 743 s = splserial(); 744 COM_LOCK(sc); 745 } 746 747 /* Turn off interrupts. */ 748 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 749 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 750 if (sc->sc_type == COM_TYPE_PXA2x0) 751 sc->sc_ier |= IER_ERXTOUT; 752 } else 753 sc->sc_ier = 0; 754 755 if (sc->sc_type == COM_TYPE_PXA2x0) 756 sc->sc_ier |= IER_EUART; 757 758 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 759 760 if (sc->disable) { 761 #ifdef DIAGNOSTIC 762 if (!sc->enabled) 763 panic("com_shutdown: not enabled?"); 764 #endif 765 (*sc->disable)(sc); 766 sc->enabled = 0; 767 } 768 COM_UNLOCK(sc); 769 splx(s); 770 } 771 772 int 773 comopen(dev_t dev, int flag, int mode, struct lwp *l) 774 { 775 struct com_softc *sc; 776 struct tty *tp; 777 int s, s2; 778 int error; 779 780 sc = device_lookup(&com_cd, COMUNIT(dev)); 781 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 782 sc->sc_rbuf == NULL) 783 return (ENXIO); 784 785 if (!device_is_active(&sc->sc_dev)) 786 return (ENXIO); 787 788 #ifdef KGDB 789 /* 790 * If this is the kgdb port, no other use is permitted. 791 */ 792 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 793 return (EBUSY); 794 #endif 795 796 tp = sc->sc_tty; 797 798 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 799 return (EBUSY); 800 801 s = spltty(); 802 803 /* 804 * Do the following iff this is a first open. 805 */ 806 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 807 struct termios t; 808 809 tp->t_dev = dev; 810 811 s2 = splserial(); 812 COM_LOCK(sc); 813 814 if (sc->enable) { 815 if ((*sc->enable)(sc)) { 816 COM_UNLOCK(sc); 817 splx(s2); 818 splx(s); 819 printf("%s: device enable failed\n", 820 sc->sc_dev.dv_xname); 821 return (EIO); 822 } 823 sc->enabled = 1; 824 com_config(sc); 825 } 826 827 /* Turn on interrupts. */ 828 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 829 if (sc->sc_type == COM_TYPE_PXA2x0) 830 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 831 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 832 833 /* Fetch the current modem control status, needed later. */ 834 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 835 836 /* Clear PPS capture state on first open. */ 837 #ifdef __HAVE_TIMECOUNTER 838 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 839 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 840 pps_init(&sc->sc_pps_state); 841 #else /* !__HAVE_TIMECOUNTER */ 842 sc->sc_ppsmask = 0; 843 sc->ppsparam.mode = 0; 844 #endif /* !__HAVE_TIMECOUNTER */ 845 846 COM_UNLOCK(sc); 847 splx(s2); 848 849 /* 850 * Initialize the termios status to the defaults. Add in the 851 * sticky bits from TIOCSFLAGS. 852 */ 853 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 854 t.c_ospeed = comconsrate; 855 t.c_cflag = comconscflag; 856 } else { 857 t.c_ospeed = TTYDEF_SPEED; 858 t.c_cflag = TTYDEF_CFLAG; 859 } 860 t.c_ispeed = t.c_ospeed; 861 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 862 SET(t.c_cflag, CLOCAL); 863 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 864 SET(t.c_cflag, CRTSCTS); 865 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 866 SET(t.c_cflag, MDMBUF); 867 /* Make sure comparam() will do something. */ 868 tp->t_ospeed = 0; 869 (void) comparam(tp, &t); 870 tp->t_iflag = TTYDEF_IFLAG; 871 tp->t_oflag = TTYDEF_OFLAG; 872 tp->t_lflag = TTYDEF_LFLAG; 873 ttychars(tp); 874 ttsetwater(tp); 875 876 s2 = splserial(); 877 COM_LOCK(sc); 878 879 /* 880 * Turn on DTR. We must always do this, even if carrier is not 881 * present, because otherwise we'd have to use TIOCSDTR 882 * immediately after setting CLOCAL, which applications do not 883 * expect. We always assert DTR while the device is open 884 * unless explicitly requested to deassert it. 885 */ 886 com_modem(sc, 1); 887 888 /* Clear the input ring, and unblock. */ 889 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 890 sc->sc_rbavail = com_rbuf_size; 891 com_iflush(sc); 892 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 893 com_hwiflow(sc); 894 895 #ifdef COM_DEBUG 896 if (com_debug) 897 comstatus(sc, "comopen "); 898 #endif 899 900 COM_UNLOCK(sc); 901 splx(s2); 902 } 903 904 splx(s); 905 906 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 907 if (error) 908 goto bad; 909 910 error = (*tp->t_linesw->l_open)(dev, tp); 911 if (error) 912 goto bad; 913 914 return (0); 915 916 bad: 917 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 918 /* 919 * We failed to open the device, and nobody else had it opened. 920 * Clean up the state as appropriate. 921 */ 922 com_shutdown(sc); 923 } 924 925 return (error); 926 } 927 928 int 929 comclose(dev_t dev, int flag, int mode, struct lwp *l) 930 { 931 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 932 struct tty *tp = sc->sc_tty; 933 934 /* XXX This is for cons.c. */ 935 if (!ISSET(tp->t_state, TS_ISOPEN)) 936 return (0); 937 938 (*tp->t_linesw->l_close)(tp, flag); 939 ttyclose(tp); 940 941 if (COM_ISALIVE(sc) == 0) 942 return (0); 943 944 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 945 /* 946 * Although we got a last close, the device may still be in 947 * use; e.g. if this was the dialout node, and there are still 948 * processes waiting for carrier on the non-dialout node. 949 */ 950 com_shutdown(sc); 951 } 952 953 return (0); 954 } 955 956 int 957 comread(dev_t dev, struct uio *uio, int flag) 958 { 959 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 960 struct tty *tp = sc->sc_tty; 961 962 if (COM_ISALIVE(sc) == 0) 963 return (EIO); 964 965 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 966 } 967 968 int 969 comwrite(dev_t dev, struct uio *uio, int flag) 970 { 971 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 972 struct tty *tp = sc->sc_tty; 973 974 if (COM_ISALIVE(sc) == 0) 975 return (EIO); 976 977 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 978 } 979 980 int 981 compoll(dev_t dev, int events, struct lwp *l) 982 { 983 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 984 struct tty *tp = sc->sc_tty; 985 986 if (COM_ISALIVE(sc) == 0) 987 return (POLLHUP); 988 989 return ((*tp->t_linesw->l_poll)(tp, events, l)); 990 } 991 992 struct tty * 993 comtty(dev_t dev) 994 { 995 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 996 struct tty *tp = sc->sc_tty; 997 998 return (tp); 999 } 1000 1001 int 1002 comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 1003 { 1004 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 1005 struct tty *tp = sc->sc_tty; 1006 int error; 1007 int s; 1008 1009 if (COM_ISALIVE(sc) == 0) 1010 return (EIO); 1011 1012 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1013 if (error != EPASSTHROUGH) 1014 return (error); 1015 1016 error = ttioctl(tp, cmd, data, flag, l); 1017 if (error != EPASSTHROUGH) 1018 return (error); 1019 1020 error = 0; 1021 switch (cmd) { 1022 case TIOCSFLAGS: 1023 error = kauth_authorize_generic(l->l_cred, 1024 KAUTH_GENERIC_ISSUSER, &l->l_acflag); 1025 break; 1026 default: 1027 /* nothing */ 1028 break; 1029 } 1030 if (error) { 1031 return error; 1032 } 1033 1034 s = splserial(); 1035 COM_LOCK(sc); 1036 1037 switch (cmd) { 1038 case TIOCSBRK: 1039 com_break(sc, 1); 1040 break; 1041 1042 case TIOCCBRK: 1043 com_break(sc, 0); 1044 break; 1045 1046 case TIOCSDTR: 1047 com_modem(sc, 1); 1048 break; 1049 1050 case TIOCCDTR: 1051 com_modem(sc, 0); 1052 break; 1053 1054 case TIOCGFLAGS: 1055 *(int *)data = sc->sc_swflags; 1056 break; 1057 1058 case TIOCSFLAGS: 1059 sc->sc_swflags = *(int *)data; 1060 break; 1061 1062 case TIOCMSET: 1063 case TIOCMBIS: 1064 case TIOCMBIC: 1065 tiocm_to_com(sc, cmd, *(int *)data); 1066 break; 1067 1068 case TIOCMGET: 1069 *(int *)data = com_to_tiocm(sc); 1070 break; 1071 1072 #ifdef __HAVE_TIMECOUNTER 1073 case PPS_IOC_CREATE: 1074 case PPS_IOC_DESTROY: 1075 case PPS_IOC_GETPARAMS: 1076 case PPS_IOC_SETPARAMS: 1077 case PPS_IOC_GETCAP: 1078 case PPS_IOC_FETCH: 1079 #ifdef PPS_SYNC 1080 case PPS_IOC_KCBIND: 1081 #endif 1082 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1083 break; 1084 #else /* !__HAVE_TIMECOUNTER */ 1085 case PPS_IOC_CREATE: 1086 break; 1087 1088 case PPS_IOC_DESTROY: 1089 break; 1090 1091 case PPS_IOC_GETPARAMS: { 1092 pps_params_t *pp; 1093 pp = (pps_params_t *)data; 1094 *pp = sc->ppsparam; 1095 break; 1096 } 1097 1098 case PPS_IOC_SETPARAMS: { 1099 pps_params_t *pp; 1100 int mode; 1101 pp = (pps_params_t *)data; 1102 if (pp->mode & ~ppscap) { 1103 error = EINVAL; 1104 break; 1105 } 1106 sc->ppsparam = *pp; 1107 /* 1108 * Compute msr masks from user-specified timestamp state. 1109 */ 1110 mode = sc->ppsparam.mode; 1111 switch (mode & PPS_CAPTUREBOTH) { 1112 case 0: 1113 sc->sc_ppsmask = 0; 1114 break; 1115 1116 case PPS_CAPTUREASSERT: 1117 sc->sc_ppsmask = MSR_DCD; 1118 sc->sc_ppsassert = MSR_DCD; 1119 sc->sc_ppsclear = -1; 1120 break; 1121 1122 case PPS_CAPTURECLEAR: 1123 sc->sc_ppsmask = MSR_DCD; 1124 sc->sc_ppsassert = -1; 1125 sc->sc_ppsclear = 0; 1126 break; 1127 1128 case PPS_CAPTUREBOTH: 1129 sc->sc_ppsmask = MSR_DCD; 1130 sc->sc_ppsassert = MSR_DCD; 1131 sc->sc_ppsclear = 0; 1132 break; 1133 1134 default: 1135 error = EINVAL; 1136 break; 1137 } 1138 break; 1139 } 1140 1141 case PPS_IOC_GETCAP: 1142 *(int*)data = ppscap; 1143 break; 1144 1145 case PPS_IOC_FETCH: { 1146 pps_info_t *pi; 1147 pi = (pps_info_t *)data; 1148 *pi = sc->ppsinfo; 1149 break; 1150 } 1151 1152 #ifdef PPS_SYNC 1153 case PPS_IOC_KCBIND: { 1154 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1155 1156 if (edge == 0) { 1157 /* 1158 * remove binding for this source; ignore 1159 * the request if this is not the current 1160 * hardpps source 1161 */ 1162 if (pps_kc_hardpps_source == sc) { 1163 pps_kc_hardpps_source = NULL; 1164 pps_kc_hardpps_mode = 0; 1165 } 1166 } else { 1167 /* 1168 * bind hardpps to this source, replacing any 1169 * previously specified source or edges 1170 */ 1171 pps_kc_hardpps_source = sc; 1172 pps_kc_hardpps_mode = edge; 1173 } 1174 break; 1175 } 1176 #endif /* PPS_SYNC */ 1177 #endif /* !__HAVE_TIMECOUNTER */ 1178 1179 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1180 #ifdef __HAVE_TIMECOUNTER 1181 #ifndef PPS_TRAILING_EDGE 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1184 #else 1185 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1186 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1187 #endif 1188 #else /* !__HAVE_TIMECOUNTER */ 1189 /* 1190 * Some GPS clocks models use the falling rather than 1191 * rising edge as the on-the-second signal. 1192 * The old API has no way to specify PPS polarity. 1193 */ 1194 sc->sc_ppsmask = MSR_DCD; 1195 #ifndef PPS_TRAILING_EDGE 1196 sc->sc_ppsassert = MSR_DCD; 1197 sc->sc_ppsclear = -1; 1198 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1199 &sc->ppsinfo.assert_timestamp); 1200 #else 1201 sc->sc_ppsassert = -1; 1202 sc->sc_ppsclear = 0; 1203 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1204 &sc->ppsinfo.clear_timestamp); 1205 #endif 1206 #endif /* !__HAVE_TIMECOUNTER */ 1207 break; 1208 1209 default: 1210 error = EPASSTHROUGH; 1211 break; 1212 } 1213 1214 COM_UNLOCK(sc); 1215 splx(s); 1216 1217 #ifdef COM_DEBUG 1218 if (com_debug) 1219 comstatus(sc, "comioctl "); 1220 #endif 1221 1222 return (error); 1223 } 1224 1225 integrate void 1226 com_schedrx(struct com_softc *sc) 1227 { 1228 1229 sc->sc_rx_ready = 1; 1230 1231 /* Wake up the poller. */ 1232 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1233 softintr_schedule(sc->sc_si); 1234 #else 1235 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1236 setsoftserial(); 1237 #else 1238 if (!com_softintr_scheduled) { 1239 com_softintr_scheduled = 1; 1240 callout_reset(&comsoft_callout, 1, comsoft, NULL); 1241 } 1242 #endif 1243 #endif 1244 } 1245 1246 void 1247 com_break(struct com_softc *sc, int onoff) 1248 { 1249 1250 if (onoff) 1251 SET(sc->sc_lcr, LCR_SBREAK); 1252 else 1253 CLR(sc->sc_lcr, LCR_SBREAK); 1254 1255 if (!sc->sc_heldchange) { 1256 if (sc->sc_tx_busy) { 1257 sc->sc_heldtbc = sc->sc_tbc; 1258 sc->sc_tbc = 0; 1259 sc->sc_heldchange = 1; 1260 } else 1261 com_loadchannelregs(sc); 1262 } 1263 } 1264 1265 void 1266 com_modem(struct com_softc *sc, int onoff) 1267 { 1268 1269 if (sc->sc_mcr_dtr == 0) 1270 return; 1271 1272 if (onoff) 1273 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1274 else 1275 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1276 1277 if (!sc->sc_heldchange) { 1278 if (sc->sc_tx_busy) { 1279 sc->sc_heldtbc = sc->sc_tbc; 1280 sc->sc_tbc = 0; 1281 sc->sc_heldchange = 1; 1282 } else 1283 com_loadchannelregs(sc); 1284 } 1285 } 1286 1287 void 1288 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1289 { 1290 u_char combits; 1291 1292 combits = 0; 1293 if (ISSET(ttybits, TIOCM_DTR)) 1294 SET(combits, MCR_DTR); 1295 if (ISSET(ttybits, TIOCM_RTS)) 1296 SET(combits, MCR_RTS); 1297 1298 switch (how) { 1299 case TIOCMBIC: 1300 CLR(sc->sc_mcr, combits); 1301 break; 1302 1303 case TIOCMBIS: 1304 SET(sc->sc_mcr, combits); 1305 break; 1306 1307 case TIOCMSET: 1308 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1309 SET(sc->sc_mcr, combits); 1310 break; 1311 } 1312 1313 if (!sc->sc_heldchange) { 1314 if (sc->sc_tx_busy) { 1315 sc->sc_heldtbc = sc->sc_tbc; 1316 sc->sc_tbc = 0; 1317 sc->sc_heldchange = 1; 1318 } else 1319 com_loadchannelregs(sc); 1320 } 1321 } 1322 1323 int 1324 com_to_tiocm(struct com_softc *sc) 1325 { 1326 u_char combits; 1327 int ttybits = 0; 1328 1329 combits = sc->sc_mcr; 1330 if (ISSET(combits, MCR_DTR)) 1331 SET(ttybits, TIOCM_DTR); 1332 if (ISSET(combits, MCR_RTS)) 1333 SET(ttybits, TIOCM_RTS); 1334 1335 combits = sc->sc_msr; 1336 if (ISSET(combits, MSR_DCD)) 1337 SET(ttybits, TIOCM_CD); 1338 if (ISSET(combits, MSR_CTS)) 1339 SET(ttybits, TIOCM_CTS); 1340 if (ISSET(combits, MSR_DSR)) 1341 SET(ttybits, TIOCM_DSR); 1342 if (ISSET(combits, MSR_RI | MSR_TERI)) 1343 SET(ttybits, TIOCM_RI); 1344 1345 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1346 SET(ttybits, TIOCM_LE); 1347 1348 return (ttybits); 1349 } 1350 1351 static u_char 1352 cflag2lcr(tcflag_t cflag) 1353 { 1354 u_char lcr = 0; 1355 1356 switch (ISSET(cflag, CSIZE)) { 1357 case CS5: 1358 SET(lcr, LCR_5BITS); 1359 break; 1360 case CS6: 1361 SET(lcr, LCR_6BITS); 1362 break; 1363 case CS7: 1364 SET(lcr, LCR_7BITS); 1365 break; 1366 case CS8: 1367 SET(lcr, LCR_8BITS); 1368 break; 1369 } 1370 if (ISSET(cflag, PARENB)) { 1371 SET(lcr, LCR_PENAB); 1372 if (!ISSET(cflag, PARODD)) 1373 SET(lcr, LCR_PEVEN); 1374 } 1375 if (ISSET(cflag, CSTOPB)) 1376 SET(lcr, LCR_STOPB); 1377 1378 return (lcr); 1379 } 1380 1381 int 1382 comparam(struct tty *tp, struct termios *t) 1383 { 1384 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1385 int ospeed; 1386 u_char lcr; 1387 int s; 1388 1389 if (COM_ISALIVE(sc) == 0) 1390 return (EIO); 1391 1392 #ifdef COM_HAYESP 1393 if (sc->sc_type == COM_TYPE_HAYESP) { 1394 int prescaler, speed; 1395 1396 /* 1397 * Calculate UART clock prescaler. It should be in 1398 * range of 0 .. 3. 1399 */ 1400 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1401 prescaler++, speed /= 2) 1402 if ((ospeed = comspeed(speed, sc->sc_frequency, 1403 sc->sc_type)) > 0) 1404 break; 1405 1406 if (prescaler == 4) 1407 return (EINVAL); 1408 sc->sc_prescaler = prescaler; 1409 } else 1410 #endif 1411 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1412 1413 /* Check requested parameters. */ 1414 if (ospeed < 0) 1415 return (EINVAL); 1416 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1417 return (EINVAL); 1418 1419 /* 1420 * For the console, always force CLOCAL and !HUPCL, so that the port 1421 * is always active. 1422 */ 1423 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1424 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1425 SET(t->c_cflag, CLOCAL); 1426 CLR(t->c_cflag, HUPCL); 1427 } 1428 1429 /* 1430 * If there were no changes, don't do anything. This avoids dropping 1431 * input and improves performance when all we did was frob things like 1432 * VMIN and VTIME. 1433 */ 1434 if (tp->t_ospeed == t->c_ospeed && 1435 tp->t_cflag == t->c_cflag) 1436 return (0); 1437 1438 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1439 1440 s = splserial(); 1441 COM_LOCK(sc); 1442 1443 sc->sc_lcr = lcr; 1444 1445 /* 1446 * If we're not in a mode that assumes a connection is present, then 1447 * ignore carrier changes. 1448 */ 1449 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1450 sc->sc_msr_dcd = 0; 1451 else 1452 sc->sc_msr_dcd = MSR_DCD; 1453 /* 1454 * Set the flow control pins depending on the current flow control 1455 * mode. 1456 */ 1457 if (ISSET(t->c_cflag, CRTSCTS)) { 1458 sc->sc_mcr_dtr = MCR_DTR; 1459 sc->sc_mcr_rts = MCR_RTS; 1460 sc->sc_msr_cts = MSR_CTS; 1461 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1462 } else if (ISSET(t->c_cflag, MDMBUF)) { 1463 /* 1464 * For DTR/DCD flow control, make sure we don't toggle DTR for 1465 * carrier detection. 1466 */ 1467 sc->sc_mcr_dtr = 0; 1468 sc->sc_mcr_rts = MCR_DTR; 1469 sc->sc_msr_cts = MSR_DCD; 1470 sc->sc_efr = 0; 1471 } else { 1472 /* 1473 * If no flow control, then always set RTS. This will make 1474 * the other side happy if it mistakenly thinks we're doing 1475 * RTS/CTS flow control. 1476 */ 1477 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1478 sc->sc_mcr_rts = 0; 1479 sc->sc_msr_cts = 0; 1480 sc->sc_efr = 0; 1481 if (ISSET(sc->sc_mcr, MCR_DTR)) 1482 SET(sc->sc_mcr, MCR_RTS); 1483 else 1484 CLR(sc->sc_mcr, MCR_RTS); 1485 } 1486 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1487 1488 #if 0 1489 if (ospeed == 0) 1490 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1491 else 1492 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1493 #endif 1494 1495 sc->sc_dlbl = ospeed; 1496 sc->sc_dlbh = ospeed >> 8; 1497 1498 /* 1499 * Set the FIFO threshold based on the receive speed. 1500 * 1501 * * If it's a low speed, it's probably a mouse or some other 1502 * interactive device, so set the threshold low. 1503 * * If it's a high speed, trim the trigger level down to prevent 1504 * overflows. 1505 * * Otherwise set it a bit higher. 1506 */ 1507 if (sc->sc_type == COM_TYPE_HAYESP) 1508 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1509 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1510 sc->sc_fifo = FIFO_ENABLE | 1511 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1512 else 1513 sc->sc_fifo = 0; 1514 1515 /* And copy to tty. */ 1516 tp->t_ispeed = t->c_ospeed; 1517 tp->t_ospeed = t->c_ospeed; 1518 tp->t_cflag = t->c_cflag; 1519 1520 if (!sc->sc_heldchange) { 1521 if (sc->sc_tx_busy) { 1522 sc->sc_heldtbc = sc->sc_tbc; 1523 sc->sc_tbc = 0; 1524 sc->sc_heldchange = 1; 1525 } else 1526 com_loadchannelregs(sc); 1527 } 1528 1529 if (!ISSET(t->c_cflag, CHWFLOW)) { 1530 /* Disable the high water mark. */ 1531 sc->sc_r_hiwat = 0; 1532 sc->sc_r_lowat = 0; 1533 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1534 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1535 com_schedrx(sc); 1536 } 1537 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1538 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1539 com_hwiflow(sc); 1540 } 1541 } else { 1542 sc->sc_r_hiwat = com_rbuf_hiwat; 1543 sc->sc_r_lowat = com_rbuf_lowat; 1544 } 1545 1546 COM_UNLOCK(sc); 1547 splx(s); 1548 1549 /* 1550 * Update the tty layer's idea of the carrier bit, in case we changed 1551 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1552 * explicit request. 1553 */ 1554 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1555 1556 #ifdef COM_DEBUG 1557 if (com_debug) 1558 comstatus(sc, "comparam "); 1559 #endif 1560 1561 if (!ISSET(t->c_cflag, CHWFLOW)) { 1562 if (sc->sc_tx_stopped) { 1563 sc->sc_tx_stopped = 0; 1564 comstart(tp); 1565 } 1566 } 1567 1568 return (0); 1569 } 1570 1571 void 1572 com_iflush(struct com_softc *sc) 1573 { 1574 struct com_regs *regsp = &sc->sc_regs; 1575 #ifdef DIAGNOSTIC 1576 int reg; 1577 #endif 1578 int timo; 1579 1580 #ifdef DIAGNOSTIC 1581 reg = 0xffff; 1582 #endif 1583 timo = 50000; 1584 /* flush any pending I/O */ 1585 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1586 && --timo) 1587 #ifdef DIAGNOSTIC 1588 reg = 1589 #else 1590 (void) 1591 #endif 1592 CSR_READ_1(regsp, COM_REG_RXDATA); 1593 #ifdef DIAGNOSTIC 1594 if (!timo) 1595 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1596 reg); 1597 #endif 1598 } 1599 1600 void 1601 com_loadchannelregs(struct com_softc *sc) 1602 { 1603 struct com_regs *regsp = &sc->sc_regs; 1604 1605 /* XXXXX necessary? */ 1606 com_iflush(sc); 1607 1608 if (sc->sc_type == COM_TYPE_PXA2x0) 1609 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1610 else 1611 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1612 1613 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1614 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1615 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1616 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1617 } 1618 } 1619 if (sc->sc_type == COM_TYPE_AU1x00) { 1620 /* alchemy has single separate 16-bit clock divisor register */ 1621 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1622 (sc->sc_dlbh << 8)); 1623 } else { 1624 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1625 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1626 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1627 } 1628 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1629 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1630 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1631 #ifdef COM_HAYESP 1632 if (sc->sc_type == COM_TYPE_HAYESP) { 1633 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD1, 1634 HAYESP_SETPRESCALER); 1635 bus_space_write_1(iot, sc->sc_hayespioh, HAYESP_CMD2, 1636 sc->sc_prescaler); 1637 } 1638 #endif 1639 1640 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1641 } 1642 1643 int 1644 comhwiflow(struct tty *tp, int block) 1645 { 1646 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1647 int s; 1648 1649 if (COM_ISALIVE(sc) == 0) 1650 return (0); 1651 1652 if (sc->sc_mcr_rts == 0) 1653 return (0); 1654 1655 s = splserial(); 1656 COM_LOCK(sc); 1657 1658 if (block) { 1659 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1660 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1661 com_hwiflow(sc); 1662 } 1663 } else { 1664 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1665 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1666 com_schedrx(sc); 1667 } 1668 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1669 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1670 com_hwiflow(sc); 1671 } 1672 } 1673 1674 COM_UNLOCK(sc); 1675 splx(s); 1676 return (1); 1677 } 1678 1679 /* 1680 * (un)block input via hw flowcontrol 1681 */ 1682 void 1683 com_hwiflow(struct com_softc *sc) 1684 { 1685 struct com_regs *regsp= &sc->sc_regs; 1686 1687 if (sc->sc_mcr_rts == 0) 1688 return; 1689 1690 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1691 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1692 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1693 } else { 1694 SET(sc->sc_mcr, sc->sc_mcr_rts); 1695 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1696 } 1697 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1698 } 1699 1700 1701 void 1702 comstart(struct tty *tp) 1703 { 1704 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1705 struct com_regs *regsp = &sc->sc_regs; 1706 int s; 1707 1708 if (COM_ISALIVE(sc) == 0) 1709 return; 1710 1711 s = spltty(); 1712 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1713 goto out; 1714 if (sc->sc_tx_stopped) 1715 goto out; 1716 1717 if (tp->t_outq.c_cc <= tp->t_lowat) { 1718 if (ISSET(tp->t_state, TS_ASLEEP)) { 1719 CLR(tp->t_state, TS_ASLEEP); 1720 wakeup(&tp->t_outq); 1721 } 1722 selwakeup(&tp->t_wsel); 1723 if (tp->t_outq.c_cc == 0) 1724 goto out; 1725 } 1726 1727 /* Grab the first contiguous region of buffer space. */ 1728 { 1729 u_char *tba; 1730 int tbc; 1731 1732 tba = tp->t_outq.c_cf; 1733 tbc = ndqb(&tp->t_outq, 0); 1734 1735 (void)splserial(); 1736 COM_LOCK(sc); 1737 1738 sc->sc_tba = tba; 1739 sc->sc_tbc = tbc; 1740 } 1741 1742 SET(tp->t_state, TS_BUSY); 1743 sc->sc_tx_busy = 1; 1744 1745 /* Enable transmit completion interrupts if necessary. */ 1746 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1747 SET(sc->sc_ier, IER_ETXRDY); 1748 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1749 } 1750 1751 /* Output the first chunk of the contiguous buffer. */ 1752 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1753 u_int n; 1754 1755 n = sc->sc_tbc; 1756 if (n > sc->sc_fifolen) 1757 n = sc->sc_fifolen; 1758 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1759 sc->sc_tbc -= n; 1760 sc->sc_tba += n; 1761 } 1762 1763 COM_UNLOCK(sc); 1764 out: 1765 splx(s); 1766 return; 1767 } 1768 1769 /* 1770 * Stop output on a line. 1771 */ 1772 void 1773 comstop(struct tty *tp, int flag) 1774 { 1775 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1776 int s; 1777 1778 s = splserial(); 1779 COM_LOCK(sc); 1780 if (ISSET(tp->t_state, TS_BUSY)) { 1781 /* Stop transmitting at the next chunk. */ 1782 sc->sc_tbc = 0; 1783 sc->sc_heldtbc = 0; 1784 if (!ISSET(tp->t_state, TS_TTSTOP)) 1785 SET(tp->t_state, TS_FLUSH); 1786 } 1787 COM_UNLOCK(sc); 1788 splx(s); 1789 } 1790 1791 void 1792 comdiag(void *arg) 1793 { 1794 struct com_softc *sc = arg; 1795 int overflows, floods; 1796 int s; 1797 1798 s = splserial(); 1799 COM_LOCK(sc); 1800 overflows = sc->sc_overflows; 1801 sc->sc_overflows = 0; 1802 floods = sc->sc_floods; 1803 sc->sc_floods = 0; 1804 sc->sc_errors = 0; 1805 COM_UNLOCK(sc); 1806 splx(s); 1807 1808 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1809 sc->sc_dev.dv_xname, 1810 overflows, overflows == 1 ? "" : "s", 1811 floods, floods == 1 ? "" : "s"); 1812 } 1813 1814 integrate void 1815 com_rxsoft(struct com_softc *sc, struct tty *tp) 1816 { 1817 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1818 u_char *get, *end; 1819 u_int cc, scc; 1820 u_char lsr; 1821 int code; 1822 int s; 1823 1824 end = sc->sc_ebuf; 1825 get = sc->sc_rbget; 1826 scc = cc = com_rbuf_size - sc->sc_rbavail; 1827 1828 if (cc == com_rbuf_size) { 1829 sc->sc_floods++; 1830 if (sc->sc_errors++ == 0) 1831 callout_reset(&sc->sc_diag_callout, 60 * hz, 1832 comdiag, sc); 1833 } 1834 1835 /* If not yet open, drop the entire buffer content here */ 1836 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1837 get += cc << 1; 1838 if (get >= end) 1839 get -= com_rbuf_size << 1; 1840 cc = 0; 1841 } 1842 while (cc) { 1843 code = get[0]; 1844 lsr = get[1]; 1845 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1846 if (ISSET(lsr, LSR_OE)) { 1847 sc->sc_overflows++; 1848 if (sc->sc_errors++ == 0) 1849 callout_reset(&sc->sc_diag_callout, 1850 60 * hz, comdiag, sc); 1851 } 1852 if (ISSET(lsr, LSR_BI | LSR_FE)) 1853 SET(code, TTY_FE); 1854 if (ISSET(lsr, LSR_PE)) 1855 SET(code, TTY_PE); 1856 } 1857 if ((*rint)(code, tp) == -1) { 1858 /* 1859 * The line discipline's buffer is out of space. 1860 */ 1861 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1862 /* 1863 * We're either not using flow control, or the 1864 * line discipline didn't tell us to block for 1865 * some reason. Either way, we have no way to 1866 * know when there's more space available, so 1867 * just drop the rest of the data. 1868 */ 1869 get += cc << 1; 1870 if (get >= end) 1871 get -= com_rbuf_size << 1; 1872 cc = 0; 1873 } else { 1874 /* 1875 * Don't schedule any more receive processing 1876 * until the line discipline tells us there's 1877 * space available (through comhwiflow()). 1878 * Leave the rest of the data in the input 1879 * buffer. 1880 */ 1881 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1882 } 1883 break; 1884 } 1885 get += 2; 1886 if (get >= end) 1887 get = sc->sc_rbuf; 1888 cc--; 1889 } 1890 1891 if (cc != scc) { 1892 sc->sc_rbget = get; 1893 s = splserial(); 1894 COM_LOCK(sc); 1895 1896 cc = sc->sc_rbavail += scc - cc; 1897 /* Buffers should be ok again, release possible block. */ 1898 if (cc >= sc->sc_r_lowat) { 1899 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1900 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1901 SET(sc->sc_ier, IER_ERXRDY); 1902 #ifdef COM_PXA2X0 1903 if (sc->sc_type == COM_TYPE_PXA2x0) 1904 SET(sc->sc_ier, IER_ERXTOUT); 1905 #endif 1906 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1907 } 1908 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1909 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1910 com_hwiflow(sc); 1911 } 1912 } 1913 COM_UNLOCK(sc); 1914 splx(s); 1915 } 1916 } 1917 1918 integrate void 1919 com_txsoft(struct com_softc *sc, struct tty *tp) 1920 { 1921 1922 CLR(tp->t_state, TS_BUSY); 1923 if (ISSET(tp->t_state, TS_FLUSH)) 1924 CLR(tp->t_state, TS_FLUSH); 1925 else 1926 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1927 (*tp->t_linesw->l_start)(tp); 1928 } 1929 1930 integrate void 1931 com_stsoft(struct com_softc *sc, struct tty *tp) 1932 { 1933 u_char msr, delta; 1934 int s; 1935 1936 s = splserial(); 1937 COM_LOCK(sc); 1938 msr = sc->sc_msr; 1939 delta = sc->sc_msr_delta; 1940 sc->sc_msr_delta = 0; 1941 COM_UNLOCK(sc); 1942 splx(s); 1943 1944 if (ISSET(delta, sc->sc_msr_dcd)) { 1945 /* 1946 * Inform the tty layer that carrier detect changed. 1947 */ 1948 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1949 } 1950 1951 if (ISSET(delta, sc->sc_msr_cts)) { 1952 /* Block or unblock output according to flow control. */ 1953 if (ISSET(msr, sc->sc_msr_cts)) { 1954 sc->sc_tx_stopped = 0; 1955 (*tp->t_linesw->l_start)(tp); 1956 } else { 1957 sc->sc_tx_stopped = 1; 1958 } 1959 } 1960 1961 #ifdef COM_DEBUG 1962 if (com_debug) 1963 comstatus(sc, "com_stsoft"); 1964 #endif 1965 } 1966 1967 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1968 void 1969 comsoft(void *arg) 1970 { 1971 struct com_softc *sc = arg; 1972 struct tty *tp; 1973 1974 if (COM_ISALIVE(sc) == 0) 1975 return; 1976 1977 { 1978 #else 1979 void 1980 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1981 comsoft(void) 1982 #else 1983 comsoft(void *arg) 1984 #endif 1985 { 1986 struct com_softc *sc; 1987 struct tty *tp; 1988 int unit; 1989 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1990 int s; 1991 1992 s = splsoftserial(); 1993 com_softintr_scheduled = 0; 1994 #endif 1995 1996 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1997 sc = device_lookup(&com_cd, unit); 1998 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK)) 1999 continue; 2000 2001 if (COM_ISALIVE(sc) == 0) 2002 continue; 2003 2004 tp = sc->sc_tty; 2005 if (tp == NULL) 2006 continue; 2007 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 2008 continue; 2009 #endif 2010 tp = sc->sc_tty; 2011 2012 if (sc->sc_rx_ready) { 2013 sc->sc_rx_ready = 0; 2014 com_rxsoft(sc, tp); 2015 } 2016 2017 if (sc->sc_st_check) { 2018 sc->sc_st_check = 0; 2019 com_stsoft(sc, tp); 2020 } 2021 2022 if (sc->sc_tx_done) { 2023 sc->sc_tx_done = 0; 2024 com_txsoft(sc, tp); 2025 } 2026 } 2027 2028 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 2029 #ifdef __NO_SOFT_SERIAL_INTERRUPT 2030 splx(s); 2031 #endif 2032 #endif 2033 } 2034 2035 #ifdef __ALIGN_BRACKET_LEVEL_FOR_CTAGS 2036 /* there has got to be a better way to do comsoft() */ 2037 }} 2038 #endif 2039 2040 int 2041 comintr(void *arg) 2042 { 2043 struct com_softc *sc = arg; 2044 struct com_regs *regsp = &sc->sc_regs; 2045 2046 u_char *put, *end; 2047 u_int cc; 2048 u_char lsr, iir; 2049 2050 if (COM_ISALIVE(sc) == 0) 2051 return (0); 2052 2053 COM_LOCK(sc); 2054 iir = CSR_READ_1(regsp, COM_REG_IIR); 2055 if (ISSET(iir, IIR_NOPEND)) { 2056 COM_UNLOCK(sc); 2057 return (0); 2058 } 2059 2060 end = sc->sc_ebuf; 2061 put = sc->sc_rbput; 2062 cc = sc->sc_rbavail; 2063 2064 again: do { 2065 u_char msr, delta; 2066 2067 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2068 if (ISSET(lsr, LSR_BI)) { 2069 int cn_trapped = 0; 2070 2071 cn_check_magic(sc->sc_tty->t_dev, 2072 CNC_BREAK, com_cnm_state); 2073 if (cn_trapped) 2074 continue; 2075 #if defined(KGDB) && !defined(DDB) 2076 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2077 kgdb_connect(1); 2078 continue; 2079 } 2080 #endif 2081 } 2082 2083 if (ISSET(lsr, LSR_RCV_MASK) && 2084 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2085 while (cc > 0) { 2086 int cn_trapped = 0; 2087 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2088 put[1] = lsr; 2089 cn_check_magic(sc->sc_tty->t_dev, 2090 put[0], com_cnm_state); 2091 if (cn_trapped) 2092 goto next; 2093 put += 2; 2094 if (put >= end) 2095 put = sc->sc_rbuf; 2096 cc--; 2097 next: 2098 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2099 if (!ISSET(lsr, LSR_RCV_MASK)) 2100 break; 2101 } 2102 2103 /* 2104 * Current string of incoming characters ended because 2105 * no more data was available or we ran out of space. 2106 * Schedule a receive event if any data was received. 2107 * If we're out of space, turn off receive interrupts. 2108 */ 2109 sc->sc_rbput = put; 2110 sc->sc_rbavail = cc; 2111 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2112 sc->sc_rx_ready = 1; 2113 2114 /* 2115 * See if we are in danger of overflowing a buffer. If 2116 * so, use hardware flow control to ease the pressure. 2117 */ 2118 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2119 cc < sc->sc_r_hiwat) { 2120 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2121 com_hwiflow(sc); 2122 } 2123 2124 /* 2125 * If we're out of space, disable receive interrupts 2126 * until the queue has drained a bit. 2127 */ 2128 if (!cc) { 2129 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2130 #ifdef COM_PXA2X0 2131 if (sc->sc_type == COM_TYPE_PXA2x0) 2132 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2133 else 2134 #endif 2135 CLR(sc->sc_ier, IER_ERXRDY); 2136 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2137 } 2138 } else { 2139 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2140 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2141 continue; 2142 } 2143 } 2144 2145 msr = CSR_READ_1(regsp, COM_REG_MSR); 2146 delta = msr ^ sc->sc_msr; 2147 sc->sc_msr = msr; 2148 #ifdef __HAVE_TIMECOUNTER 2149 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2150 (delta & MSR_DCD)) { 2151 pps_capture(&sc->sc_pps_state); 2152 pps_event(&sc->sc_pps_state, 2153 (msr & MSR_DCD) ? 2154 PPS_CAPTUREASSERT : 2155 PPS_CAPTURECLEAR); 2156 } 2157 #else /* !__HAVE_TIMECOUNTER */ 2158 /* 2159 * Pulse-per-second (PSS) signals on edge of DCD? 2160 * Process these even if line discipline is ignoring DCD. 2161 */ 2162 if (delta & sc->sc_ppsmask) { 2163 struct timeval tv; 2164 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2165 /* XXX nanotime() */ 2166 microtime(&tv); 2167 TIMEVAL_TO_TIMESPEC(&tv, 2168 &sc->ppsinfo.assert_timestamp); 2169 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2170 timespecadd(&sc->ppsinfo.assert_timestamp, 2171 &sc->ppsparam.assert_offset, 2172 &sc->ppsinfo.assert_timestamp); 2173 } 2174 2175 #ifdef PPS_SYNC 2176 if (pps_kc_hardpps_source == sc && 2177 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2178 hardpps(&tv, tv.tv_usec); 2179 } 2180 #endif 2181 sc->ppsinfo.assert_sequence++; 2182 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2183 2184 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2185 /* XXX nanotime() */ 2186 microtime(&tv); 2187 TIMEVAL_TO_TIMESPEC(&tv, 2188 &sc->ppsinfo.clear_timestamp); 2189 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2190 timespecadd(&sc->ppsinfo.clear_timestamp, 2191 &sc->ppsparam.clear_offset, 2192 &sc->ppsinfo.clear_timestamp); 2193 } 2194 2195 #ifdef PPS_SYNC 2196 if (pps_kc_hardpps_source == sc && 2197 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2198 hardpps(&tv, tv.tv_usec); 2199 } 2200 #endif 2201 sc->ppsinfo.clear_sequence++; 2202 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2203 } 2204 } 2205 #endif /* !__HAVE_TIMECOUNTER */ 2206 2207 /* 2208 * Process normal status changes 2209 */ 2210 if (ISSET(delta, sc->sc_msr_mask)) { 2211 SET(sc->sc_msr_delta, delta); 2212 2213 /* 2214 * Stop output immediately if we lose the output 2215 * flow control signal or carrier detect. 2216 */ 2217 if (ISSET(~msr, sc->sc_msr_mask)) { 2218 sc->sc_tbc = 0; 2219 sc->sc_heldtbc = 0; 2220 #ifdef COM_DEBUG 2221 if (com_debug) 2222 comstatus(sc, "comintr "); 2223 #endif 2224 } 2225 2226 sc->sc_st_check = 1; 2227 } 2228 } while (!ISSET((iir = 2229 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2230 /* 2231 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2232 * by IIR read, so we can't do this way: `process all interrupts, 2233 * then do TX if possble'. 2234 */ 2235 (iir & IIR_IMASK) != IIR_TXRDY); 2236 2237 /* 2238 * Read LSR again, since there may be an interrupt between 2239 * the last LSR read and IIR read above. 2240 */ 2241 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2242 2243 /* 2244 * See if data can be transmitted as well. 2245 * Schedule tx done event if no data left 2246 * and tty was marked busy. 2247 */ 2248 if (ISSET(lsr, LSR_TXRDY)) { 2249 /* 2250 * If we've delayed a parameter change, do it now, and restart 2251 * output. 2252 */ 2253 if (sc->sc_heldchange) { 2254 com_loadchannelregs(sc); 2255 sc->sc_heldchange = 0; 2256 sc->sc_tbc = sc->sc_heldtbc; 2257 sc->sc_heldtbc = 0; 2258 } 2259 2260 /* Output the next chunk of the contiguous buffer, if any. */ 2261 if (sc->sc_tbc > 0) { 2262 u_int n; 2263 2264 n = sc->sc_tbc; 2265 if (n > sc->sc_fifolen) 2266 n = sc->sc_fifolen; 2267 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2268 sc->sc_tbc -= n; 2269 sc->sc_tba += n; 2270 } else { 2271 /* Disable transmit completion interrupts if necessary. */ 2272 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2273 CLR(sc->sc_ier, IER_ETXRDY); 2274 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2275 } 2276 if (sc->sc_tx_busy) { 2277 sc->sc_tx_busy = 0; 2278 sc->sc_tx_done = 1; 2279 } 2280 } 2281 } 2282 2283 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2284 goto again; 2285 2286 COM_UNLOCK(sc); 2287 2288 /* Wake up the poller. */ 2289 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2290 softintr_schedule(sc->sc_si); 2291 #else 2292 #ifndef __NO_SOFT_SERIAL_INTERRUPT 2293 setsoftserial(); 2294 #else 2295 if (!com_softintr_scheduled) { 2296 com_softintr_scheduled = 1; 2297 callout_reset(&comsoft_callout, 1, comsoft, NULL); 2298 } 2299 #endif 2300 #endif 2301 2302 #if NRND > 0 && defined(RND_COM) 2303 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2304 #endif 2305 2306 return (1); 2307 } 2308 2309 /* 2310 * The following functions are polled getc and putc routines, shared 2311 * by the console and kgdb glue. 2312 * 2313 * The read-ahead code is so that you can detect pending in-band 2314 * cn_magic in polled mode while doing output rather than having to 2315 * wait until the kernel decides it needs input. 2316 */ 2317 2318 #define MAX_READAHEAD 20 2319 static int com_readahead[MAX_READAHEAD]; 2320 static int com_readaheadcount = 0; 2321 2322 int 2323 com_common_getc(dev_t dev, struct com_regs *regsp) 2324 { 2325 int s = splserial(); 2326 u_char stat, c; 2327 2328 /* got a character from reading things earlier */ 2329 if (com_readaheadcount > 0) { 2330 int i; 2331 2332 c = com_readahead[0]; 2333 for (i = 1; i < com_readaheadcount; i++) { 2334 com_readahead[i-1] = com_readahead[i]; 2335 } 2336 com_readaheadcount--; 2337 splx(s); 2338 return (c); 2339 } 2340 2341 /* block until a character becomes available */ 2342 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2343 ; 2344 2345 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2346 stat = CSR_READ_1(regsp, COM_REG_IIR); 2347 { 2348 int cn_trapped = 0; /* unused */ 2349 #ifdef DDB 2350 extern int db_active; 2351 if (!db_active) 2352 #endif 2353 cn_check_magic(dev, c, com_cnm_state); 2354 } 2355 splx(s); 2356 return (c); 2357 } 2358 2359 void 2360 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2361 { 2362 int s = splserial(); 2363 int cin, stat, timo; 2364 2365 if (com_readaheadcount < MAX_READAHEAD 2366 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2367 int cn_trapped = 0; 2368 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2369 stat = CSR_READ_1(regsp, COM_REG_IIR); 2370 cn_check_magic(dev, cin, com_cnm_state); 2371 com_readahead[com_readaheadcount++] = cin; 2372 } 2373 2374 /* wait for any pending transmission to finish */ 2375 timo = 150000; 2376 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2377 continue; 2378 2379 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2380 COM_BARRIER(regsp, BR | BW); 2381 2382 splx(s); 2383 } 2384 2385 /* 2386 * Initialize UART for use as console or KGDB line. 2387 */ 2388 int 2389 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2390 tcflag_t cflag) 2391 { 2392 2393 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2394 ®sp->cr_ioh)) 2395 return (ENOMEM); /* ??? */ 2396 2397 rate = comspeed(rate, frequency, type); 2398 if (type != COM_TYPE_AU1x00) { 2399 /* no EFR on alchemy */ 2400 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2401 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2402 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2403 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2404 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2405 } else { 2406 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2407 } 2408 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2409 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2410 CSR_WRITE_1(regsp, COM_REG_FIFO, 2411 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2412 #ifdef COM_PXA2X0 2413 if (type == COM_TYPE_PXA2x0) 2414 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2415 else 2416 #endif 2417 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2418 2419 return (0); 2420 } 2421 2422 /* 2423 * Following are all routines needed for COM to act as console 2424 */ 2425 struct consdev comcons = { 2426 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2427 NODEV, CN_NORMAL 2428 }; 2429 2430 2431 int 2432 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2433 tcflag_t cflag) 2434 { 2435 int res; 2436 2437 comconsregs = *regsp; 2438 2439 res = cominit(&comconsregs, rate, frequency, type, cflag); 2440 if (res) 2441 return (res); 2442 2443 cn_tab = &comcons; 2444 cn_init_magic(&com_cnm_state); 2445 cn_set_magic("\047\001"); /* default magic is BREAK */ 2446 2447 comconsrate = rate; 2448 comconscflag = cflag; 2449 2450 return (0); 2451 } 2452 2453 int 2454 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2455 int type, tcflag_t cflag) 2456 { 2457 struct com_regs regs; 2458 2459 memset(®s, 0, sizeof regs); 2460 regs.cr_iot = iot; 2461 regs.cr_iobase = iobase; 2462 regs.cr_nports = COM_NPORTS; 2463 #ifdef COM_REGMAP 2464 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2465 #endif 2466 2467 return comcnattach1(®s, rate, frequency, type, cflag); 2468 } 2469 2470 int 2471 comcngetc(dev_t dev) 2472 { 2473 2474 return (com_common_getc(dev, &comconsregs)); 2475 } 2476 2477 /* 2478 * Console kernel output character routine. 2479 */ 2480 void 2481 comcnputc(dev_t dev, int c) 2482 { 2483 2484 com_common_putc(dev, &comconsregs, c); 2485 } 2486 2487 void 2488 comcnpollc(dev_t dev, int on) 2489 { 2490 2491 } 2492 2493 #ifdef KGDB 2494 int 2495 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2496 tcflag_t cflag) 2497 { 2498 int res; 2499 2500 if (regsp->cr_iot == comconsregs.cr_iot && 2501 regsp->cr_iobase == comconsregs.cr_iobase) { 2502 #if !defined(DDB) 2503 return (EBUSY); /* cannot share with console */ 2504 #else 2505 comkgdbregs = *regsp; 2506 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2507 #endif 2508 } else { 2509 comkgdbregs = *regsp; 2510 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2511 if (res) 2512 return (res); 2513 2514 /* 2515 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2516 * expects this to be initialized 2517 */ 2518 cn_init_magic(&com_cnm_state); 2519 cn_set_magic("\047\001"); 2520 } 2521 2522 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2523 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2524 2525 return (0); 2526 } 2527 2528 int 2529 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2530 int frequency, int type, tcflag_t cflag) 2531 { 2532 struct com_regs regs; 2533 2534 regs.cr_iot = iot; 2535 regs.cr_nports = COM_NPORTS; 2536 regs.cr_iobase = iobase; 2537 #ifdef COM_REGMAP 2538 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2539 #endif 2540 2541 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2542 } 2543 2544 /* ARGSUSED */ 2545 int 2546 com_kgdb_getc(void *arg) 2547 { 2548 2549 return (com_common_getc(NODEV, &comkgdbregs)); 2550 } 2551 2552 /* ARGSUSED */ 2553 void 2554 com_kgdb_putc(void *arg, int c) 2555 { 2556 2557 com_common_putc(NODEV, &comkgdbregs, c); 2558 } 2559 #endif /* KGDB */ 2560 2561 /* helper function to identify the com ports used by 2562 console or KGDB (and not yet autoconf attached) */ 2563 int 2564 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2565 { 2566 bus_space_handle_t help; 2567 2568 if (!comconsattached && 2569 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2570 help = comconsregs.cr_ioh; 2571 #ifdef KGDB 2572 else if (!com_kgdb_attached && 2573 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2574 help = comkgdbregs.cr_ioh; 2575 #endif 2576 else 2577 return (0); 2578 2579 if (ioh) 2580 *ioh = help; 2581 return (1); 2582 } 2583 2584 /* 2585 * this routine exists to serve as a shutdown hook for systems that 2586 * have firmware which doesn't interact properly with a com device in 2587 * FIFO mode. 2588 */ 2589 void 2590 com_cleanup(void *arg) 2591 { 2592 struct com_softc *sc = arg; 2593 2594 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2595 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2596 } 2597 2598 void 2599 com_power(int why, void *arg) 2600 { 2601 struct com_softc *sc = arg; 2602 int s; 2603 2604 s = splserial(); 2605 switch (why) { 2606 case PWR_SUSPEND: 2607 case PWR_STANDBY: 2608 /* XXX should we do something to stop the device? */ 2609 break; 2610 case PWR_RESUME: 2611 com_loadchannelregs(sc); 2612 break; 2613 case PWR_SOFTSUSPEND: 2614 case PWR_SOFTSTANDBY: 2615 case PWR_SOFTRESUME: 2616 break; 2617 } 2618 splx(s); 2619 } 2620
Indexes created Wed Sep 24 15:09:51 GMT 2025