com.c revision 1.259
1 /* $NetBSD: com.c,v 1.259 2007/03/04 06:01:53 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.259 2007/03/04 06:01:53 christos Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 194 void comsoft(void *); 195 #else 196 #ifndef __NO_SOFT_SERIAL_INTERRUPT 197 void comsoft(void); 198 #else 199 void comsoft(void *); 200 static struct callout comsoft_callout = CALLOUT_INITIALIZER; 201 #endif 202 #endif 203 integrate void com_rxsoft(struct com_softc *, struct tty *); 204 integrate void com_txsoft(struct com_softc *, struct tty *); 205 integrate void com_stsoft(struct com_softc *, struct tty *); 206 integrate void com_schedrx(struct com_softc *); 207 void comdiag(void *); 208 209 extern struct cfdriver com_cd; 210 211 dev_type_open(comopen); 212 dev_type_close(comclose); 213 dev_type_read(comread); 214 dev_type_write(comwrite); 215 dev_type_ioctl(comioctl); 216 dev_type_stop(comstop); 217 dev_type_tty(comtty); 218 dev_type_poll(compoll); 219 220 const struct cdevsw com_cdevsw = { 221 comopen, comclose, comread, comwrite, comioctl, 222 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 223 }; 224 225 /* 226 * Make this an option variable one can patch. 227 * But be warned: this must be a power of 2! 228 */ 229 u_int com_rbuf_size = COM_RING_SIZE; 230 231 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 232 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 233 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 234 235 static struct com_regs comconsregs; 236 static int comconsattached; 237 static int comconsrate; 238 static tcflag_t comconscflag; 239 static struct cnm_state com_cnm_state; 240 241 #ifndef __HAVE_TIMECOUNTER 242 static int ppscap = 243 PPS_TSFMT_TSPEC | 244 PPS_CAPTUREASSERT | 245 PPS_CAPTURECLEAR | 246 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 247 #endif /* !__HAVE_TIMECOUNTER */ 248 249 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 250 #ifdef __NO_SOFT_SERIAL_INTERRUPT 251 volatile int com_softintr_scheduled; 252 #endif 253 #endif 254 255 #ifdef KGDB 256 #include <sys/kgdb.h> 257 258 static struct com_regs comkgdbregs; 259 static int com_kgdb_attached; 260 261 int com_kgdb_getc(void *); 262 void com_kgdb_putc(void *, int); 263 #endif /* KGDB */ 264 265 #ifdef COM_REGMAP 266 /* initializer for typical 16550-ish hardware */ 267 #define COM_REG_16550 { \ 268 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 269 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 270 271 const bus_size_t com_std_map[16] = COM_REG_16550; 272 #endif /* COM_REGMAP */ 273 274 #define COMUNIT_MASK 0x7ffff 275 #define COMDIALOUT_MASK 0x80000 276 277 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 278 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 279 280 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 281 device_is_active(&(sc)->sc_dev)) 282 283 #define BR BUS_SPACE_BARRIER_READ 284 #define BW BUS_SPACE_BARRIER_WRITE 285 #define COM_BARRIER(r, f) \ 286 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 287 288 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 289 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 290 291 /*ARGSUSED*/ 292 int 293 comspeed(long speed, long frequency, int type) 294 { 295 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 296 297 int x, err; 298 299 #if 0 300 if (speed == 0) 301 return (0); 302 #endif 303 if (speed <= 0) 304 return (-1); 305 x = divrnd(frequency / 16, speed); 306 if (x <= 0) 307 return (-1); 308 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 309 if (err < 0) 310 err = -err; 311 if (err > COM_TOLERANCE) 312 return (-1); 313 return (x); 314 315 #undef divrnd 316 } 317 318 #ifdef COM_DEBUG 319 int com_debug = 0; 320 321 void comstatus(struct com_softc *, const char *); 322 void 323 comstatus(struct com_softc *sc, const char *str) 324 { 325 struct tty *tp = sc->sc_tty; 326 327 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 328 sc->sc_dev.dv_xname, str, 329 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 331 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 333 sc->sc_tx_stopped ? '+' : '-'); 334 335 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 sc->sc_dev.dv_xname, str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 static void 374 com_enable_debugport(struct com_softc *sc) 375 { 376 int s; 377 378 /* Turn on line break interrupt, set carrier. */ 379 s = splserial(); 380 COM_LOCK(sc); 381 sc->sc_ier = IER_ERXRDY; 382 if (sc->sc_type == COM_TYPE_PXA2x0) 383 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 384 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 385 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 386 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 387 COM_UNLOCK(sc); 388 splx(s); 389 } 390 391 void 392 com_attach_subr(struct com_softc *sc) 393 { 394 struct com_regs *regsp = &sc->sc_regs; 395 struct tty *tp; 396 #ifdef COM_16650 397 u_int8_t lcr; 398 #endif 399 const char *fifo_msg = NULL; 400 401 aprint_naive("\n"); 402 403 callout_init(&sc->sc_diag_callout); 404 simple_lock_init(&sc->sc_lock); 405 406 /* Disable interrupts before configuring the device. */ 407 if (sc->sc_type == COM_TYPE_PXA2x0) 408 sc->sc_ier = IER_EUART; 409 else 410 sc->sc_ier = 0; 411 412 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 413 414 if (regsp->cr_iot == comconsregs.cr_iot && 415 regsp->cr_iobase == comconsregs.cr_iobase) { 416 comconsattached = 1; 417 418 /* Make sure the console is always "hardwired". */ 419 delay(10000); /* wait for output to finish */ 420 SET(sc->sc_hwflags, COM_HW_CONSOLE); 421 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 422 } 423 424 /* Probe for FIFO */ 425 switch (sc->sc_type) { 426 case COM_TYPE_HAYESP: 427 goto fifodone; 428 429 case COM_TYPE_AU1x00: 430 sc->sc_fifolen = 16; 431 fifo_msg = "Au1X00 UART, working fifo"; 432 SET(sc->sc_hwflags, COM_HW_FIFO); 433 goto fifodelay; 434 } 435 436 sc->sc_fifolen = 1; 437 /* look for a NS 16550AF UART with FIFOs */ 438 CSR_WRITE_1(regsp, COM_REG_FIFO, 439 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 440 delay(100); 441 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 442 == IIR_FIFO_MASK) 443 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 444 == FIFO_TRIGGER_14) { 445 SET(sc->sc_hwflags, COM_HW_FIFO); 446 447 #ifdef COM_16650 448 /* 449 * IIR changes into the EFR if LCR is set to LCR_EERS 450 * on 16650s. We also know IIR != 0 at this point. 451 * Write 0 into the EFR, and read it. If the result 452 * is 0, we have a 16650. 453 * 454 * Older 16650s were broken; the test to detect them 455 * is taken from the Linux driver. Apparently 456 * setting DLAB enable gives access to the EFR on 457 * these chips. 458 */ 459 lcr = CSR_READ_1(regsp, COM_REG_LCR); 460 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 461 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 462 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 463 CSR_WRITE_1(regsp, COM_REG_LCR, 464 lcr | LCR_DLAB); 465 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 466 CLR(sc->sc_hwflags, COM_HW_FIFO); 467 sc->sc_fifolen = 0; 468 } else { 469 SET(sc->sc_hwflags, COM_HW_FLOW); 470 sc->sc_fifolen = 32; 471 } 472 } else 473 #endif 474 sc->sc_fifolen = 16; 475 476 #ifdef COM_16650 477 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 478 if (sc->sc_fifolen == 0) 479 fifo_msg = "st16650, broken fifo"; 480 else if (sc->sc_fifolen == 32) 481 fifo_msg = "st16650a, working fifo"; 482 else 483 #endif 484 fifo_msg = "ns16550a, working fifo"; 485 } else 486 fifo_msg = "ns16550, broken fifo"; 487 else 488 fifo_msg = "ns8250 or ns16450, no fifo"; 489 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 490 fifodelay: 491 /* 492 * Some chips will clear down both Tx and Rx FIFOs when zero is 493 * written to com_fifo. If this chip is the console, writing zero 494 * results in some of the chip/FIFO description being lost, so delay 495 * printing it until now. 496 */ 497 delay(10); 498 aprint_normal(": %s\n", fifo_msg); 499 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 500 sc->sc_fifolen = 1; 501 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 502 } 503 504 fifodone: 505 506 tp = ttymalloc(); 507 tp->t_oproc = comstart; 508 tp->t_param = comparam; 509 tp->t_hwiflow = comhwiflow; 510 511 sc->sc_tty = tp; 512 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 513 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 514 sc->sc_rbavail = com_rbuf_size; 515 if (sc->sc_rbuf == NULL) { 516 aprint_error("%s: unable to allocate ring buffer\n", 517 sc->sc_dev.dv_xname); 518 return; 519 } 520 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 521 522 tty_attach(tp); 523 524 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 525 SET(sc->sc_mcr, MCR_IENABLE); 526 527 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 528 int maj; 529 530 /* locate the major number */ 531 maj = cdevsw_lookup_major(&com_cdevsw); 532 533 tp->t_dev = cn_tab->cn_dev = makedev(maj, 534 device_unit(&sc->sc_dev)); 535 536 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 537 } 538 539 #ifdef KGDB 540 /* 541 * Allow kgdb to "take over" this port. If this is 542 * not the console and is the kgdb device, it has 543 * exclusive use. If it's the console _and_ the 544 * kgdb device, it doesn't. 545 */ 546 if (regsp->cr_iot == comkgdbregs.cr_iot && 547 regsp->cr_iobase == comkgdbregs.cr_iobase) { 548 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 549 com_kgdb_attached = 1; 550 551 SET(sc->sc_hwflags, COM_HW_KGDB); 552 } 553 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 554 } 555 #endif 556 557 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 558 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 559 #endif 560 561 #if NRND > 0 && defined(RND_COM) 562 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 563 RND_TYPE_TTY, 0); 564 #endif 565 566 /* if there are no enable/disable functions, assume the device 567 is always enabled */ 568 if (!sc->enable) 569 sc->enabled = 1; 570 571 com_config(sc); 572 573 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 574 com_power, sc); 575 if (sc->sc_powerhook == NULL) 576 aprint_error("%s: WARNING: unable to establish power hook\n", 577 sc->sc_dev.dv_xname); 578 579 SET(sc->sc_hwflags, COM_HW_DEV_OK); 580 } 581 582 void 583 com_config(struct com_softc *sc) 584 { 585 struct com_regs *regsp = &sc->sc_regs; 586 587 /* Disable interrupts before configuring the device. */ 588 if (sc->sc_type == COM_TYPE_PXA2x0) 589 sc->sc_ier = IER_EUART; 590 else 591 sc->sc_ier = 0; 592 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 593 (void) CSR_READ_1(regsp, COM_REG_IIR); 594 595 #ifdef COM_HAYESP 596 /* Look for a Hayes ESP board. */ 597 if (sc->sc_type == COM_TYPE_HAYESP) { 598 599 /* Set 16550 compatibility mode */ 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 601 HAYESP_SETMODE); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 604 HAYESP_MODE_SCALE); 605 606 /* Set RTS/CTS flow control */ 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 608 HAYESP_SETFLOWTYPE); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_FLOW_RTS); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_FLOW_CTS); 613 614 /* Set flow control levels */ 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 616 HAYESP_SETRXFLOW); 617 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 618 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 619 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 621 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 622 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 623 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 624 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 625 } 626 #endif 627 628 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 629 com_enable_debugport(sc); 630 } 631 632 int 633 com_detach(struct device *self, int flags) 634 { 635 struct com_softc *sc = (struct com_softc *)self; 636 int maj, mn; 637 638 /* kill the power hook */ 639 if (sc->sc_powerhook != NULL) 640 powerhook_disestablish(sc->sc_powerhook); 641 642 /* locate the major number */ 643 maj = cdevsw_lookup_major(&com_cdevsw); 644 645 /* Nuke the vnodes for any open instances. */ 646 mn = device_unit(self); 647 vdevgone(maj, mn, mn, VCHR); 648 649 mn |= COMDIALOUT_MASK; 650 vdevgone(maj, mn, mn, VCHR); 651 652 if (sc->sc_rbuf == NULL) { 653 /* 654 * Ring buffer allocation failed in the com_attach_subr, 655 * only the tty is allocated, and nothing else. 656 */ 657 ttyfree(sc->sc_tty); 658 return 0; 659 } 660 661 /* Free the receive buffer. */ 662 free(sc->sc_rbuf, M_DEVBUF); 663 664 /* Detach and free the tty. */ 665 tty_detach(sc->sc_tty); 666 ttyfree(sc->sc_tty); 667 668 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 669 /* Unhook the soft interrupt handler. */ 670 softintr_disestablish(sc->sc_si); 671 #endif 672 673 #if NRND > 0 && defined(RND_COM) 674 /* Unhook the entropy source. */ 675 rnd_detach_source(&sc->rnd_source); 676 #endif 677 678 return (0); 679 } 680 681 int 682 com_activate(struct device *self, enum devact act) 683 { 684 struct com_softc *sc = (struct com_softc *)self; 685 int s, rv = 0; 686 687 s = splserial(); 688 COM_LOCK(sc); 689 switch (act) { 690 case DVACT_ACTIVATE: 691 rv = EOPNOTSUPP; 692 break; 693 694 case DVACT_DEACTIVATE: 695 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 696 rv = EBUSY; 697 break; 698 } 699 700 if (sc->disable != NULL && sc->enabled != 0) { 701 (*sc->disable)(sc); 702 sc->enabled = 0; 703 } 704 break; 705 } 706 707 COM_UNLOCK(sc); 708 splx(s); 709 return (rv); 710 } 711 712 void 713 com_shutdown(struct com_softc *sc) 714 { 715 struct tty *tp = sc->sc_tty; 716 int s; 717 718 s = splserial(); 719 COM_LOCK(sc); 720 721 /* If we were asserting flow control, then deassert it. */ 722 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 723 com_hwiflow(sc); 724 725 /* Clear any break condition set with TIOCSBRK. */ 726 com_break(sc, 0); 727 728 #ifndef __HAVE_TIMECOUNTER 729 /* Turn off PPS capture on last close. */ 730 sc->sc_ppsmask = 0; 731 sc->ppsparam.mode = 0; 732 #endif /* !__HAVE_TIMECOUNTER */ 733 734 /* 735 * Hang up if necessary. Wait a bit, so the other side has time to 736 * notice even if we immediately open the port again. 737 * Avoid tsleeping above splhigh(). 738 */ 739 if (ISSET(tp->t_cflag, HUPCL)) { 740 com_modem(sc, 0); 741 COM_UNLOCK(sc); 742 splx(s); 743 /* XXX tsleep will only timeout */ 744 (void) tsleep(sc, TTIPRI, ttclos, hz); 745 s = splserial(); 746 COM_LOCK(sc); 747 } 748 749 /* Turn off interrupts. */ 750 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 751 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 752 if (sc->sc_type == COM_TYPE_PXA2x0) 753 sc->sc_ier |= IER_ERXTOUT; 754 } else 755 sc->sc_ier = 0; 756 757 if (sc->sc_type == COM_TYPE_PXA2x0) 758 sc->sc_ier |= IER_EUART; 759 760 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 761 762 if (sc->disable) { 763 #ifdef DIAGNOSTIC 764 if (!sc->enabled) 765 panic("com_shutdown: not enabled?"); 766 #endif 767 (*sc->disable)(sc); 768 sc->enabled = 0; 769 } 770 COM_UNLOCK(sc); 771 splx(s); 772 } 773 774 int 775 comopen(dev_t dev, int flag, int mode, struct lwp *l) 776 { 777 struct com_softc *sc; 778 struct tty *tp; 779 int s, s2; 780 int error; 781 782 sc = device_lookup(&com_cd, COMUNIT(dev)); 783 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 784 sc->sc_rbuf == NULL) 785 return (ENXIO); 786 787 if (!device_is_active(&sc->sc_dev)) 788 return (ENXIO); 789 790 #ifdef KGDB 791 /* 792 * If this is the kgdb port, no other use is permitted. 793 */ 794 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 795 return (EBUSY); 796 #endif 797 798 tp = sc->sc_tty; 799 800 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 801 return (EBUSY); 802 803 s = spltty(); 804 805 /* 806 * Do the following iff this is a first open. 807 */ 808 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 809 struct termios t; 810 811 tp->t_dev = dev; 812 813 s2 = splserial(); 814 COM_LOCK(sc); 815 816 if (sc->enable) { 817 if ((*sc->enable)(sc)) { 818 COM_UNLOCK(sc); 819 splx(s2); 820 splx(s); 821 printf("%s: device enable failed\n", 822 sc->sc_dev.dv_xname); 823 return (EIO); 824 } 825 sc->enabled = 1; 826 com_config(sc); 827 } 828 829 /* Turn on interrupts. */ 830 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 831 if (sc->sc_type == COM_TYPE_PXA2x0) 832 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 833 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 834 835 /* Fetch the current modem control status, needed later. */ 836 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 837 838 /* Clear PPS capture state on first open. */ 839 #ifdef __HAVE_TIMECOUNTER 840 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 841 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 842 pps_init(&sc->sc_pps_state); 843 #else /* !__HAVE_TIMECOUNTER */ 844 sc->sc_ppsmask = 0; 845 sc->ppsparam.mode = 0; 846 #endif /* !__HAVE_TIMECOUNTER */ 847 848 COM_UNLOCK(sc); 849 splx(s2); 850 851 /* 852 * Initialize the termios status to the defaults. Add in the 853 * sticky bits from TIOCSFLAGS. 854 */ 855 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 856 t.c_ospeed = comconsrate; 857 t.c_cflag = comconscflag; 858 } else { 859 t.c_ospeed = TTYDEF_SPEED; 860 t.c_cflag = TTYDEF_CFLAG; 861 } 862 t.c_ispeed = t.c_ospeed; 863 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 864 SET(t.c_cflag, CLOCAL); 865 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 866 SET(t.c_cflag, CRTSCTS); 867 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 868 SET(t.c_cflag, MDMBUF); 869 /* Make sure comparam() will do something. */ 870 tp->t_ospeed = 0; 871 (void) comparam(tp, &t); 872 tp->t_iflag = TTYDEF_IFLAG; 873 tp->t_oflag = TTYDEF_OFLAG; 874 tp->t_lflag = TTYDEF_LFLAG; 875 ttychars(tp); 876 ttsetwater(tp); 877 878 s2 = splserial(); 879 COM_LOCK(sc); 880 881 /* 882 * Turn on DTR. We must always do this, even if carrier is not 883 * present, because otherwise we'd have to use TIOCSDTR 884 * immediately after setting CLOCAL, which applications do not 885 * expect. We always assert DTR while the device is open 886 * unless explicitly requested to deassert it. 887 */ 888 com_modem(sc, 1); 889 890 /* Clear the input ring, and unblock. */ 891 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 892 sc->sc_rbavail = com_rbuf_size; 893 com_iflush(sc); 894 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 895 com_hwiflow(sc); 896 897 #ifdef COM_DEBUG 898 if (com_debug) 899 comstatus(sc, "comopen "); 900 #endif 901 902 COM_UNLOCK(sc); 903 splx(s2); 904 } 905 906 splx(s); 907 908 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 909 if (error) 910 goto bad; 911 912 error = (*tp->t_linesw->l_open)(dev, tp); 913 if (error) 914 goto bad; 915 916 return (0); 917 918 bad: 919 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 920 /* 921 * We failed to open the device, and nobody else had it opened. 922 * Clean up the state as appropriate. 923 */ 924 com_shutdown(sc); 925 } 926 927 return (error); 928 } 929 930 int 931 comclose(dev_t dev, int flag, int mode, struct lwp *l) 932 { 933 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 934 struct tty *tp = sc->sc_tty; 935 936 /* XXX This is for cons.c. */ 937 if (!ISSET(tp->t_state, TS_ISOPEN)) 938 return (0); 939 940 (*tp->t_linesw->l_close)(tp, flag); 941 ttyclose(tp); 942 943 if (COM_ISALIVE(sc) == 0) 944 return (0); 945 946 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 947 /* 948 * Although we got a last close, the device may still be in 949 * use; e.g. if this was the dialout node, and there are still 950 * processes waiting for carrier on the non-dialout node. 951 */ 952 com_shutdown(sc); 953 } 954 955 return (0); 956 } 957 958 int 959 comread(dev_t dev, struct uio *uio, int flag) 960 { 961 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 962 struct tty *tp = sc->sc_tty; 963 964 if (COM_ISALIVE(sc) == 0) 965 return (EIO); 966 967 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 968 } 969 970 int 971 comwrite(dev_t dev, struct uio *uio, int flag) 972 { 973 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 974 struct tty *tp = sc->sc_tty; 975 976 if (COM_ISALIVE(sc) == 0) 977 return (EIO); 978 979 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 980 } 981 982 int 983 compoll(dev_t dev, int events, struct lwp *l) 984 { 985 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 986 struct tty *tp = sc->sc_tty; 987 988 if (COM_ISALIVE(sc) == 0) 989 return (POLLHUP); 990 991 return ((*tp->t_linesw->l_poll)(tp, events, l)); 992 } 993 994 struct tty * 995 comtty(dev_t dev) 996 { 997 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 998 struct tty *tp = sc->sc_tty; 999 1000 return (tp); 1001 } 1002 1003 int 1004 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1005 { 1006 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 1007 struct tty *tp = sc->sc_tty; 1008 int error; 1009 int s; 1010 1011 if (COM_ISALIVE(sc) == 0) 1012 return (EIO); 1013 1014 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1015 if (error != EPASSTHROUGH) 1016 return (error); 1017 1018 error = ttioctl(tp, cmd, data, flag, l); 1019 if (error != EPASSTHROUGH) 1020 return (error); 1021 1022 error = 0; 1023 switch (cmd) { 1024 case TIOCSFLAGS: 1025 error = kauth_authorize_device_tty(l->l_cred, 1026 KAUTH_DEVICE_TTY_PRIVSET, tp); 1027 break; 1028 default: 1029 /* nothing */ 1030 break; 1031 } 1032 if (error) { 1033 return error; 1034 } 1035 1036 s = splserial(); 1037 COM_LOCK(sc); 1038 1039 switch (cmd) { 1040 case TIOCSBRK: 1041 com_break(sc, 1); 1042 break; 1043 1044 case TIOCCBRK: 1045 com_break(sc, 0); 1046 break; 1047 1048 case TIOCSDTR: 1049 com_modem(sc, 1); 1050 break; 1051 1052 case TIOCCDTR: 1053 com_modem(sc, 0); 1054 break; 1055 1056 case TIOCGFLAGS: 1057 *(int *)data = sc->sc_swflags; 1058 break; 1059 1060 case TIOCSFLAGS: 1061 sc->sc_swflags = *(int *)data; 1062 break; 1063 1064 case TIOCMSET: 1065 case TIOCMBIS: 1066 case TIOCMBIC: 1067 tiocm_to_com(sc, cmd, *(int *)data); 1068 break; 1069 1070 case TIOCMGET: 1071 *(int *)data = com_to_tiocm(sc); 1072 break; 1073 1074 #ifdef __HAVE_TIMECOUNTER 1075 case PPS_IOC_CREATE: 1076 case PPS_IOC_DESTROY: 1077 case PPS_IOC_GETPARAMS: 1078 case PPS_IOC_SETPARAMS: 1079 case PPS_IOC_GETCAP: 1080 case PPS_IOC_FETCH: 1081 #ifdef PPS_SYNC 1082 case PPS_IOC_KCBIND: 1083 #endif 1084 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1085 break; 1086 #else /* !__HAVE_TIMECOUNTER */ 1087 case PPS_IOC_CREATE: 1088 break; 1089 1090 case PPS_IOC_DESTROY: 1091 break; 1092 1093 case PPS_IOC_GETPARAMS: { 1094 pps_params_t *pp; 1095 pp = (pps_params_t *)data; 1096 *pp = sc->ppsparam; 1097 break; 1098 } 1099 1100 case PPS_IOC_SETPARAMS: { 1101 pps_params_t *pp; 1102 int mode; 1103 pp = (pps_params_t *)data; 1104 if (pp->mode & ~ppscap) { 1105 error = EINVAL; 1106 break; 1107 } 1108 sc->ppsparam = *pp; 1109 /* 1110 * Compute msr masks from user-specified timestamp state. 1111 */ 1112 mode = sc->ppsparam.mode; 1113 switch (mode & PPS_CAPTUREBOTH) { 1114 case 0: 1115 sc->sc_ppsmask = 0; 1116 break; 1117 1118 case PPS_CAPTUREASSERT: 1119 sc->sc_ppsmask = MSR_DCD; 1120 sc->sc_ppsassert = MSR_DCD; 1121 sc->sc_ppsclear = -1; 1122 break; 1123 1124 case PPS_CAPTURECLEAR: 1125 sc->sc_ppsmask = MSR_DCD; 1126 sc->sc_ppsassert = -1; 1127 sc->sc_ppsclear = 0; 1128 break; 1129 1130 case PPS_CAPTUREBOTH: 1131 sc->sc_ppsmask = MSR_DCD; 1132 sc->sc_ppsassert = MSR_DCD; 1133 sc->sc_ppsclear = 0; 1134 break; 1135 1136 default: 1137 error = EINVAL; 1138 break; 1139 } 1140 break; 1141 } 1142 1143 case PPS_IOC_GETCAP: 1144 *(int*)data = ppscap; 1145 break; 1146 1147 case PPS_IOC_FETCH: { 1148 pps_info_t *pi; 1149 pi = (pps_info_t *)data; 1150 *pi = sc->ppsinfo; 1151 break; 1152 } 1153 1154 #ifdef PPS_SYNC 1155 case PPS_IOC_KCBIND: { 1156 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1157 1158 if (edge == 0) { 1159 /* 1160 * remove binding for this source; ignore 1161 * the request if this is not the current 1162 * hardpps source 1163 */ 1164 if (pps_kc_hardpps_source == sc) { 1165 pps_kc_hardpps_source = NULL; 1166 pps_kc_hardpps_mode = 0; 1167 } 1168 } else { 1169 /* 1170 * bind hardpps to this source, replacing any 1171 * previously specified source or edges 1172 */ 1173 pps_kc_hardpps_source = sc; 1174 pps_kc_hardpps_mode = edge; 1175 } 1176 break; 1177 } 1178 #endif /* PPS_SYNC */ 1179 #endif /* !__HAVE_TIMECOUNTER */ 1180 1181 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1182 #ifdef __HAVE_TIMECOUNTER 1183 #ifndef PPS_TRAILING_EDGE 1184 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1185 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1186 #else 1187 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1188 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1189 #endif 1190 #else /* !__HAVE_TIMECOUNTER */ 1191 /* 1192 * Some GPS clocks models use the falling rather than 1193 * rising edge as the on-the-second signal. 1194 * The old API has no way to specify PPS polarity. 1195 */ 1196 sc->sc_ppsmask = MSR_DCD; 1197 #ifndef PPS_TRAILING_EDGE 1198 sc->sc_ppsassert = MSR_DCD; 1199 sc->sc_ppsclear = -1; 1200 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1201 &sc->ppsinfo.assert_timestamp); 1202 #else 1203 sc->sc_ppsassert = -1; 1204 sc->sc_ppsclear = 0; 1205 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1206 &sc->ppsinfo.clear_timestamp); 1207 #endif 1208 #endif /* !__HAVE_TIMECOUNTER */ 1209 break; 1210 1211 default: 1212 error = EPASSTHROUGH; 1213 break; 1214 } 1215 1216 COM_UNLOCK(sc); 1217 splx(s); 1218 1219 #ifdef COM_DEBUG 1220 if (com_debug) 1221 comstatus(sc, "comioctl "); 1222 #endif 1223 1224 return (error); 1225 } 1226 1227 integrate void 1228 com_schedrx(struct com_softc *sc) 1229 { 1230 1231 sc->sc_rx_ready = 1; 1232 1233 /* Wake up the poller. */ 1234 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1235 softintr_schedule(sc->sc_si); 1236 #else 1237 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1238 setsoftserial(); 1239 #else 1240 if (!com_softintr_scheduled) { 1241 com_softintr_scheduled = 1; 1242 callout_reset(&comsoft_callout, 1, comsoft, NULL); 1243 } 1244 #endif 1245 #endif 1246 } 1247 1248 void 1249 com_break(struct com_softc *sc, int onoff) 1250 { 1251 1252 if (onoff) 1253 SET(sc->sc_lcr, LCR_SBREAK); 1254 else 1255 CLR(sc->sc_lcr, LCR_SBREAK); 1256 1257 if (!sc->sc_heldchange) { 1258 if (sc->sc_tx_busy) { 1259 sc->sc_heldtbc = sc->sc_tbc; 1260 sc->sc_tbc = 0; 1261 sc->sc_heldchange = 1; 1262 } else 1263 com_loadchannelregs(sc); 1264 } 1265 } 1266 1267 void 1268 com_modem(struct com_softc *sc, int onoff) 1269 { 1270 1271 if (sc->sc_mcr_dtr == 0) 1272 return; 1273 1274 if (onoff) 1275 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1276 else 1277 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1278 1279 if (!sc->sc_heldchange) { 1280 if (sc->sc_tx_busy) { 1281 sc->sc_heldtbc = sc->sc_tbc; 1282 sc->sc_tbc = 0; 1283 sc->sc_heldchange = 1; 1284 } else 1285 com_loadchannelregs(sc); 1286 } 1287 } 1288 1289 void 1290 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1291 { 1292 u_char combits; 1293 1294 combits = 0; 1295 if (ISSET(ttybits, TIOCM_DTR)) 1296 SET(combits, MCR_DTR); 1297 if (ISSET(ttybits, TIOCM_RTS)) 1298 SET(combits, MCR_RTS); 1299 1300 switch (how) { 1301 case TIOCMBIC: 1302 CLR(sc->sc_mcr, combits); 1303 break; 1304 1305 case TIOCMBIS: 1306 SET(sc->sc_mcr, combits); 1307 break; 1308 1309 case TIOCMSET: 1310 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1311 SET(sc->sc_mcr, combits); 1312 break; 1313 } 1314 1315 if (!sc->sc_heldchange) { 1316 if (sc->sc_tx_busy) { 1317 sc->sc_heldtbc = sc->sc_tbc; 1318 sc->sc_tbc = 0; 1319 sc->sc_heldchange = 1; 1320 } else 1321 com_loadchannelregs(sc); 1322 } 1323 } 1324 1325 int 1326 com_to_tiocm(struct com_softc *sc) 1327 { 1328 u_char combits; 1329 int ttybits = 0; 1330 1331 combits = sc->sc_mcr; 1332 if (ISSET(combits, MCR_DTR)) 1333 SET(ttybits, TIOCM_DTR); 1334 if (ISSET(combits, MCR_RTS)) 1335 SET(ttybits, TIOCM_RTS); 1336 1337 combits = sc->sc_msr; 1338 if (ISSET(combits, MSR_DCD)) 1339 SET(ttybits, TIOCM_CD); 1340 if (ISSET(combits, MSR_CTS)) 1341 SET(ttybits, TIOCM_CTS); 1342 if (ISSET(combits, MSR_DSR)) 1343 SET(ttybits, TIOCM_DSR); 1344 if (ISSET(combits, MSR_RI | MSR_TERI)) 1345 SET(ttybits, TIOCM_RI); 1346 1347 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1348 SET(ttybits, TIOCM_LE); 1349 1350 return (ttybits); 1351 } 1352 1353 static u_char 1354 cflag2lcr(tcflag_t cflag) 1355 { 1356 u_char lcr = 0; 1357 1358 switch (ISSET(cflag, CSIZE)) { 1359 case CS5: 1360 SET(lcr, LCR_5BITS); 1361 break; 1362 case CS6: 1363 SET(lcr, LCR_6BITS); 1364 break; 1365 case CS7: 1366 SET(lcr, LCR_7BITS); 1367 break; 1368 case CS8: 1369 SET(lcr, LCR_8BITS); 1370 break; 1371 } 1372 if (ISSET(cflag, PARENB)) { 1373 SET(lcr, LCR_PENAB); 1374 if (!ISSET(cflag, PARODD)) 1375 SET(lcr, LCR_PEVEN); 1376 } 1377 if (ISSET(cflag, CSTOPB)) 1378 SET(lcr, LCR_STOPB); 1379 1380 return (lcr); 1381 } 1382 1383 int 1384 comparam(struct tty *tp, struct termios *t) 1385 { 1386 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1387 int ospeed; 1388 u_char lcr; 1389 int s; 1390 1391 if (COM_ISALIVE(sc) == 0) 1392 return (EIO); 1393 1394 #ifdef COM_HAYESP 1395 if (sc->sc_type == COM_TYPE_HAYESP) { 1396 int prescaler, speed; 1397 1398 /* 1399 * Calculate UART clock prescaler. It should be in 1400 * range of 0 .. 3. 1401 */ 1402 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1403 prescaler++, speed /= 2) 1404 if ((ospeed = comspeed(speed, sc->sc_frequency, 1405 sc->sc_type)) > 0) 1406 break; 1407 1408 if (prescaler == 4) 1409 return (EINVAL); 1410 sc->sc_prescaler = prescaler; 1411 } else 1412 #endif 1413 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1414 1415 /* Check requested parameters. */ 1416 if (ospeed < 0) 1417 return (EINVAL); 1418 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1419 return (EINVAL); 1420 1421 /* 1422 * For the console, always force CLOCAL and !HUPCL, so that the port 1423 * is always active. 1424 */ 1425 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1426 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1427 SET(t->c_cflag, CLOCAL); 1428 CLR(t->c_cflag, HUPCL); 1429 } 1430 1431 /* 1432 * If there were no changes, don't do anything. This avoids dropping 1433 * input and improves performance when all we did was frob things like 1434 * VMIN and VTIME. 1435 */ 1436 if (tp->t_ospeed == t->c_ospeed && 1437 tp->t_cflag == t->c_cflag) 1438 return (0); 1439 1440 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1441 1442 s = splserial(); 1443 COM_LOCK(sc); 1444 1445 sc->sc_lcr = lcr; 1446 1447 /* 1448 * If we're not in a mode that assumes a connection is present, then 1449 * ignore carrier changes. 1450 */ 1451 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1452 sc->sc_msr_dcd = 0; 1453 else 1454 sc->sc_msr_dcd = MSR_DCD; 1455 /* 1456 * Set the flow control pins depending on the current flow control 1457 * mode. 1458 */ 1459 if (ISSET(t->c_cflag, CRTSCTS)) { 1460 sc->sc_mcr_dtr = MCR_DTR; 1461 sc->sc_mcr_rts = MCR_RTS; 1462 sc->sc_msr_cts = MSR_CTS; 1463 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1464 } else if (ISSET(t->c_cflag, MDMBUF)) { 1465 /* 1466 * For DTR/DCD flow control, make sure we don't toggle DTR for 1467 * carrier detection. 1468 */ 1469 sc->sc_mcr_dtr = 0; 1470 sc->sc_mcr_rts = MCR_DTR; 1471 sc->sc_msr_cts = MSR_DCD; 1472 sc->sc_efr = 0; 1473 } else { 1474 /* 1475 * If no flow control, then always set RTS. This will make 1476 * the other side happy if it mistakenly thinks we're doing 1477 * RTS/CTS flow control. 1478 */ 1479 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1480 sc->sc_mcr_rts = 0; 1481 sc->sc_msr_cts = 0; 1482 sc->sc_efr = 0; 1483 if (ISSET(sc->sc_mcr, MCR_DTR)) 1484 SET(sc->sc_mcr, MCR_RTS); 1485 else 1486 CLR(sc->sc_mcr, MCR_RTS); 1487 } 1488 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1489 1490 #if 0 1491 if (ospeed == 0) 1492 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1493 else 1494 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1495 #endif 1496 1497 sc->sc_dlbl = ospeed; 1498 sc->sc_dlbh = ospeed >> 8; 1499 1500 /* 1501 * Set the FIFO threshold based on the receive speed. 1502 * 1503 * * If it's a low speed, it's probably a mouse or some other 1504 * interactive device, so set the threshold low. 1505 * * If it's a high speed, trim the trigger level down to prevent 1506 * overflows. 1507 * * Otherwise set it a bit higher. 1508 */ 1509 if (sc->sc_type == COM_TYPE_HAYESP) 1510 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1511 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1512 sc->sc_fifo = FIFO_ENABLE | 1513 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1514 else 1515 sc->sc_fifo = 0; 1516 1517 /* And copy to tty. */ 1518 tp->t_ispeed = t->c_ospeed; 1519 tp->t_ospeed = t->c_ospeed; 1520 tp->t_cflag = t->c_cflag; 1521 1522 if (!sc->sc_heldchange) { 1523 if (sc->sc_tx_busy) { 1524 sc->sc_heldtbc = sc->sc_tbc; 1525 sc->sc_tbc = 0; 1526 sc->sc_heldchange = 1; 1527 } else 1528 com_loadchannelregs(sc); 1529 } 1530 1531 if (!ISSET(t->c_cflag, CHWFLOW)) { 1532 /* Disable the high water mark. */ 1533 sc->sc_r_hiwat = 0; 1534 sc->sc_r_lowat = 0; 1535 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1536 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1537 com_schedrx(sc); 1538 } 1539 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1540 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1541 com_hwiflow(sc); 1542 } 1543 } else { 1544 sc->sc_r_hiwat = com_rbuf_hiwat; 1545 sc->sc_r_lowat = com_rbuf_lowat; 1546 } 1547 1548 COM_UNLOCK(sc); 1549 splx(s); 1550 1551 /* 1552 * Update the tty layer's idea of the carrier bit, in case we changed 1553 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1554 * explicit request. 1555 */ 1556 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1557 1558 #ifdef COM_DEBUG 1559 if (com_debug) 1560 comstatus(sc, "comparam "); 1561 #endif 1562 1563 if (!ISSET(t->c_cflag, CHWFLOW)) { 1564 if (sc->sc_tx_stopped) { 1565 sc->sc_tx_stopped = 0; 1566 comstart(tp); 1567 } 1568 } 1569 1570 return (0); 1571 } 1572 1573 void 1574 com_iflush(struct com_softc *sc) 1575 { 1576 struct com_regs *regsp = &sc->sc_regs; 1577 #ifdef DIAGNOSTIC 1578 int reg; 1579 #endif 1580 int timo; 1581 1582 #ifdef DIAGNOSTIC 1583 reg = 0xffff; 1584 #endif 1585 timo = 50000; 1586 /* flush any pending I/O */ 1587 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1588 && --timo) 1589 #ifdef DIAGNOSTIC 1590 reg = 1591 #else 1592 (void) 1593 #endif 1594 CSR_READ_1(regsp, COM_REG_RXDATA); 1595 #ifdef DIAGNOSTIC 1596 if (!timo) 1597 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1598 reg); 1599 #endif 1600 } 1601 1602 void 1603 com_loadchannelregs(struct com_softc *sc) 1604 { 1605 struct com_regs *regsp = &sc->sc_regs; 1606 1607 /* XXXXX necessary? */ 1608 com_iflush(sc); 1609 1610 if (sc->sc_type == COM_TYPE_PXA2x0) 1611 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1612 else 1613 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1614 1615 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1616 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1617 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1618 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1619 } 1620 } 1621 if (sc->sc_type == COM_TYPE_AU1x00) { 1622 /* alchemy has single separate 16-bit clock divisor register */ 1623 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1624 (sc->sc_dlbh << 8)); 1625 } else { 1626 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1627 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1628 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1629 } 1630 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1631 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1632 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1633 #ifdef COM_HAYESP 1634 if (sc->sc_type == COM_TYPE_HAYESP) { 1635 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1636 HAYESP_SETPRESCALER); 1637 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1638 sc->sc_prescaler); 1639 } 1640 #endif 1641 1642 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1643 } 1644 1645 int 1646 comhwiflow(struct tty *tp, int block) 1647 { 1648 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1649 int s; 1650 1651 if (COM_ISALIVE(sc) == 0) 1652 return (0); 1653 1654 if (sc->sc_mcr_rts == 0) 1655 return (0); 1656 1657 s = splserial(); 1658 COM_LOCK(sc); 1659 1660 if (block) { 1661 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1662 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1663 com_hwiflow(sc); 1664 } 1665 } else { 1666 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1667 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1668 com_schedrx(sc); 1669 } 1670 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1671 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1672 com_hwiflow(sc); 1673 } 1674 } 1675 1676 COM_UNLOCK(sc); 1677 splx(s); 1678 return (1); 1679 } 1680 1681 /* 1682 * (un)block input via hw flowcontrol 1683 */ 1684 void 1685 com_hwiflow(struct com_softc *sc) 1686 { 1687 struct com_regs *regsp= &sc->sc_regs; 1688 1689 if (sc->sc_mcr_rts == 0) 1690 return; 1691 1692 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1693 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1694 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1695 } else { 1696 SET(sc->sc_mcr, sc->sc_mcr_rts); 1697 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1698 } 1699 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1700 } 1701 1702 1703 void 1704 comstart(struct tty *tp) 1705 { 1706 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1707 struct com_regs *regsp = &sc->sc_regs; 1708 int s; 1709 1710 if (COM_ISALIVE(sc) == 0) 1711 return; 1712 1713 s = spltty(); 1714 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1715 goto out; 1716 if (sc->sc_tx_stopped) 1717 goto out; 1718 1719 if (tp->t_outq.c_cc <= tp->t_lowat) { 1720 if (ISSET(tp->t_state, TS_ASLEEP)) { 1721 CLR(tp->t_state, TS_ASLEEP); 1722 wakeup(&tp->t_outq); 1723 } 1724 selwakeup(&tp->t_wsel); 1725 if (tp->t_outq.c_cc == 0) 1726 goto out; 1727 } 1728 1729 /* Grab the first contiguous region of buffer space. */ 1730 { 1731 u_char *tba; 1732 int tbc; 1733 1734 tba = tp->t_outq.c_cf; 1735 tbc = ndqb(&tp->t_outq, 0); 1736 1737 (void)splserial(); 1738 COM_LOCK(sc); 1739 1740 sc->sc_tba = tba; 1741 sc->sc_tbc = tbc; 1742 } 1743 1744 SET(tp->t_state, TS_BUSY); 1745 sc->sc_tx_busy = 1; 1746 1747 /* Enable transmit completion interrupts if necessary. */ 1748 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1749 SET(sc->sc_ier, IER_ETXRDY); 1750 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1751 } 1752 1753 /* Output the first chunk of the contiguous buffer. */ 1754 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1755 u_int n; 1756 1757 n = sc->sc_tbc; 1758 if (n > sc->sc_fifolen) 1759 n = sc->sc_fifolen; 1760 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1761 sc->sc_tbc -= n; 1762 sc->sc_tba += n; 1763 } 1764 1765 COM_UNLOCK(sc); 1766 out: 1767 splx(s); 1768 return; 1769 } 1770 1771 /* 1772 * Stop output on a line. 1773 */ 1774 void 1775 comstop(struct tty *tp, int flag) 1776 { 1777 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1778 int s; 1779 1780 s = splserial(); 1781 COM_LOCK(sc); 1782 if (ISSET(tp->t_state, TS_BUSY)) { 1783 /* Stop transmitting at the next chunk. */ 1784 sc->sc_tbc = 0; 1785 sc->sc_heldtbc = 0; 1786 if (!ISSET(tp->t_state, TS_TTSTOP)) 1787 SET(tp->t_state, TS_FLUSH); 1788 } 1789 COM_UNLOCK(sc); 1790 splx(s); 1791 } 1792 1793 void 1794 comdiag(void *arg) 1795 { 1796 struct com_softc *sc = arg; 1797 int overflows, floods; 1798 int s; 1799 1800 s = splserial(); 1801 COM_LOCK(sc); 1802 overflows = sc->sc_overflows; 1803 sc->sc_overflows = 0; 1804 floods = sc->sc_floods; 1805 sc->sc_floods = 0; 1806 sc->sc_errors = 0; 1807 COM_UNLOCK(sc); 1808 splx(s); 1809 1810 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1811 sc->sc_dev.dv_xname, 1812 overflows, overflows == 1 ? "" : "s", 1813 floods, floods == 1 ? "" : "s"); 1814 } 1815 1816 integrate void 1817 com_rxsoft(struct com_softc *sc, struct tty *tp) 1818 { 1819 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1820 u_char *get, *end; 1821 u_int cc, scc; 1822 u_char lsr; 1823 int code; 1824 int s; 1825 1826 end = sc->sc_ebuf; 1827 get = sc->sc_rbget; 1828 scc = cc = com_rbuf_size - sc->sc_rbavail; 1829 1830 if (cc == com_rbuf_size) { 1831 sc->sc_floods++; 1832 if (sc->sc_errors++ == 0) 1833 callout_reset(&sc->sc_diag_callout, 60 * hz, 1834 comdiag, sc); 1835 } 1836 1837 /* If not yet open, drop the entire buffer content here */ 1838 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1839 get += cc << 1; 1840 if (get >= end) 1841 get -= com_rbuf_size << 1; 1842 cc = 0; 1843 } 1844 while (cc) { 1845 code = get[0]; 1846 lsr = get[1]; 1847 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1848 if (ISSET(lsr, LSR_OE)) { 1849 sc->sc_overflows++; 1850 if (sc->sc_errors++ == 0) 1851 callout_reset(&sc->sc_diag_callout, 1852 60 * hz, comdiag, sc); 1853 } 1854 if (ISSET(lsr, LSR_BI | LSR_FE)) 1855 SET(code, TTY_FE); 1856 if (ISSET(lsr, LSR_PE)) 1857 SET(code, TTY_PE); 1858 } 1859 if ((*rint)(code, tp) == -1) { 1860 /* 1861 * The line discipline's buffer is out of space. 1862 */ 1863 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1864 /* 1865 * We're either not using flow control, or the 1866 * line discipline didn't tell us to block for 1867 * some reason. Either way, we have no way to 1868 * know when there's more space available, so 1869 * just drop the rest of the data. 1870 */ 1871 get += cc << 1; 1872 if (get >= end) 1873 get -= com_rbuf_size << 1; 1874 cc = 0; 1875 } else { 1876 /* 1877 * Don't schedule any more receive processing 1878 * until the line discipline tells us there's 1879 * space available (through comhwiflow()). 1880 * Leave the rest of the data in the input 1881 * buffer. 1882 */ 1883 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1884 } 1885 break; 1886 } 1887 get += 2; 1888 if (get >= end) 1889 get = sc->sc_rbuf; 1890 cc--; 1891 } 1892 1893 if (cc != scc) { 1894 sc->sc_rbget = get; 1895 s = splserial(); 1896 COM_LOCK(sc); 1897 1898 cc = sc->sc_rbavail += scc - cc; 1899 /* Buffers should be ok again, release possible block. */ 1900 if (cc >= sc->sc_r_lowat) { 1901 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1902 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1903 SET(sc->sc_ier, IER_ERXRDY); 1904 #ifdef COM_PXA2X0 1905 if (sc->sc_type == COM_TYPE_PXA2x0) 1906 SET(sc->sc_ier, IER_ERXTOUT); 1907 #endif 1908 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1909 } 1910 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1911 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1912 com_hwiflow(sc); 1913 } 1914 } 1915 COM_UNLOCK(sc); 1916 splx(s); 1917 } 1918 } 1919 1920 integrate void 1921 com_txsoft(struct com_softc *sc, struct tty *tp) 1922 { 1923 1924 CLR(tp->t_state, TS_BUSY); 1925 if (ISSET(tp->t_state, TS_FLUSH)) 1926 CLR(tp->t_state, TS_FLUSH); 1927 else 1928 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1929 (*tp->t_linesw->l_start)(tp); 1930 } 1931 1932 integrate void 1933 com_stsoft(struct com_softc *sc, struct tty *tp) 1934 { 1935 u_char msr, delta; 1936 int s; 1937 1938 s = splserial(); 1939 COM_LOCK(sc); 1940 msr = sc->sc_msr; 1941 delta = sc->sc_msr_delta; 1942 sc->sc_msr_delta = 0; 1943 COM_UNLOCK(sc); 1944 splx(s); 1945 1946 if (ISSET(delta, sc->sc_msr_dcd)) { 1947 /* 1948 * Inform the tty layer that carrier detect changed. 1949 */ 1950 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1951 } 1952 1953 if (ISSET(delta, sc->sc_msr_cts)) { 1954 /* Block or unblock output according to flow control. */ 1955 if (ISSET(msr, sc->sc_msr_cts)) { 1956 sc->sc_tx_stopped = 0; 1957 (*tp->t_linesw->l_start)(tp); 1958 } else { 1959 sc->sc_tx_stopped = 1; 1960 } 1961 } 1962 1963 #ifdef COM_DEBUG 1964 if (com_debug) 1965 comstatus(sc, "com_stsoft"); 1966 #endif 1967 } 1968 1969 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1970 void 1971 comsoft(void *arg) 1972 { 1973 struct com_softc *sc = arg; 1974 struct tty *tp; 1975 1976 if (COM_ISALIVE(sc) == 0) 1977 return; 1978 1979 { 1980 #else 1981 void 1982 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1983 comsoft(void) 1984 #else 1985 comsoft(void *arg) 1986 #endif 1987 { 1988 struct com_softc *sc; 1989 struct tty *tp; 1990 int unit; 1991 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1992 int s; 1993 1994 s = splsoftserial(); 1995 com_softintr_scheduled = 0; 1996 #endif 1997 1998 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1999 sc = device_lookup(&com_cd, unit); 2000 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK)) 2001 continue; 2002 2003 if (COM_ISALIVE(sc) == 0) 2004 continue; 2005 2006 tp = sc->sc_tty; 2007 if (tp == NULL) 2008 continue; 2009 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 2010 continue; 2011 #endif 2012 tp = sc->sc_tty; 2013 2014 if (sc->sc_rx_ready) { 2015 sc->sc_rx_ready = 0; 2016 com_rxsoft(sc, tp); 2017 } 2018 2019 if (sc->sc_st_check) { 2020 sc->sc_st_check = 0; 2021 com_stsoft(sc, tp); 2022 } 2023 2024 if (sc->sc_tx_done) { 2025 sc->sc_tx_done = 0; 2026 com_txsoft(sc, tp); 2027 } 2028 } 2029 2030 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 2031 #ifdef __NO_SOFT_SERIAL_INTERRUPT 2032 splx(s); 2033 #endif 2034 #endif 2035 } 2036 2037 #ifdef __ALIGN_BRACKET_LEVEL_FOR_CTAGS 2038 /* there has got to be a better way to do comsoft() */ 2039 }} 2040 #endif 2041 2042 int 2043 comintr(void *arg) 2044 { 2045 struct com_softc *sc = arg; 2046 struct com_regs *regsp = &sc->sc_regs; 2047 2048 u_char *put, *end; 2049 u_int cc; 2050 u_char lsr, iir; 2051 2052 if (COM_ISALIVE(sc) == 0) 2053 return (0); 2054 2055 COM_LOCK(sc); 2056 iir = CSR_READ_1(regsp, COM_REG_IIR); 2057 if (ISSET(iir, IIR_NOPEND)) { 2058 COM_UNLOCK(sc); 2059 return (0); 2060 } 2061 2062 end = sc->sc_ebuf; 2063 put = sc->sc_rbput; 2064 cc = sc->sc_rbavail; 2065 2066 again: do { 2067 u_char msr, delta; 2068 2069 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2070 if (ISSET(lsr, LSR_BI)) { 2071 int cn_trapped = 0; 2072 2073 cn_check_magic(sc->sc_tty->t_dev, 2074 CNC_BREAK, com_cnm_state); 2075 if (cn_trapped) 2076 continue; 2077 #if defined(KGDB) && !defined(DDB) 2078 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2079 kgdb_connect(1); 2080 continue; 2081 } 2082 #endif 2083 } 2084 2085 if (ISSET(lsr, LSR_RCV_MASK) && 2086 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2087 while (cc > 0) { 2088 int cn_trapped = 0; 2089 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2090 put[1] = lsr; 2091 cn_check_magic(sc->sc_tty->t_dev, 2092 put[0], com_cnm_state); 2093 if (cn_trapped) 2094 goto next; 2095 put += 2; 2096 if (put >= end) 2097 put = sc->sc_rbuf; 2098 cc--; 2099 next: 2100 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2101 if (!ISSET(lsr, LSR_RCV_MASK)) 2102 break; 2103 } 2104 2105 /* 2106 * Current string of incoming characters ended because 2107 * no more data was available or we ran out of space. 2108 * Schedule a receive event if any data was received. 2109 * If we're out of space, turn off receive interrupts. 2110 */ 2111 sc->sc_rbput = put; 2112 sc->sc_rbavail = cc; 2113 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2114 sc->sc_rx_ready = 1; 2115 2116 /* 2117 * See if we are in danger of overflowing a buffer. If 2118 * so, use hardware flow control to ease the pressure. 2119 */ 2120 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2121 cc < sc->sc_r_hiwat) { 2122 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2123 com_hwiflow(sc); 2124 } 2125 2126 /* 2127 * If we're out of space, disable receive interrupts 2128 * until the queue has drained a bit. 2129 */ 2130 if (!cc) { 2131 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2132 #ifdef COM_PXA2X0 2133 if (sc->sc_type == COM_TYPE_PXA2x0) 2134 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2135 else 2136 #endif 2137 CLR(sc->sc_ier, IER_ERXRDY); 2138 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2139 } 2140 } else { 2141 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2142 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2143 continue; 2144 } 2145 } 2146 2147 msr = CSR_READ_1(regsp, COM_REG_MSR); 2148 delta = msr ^ sc->sc_msr; 2149 sc->sc_msr = msr; 2150 #ifdef __HAVE_TIMECOUNTER 2151 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2152 (delta & MSR_DCD)) { 2153 pps_capture(&sc->sc_pps_state); 2154 pps_event(&sc->sc_pps_state, 2155 (msr & MSR_DCD) ? 2156 PPS_CAPTUREASSERT : 2157 PPS_CAPTURECLEAR); 2158 } 2159 #else /* !__HAVE_TIMECOUNTER */ 2160 /* 2161 * Pulse-per-second (PSS) signals on edge of DCD? 2162 * Process these even if line discipline is ignoring DCD. 2163 */ 2164 if (delta & sc->sc_ppsmask) { 2165 struct timeval tv; 2166 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2167 /* XXX nanotime() */ 2168 microtime(&tv); 2169 TIMEVAL_TO_TIMESPEC(&tv, 2170 &sc->ppsinfo.assert_timestamp); 2171 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2172 timespecadd(&sc->ppsinfo.assert_timestamp, 2173 &sc->ppsparam.assert_offset, 2174 &sc->ppsinfo.assert_timestamp); 2175 } 2176 2177 #ifdef PPS_SYNC 2178 if (pps_kc_hardpps_source == sc && 2179 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2180 hardpps(&tv, tv.tv_usec); 2181 } 2182 #endif 2183 sc->ppsinfo.assert_sequence++; 2184 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2185 2186 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2187 /* XXX nanotime() */ 2188 microtime(&tv); 2189 TIMEVAL_TO_TIMESPEC(&tv, 2190 &sc->ppsinfo.clear_timestamp); 2191 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2192 timespecadd(&sc->ppsinfo.clear_timestamp, 2193 &sc->ppsparam.clear_offset, 2194 &sc->ppsinfo.clear_timestamp); 2195 } 2196 2197 #ifdef PPS_SYNC 2198 if (pps_kc_hardpps_source == sc && 2199 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2200 hardpps(&tv, tv.tv_usec); 2201 } 2202 #endif 2203 sc->ppsinfo.clear_sequence++; 2204 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2205 } 2206 } 2207 #endif /* !__HAVE_TIMECOUNTER */ 2208 2209 /* 2210 * Process normal status changes 2211 */ 2212 if (ISSET(delta, sc->sc_msr_mask)) { 2213 SET(sc->sc_msr_delta, delta); 2214 2215 /* 2216 * Stop output immediately if we lose the output 2217 * flow control signal or carrier detect. 2218 */ 2219 if (ISSET(~msr, sc->sc_msr_mask)) { 2220 sc->sc_tbc = 0; 2221 sc->sc_heldtbc = 0; 2222 #ifdef COM_DEBUG 2223 if (com_debug) 2224 comstatus(sc, "comintr "); 2225 #endif 2226 } 2227 2228 sc->sc_st_check = 1; 2229 } 2230 } while (!ISSET((iir = 2231 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2232 /* 2233 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2234 * by IIR read, so we can't do this way: `process all interrupts, 2235 * then do TX if possble'. 2236 */ 2237 (iir & IIR_IMASK) != IIR_TXRDY); 2238 2239 /* 2240 * Read LSR again, since there may be an interrupt between 2241 * the last LSR read and IIR read above. 2242 */ 2243 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2244 2245 /* 2246 * See if data can be transmitted as well. 2247 * Schedule tx done event if no data left 2248 * and tty was marked busy. 2249 */ 2250 if (ISSET(lsr, LSR_TXRDY)) { 2251 /* 2252 * If we've delayed a parameter change, do it now, and restart 2253 * output. 2254 */ 2255 if (sc->sc_heldchange) { 2256 com_loadchannelregs(sc); 2257 sc->sc_heldchange = 0; 2258 sc->sc_tbc = sc->sc_heldtbc; 2259 sc->sc_heldtbc = 0; 2260 } 2261 2262 /* Output the next chunk of the contiguous buffer, if any. */ 2263 if (sc->sc_tbc > 0) { 2264 u_int n; 2265 2266 n = sc->sc_tbc; 2267 if (n > sc->sc_fifolen) 2268 n = sc->sc_fifolen; 2269 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2270 sc->sc_tbc -= n; 2271 sc->sc_tba += n; 2272 } else { 2273 /* Disable transmit completion interrupts if necessary. */ 2274 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2275 CLR(sc->sc_ier, IER_ETXRDY); 2276 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2277 } 2278 if (sc->sc_tx_busy) { 2279 sc->sc_tx_busy = 0; 2280 sc->sc_tx_done = 1; 2281 } 2282 } 2283 } 2284 2285 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2286 goto again; 2287 2288 COM_UNLOCK(sc); 2289 2290 /* Wake up the poller. */ 2291 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2292 softintr_schedule(sc->sc_si); 2293 #else 2294 #ifndef __NO_SOFT_SERIAL_INTERRUPT 2295 setsoftserial(); 2296 #else 2297 if (!com_softintr_scheduled) { 2298 com_softintr_scheduled = 1; 2299 callout_reset(&comsoft_callout, 1, comsoft, NULL); 2300 } 2301 #endif 2302 #endif 2303 2304 #if NRND > 0 && defined(RND_COM) 2305 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2306 #endif 2307 2308 return (1); 2309 } 2310 2311 /* 2312 * The following functions are polled getc and putc routines, shared 2313 * by the console and kgdb glue. 2314 * 2315 * The read-ahead code is so that you can detect pending in-band 2316 * cn_magic in polled mode while doing output rather than having to 2317 * wait until the kernel decides it needs input. 2318 */ 2319 2320 #define MAX_READAHEAD 20 2321 static int com_readahead[MAX_READAHEAD]; 2322 static int com_readaheadcount = 0; 2323 2324 int 2325 com_common_getc(dev_t dev, struct com_regs *regsp) 2326 { 2327 int s = splserial(); 2328 u_char stat, c; 2329 2330 /* got a character from reading things earlier */ 2331 if (com_readaheadcount > 0) { 2332 int i; 2333 2334 c = com_readahead[0]; 2335 for (i = 1; i < com_readaheadcount; i++) { 2336 com_readahead[i-1] = com_readahead[i]; 2337 } 2338 com_readaheadcount--; 2339 splx(s); 2340 return (c); 2341 } 2342 2343 /* block until a character becomes available */ 2344 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2345 ; 2346 2347 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2348 stat = CSR_READ_1(regsp, COM_REG_IIR); 2349 { 2350 int cn_trapped = 0; /* unused */ 2351 #ifdef DDB 2352 extern int db_active; 2353 if (!db_active) 2354 #endif 2355 cn_check_magic(dev, c, com_cnm_state); 2356 } 2357 splx(s); 2358 return (c); 2359 } 2360 2361 void 2362 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2363 { 2364 int s = splserial(); 2365 int cin, stat, timo; 2366 2367 if (com_readaheadcount < MAX_READAHEAD 2368 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2369 int cn_trapped = 0; 2370 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2371 stat = CSR_READ_1(regsp, COM_REG_IIR); 2372 cn_check_magic(dev, cin, com_cnm_state); 2373 com_readahead[com_readaheadcount++] = cin; 2374 } 2375 2376 /* wait for any pending transmission to finish */ 2377 timo = 150000; 2378 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2379 continue; 2380 2381 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2382 COM_BARRIER(regsp, BR | BW); 2383 2384 splx(s); 2385 } 2386 2387 /* 2388 * Initialize UART for use as console or KGDB line. 2389 */ 2390 int 2391 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2392 tcflag_t cflag) 2393 { 2394 2395 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2396 ®sp->cr_ioh)) 2397 return (ENOMEM); /* ??? */ 2398 2399 rate = comspeed(rate, frequency, type); 2400 if (type != COM_TYPE_AU1x00) { 2401 /* no EFR on alchemy */ 2402 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2403 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2404 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2405 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2406 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2407 } else { 2408 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2409 } 2410 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2411 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2412 CSR_WRITE_1(regsp, COM_REG_FIFO, 2413 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2414 #ifdef COM_PXA2X0 2415 if (type == COM_TYPE_PXA2x0) 2416 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2417 else 2418 #endif 2419 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2420 2421 return (0); 2422 } 2423 2424 /* 2425 * Following are all routines needed for COM to act as console 2426 */ 2427 struct consdev comcons = { 2428 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2429 NODEV, CN_NORMAL 2430 }; 2431 2432 2433 int 2434 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2435 tcflag_t cflag) 2436 { 2437 int res; 2438 2439 comconsregs = *regsp; 2440 2441 res = cominit(&comconsregs, rate, frequency, type, cflag); 2442 if (res) 2443 return (res); 2444 2445 cn_tab = &comcons; 2446 cn_init_magic(&com_cnm_state); 2447 cn_set_magic("\047\001"); /* default magic is BREAK */ 2448 2449 comconsrate = rate; 2450 comconscflag = cflag; 2451 2452 return (0); 2453 } 2454 2455 int 2456 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2457 int type, tcflag_t cflag) 2458 { 2459 struct com_regs regs; 2460 2461 memset(®s, 0, sizeof regs); 2462 regs.cr_iot = iot; 2463 regs.cr_iobase = iobase; 2464 regs.cr_nports = COM_NPORTS; 2465 #ifdef COM_REGMAP 2466 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2467 #endif 2468 2469 return comcnattach1(®s, rate, frequency, type, cflag); 2470 } 2471 2472 int 2473 comcngetc(dev_t dev) 2474 { 2475 2476 return (com_common_getc(dev, &comconsregs)); 2477 } 2478 2479 /* 2480 * Console kernel output character routine. 2481 */ 2482 void 2483 comcnputc(dev_t dev, int c) 2484 { 2485 2486 com_common_putc(dev, &comconsregs, c); 2487 } 2488 2489 void 2490 comcnpollc(dev_t dev, int on) 2491 { 2492 2493 } 2494 2495 #ifdef KGDB 2496 int 2497 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2498 tcflag_t cflag) 2499 { 2500 int res; 2501 2502 if (regsp->cr_iot == comconsregs.cr_iot && 2503 regsp->cr_iobase == comconsregs.cr_iobase) { 2504 #if !defined(DDB) 2505 return (EBUSY); /* cannot share with console */ 2506 #else 2507 comkgdbregs = *regsp; 2508 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2509 #endif 2510 } else { 2511 comkgdbregs = *regsp; 2512 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2513 if (res) 2514 return (res); 2515 2516 /* 2517 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2518 * expects this to be initialized 2519 */ 2520 cn_init_magic(&com_cnm_state); 2521 cn_set_magic("\047\001"); 2522 } 2523 2524 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2525 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2526 2527 return (0); 2528 } 2529 2530 int 2531 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2532 int frequency, int type, tcflag_t cflag) 2533 { 2534 struct com_regs regs; 2535 2536 regs.cr_iot = iot; 2537 regs.cr_nports = COM_NPORTS; 2538 regs.cr_iobase = iobase; 2539 #ifdef COM_REGMAP 2540 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2541 #endif 2542 2543 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2544 } 2545 2546 /* ARGSUSED */ 2547 int 2548 com_kgdb_getc(void *arg) 2549 { 2550 2551 return (com_common_getc(NODEV, &comkgdbregs)); 2552 } 2553 2554 /* ARGSUSED */ 2555 void 2556 com_kgdb_putc(void *arg, int c) 2557 { 2558 2559 com_common_putc(NODEV, &comkgdbregs, c); 2560 } 2561 #endif /* KGDB */ 2562 2563 /* helper function to identify the com ports used by 2564 console or KGDB (and not yet autoconf attached) */ 2565 int 2566 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2567 { 2568 bus_space_handle_t help; 2569 2570 if (!comconsattached && 2571 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2572 help = comconsregs.cr_ioh; 2573 #ifdef KGDB 2574 else if (!com_kgdb_attached && 2575 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2576 help = comkgdbregs.cr_ioh; 2577 #endif 2578 else 2579 return (0); 2580 2581 if (ioh) 2582 *ioh = help; 2583 return (1); 2584 } 2585 2586 /* 2587 * this routine exists to serve as a shutdown hook for systems that 2588 * have firmware which doesn't interact properly with a com device in 2589 * FIFO mode. 2590 */ 2591 void 2592 com_cleanup(void *arg) 2593 { 2594 struct com_softc *sc = arg; 2595 2596 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2597 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2598 } 2599 2600 void 2601 com_power(int why, void *arg) 2602 { 2603 struct com_softc *sc = arg; 2604 int s; 2605 2606 s = splserial(); 2607 switch (why) { 2608 case PWR_SUSPEND: 2609 case PWR_STANDBY: 2610 /* XXX should we do something to stop the device? */ 2611 break; 2612 case PWR_RESUME: 2613 com_loadchannelregs(sc); 2614 break; 2615 case PWR_SOFTSUSPEND: 2616 case PWR_SOFTSTANDBY: 2617 case PWR_SOFTRESUME: 2618 break; 2619 } 2620 splx(s); 2621 } 2622
Indexes created Wed Sep 24 05:09:52 GMT 2025