com.c revision 1.259.2.1
1 /* $NetBSD: com.c,v 1.259.2.1 2007/06/17 21:30:58 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.259.2.1 2007/06/17 21:30:58 ad Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 194 void comsoft(void *); 195 #else 196 #ifndef __NO_SOFT_SERIAL_INTERRUPT 197 void comsoft(void); 198 #else 199 void comsoft(void *); 200 static struct callout comsoft_callout = CALLOUT_INITIALIZER; 201 #endif 202 #endif 203 integrate void com_rxsoft(struct com_softc *, struct tty *); 204 integrate void com_txsoft(struct com_softc *, struct tty *); 205 integrate void com_stsoft(struct com_softc *, struct tty *); 206 integrate void com_schedrx(struct com_softc *); 207 void comdiag(void *); 208 209 extern struct cfdriver com_cd; 210 211 dev_type_open(comopen); 212 dev_type_close(comclose); 213 dev_type_read(comread); 214 dev_type_write(comwrite); 215 dev_type_ioctl(comioctl); 216 dev_type_stop(comstop); 217 dev_type_tty(comtty); 218 dev_type_poll(compoll); 219 220 const struct cdevsw com_cdevsw = { 221 comopen, comclose, comread, comwrite, comioctl, 222 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 223 }; 224 225 /* 226 * Make this an option variable one can patch. 227 * But be warned: this must be a power of 2! 228 */ 229 u_int com_rbuf_size = COM_RING_SIZE; 230 231 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 232 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 233 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 234 235 static struct com_regs comconsregs; 236 static int comconsattached; 237 static int comconsrate; 238 static tcflag_t comconscflag; 239 static struct cnm_state com_cnm_state; 240 241 #ifndef __HAVE_TIMECOUNTER 242 static int ppscap = 243 PPS_TSFMT_TSPEC | 244 PPS_CAPTUREASSERT | 245 PPS_CAPTURECLEAR | 246 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 247 #endif /* !__HAVE_TIMECOUNTER */ 248 249 #ifdef KGDB 250 #include <sys/kgdb.h> 251 252 static struct com_regs comkgdbregs; 253 static int com_kgdb_attached; 254 255 int com_kgdb_getc(void *); 256 void com_kgdb_putc(void *, int); 257 #endif /* KGDB */ 258 259 #ifdef COM_REGMAP 260 /* initializer for typical 16550-ish hardware */ 261 #define COM_REG_16550 { \ 262 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 263 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 264 265 const bus_size_t com_std_map[16] = COM_REG_16550; 266 #endif /* COM_REGMAP */ 267 268 #define COMUNIT_MASK 0x7ffff 269 #define COMDIALOUT_MASK 0x80000 270 271 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 272 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 273 274 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 275 device_is_active(&(sc)->sc_dev)) 276 277 #define BR BUS_SPACE_BARRIER_READ 278 #define BW BUS_SPACE_BARRIER_WRITE 279 #define COM_BARRIER(r, f) \ 280 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 281 282 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 283 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 284 285 /*ARGSUSED*/ 286 int 287 comspeed(long speed, long frequency, int type) 288 { 289 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 290 291 int x, err; 292 293 #if 0 294 if (speed == 0) 295 return (0); 296 #endif 297 if (speed <= 0) 298 return (-1); 299 x = divrnd(frequency / 16, speed); 300 if (x <= 0) 301 return (-1); 302 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 303 if (err < 0) 304 err = -err; 305 if (err > COM_TOLERANCE) 306 return (-1); 307 return (x); 308 309 #undef divrnd 310 } 311 312 #ifdef COM_DEBUG 313 int com_debug = 0; 314 315 void comstatus(struct com_softc *, const char *); 316 void 317 comstatus(struct com_softc *sc, const char *str) 318 { 319 struct tty *tp = sc->sc_tty; 320 321 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 322 sc->sc_dev.dv_xname, str, 323 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 324 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 325 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 326 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 327 sc->sc_tx_stopped ? '+' : '-'); 328 329 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 330 sc->sc_dev.dv_xname, str, 331 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 332 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 333 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 334 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 335 sc->sc_rx_flags); 336 } 337 #endif 338 339 int 340 com_probe_subr(struct com_regs *regs) 341 { 342 343 /* force access to id reg */ 344 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 345 CSR_WRITE_1(regs, COM_REG_IIR, 0); 346 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 347 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 348 return (0); 349 350 return (1); 351 } 352 353 int 354 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 355 { 356 struct com_regs regs; 357 358 regs.cr_iot = iot; 359 regs.cr_ioh = ioh; 360 #ifdef COM_REGMAP 361 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 362 #endif 363 364 return com_probe_subr(®s); 365 } 366 367 static void 368 com_enable_debugport(struct com_softc *sc) 369 { 370 int s; 371 372 /* Turn on line break interrupt, set carrier. */ 373 s = splserial(); 374 COM_LOCK(sc); 375 sc->sc_ier = IER_ERXRDY; 376 if (sc->sc_type == COM_TYPE_PXA2x0) 377 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 378 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 379 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 380 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 381 COM_UNLOCK(sc); 382 splx(s); 383 } 384 385 void 386 com_attach_subr(struct com_softc *sc) 387 { 388 struct com_regs *regsp = &sc->sc_regs; 389 struct tty *tp; 390 #ifdef COM_16650 391 u_int8_t lcr; 392 #endif 393 const char *fifo_msg = NULL; 394 395 aprint_naive("\n"); 396 397 callout_init(&sc->sc_diag_callout); 398 simple_lock_init(&sc->sc_lock); 399 400 /* Disable interrupts before configuring the device. */ 401 if (sc->sc_type == COM_TYPE_PXA2x0) 402 sc->sc_ier = IER_EUART; 403 else 404 sc->sc_ier = 0; 405 406 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 407 408 if (regsp->cr_iot == comconsregs.cr_iot && 409 regsp->cr_iobase == comconsregs.cr_iobase) { 410 comconsattached = 1; 411 412 /* Make sure the console is always "hardwired". */ 413 delay(10000); /* wait for output to finish */ 414 SET(sc->sc_hwflags, COM_HW_CONSOLE); 415 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 416 } 417 418 /* Probe for FIFO */ 419 switch (sc->sc_type) { 420 case COM_TYPE_HAYESP: 421 goto fifodone; 422 423 case COM_TYPE_AU1x00: 424 sc->sc_fifolen = 16; 425 fifo_msg = "Au1X00 UART, working fifo"; 426 SET(sc->sc_hwflags, COM_HW_FIFO); 427 goto fifodelay; 428 } 429 430 sc->sc_fifolen = 1; 431 /* look for a NS 16550AF UART with FIFOs */ 432 CSR_WRITE_1(regsp, COM_REG_FIFO, 433 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 434 delay(100); 435 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 436 == IIR_FIFO_MASK) 437 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 438 == FIFO_TRIGGER_14) { 439 SET(sc->sc_hwflags, COM_HW_FIFO); 440 441 #ifdef COM_16650 442 /* 443 * IIR changes into the EFR if LCR is set to LCR_EERS 444 * on 16650s. We also know IIR != 0 at this point. 445 * Write 0 into the EFR, and read it. If the result 446 * is 0, we have a 16650. 447 * 448 * Older 16650s were broken; the test to detect them 449 * is taken from the Linux driver. Apparently 450 * setting DLAB enable gives access to the EFR on 451 * these chips. 452 */ 453 lcr = CSR_READ_1(regsp, COM_REG_LCR); 454 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 455 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 456 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 457 CSR_WRITE_1(regsp, COM_REG_LCR, 458 lcr | LCR_DLAB); 459 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 460 CLR(sc->sc_hwflags, COM_HW_FIFO); 461 sc->sc_fifolen = 0; 462 } else { 463 SET(sc->sc_hwflags, COM_HW_FLOW); 464 sc->sc_fifolen = 32; 465 } 466 } else 467 #endif 468 sc->sc_fifolen = 16; 469 470 #ifdef COM_16650 471 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 472 if (sc->sc_fifolen == 0) 473 fifo_msg = "st16650, broken fifo"; 474 else if (sc->sc_fifolen == 32) 475 fifo_msg = "st16650a, working fifo"; 476 else 477 #endif 478 fifo_msg = "ns16550a, working fifo"; 479 } else 480 fifo_msg = "ns16550, broken fifo"; 481 else 482 fifo_msg = "ns8250 or ns16450, no fifo"; 483 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 484 fifodelay: 485 /* 486 * Some chips will clear down both Tx and Rx FIFOs when zero is 487 * written to com_fifo. If this chip is the console, writing zero 488 * results in some of the chip/FIFO description being lost, so delay 489 * printing it until now. 490 */ 491 delay(10); 492 aprint_normal(": %s\n", fifo_msg); 493 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 494 sc->sc_fifolen = 1; 495 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 496 } 497 498 fifodone: 499 500 tp = ttymalloc(); 501 tp->t_oproc = comstart; 502 tp->t_param = comparam; 503 tp->t_hwiflow = comhwiflow; 504 505 sc->sc_tty = tp; 506 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 507 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 508 sc->sc_rbavail = com_rbuf_size; 509 if (sc->sc_rbuf == NULL) { 510 aprint_error("%s: unable to allocate ring buffer\n", 511 sc->sc_dev.dv_xname); 512 return; 513 } 514 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 515 516 tty_attach(tp); 517 518 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 519 SET(sc->sc_mcr, MCR_IENABLE); 520 521 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 522 int maj; 523 524 /* locate the major number */ 525 maj = cdevsw_lookup_major(&com_cdevsw); 526 527 tp->t_dev = cn_tab->cn_dev = makedev(maj, 528 device_unit(&sc->sc_dev)); 529 530 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 531 } 532 533 #ifdef KGDB 534 /* 535 * Allow kgdb to "take over" this port. If this is 536 * not the console and is the kgdb device, it has 537 * exclusive use. If it's the console _and_ the 538 * kgdb device, it doesn't. 539 */ 540 if (regsp->cr_iot == comkgdbregs.cr_iot && 541 regsp->cr_iobase == comkgdbregs.cr_iobase) { 542 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 543 com_kgdb_attached = 1; 544 545 SET(sc->sc_hwflags, COM_HW_KGDB); 546 } 547 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 548 } 549 #endif 550 551 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 552 553 #if NRND > 0 && defined(RND_COM) 554 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 555 RND_TYPE_TTY, 0); 556 #endif 557 558 /* if there are no enable/disable functions, assume the device 559 is always enabled */ 560 if (!sc->enable) 561 sc->enabled = 1; 562 563 com_config(sc); 564 565 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 566 com_power, sc); 567 if (sc->sc_powerhook == NULL) 568 aprint_error("%s: WARNING: unable to establish power hook\n", 569 sc->sc_dev.dv_xname); 570 571 SET(sc->sc_hwflags, COM_HW_DEV_OK); 572 } 573 574 void 575 com_config(struct com_softc *sc) 576 { 577 struct com_regs *regsp = &sc->sc_regs; 578 579 /* Disable interrupts before configuring the device. */ 580 if (sc->sc_type == COM_TYPE_PXA2x0) 581 sc->sc_ier = IER_EUART; 582 else 583 sc->sc_ier = 0; 584 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 585 (void) CSR_READ_1(regsp, COM_REG_IIR); 586 587 #ifdef COM_HAYESP 588 /* Look for a Hayes ESP board. */ 589 if (sc->sc_type == COM_TYPE_HAYESP) { 590 591 /* Set 16550 compatibility mode */ 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 593 HAYESP_SETMODE); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 596 HAYESP_MODE_SCALE); 597 598 /* Set RTS/CTS flow control */ 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 600 HAYESP_SETFLOWTYPE); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_FLOW_RTS); 603 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 604 HAYESP_FLOW_CTS); 605 606 /* Set flow control levels */ 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 608 HAYESP_SETRXFLOW); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 613 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 614 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 616 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 617 } 618 #endif 619 620 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 621 com_enable_debugport(sc); 622 } 623 624 int 625 com_detach(struct device *self, int flags) 626 { 627 struct com_softc *sc = (struct com_softc *)self; 628 int maj, mn; 629 630 /* kill the power hook */ 631 if (sc->sc_powerhook != NULL) 632 powerhook_disestablish(sc->sc_powerhook); 633 634 /* locate the major number */ 635 maj = cdevsw_lookup_major(&com_cdevsw); 636 637 /* Nuke the vnodes for any open instances. */ 638 mn = device_unit(self); 639 vdevgone(maj, mn, mn, VCHR); 640 641 mn |= COMDIALOUT_MASK; 642 vdevgone(maj, mn, mn, VCHR); 643 644 if (sc->sc_rbuf == NULL) { 645 /* 646 * Ring buffer allocation failed in the com_attach_subr, 647 * only the tty is allocated, and nothing else. 648 */ 649 ttyfree(sc->sc_tty); 650 return 0; 651 } 652 653 /* Free the receive buffer. */ 654 free(sc->sc_rbuf, M_DEVBUF); 655 656 /* Detach and free the tty. */ 657 tty_detach(sc->sc_tty); 658 ttyfree(sc->sc_tty); 659 660 /* Unhook the soft interrupt handler. */ 661 softint_disestablish(sc->sc_si); 662 663 #if NRND > 0 && defined(RND_COM) 664 /* Unhook the entropy source. */ 665 rnd_detach_source(&sc->rnd_source); 666 #endif 667 668 return (0); 669 } 670 671 int 672 com_activate(struct device *self, enum devact act) 673 { 674 struct com_softc *sc = (struct com_softc *)self; 675 int s, rv = 0; 676 677 s = splserial(); 678 COM_LOCK(sc); 679 switch (act) { 680 case DVACT_ACTIVATE: 681 rv = EOPNOTSUPP; 682 break; 683 684 case DVACT_DEACTIVATE: 685 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 686 rv = EBUSY; 687 break; 688 } 689 690 if (sc->disable != NULL && sc->enabled != 0) { 691 (*sc->disable)(sc); 692 sc->enabled = 0; 693 } 694 break; 695 } 696 697 COM_UNLOCK(sc); 698 splx(s); 699 return (rv); 700 } 701 702 void 703 com_shutdown(struct com_softc *sc) 704 { 705 struct tty *tp = sc->sc_tty; 706 int s; 707 708 s = splserial(); 709 COM_LOCK(sc); 710 711 /* If we were asserting flow control, then deassert it. */ 712 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 713 com_hwiflow(sc); 714 715 /* Clear any break condition set with TIOCSBRK. */ 716 com_break(sc, 0); 717 718 #ifndef __HAVE_TIMECOUNTER 719 /* Turn off PPS capture on last close. */ 720 sc->sc_ppsmask = 0; 721 sc->ppsparam.mode = 0; 722 #endif /* !__HAVE_TIMECOUNTER */ 723 724 /* 725 * Hang up if necessary. Wait a bit, so the other side has time to 726 * notice even if we immediately open the port again. 727 * Avoid tsleeping above splhigh(). 728 */ 729 if (ISSET(tp->t_cflag, HUPCL)) { 730 com_modem(sc, 0); 731 COM_UNLOCK(sc); 732 splx(s); 733 /* XXX tsleep will only timeout */ 734 (void) tsleep(sc, TTIPRI, ttclos, hz); 735 s = splserial(); 736 COM_LOCK(sc); 737 } 738 739 /* Turn off interrupts. */ 740 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 741 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 742 if (sc->sc_type == COM_TYPE_PXA2x0) 743 sc->sc_ier |= IER_ERXTOUT; 744 } else 745 sc->sc_ier = 0; 746 747 if (sc->sc_type == COM_TYPE_PXA2x0) 748 sc->sc_ier |= IER_EUART; 749 750 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 751 752 if (sc->disable) { 753 #ifdef DIAGNOSTIC 754 if (!sc->enabled) 755 panic("com_shutdown: not enabled?"); 756 #endif 757 (*sc->disable)(sc); 758 sc->enabled = 0; 759 } 760 COM_UNLOCK(sc); 761 splx(s); 762 } 763 764 int 765 comopen(dev_t dev, int flag, int mode, struct lwp *l) 766 { 767 struct com_softc *sc; 768 struct tty *tp; 769 int s, s2; 770 int error; 771 772 sc = device_lookup(&com_cd, COMUNIT(dev)); 773 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 774 sc->sc_rbuf == NULL) 775 return (ENXIO); 776 777 if (!device_is_active(&sc->sc_dev)) 778 return (ENXIO); 779 780 #ifdef KGDB 781 /* 782 * If this is the kgdb port, no other use is permitted. 783 */ 784 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 785 return (EBUSY); 786 #endif 787 788 tp = sc->sc_tty; 789 790 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 791 return (EBUSY); 792 793 s = spltty(); 794 795 /* 796 * Do the following iff this is a first open. 797 */ 798 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 799 struct termios t; 800 801 tp->t_dev = dev; 802 803 s2 = splserial(); 804 COM_LOCK(sc); 805 806 if (sc->enable) { 807 if ((*sc->enable)(sc)) { 808 COM_UNLOCK(sc); 809 splx(s2); 810 splx(s); 811 printf("%s: device enable failed\n", 812 sc->sc_dev.dv_xname); 813 return (EIO); 814 } 815 sc->enabled = 1; 816 com_config(sc); 817 } 818 819 /* Turn on interrupts. */ 820 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 821 if (sc->sc_type == COM_TYPE_PXA2x0) 822 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 823 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 824 825 /* Fetch the current modem control status, needed later. */ 826 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 827 828 /* Clear PPS capture state on first open. */ 829 #ifdef __HAVE_TIMECOUNTER 830 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 831 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 832 pps_init(&sc->sc_pps_state); 833 #else /* !__HAVE_TIMECOUNTER */ 834 sc->sc_ppsmask = 0; 835 sc->ppsparam.mode = 0; 836 #endif /* !__HAVE_TIMECOUNTER */ 837 838 COM_UNLOCK(sc); 839 splx(s2); 840 841 /* 842 * Initialize the termios status to the defaults. Add in the 843 * sticky bits from TIOCSFLAGS. 844 */ 845 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 846 t.c_ospeed = comconsrate; 847 t.c_cflag = comconscflag; 848 } else { 849 t.c_ospeed = TTYDEF_SPEED; 850 t.c_cflag = TTYDEF_CFLAG; 851 } 852 t.c_ispeed = t.c_ospeed; 853 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 854 SET(t.c_cflag, CLOCAL); 855 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 856 SET(t.c_cflag, CRTSCTS); 857 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 858 SET(t.c_cflag, MDMBUF); 859 /* Make sure comparam() will do something. */ 860 tp->t_ospeed = 0; 861 (void) comparam(tp, &t); 862 tp->t_iflag = TTYDEF_IFLAG; 863 tp->t_oflag = TTYDEF_OFLAG; 864 tp->t_lflag = TTYDEF_LFLAG; 865 ttychars(tp); 866 ttsetwater(tp); 867 868 s2 = splserial(); 869 COM_LOCK(sc); 870 871 /* 872 * Turn on DTR. We must always do this, even if carrier is not 873 * present, because otherwise we'd have to use TIOCSDTR 874 * immediately after setting CLOCAL, which applications do not 875 * expect. We always assert DTR while the device is open 876 * unless explicitly requested to deassert it. 877 */ 878 com_modem(sc, 1); 879 880 /* Clear the input ring, and unblock. */ 881 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 882 sc->sc_rbavail = com_rbuf_size; 883 com_iflush(sc); 884 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 885 com_hwiflow(sc); 886 887 #ifdef COM_DEBUG 888 if (com_debug) 889 comstatus(sc, "comopen "); 890 #endif 891 892 COM_UNLOCK(sc); 893 splx(s2); 894 } 895 896 splx(s); 897 898 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 899 if (error) 900 goto bad; 901 902 error = (*tp->t_linesw->l_open)(dev, tp); 903 if (error) 904 goto bad; 905 906 return (0); 907 908 bad: 909 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 910 /* 911 * We failed to open the device, and nobody else had it opened. 912 * Clean up the state as appropriate. 913 */ 914 com_shutdown(sc); 915 } 916 917 return (error); 918 } 919 920 int 921 comclose(dev_t dev, int flag, int mode, struct lwp *l) 922 { 923 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 924 struct tty *tp = sc->sc_tty; 925 926 /* XXX This is for cons.c. */ 927 if (!ISSET(tp->t_state, TS_ISOPEN)) 928 return (0); 929 930 (*tp->t_linesw->l_close)(tp, flag); 931 ttyclose(tp); 932 933 if (COM_ISALIVE(sc) == 0) 934 return (0); 935 936 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 937 /* 938 * Although we got a last close, the device may still be in 939 * use; e.g. if this was the dialout node, and there are still 940 * processes waiting for carrier on the non-dialout node. 941 */ 942 com_shutdown(sc); 943 } 944 945 return (0); 946 } 947 948 int 949 comread(dev_t dev, struct uio *uio, int flag) 950 { 951 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 952 struct tty *tp = sc->sc_tty; 953 954 if (COM_ISALIVE(sc) == 0) 955 return (EIO); 956 957 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 958 } 959 960 int 961 comwrite(dev_t dev, struct uio *uio, int flag) 962 { 963 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 964 struct tty *tp = sc->sc_tty; 965 966 if (COM_ISALIVE(sc) == 0) 967 return (EIO); 968 969 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 970 } 971 972 int 973 compoll(dev_t dev, int events, struct lwp *l) 974 { 975 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 976 struct tty *tp = sc->sc_tty; 977 978 if (COM_ISALIVE(sc) == 0) 979 return (POLLHUP); 980 981 return ((*tp->t_linesw->l_poll)(tp, events, l)); 982 } 983 984 struct tty * 985 comtty(dev_t dev) 986 { 987 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 988 struct tty *tp = sc->sc_tty; 989 990 return (tp); 991 } 992 993 int 994 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 995 { 996 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 997 struct tty *tp = sc->sc_tty; 998 int error; 999 int s; 1000 1001 if (COM_ISALIVE(sc) == 0) 1002 return (EIO); 1003 1004 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1005 if (error != EPASSTHROUGH) 1006 return (error); 1007 1008 error = ttioctl(tp, cmd, data, flag, l); 1009 if (error != EPASSTHROUGH) 1010 return (error); 1011 1012 error = 0; 1013 switch (cmd) { 1014 case TIOCSFLAGS: 1015 error = kauth_authorize_device_tty(l->l_cred, 1016 KAUTH_DEVICE_TTY_PRIVSET, tp); 1017 break; 1018 default: 1019 /* nothing */ 1020 break; 1021 } 1022 if (error) { 1023 return error; 1024 } 1025 1026 s = splserial(); 1027 COM_LOCK(sc); 1028 1029 switch (cmd) { 1030 case TIOCSBRK: 1031 com_break(sc, 1); 1032 break; 1033 1034 case TIOCCBRK: 1035 com_break(sc, 0); 1036 break; 1037 1038 case TIOCSDTR: 1039 com_modem(sc, 1); 1040 break; 1041 1042 case TIOCCDTR: 1043 com_modem(sc, 0); 1044 break; 1045 1046 case TIOCGFLAGS: 1047 *(int *)data = sc->sc_swflags; 1048 break; 1049 1050 case TIOCSFLAGS: 1051 sc->sc_swflags = *(int *)data; 1052 break; 1053 1054 case TIOCMSET: 1055 case TIOCMBIS: 1056 case TIOCMBIC: 1057 tiocm_to_com(sc, cmd, *(int *)data); 1058 break; 1059 1060 case TIOCMGET: 1061 *(int *)data = com_to_tiocm(sc); 1062 break; 1063 1064 #ifdef __HAVE_TIMECOUNTER 1065 case PPS_IOC_CREATE: 1066 case PPS_IOC_DESTROY: 1067 case PPS_IOC_GETPARAMS: 1068 case PPS_IOC_SETPARAMS: 1069 case PPS_IOC_GETCAP: 1070 case PPS_IOC_FETCH: 1071 #ifdef PPS_SYNC 1072 case PPS_IOC_KCBIND: 1073 #endif 1074 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1075 break; 1076 #else /* !__HAVE_TIMECOUNTER */ 1077 case PPS_IOC_CREATE: 1078 break; 1079 1080 case PPS_IOC_DESTROY: 1081 break; 1082 1083 case PPS_IOC_GETPARAMS: { 1084 pps_params_t *pp; 1085 pp = (pps_params_t *)data; 1086 *pp = sc->ppsparam; 1087 break; 1088 } 1089 1090 case PPS_IOC_SETPARAMS: { 1091 pps_params_t *pp; 1092 int mode; 1093 pp = (pps_params_t *)data; 1094 if (pp->mode & ~ppscap) { 1095 error = EINVAL; 1096 break; 1097 } 1098 sc->ppsparam = *pp; 1099 /* 1100 * Compute msr masks from user-specified timestamp state. 1101 */ 1102 mode = sc->ppsparam.mode; 1103 switch (mode & PPS_CAPTUREBOTH) { 1104 case 0: 1105 sc->sc_ppsmask = 0; 1106 break; 1107 1108 case PPS_CAPTUREASSERT: 1109 sc->sc_ppsmask = MSR_DCD; 1110 sc->sc_ppsassert = MSR_DCD; 1111 sc->sc_ppsclear = -1; 1112 break; 1113 1114 case PPS_CAPTURECLEAR: 1115 sc->sc_ppsmask = MSR_DCD; 1116 sc->sc_ppsassert = -1; 1117 sc->sc_ppsclear = 0; 1118 break; 1119 1120 case PPS_CAPTUREBOTH: 1121 sc->sc_ppsmask = MSR_DCD; 1122 sc->sc_ppsassert = MSR_DCD; 1123 sc->sc_ppsclear = 0; 1124 break; 1125 1126 default: 1127 error = EINVAL; 1128 break; 1129 } 1130 break; 1131 } 1132 1133 case PPS_IOC_GETCAP: 1134 *(int*)data = ppscap; 1135 break; 1136 1137 case PPS_IOC_FETCH: { 1138 pps_info_t *pi; 1139 pi = (pps_info_t *)data; 1140 *pi = sc->ppsinfo; 1141 break; 1142 } 1143 1144 #ifdef PPS_SYNC 1145 case PPS_IOC_KCBIND: { 1146 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1147 1148 if (edge == 0) { 1149 /* 1150 * remove binding for this source; ignore 1151 * the request if this is not the current 1152 * hardpps source 1153 */ 1154 if (pps_kc_hardpps_source == sc) { 1155 pps_kc_hardpps_source = NULL; 1156 pps_kc_hardpps_mode = 0; 1157 } 1158 } else { 1159 /* 1160 * bind hardpps to this source, replacing any 1161 * previously specified source or edges 1162 */ 1163 pps_kc_hardpps_source = sc; 1164 pps_kc_hardpps_mode = edge; 1165 } 1166 break; 1167 } 1168 #endif /* PPS_SYNC */ 1169 #endif /* !__HAVE_TIMECOUNTER */ 1170 1171 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1172 #ifdef __HAVE_TIMECOUNTER 1173 #ifndef PPS_TRAILING_EDGE 1174 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1175 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1176 #else 1177 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1178 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1179 #endif 1180 #else /* !__HAVE_TIMECOUNTER */ 1181 /* 1182 * Some GPS clocks models use the falling rather than 1183 * rising edge as the on-the-second signal. 1184 * The old API has no way to specify PPS polarity. 1185 */ 1186 sc->sc_ppsmask = MSR_DCD; 1187 #ifndef PPS_TRAILING_EDGE 1188 sc->sc_ppsassert = MSR_DCD; 1189 sc->sc_ppsclear = -1; 1190 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1191 &sc->ppsinfo.assert_timestamp); 1192 #else 1193 sc->sc_ppsassert = -1; 1194 sc->sc_ppsclear = 0; 1195 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1196 &sc->ppsinfo.clear_timestamp); 1197 #endif 1198 #endif /* !__HAVE_TIMECOUNTER */ 1199 break; 1200 1201 default: 1202 error = EPASSTHROUGH; 1203 break; 1204 } 1205 1206 COM_UNLOCK(sc); 1207 splx(s); 1208 1209 #ifdef COM_DEBUG 1210 if (com_debug) 1211 comstatus(sc, "comioctl "); 1212 #endif 1213 1214 return (error); 1215 } 1216 1217 integrate void 1218 com_schedrx(struct com_softc *sc) 1219 { 1220 1221 sc->sc_rx_ready = 1; 1222 1223 /* Wake up the poller. */ 1224 softint_schedule(sc->sc_si); 1225 } 1226 1227 void 1228 com_break(struct com_softc *sc, int onoff) 1229 { 1230 1231 if (onoff) 1232 SET(sc->sc_lcr, LCR_SBREAK); 1233 else 1234 CLR(sc->sc_lcr, LCR_SBREAK); 1235 1236 if (!sc->sc_heldchange) { 1237 if (sc->sc_tx_busy) { 1238 sc->sc_heldtbc = sc->sc_tbc; 1239 sc->sc_tbc = 0; 1240 sc->sc_heldchange = 1; 1241 } else 1242 com_loadchannelregs(sc); 1243 } 1244 } 1245 1246 void 1247 com_modem(struct com_softc *sc, int onoff) 1248 { 1249 1250 if (sc->sc_mcr_dtr == 0) 1251 return; 1252 1253 if (onoff) 1254 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1255 else 1256 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1257 1258 if (!sc->sc_heldchange) { 1259 if (sc->sc_tx_busy) { 1260 sc->sc_heldtbc = sc->sc_tbc; 1261 sc->sc_tbc = 0; 1262 sc->sc_heldchange = 1; 1263 } else 1264 com_loadchannelregs(sc); 1265 } 1266 } 1267 1268 void 1269 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1270 { 1271 u_char combits; 1272 1273 combits = 0; 1274 if (ISSET(ttybits, TIOCM_DTR)) 1275 SET(combits, MCR_DTR); 1276 if (ISSET(ttybits, TIOCM_RTS)) 1277 SET(combits, MCR_RTS); 1278 1279 switch (how) { 1280 case TIOCMBIC: 1281 CLR(sc->sc_mcr, combits); 1282 break; 1283 1284 case TIOCMBIS: 1285 SET(sc->sc_mcr, combits); 1286 break; 1287 1288 case TIOCMSET: 1289 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1290 SET(sc->sc_mcr, combits); 1291 break; 1292 } 1293 1294 if (!sc->sc_heldchange) { 1295 if (sc->sc_tx_busy) { 1296 sc->sc_heldtbc = sc->sc_tbc; 1297 sc->sc_tbc = 0; 1298 sc->sc_heldchange = 1; 1299 } else 1300 com_loadchannelregs(sc); 1301 } 1302 } 1303 1304 int 1305 com_to_tiocm(struct com_softc *sc) 1306 { 1307 u_char combits; 1308 int ttybits = 0; 1309 1310 combits = sc->sc_mcr; 1311 if (ISSET(combits, MCR_DTR)) 1312 SET(ttybits, TIOCM_DTR); 1313 if (ISSET(combits, MCR_RTS)) 1314 SET(ttybits, TIOCM_RTS); 1315 1316 combits = sc->sc_msr; 1317 if (ISSET(combits, MSR_DCD)) 1318 SET(ttybits, TIOCM_CD); 1319 if (ISSET(combits, MSR_CTS)) 1320 SET(ttybits, TIOCM_CTS); 1321 if (ISSET(combits, MSR_DSR)) 1322 SET(ttybits, TIOCM_DSR); 1323 if (ISSET(combits, MSR_RI | MSR_TERI)) 1324 SET(ttybits, TIOCM_RI); 1325 1326 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1327 SET(ttybits, TIOCM_LE); 1328 1329 return (ttybits); 1330 } 1331 1332 static u_char 1333 cflag2lcr(tcflag_t cflag) 1334 { 1335 u_char lcr = 0; 1336 1337 switch (ISSET(cflag, CSIZE)) { 1338 case CS5: 1339 SET(lcr, LCR_5BITS); 1340 break; 1341 case CS6: 1342 SET(lcr, LCR_6BITS); 1343 break; 1344 case CS7: 1345 SET(lcr, LCR_7BITS); 1346 break; 1347 case CS8: 1348 SET(lcr, LCR_8BITS); 1349 break; 1350 } 1351 if (ISSET(cflag, PARENB)) { 1352 SET(lcr, LCR_PENAB); 1353 if (!ISSET(cflag, PARODD)) 1354 SET(lcr, LCR_PEVEN); 1355 } 1356 if (ISSET(cflag, CSTOPB)) 1357 SET(lcr, LCR_STOPB); 1358 1359 return (lcr); 1360 } 1361 1362 int 1363 comparam(struct tty *tp, struct termios *t) 1364 { 1365 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1366 int ospeed; 1367 u_char lcr; 1368 int s; 1369 1370 if (COM_ISALIVE(sc) == 0) 1371 return (EIO); 1372 1373 #ifdef COM_HAYESP 1374 if (sc->sc_type == COM_TYPE_HAYESP) { 1375 int prescaler, speed; 1376 1377 /* 1378 * Calculate UART clock prescaler. It should be in 1379 * range of 0 .. 3. 1380 */ 1381 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1382 prescaler++, speed /= 2) 1383 if ((ospeed = comspeed(speed, sc->sc_frequency, 1384 sc->sc_type)) > 0) 1385 break; 1386 1387 if (prescaler == 4) 1388 return (EINVAL); 1389 sc->sc_prescaler = prescaler; 1390 } else 1391 #endif 1392 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1393 1394 /* Check requested parameters. */ 1395 if (ospeed < 0) 1396 return (EINVAL); 1397 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1398 return (EINVAL); 1399 1400 /* 1401 * For the console, always force CLOCAL and !HUPCL, so that the port 1402 * is always active. 1403 */ 1404 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1405 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1406 SET(t->c_cflag, CLOCAL); 1407 CLR(t->c_cflag, HUPCL); 1408 } 1409 1410 /* 1411 * If there were no changes, don't do anything. This avoids dropping 1412 * input and improves performance when all we did was frob things like 1413 * VMIN and VTIME. 1414 */ 1415 if (tp->t_ospeed == t->c_ospeed && 1416 tp->t_cflag == t->c_cflag) 1417 return (0); 1418 1419 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1420 1421 s = splserial(); 1422 COM_LOCK(sc); 1423 1424 sc->sc_lcr = lcr; 1425 1426 /* 1427 * If we're not in a mode that assumes a connection is present, then 1428 * ignore carrier changes. 1429 */ 1430 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1431 sc->sc_msr_dcd = 0; 1432 else 1433 sc->sc_msr_dcd = MSR_DCD; 1434 /* 1435 * Set the flow control pins depending on the current flow control 1436 * mode. 1437 */ 1438 if (ISSET(t->c_cflag, CRTSCTS)) { 1439 sc->sc_mcr_dtr = MCR_DTR; 1440 sc->sc_mcr_rts = MCR_RTS; 1441 sc->sc_msr_cts = MSR_CTS; 1442 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1443 } else if (ISSET(t->c_cflag, MDMBUF)) { 1444 /* 1445 * For DTR/DCD flow control, make sure we don't toggle DTR for 1446 * carrier detection. 1447 */ 1448 sc->sc_mcr_dtr = 0; 1449 sc->sc_mcr_rts = MCR_DTR; 1450 sc->sc_msr_cts = MSR_DCD; 1451 sc->sc_efr = 0; 1452 } else { 1453 /* 1454 * If no flow control, then always set RTS. This will make 1455 * the other side happy if it mistakenly thinks we're doing 1456 * RTS/CTS flow control. 1457 */ 1458 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1459 sc->sc_mcr_rts = 0; 1460 sc->sc_msr_cts = 0; 1461 sc->sc_efr = 0; 1462 if (ISSET(sc->sc_mcr, MCR_DTR)) 1463 SET(sc->sc_mcr, MCR_RTS); 1464 else 1465 CLR(sc->sc_mcr, MCR_RTS); 1466 } 1467 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1468 1469 #if 0 1470 if (ospeed == 0) 1471 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1472 else 1473 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1474 #endif 1475 1476 sc->sc_dlbl = ospeed; 1477 sc->sc_dlbh = ospeed >> 8; 1478 1479 /* 1480 * Set the FIFO threshold based on the receive speed. 1481 * 1482 * * If it's a low speed, it's probably a mouse or some other 1483 * interactive device, so set the threshold low. 1484 * * If it's a high speed, trim the trigger level down to prevent 1485 * overflows. 1486 * * Otherwise set it a bit higher. 1487 */ 1488 if (sc->sc_type == COM_TYPE_HAYESP) 1489 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1490 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1491 sc->sc_fifo = FIFO_ENABLE | 1492 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1493 else 1494 sc->sc_fifo = 0; 1495 1496 /* And copy to tty. */ 1497 tp->t_ispeed = t->c_ospeed; 1498 tp->t_ospeed = t->c_ospeed; 1499 tp->t_cflag = t->c_cflag; 1500 1501 if (!sc->sc_heldchange) { 1502 if (sc->sc_tx_busy) { 1503 sc->sc_heldtbc = sc->sc_tbc; 1504 sc->sc_tbc = 0; 1505 sc->sc_heldchange = 1; 1506 } else 1507 com_loadchannelregs(sc); 1508 } 1509 1510 if (!ISSET(t->c_cflag, CHWFLOW)) { 1511 /* Disable the high water mark. */ 1512 sc->sc_r_hiwat = 0; 1513 sc->sc_r_lowat = 0; 1514 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1515 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1516 com_schedrx(sc); 1517 } 1518 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1519 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1520 com_hwiflow(sc); 1521 } 1522 } else { 1523 sc->sc_r_hiwat = com_rbuf_hiwat; 1524 sc->sc_r_lowat = com_rbuf_lowat; 1525 } 1526 1527 COM_UNLOCK(sc); 1528 splx(s); 1529 1530 /* 1531 * Update the tty layer's idea of the carrier bit, in case we changed 1532 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1533 * explicit request. 1534 */ 1535 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1536 1537 #ifdef COM_DEBUG 1538 if (com_debug) 1539 comstatus(sc, "comparam "); 1540 #endif 1541 1542 if (!ISSET(t->c_cflag, CHWFLOW)) { 1543 if (sc->sc_tx_stopped) { 1544 sc->sc_tx_stopped = 0; 1545 comstart(tp); 1546 } 1547 } 1548 1549 return (0); 1550 } 1551 1552 void 1553 com_iflush(struct com_softc *sc) 1554 { 1555 struct com_regs *regsp = &sc->sc_regs; 1556 #ifdef DIAGNOSTIC 1557 int reg; 1558 #endif 1559 int timo; 1560 1561 #ifdef DIAGNOSTIC 1562 reg = 0xffff; 1563 #endif 1564 timo = 50000; 1565 /* flush any pending I/O */ 1566 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1567 && --timo) 1568 #ifdef DIAGNOSTIC 1569 reg = 1570 #else 1571 (void) 1572 #endif 1573 CSR_READ_1(regsp, COM_REG_RXDATA); 1574 #ifdef DIAGNOSTIC 1575 if (!timo) 1576 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1577 reg); 1578 #endif 1579 } 1580 1581 void 1582 com_loadchannelregs(struct com_softc *sc) 1583 { 1584 struct com_regs *regsp = &sc->sc_regs; 1585 1586 /* XXXXX necessary? */ 1587 com_iflush(sc); 1588 1589 if (sc->sc_type == COM_TYPE_PXA2x0) 1590 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1591 else 1592 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1593 1594 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1595 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1596 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1597 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1598 } 1599 } 1600 if (sc->sc_type == COM_TYPE_AU1x00) { 1601 /* alchemy has single separate 16-bit clock divisor register */ 1602 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1603 (sc->sc_dlbh << 8)); 1604 } else { 1605 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1606 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1607 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1608 } 1609 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1610 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1611 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1612 #ifdef COM_HAYESP 1613 if (sc->sc_type == COM_TYPE_HAYESP) { 1614 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1615 HAYESP_SETPRESCALER); 1616 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1617 sc->sc_prescaler); 1618 } 1619 #endif 1620 1621 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1622 } 1623 1624 int 1625 comhwiflow(struct tty *tp, int block) 1626 { 1627 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1628 int s; 1629 1630 if (COM_ISALIVE(sc) == 0) 1631 return (0); 1632 1633 if (sc->sc_mcr_rts == 0) 1634 return (0); 1635 1636 s = splserial(); 1637 COM_LOCK(sc); 1638 1639 if (block) { 1640 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1641 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1642 com_hwiflow(sc); 1643 } 1644 } else { 1645 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1646 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1647 com_schedrx(sc); 1648 } 1649 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1650 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1651 com_hwiflow(sc); 1652 } 1653 } 1654 1655 COM_UNLOCK(sc); 1656 splx(s); 1657 return (1); 1658 } 1659 1660 /* 1661 * (un)block input via hw flowcontrol 1662 */ 1663 void 1664 com_hwiflow(struct com_softc *sc) 1665 { 1666 struct com_regs *regsp= &sc->sc_regs; 1667 1668 if (sc->sc_mcr_rts == 0) 1669 return; 1670 1671 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1672 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1673 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1674 } else { 1675 SET(sc->sc_mcr, sc->sc_mcr_rts); 1676 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1677 } 1678 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1679 } 1680 1681 1682 void 1683 comstart(struct tty *tp) 1684 { 1685 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1686 struct com_regs *regsp = &sc->sc_regs; 1687 int s; 1688 1689 if (COM_ISALIVE(sc) == 0) 1690 return; 1691 1692 s = spltty(); 1693 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1694 goto out; 1695 if (sc->sc_tx_stopped) 1696 goto out; 1697 1698 if (tp->t_outq.c_cc <= tp->t_lowat) { 1699 if (ISSET(tp->t_state, TS_ASLEEP)) { 1700 CLR(tp->t_state, TS_ASLEEP); 1701 wakeup(&tp->t_outq); 1702 } 1703 selwakeup(&tp->t_wsel); 1704 if (tp->t_outq.c_cc == 0) 1705 goto out; 1706 } 1707 1708 /* Grab the first contiguous region of buffer space. */ 1709 { 1710 u_char *tba; 1711 int tbc; 1712 1713 tba = tp->t_outq.c_cf; 1714 tbc = ndqb(&tp->t_outq, 0); 1715 1716 (void)splserial(); 1717 COM_LOCK(sc); 1718 1719 sc->sc_tba = tba; 1720 sc->sc_tbc = tbc; 1721 } 1722 1723 SET(tp->t_state, TS_BUSY); 1724 sc->sc_tx_busy = 1; 1725 1726 /* Enable transmit completion interrupts if necessary. */ 1727 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1728 SET(sc->sc_ier, IER_ETXRDY); 1729 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1730 } 1731 1732 /* Output the first chunk of the contiguous buffer. */ 1733 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1734 u_int n; 1735 1736 n = sc->sc_tbc; 1737 if (n > sc->sc_fifolen) 1738 n = sc->sc_fifolen; 1739 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1740 sc->sc_tbc -= n; 1741 sc->sc_tba += n; 1742 } 1743 1744 COM_UNLOCK(sc); 1745 out: 1746 splx(s); 1747 return; 1748 } 1749 1750 /* 1751 * Stop output on a line. 1752 */ 1753 void 1754 comstop(struct tty *tp, int flag) 1755 { 1756 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1757 int s; 1758 1759 s = splserial(); 1760 COM_LOCK(sc); 1761 if (ISSET(tp->t_state, TS_BUSY)) { 1762 /* Stop transmitting at the next chunk. */ 1763 sc->sc_tbc = 0; 1764 sc->sc_heldtbc = 0; 1765 if (!ISSET(tp->t_state, TS_TTSTOP)) 1766 SET(tp->t_state, TS_FLUSH); 1767 } 1768 COM_UNLOCK(sc); 1769 splx(s); 1770 } 1771 1772 void 1773 comdiag(void *arg) 1774 { 1775 struct com_softc *sc = arg; 1776 int overflows, floods; 1777 int s; 1778 1779 s = splserial(); 1780 COM_LOCK(sc); 1781 overflows = sc->sc_overflows; 1782 sc->sc_overflows = 0; 1783 floods = sc->sc_floods; 1784 sc->sc_floods = 0; 1785 sc->sc_errors = 0; 1786 COM_UNLOCK(sc); 1787 splx(s); 1788 1789 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1790 sc->sc_dev.dv_xname, 1791 overflows, overflows == 1 ? "" : "s", 1792 floods, floods == 1 ? "" : "s"); 1793 } 1794 1795 integrate void 1796 com_rxsoft(struct com_softc *sc, struct tty *tp) 1797 { 1798 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1799 u_char *get, *end; 1800 u_int cc, scc; 1801 u_char lsr; 1802 int code; 1803 int s; 1804 1805 end = sc->sc_ebuf; 1806 get = sc->sc_rbget; 1807 scc = cc = com_rbuf_size - sc->sc_rbavail; 1808 1809 if (cc == com_rbuf_size) { 1810 sc->sc_floods++; 1811 if (sc->sc_errors++ == 0) 1812 callout_reset(&sc->sc_diag_callout, 60 * hz, 1813 comdiag, sc); 1814 } 1815 1816 /* If not yet open, drop the entire buffer content here */ 1817 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1818 get += cc << 1; 1819 if (get >= end) 1820 get -= com_rbuf_size << 1; 1821 cc = 0; 1822 } 1823 while (cc) { 1824 code = get[0]; 1825 lsr = get[1]; 1826 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1827 if (ISSET(lsr, LSR_OE)) { 1828 sc->sc_overflows++; 1829 if (sc->sc_errors++ == 0) 1830 callout_reset(&sc->sc_diag_callout, 1831 60 * hz, comdiag, sc); 1832 } 1833 if (ISSET(lsr, LSR_BI | LSR_FE)) 1834 SET(code, TTY_FE); 1835 if (ISSET(lsr, LSR_PE)) 1836 SET(code, TTY_PE); 1837 } 1838 if ((*rint)(code, tp) == -1) { 1839 /* 1840 * The line discipline's buffer is out of space. 1841 */ 1842 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1843 /* 1844 * We're either not using flow control, or the 1845 * line discipline didn't tell us to block for 1846 * some reason. Either way, we have no way to 1847 * know when there's more space available, so 1848 * just drop the rest of the data. 1849 */ 1850 get += cc << 1; 1851 if (get >= end) 1852 get -= com_rbuf_size << 1; 1853 cc = 0; 1854 } else { 1855 /* 1856 * Don't schedule any more receive processing 1857 * until the line discipline tells us there's 1858 * space available (through comhwiflow()). 1859 * Leave the rest of the data in the input 1860 * buffer. 1861 */ 1862 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1863 } 1864 break; 1865 } 1866 get += 2; 1867 if (get >= end) 1868 get = sc->sc_rbuf; 1869 cc--; 1870 } 1871 1872 if (cc != scc) { 1873 sc->sc_rbget = get; 1874 s = splserial(); 1875 COM_LOCK(sc); 1876 1877 cc = sc->sc_rbavail += scc - cc; 1878 /* Buffers should be ok again, release possible block. */ 1879 if (cc >= sc->sc_r_lowat) { 1880 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1881 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1882 SET(sc->sc_ier, IER_ERXRDY); 1883 #ifdef COM_PXA2X0 1884 if (sc->sc_type == COM_TYPE_PXA2x0) 1885 SET(sc->sc_ier, IER_ERXTOUT); 1886 #endif 1887 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1888 } 1889 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1890 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1891 com_hwiflow(sc); 1892 } 1893 } 1894 COM_UNLOCK(sc); 1895 splx(s); 1896 } 1897 } 1898 1899 integrate void 1900 com_txsoft(struct com_softc *sc, struct tty *tp) 1901 { 1902 1903 CLR(tp->t_state, TS_BUSY); 1904 if (ISSET(tp->t_state, TS_FLUSH)) 1905 CLR(tp->t_state, TS_FLUSH); 1906 else 1907 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1908 (*tp->t_linesw->l_start)(tp); 1909 } 1910 1911 integrate void 1912 com_stsoft(struct com_softc *sc, struct tty *tp) 1913 { 1914 u_char msr, delta; 1915 int s; 1916 1917 s = splserial(); 1918 COM_LOCK(sc); 1919 msr = sc->sc_msr; 1920 delta = sc->sc_msr_delta; 1921 sc->sc_msr_delta = 0; 1922 COM_UNLOCK(sc); 1923 splx(s); 1924 1925 if (ISSET(delta, sc->sc_msr_dcd)) { 1926 /* 1927 * Inform the tty layer that carrier detect changed. 1928 */ 1929 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1930 } 1931 1932 if (ISSET(delta, sc->sc_msr_cts)) { 1933 /* Block or unblock output according to flow control. */ 1934 if (ISSET(msr, sc->sc_msr_cts)) { 1935 sc->sc_tx_stopped = 0; 1936 (*tp->t_linesw->l_start)(tp); 1937 } else { 1938 sc->sc_tx_stopped = 1; 1939 } 1940 } 1941 1942 #ifdef COM_DEBUG 1943 if (com_debug) 1944 comstatus(sc, "com_stsoft"); 1945 #endif 1946 } 1947 1948 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1949 void 1950 comsoft(void *arg) 1951 { 1952 struct com_softc *sc = arg; 1953 struct tty *tp; 1954 1955 if (COM_ISALIVE(sc) == 0) 1956 return; 1957 1958 { 1959 #else 1960 void 1961 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1962 comsoft(void) 1963 #else 1964 comsoft(void *arg) 1965 #endif 1966 { 1967 struct com_softc *sc; 1968 struct tty *tp; 1969 int unit; 1970 1971 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1972 sc = device_lookup(&com_cd, unit); 1973 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK)) 1974 continue; 1975 1976 if (COM_ISALIVE(sc) == 0) 1977 continue; 1978 1979 tp = sc->sc_tty; 1980 if (tp == NULL) 1981 continue; 1982 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1983 continue; 1984 #endif 1985 tp = sc->sc_tty; 1986 1987 if (sc->sc_rx_ready) { 1988 sc->sc_rx_ready = 0; 1989 com_rxsoft(sc, tp); 1990 } 1991 1992 if (sc->sc_st_check) { 1993 sc->sc_st_check = 0; 1994 com_stsoft(sc, tp); 1995 } 1996 1997 if (sc->sc_tx_done) { 1998 sc->sc_tx_done = 0; 1999 com_txsoft(sc, tp); 2000 } 2001 } 2002 2003 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 2004 #ifdef __NO_SOFT_SERIAL_INTERRUPT 2005 splx(s); 2006 #endif 2007 #endif 2008 } 2009 2010 #ifdef __ALIGN_BRACKET_LEVEL_FOR_CTAGS 2011 /* there has got to be a better way to do comsoft() */ 2012 }} 2013 #endif 2014 2015 int 2016 comintr(void *arg) 2017 { 2018 struct com_softc *sc = arg; 2019 struct com_regs *regsp = &sc->sc_regs; 2020 2021 u_char *put, *end; 2022 u_int cc; 2023 u_char lsr, iir; 2024 2025 if (COM_ISALIVE(sc) == 0) 2026 return (0); 2027 2028 COM_LOCK(sc); 2029 iir = CSR_READ_1(regsp, COM_REG_IIR); 2030 if (ISSET(iir, IIR_NOPEND)) { 2031 COM_UNLOCK(sc); 2032 return (0); 2033 } 2034 2035 end = sc->sc_ebuf; 2036 put = sc->sc_rbput; 2037 cc = sc->sc_rbavail; 2038 2039 again: do { 2040 u_char msr, delta; 2041 2042 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2043 if (ISSET(lsr, LSR_BI)) { 2044 int cn_trapped = 0; 2045 2046 cn_check_magic(sc->sc_tty->t_dev, 2047 CNC_BREAK, com_cnm_state); 2048 if (cn_trapped) 2049 continue; 2050 #if defined(KGDB) && !defined(DDB) 2051 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2052 kgdb_connect(1); 2053 continue; 2054 } 2055 #endif 2056 } 2057 2058 if (ISSET(lsr, LSR_RCV_MASK) && 2059 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2060 while (cc > 0) { 2061 int cn_trapped = 0; 2062 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2063 put[1] = lsr; 2064 cn_check_magic(sc->sc_tty->t_dev, 2065 put[0], com_cnm_state); 2066 if (cn_trapped) 2067 goto next; 2068 put += 2; 2069 if (put >= end) 2070 put = sc->sc_rbuf; 2071 cc--; 2072 next: 2073 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2074 if (!ISSET(lsr, LSR_RCV_MASK)) 2075 break; 2076 } 2077 2078 /* 2079 * Current string of incoming characters ended because 2080 * no more data was available or we ran out of space. 2081 * Schedule a receive event if any data was received. 2082 * If we're out of space, turn off receive interrupts. 2083 */ 2084 sc->sc_rbput = put; 2085 sc->sc_rbavail = cc; 2086 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2087 sc->sc_rx_ready = 1; 2088 2089 /* 2090 * See if we are in danger of overflowing a buffer. If 2091 * so, use hardware flow control to ease the pressure. 2092 */ 2093 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2094 cc < sc->sc_r_hiwat) { 2095 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2096 com_hwiflow(sc); 2097 } 2098 2099 /* 2100 * If we're out of space, disable receive interrupts 2101 * until the queue has drained a bit. 2102 */ 2103 if (!cc) { 2104 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2105 #ifdef COM_PXA2X0 2106 if (sc->sc_type == COM_TYPE_PXA2x0) 2107 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2108 else 2109 #endif 2110 CLR(sc->sc_ier, IER_ERXRDY); 2111 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2112 } 2113 } else { 2114 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2115 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2116 continue; 2117 } 2118 } 2119 2120 msr = CSR_READ_1(regsp, COM_REG_MSR); 2121 delta = msr ^ sc->sc_msr; 2122 sc->sc_msr = msr; 2123 #ifdef __HAVE_TIMECOUNTER 2124 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2125 (delta & MSR_DCD)) { 2126 pps_capture(&sc->sc_pps_state); 2127 pps_event(&sc->sc_pps_state, 2128 (msr & MSR_DCD) ? 2129 PPS_CAPTUREASSERT : 2130 PPS_CAPTURECLEAR); 2131 } 2132 #else /* !__HAVE_TIMECOUNTER */ 2133 /* 2134 * Pulse-per-second (PSS) signals on edge of DCD? 2135 * Process these even if line discipline is ignoring DCD. 2136 */ 2137 if (delta & sc->sc_ppsmask) { 2138 struct timeval tv; 2139 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2140 /* XXX nanotime() */ 2141 microtime(&tv); 2142 TIMEVAL_TO_TIMESPEC(&tv, 2143 &sc->ppsinfo.assert_timestamp); 2144 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2145 timespecadd(&sc->ppsinfo.assert_timestamp, 2146 &sc->ppsparam.assert_offset, 2147 &sc->ppsinfo.assert_timestamp); 2148 } 2149 2150 #ifdef PPS_SYNC 2151 if (pps_kc_hardpps_source == sc && 2152 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2153 hardpps(&tv, tv.tv_usec); 2154 } 2155 #endif 2156 sc->ppsinfo.assert_sequence++; 2157 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2158 2159 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2160 /* XXX nanotime() */ 2161 microtime(&tv); 2162 TIMEVAL_TO_TIMESPEC(&tv, 2163 &sc->ppsinfo.clear_timestamp); 2164 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2165 timespecadd(&sc->ppsinfo.clear_timestamp, 2166 &sc->ppsparam.clear_offset, 2167 &sc->ppsinfo.clear_timestamp); 2168 } 2169 2170 #ifdef PPS_SYNC 2171 if (pps_kc_hardpps_source == sc && 2172 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2173 hardpps(&tv, tv.tv_usec); 2174 } 2175 #endif 2176 sc->ppsinfo.clear_sequence++; 2177 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2178 } 2179 } 2180 #endif /* !__HAVE_TIMECOUNTER */ 2181 2182 /* 2183 * Process normal status changes 2184 */ 2185 if (ISSET(delta, sc->sc_msr_mask)) { 2186 SET(sc->sc_msr_delta, delta); 2187 2188 /* 2189 * Stop output immediately if we lose the output 2190 * flow control signal or carrier detect. 2191 */ 2192 if (ISSET(~msr, sc->sc_msr_mask)) { 2193 sc->sc_tbc = 0; 2194 sc->sc_heldtbc = 0; 2195 #ifdef COM_DEBUG 2196 if (com_debug) 2197 comstatus(sc, "comintr "); 2198 #endif 2199 } 2200 2201 sc->sc_st_check = 1; 2202 } 2203 } while (!ISSET((iir = 2204 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2205 /* 2206 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2207 * by IIR read, so we can't do this way: `process all interrupts, 2208 * then do TX if possble'. 2209 */ 2210 (iir & IIR_IMASK) != IIR_TXRDY); 2211 2212 /* 2213 * Read LSR again, since there may be an interrupt between 2214 * the last LSR read and IIR read above. 2215 */ 2216 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2217 2218 /* 2219 * See if data can be transmitted as well. 2220 * Schedule tx done event if no data left 2221 * and tty was marked busy. 2222 */ 2223 if (ISSET(lsr, LSR_TXRDY)) { 2224 /* 2225 * If we've delayed a parameter change, do it now, and restart 2226 * output. 2227 */ 2228 if (sc->sc_heldchange) { 2229 com_loadchannelregs(sc); 2230 sc->sc_heldchange = 0; 2231 sc->sc_tbc = sc->sc_heldtbc; 2232 sc->sc_heldtbc = 0; 2233 } 2234 2235 /* Output the next chunk of the contiguous buffer, if any. */ 2236 if (sc->sc_tbc > 0) { 2237 u_int n; 2238 2239 n = sc->sc_tbc; 2240 if (n > sc->sc_fifolen) 2241 n = sc->sc_fifolen; 2242 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2243 sc->sc_tbc -= n; 2244 sc->sc_tba += n; 2245 } else { 2246 /* Disable transmit completion interrupts if necessary. */ 2247 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2248 CLR(sc->sc_ier, IER_ETXRDY); 2249 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2250 } 2251 if (sc->sc_tx_busy) { 2252 sc->sc_tx_busy = 0; 2253 sc->sc_tx_done = 1; 2254 } 2255 } 2256 } 2257 2258 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2259 goto again; 2260 2261 COM_UNLOCK(sc); 2262 2263 /* Wake up the poller. */ 2264 softint_schedule(sc->sc_si); 2265 2266 #if NRND > 0 && defined(RND_COM) 2267 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2268 #endif 2269 2270 return (1); 2271 } 2272 2273 /* 2274 * The following functions are polled getc and putc routines, shared 2275 * by the console and kgdb glue. 2276 * 2277 * The read-ahead code is so that you can detect pending in-band 2278 * cn_magic in polled mode while doing output rather than having to 2279 * wait until the kernel decides it needs input. 2280 */ 2281 2282 #define MAX_READAHEAD 20 2283 static int com_readahead[MAX_READAHEAD]; 2284 static int com_readaheadcount = 0; 2285 2286 int 2287 com_common_getc(dev_t dev, struct com_regs *regsp) 2288 { 2289 int s = splserial(); 2290 u_char stat, c; 2291 2292 /* got a character from reading things earlier */ 2293 if (com_readaheadcount > 0) { 2294 int i; 2295 2296 c = com_readahead[0]; 2297 for (i = 1; i < com_readaheadcount; i++) { 2298 com_readahead[i-1] = com_readahead[i]; 2299 } 2300 com_readaheadcount--; 2301 splx(s); 2302 return (c); 2303 } 2304 2305 /* block until a character becomes available */ 2306 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2307 ; 2308 2309 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2310 stat = CSR_READ_1(regsp, COM_REG_IIR); 2311 { 2312 int cn_trapped = 0; /* unused */ 2313 #ifdef DDB 2314 extern int db_active; 2315 if (!db_active) 2316 #endif 2317 cn_check_magic(dev, c, com_cnm_state); 2318 } 2319 splx(s); 2320 return (c); 2321 } 2322 2323 void 2324 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2325 { 2326 int s = splserial(); 2327 int cin, stat, timo; 2328 2329 if (com_readaheadcount < MAX_READAHEAD 2330 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2331 int cn_trapped = 0; 2332 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2333 stat = CSR_READ_1(regsp, COM_REG_IIR); 2334 cn_check_magic(dev, cin, com_cnm_state); 2335 com_readahead[com_readaheadcount++] = cin; 2336 } 2337 2338 /* wait for any pending transmission to finish */ 2339 timo = 150000; 2340 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2341 continue; 2342 2343 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2344 COM_BARRIER(regsp, BR | BW); 2345 2346 splx(s); 2347 } 2348 2349 /* 2350 * Initialize UART for use as console or KGDB line. 2351 */ 2352 int 2353 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2354 tcflag_t cflag) 2355 { 2356 2357 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2358 ®sp->cr_ioh)) 2359 return (ENOMEM); /* ??? */ 2360 2361 rate = comspeed(rate, frequency, type); 2362 if (type != COM_TYPE_AU1x00) { 2363 /* no EFR on alchemy */ 2364 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2365 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2366 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2367 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2368 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2369 } else { 2370 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2371 } 2372 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2373 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2374 CSR_WRITE_1(regsp, COM_REG_FIFO, 2375 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2376 #ifdef COM_PXA2X0 2377 if (type == COM_TYPE_PXA2x0) 2378 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2379 else 2380 #endif 2381 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2382 2383 return (0); 2384 } 2385 2386 /* 2387 * Following are all routines needed for COM to act as console 2388 */ 2389 struct consdev comcons = { 2390 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2391 NODEV, CN_NORMAL 2392 }; 2393 2394 2395 int 2396 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2397 tcflag_t cflag) 2398 { 2399 int res; 2400 2401 comconsregs = *regsp; 2402 2403 res = cominit(&comconsregs, rate, frequency, type, cflag); 2404 if (res) 2405 return (res); 2406 2407 cn_tab = &comcons; 2408 cn_init_magic(&com_cnm_state); 2409 cn_set_magic("\047\001"); /* default magic is BREAK */ 2410 2411 comconsrate = rate; 2412 comconscflag = cflag; 2413 2414 return (0); 2415 } 2416 2417 int 2418 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2419 int type, tcflag_t cflag) 2420 { 2421 struct com_regs regs; 2422 2423 memset(®s, 0, sizeof regs); 2424 regs.cr_iot = iot; 2425 regs.cr_iobase = iobase; 2426 regs.cr_nports = COM_NPORTS; 2427 #ifdef COM_REGMAP 2428 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2429 #endif 2430 2431 return comcnattach1(®s, rate, frequency, type, cflag); 2432 } 2433 2434 int 2435 comcngetc(dev_t dev) 2436 { 2437 2438 return (com_common_getc(dev, &comconsregs)); 2439 } 2440 2441 /* 2442 * Console kernel output character routine. 2443 */ 2444 void 2445 comcnputc(dev_t dev, int c) 2446 { 2447 2448 com_common_putc(dev, &comconsregs, c); 2449 } 2450 2451 void 2452 comcnpollc(dev_t dev, int on) 2453 { 2454 2455 } 2456 2457 #ifdef KGDB 2458 int 2459 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2460 tcflag_t cflag) 2461 { 2462 int res; 2463 2464 if (regsp->cr_iot == comconsregs.cr_iot && 2465 regsp->cr_iobase == comconsregs.cr_iobase) { 2466 #if !defined(DDB) 2467 return (EBUSY); /* cannot share with console */ 2468 #else 2469 comkgdbregs = *regsp; 2470 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2471 #endif 2472 } else { 2473 comkgdbregs = *regsp; 2474 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2475 if (res) 2476 return (res); 2477 2478 /* 2479 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2480 * expects this to be initialized 2481 */ 2482 cn_init_magic(&com_cnm_state); 2483 cn_set_magic("\047\001"); 2484 } 2485 2486 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2487 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2488 2489 return (0); 2490 } 2491 2492 int 2493 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2494 int frequency, int type, tcflag_t cflag) 2495 { 2496 struct com_regs regs; 2497 2498 regs.cr_iot = iot; 2499 regs.cr_nports = COM_NPORTS; 2500 regs.cr_iobase = iobase; 2501 #ifdef COM_REGMAP 2502 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2503 #endif 2504 2505 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2506 } 2507 2508 /* ARGSUSED */ 2509 int 2510 com_kgdb_getc(void *arg) 2511 { 2512 2513 return (com_common_getc(NODEV, &comkgdbregs)); 2514 } 2515 2516 /* ARGSUSED */ 2517 void 2518 com_kgdb_putc(void *arg, int c) 2519 { 2520 2521 com_common_putc(NODEV, &comkgdbregs, c); 2522 } 2523 #endif /* KGDB */ 2524 2525 /* helper function to identify the com ports used by 2526 console or KGDB (and not yet autoconf attached) */ 2527 int 2528 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2529 { 2530 bus_space_handle_t help; 2531 2532 if (!comconsattached && 2533 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2534 help = comconsregs.cr_ioh; 2535 #ifdef KGDB 2536 else if (!com_kgdb_attached && 2537 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2538 help = comkgdbregs.cr_ioh; 2539 #endif 2540 else 2541 return (0); 2542 2543 if (ioh) 2544 *ioh = help; 2545 return (1); 2546 } 2547 2548 /* 2549 * this routine exists to serve as a shutdown hook for systems that 2550 * have firmware which doesn't interact properly with a com device in 2551 * FIFO mode. 2552 */ 2553 void 2554 com_cleanup(void *arg) 2555 { 2556 struct com_softc *sc = arg; 2557 2558 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2559 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2560 } 2561 2562 void 2563 com_power(int why, void *arg) 2564 { 2565 struct com_softc *sc = arg; 2566 int s; 2567 2568 s = splserial(); 2569 switch (why) { 2570 case PWR_SUSPEND: 2571 case PWR_STANDBY: 2572 /* XXX should we do something to stop the device? */ 2573 break; 2574 case PWR_RESUME: 2575 com_loadchannelregs(sc); 2576 break; 2577 case PWR_SOFTSUSPEND: 2578 case PWR_SOFTSTANDBY: 2579 case PWR_SOFTRESUME: 2580 break; 2581 } 2582 splx(s); 2583 } 2584
Indexes created Mon Oct 20 11:09:49 GMT 2025