com.c revision 1.261
1 /* $NetBSD: com.c,v 1.261 2007/07/14 21:02:37 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.261 2007/07/14 21:02:37 ad Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 195 integrate void com_rxsoft(struct com_softc *, struct tty *); 196 integrate void com_txsoft(struct com_softc *, struct tty *); 197 integrate void com_stsoft(struct com_softc *, struct tty *); 198 integrate void com_schedrx(struct com_softc *); 199 void comdiag(void *); 200 201 extern struct cfdriver com_cd; 202 203 dev_type_open(comopen); 204 dev_type_close(comclose); 205 dev_type_read(comread); 206 dev_type_write(comwrite); 207 dev_type_ioctl(comioctl); 208 dev_type_stop(comstop); 209 dev_type_tty(comtty); 210 dev_type_poll(compoll); 211 212 const struct cdevsw com_cdevsw = { 213 comopen, comclose, comread, comwrite, comioctl, 214 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 215 }; 216 217 /* 218 * Make this an option variable one can patch. 219 * But be warned: this must be a power of 2! 220 */ 221 u_int com_rbuf_size = COM_RING_SIZE; 222 223 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 224 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 225 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 226 227 static struct com_regs comconsregs; 228 static int comconsattached; 229 static int comconsrate; 230 static tcflag_t comconscflag; 231 static struct cnm_state com_cnm_state; 232 233 #ifndef __HAVE_TIMECOUNTER 234 static int ppscap = 235 PPS_TSFMT_TSPEC | 236 PPS_CAPTUREASSERT | 237 PPS_CAPTURECLEAR | 238 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 239 #endif /* !__HAVE_TIMECOUNTER */ 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_16550 { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 256 257 const bus_size_t com_std_map[16] = COM_REG_16550; 258 #endif /* COM_REGMAP */ 259 260 #define COMUNIT_MASK 0x7ffff 261 #define COMDIALOUT_MASK 0x80000 262 263 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 264 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active(&(sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 275 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 276 277 /*ARGSUSED*/ 278 int 279 comspeed(long speed, long frequency, int type) 280 { 281 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 282 283 int x, err; 284 285 #if 0 286 if (speed == 0) 287 return (0); 288 #endif 289 if (speed <= 0) 290 return (-1); 291 x = divrnd(frequency / 16, speed); 292 if (x <= 0) 293 return (-1); 294 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 295 if (err < 0) 296 err = -err; 297 if (err > COM_TOLERANCE) 298 return (-1); 299 return (x); 300 301 #undef divrnd 302 } 303 304 #ifdef COM_DEBUG 305 int com_debug = 0; 306 307 void comstatus(struct com_softc *, const char *); 308 void 309 comstatus(struct com_softc *sc, const char *str) 310 { 311 struct tty *tp = sc->sc_tty; 312 313 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 314 sc->sc_dev.dv_xname, str, 315 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 316 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 317 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 318 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 319 sc->sc_tx_stopped ? '+' : '-'); 320 321 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 322 sc->sc_dev.dv_xname, str, 323 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 324 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 325 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 326 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 327 sc->sc_rx_flags); 328 } 329 #endif 330 331 int 332 com_probe_subr(struct com_regs *regs) 333 { 334 335 /* force access to id reg */ 336 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 337 CSR_WRITE_1(regs, COM_REG_IIR, 0); 338 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 339 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 340 return (0); 341 342 return (1); 343 } 344 345 int 346 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 347 { 348 struct com_regs regs; 349 350 regs.cr_iot = iot; 351 regs.cr_ioh = ioh; 352 #ifdef COM_REGMAP 353 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 354 #endif 355 356 return com_probe_subr(®s); 357 } 358 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 int s; 363 364 /* Turn on line break interrupt, set carrier. */ 365 s = splserial(); 366 COM_LOCK(sc); 367 sc->sc_ier = IER_ERXRDY; 368 if (sc->sc_type == COM_TYPE_PXA2x0) 369 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 370 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 371 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 372 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 373 COM_UNLOCK(sc); 374 splx(s); 375 } 376 377 void 378 com_attach_subr(struct com_softc *sc) 379 { 380 struct com_regs *regsp = &sc->sc_regs; 381 struct tty *tp; 382 #ifdef COM_16650 383 u_int8_t lcr; 384 #endif 385 const char *fifo_msg = NULL; 386 387 aprint_naive("\n"); 388 389 callout_init(&sc->sc_diag_callout, 0); 390 simple_lock_init(&sc->sc_lock); 391 392 /* Disable interrupts before configuring the device. */ 393 if (sc->sc_type == COM_TYPE_PXA2x0) 394 sc->sc_ier = IER_EUART; 395 else 396 sc->sc_ier = 0; 397 398 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 399 400 if (regsp->cr_iot == comconsregs.cr_iot && 401 regsp->cr_iobase == comconsregs.cr_iobase) { 402 comconsattached = 1; 403 404 /* Make sure the console is always "hardwired". */ 405 delay(10000); /* wait for output to finish */ 406 SET(sc->sc_hwflags, COM_HW_CONSOLE); 407 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 408 } 409 410 /* Probe for FIFO */ 411 switch (sc->sc_type) { 412 case COM_TYPE_HAYESP: 413 goto fifodone; 414 415 case COM_TYPE_AU1x00: 416 sc->sc_fifolen = 16; 417 fifo_msg = "Au1X00 UART, working fifo"; 418 SET(sc->sc_hwflags, COM_HW_FIFO); 419 goto fifodelay; 420 } 421 422 sc->sc_fifolen = 1; 423 /* look for a NS 16550AF UART with FIFOs */ 424 CSR_WRITE_1(regsp, COM_REG_FIFO, 425 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 426 delay(100); 427 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 428 == IIR_FIFO_MASK) 429 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 430 == FIFO_TRIGGER_14) { 431 SET(sc->sc_hwflags, COM_HW_FIFO); 432 433 #ifdef COM_16650 434 /* 435 * IIR changes into the EFR if LCR is set to LCR_EERS 436 * on 16650s. We also know IIR != 0 at this point. 437 * Write 0 into the EFR, and read it. If the result 438 * is 0, we have a 16650. 439 * 440 * Older 16650s were broken; the test to detect them 441 * is taken from the Linux driver. Apparently 442 * setting DLAB enable gives access to the EFR on 443 * these chips. 444 */ 445 lcr = CSR_READ_1(regsp, COM_REG_LCR); 446 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 447 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 448 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 449 CSR_WRITE_1(regsp, COM_REG_LCR, 450 lcr | LCR_DLAB); 451 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 452 CLR(sc->sc_hwflags, COM_HW_FIFO); 453 sc->sc_fifolen = 0; 454 } else { 455 SET(sc->sc_hwflags, COM_HW_FLOW); 456 sc->sc_fifolen = 32; 457 } 458 } else 459 #endif 460 sc->sc_fifolen = 16; 461 462 #ifdef COM_16650 463 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 464 if (sc->sc_fifolen == 0) 465 fifo_msg = "st16650, broken fifo"; 466 else if (sc->sc_fifolen == 32) 467 fifo_msg = "st16650a, working fifo"; 468 else 469 #endif 470 fifo_msg = "ns16550a, working fifo"; 471 } else 472 fifo_msg = "ns16550, broken fifo"; 473 else 474 fifo_msg = "ns8250 or ns16450, no fifo"; 475 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 476 fifodelay: 477 /* 478 * Some chips will clear down both Tx and Rx FIFOs when zero is 479 * written to com_fifo. If this chip is the console, writing zero 480 * results in some of the chip/FIFO description being lost, so delay 481 * printing it until now. 482 */ 483 delay(10); 484 aprint_normal(": %s\n", fifo_msg); 485 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 486 sc->sc_fifolen = 1; 487 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 488 } 489 490 fifodone: 491 492 tp = ttymalloc(); 493 tp->t_oproc = comstart; 494 tp->t_param = comparam; 495 tp->t_hwiflow = comhwiflow; 496 497 sc->sc_tty = tp; 498 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 499 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 500 sc->sc_rbavail = com_rbuf_size; 501 if (sc->sc_rbuf == NULL) { 502 aprint_error("%s: unable to allocate ring buffer\n", 503 sc->sc_dev.dv_xname); 504 return; 505 } 506 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 507 508 tty_attach(tp); 509 510 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 511 SET(sc->sc_mcr, MCR_IENABLE); 512 513 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 514 int maj; 515 516 /* locate the major number */ 517 maj = cdevsw_lookup_major(&com_cdevsw); 518 519 tp->t_dev = cn_tab->cn_dev = makedev(maj, 520 device_unit(&sc->sc_dev)); 521 522 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 523 } 524 525 #ifdef KGDB 526 /* 527 * Allow kgdb to "take over" this port. If this is 528 * not the console and is the kgdb device, it has 529 * exclusive use. If it's the console _and_ the 530 * kgdb device, it doesn't. 531 */ 532 if (regsp->cr_iot == comkgdbregs.cr_iot && 533 regsp->cr_iobase == comkgdbregs.cr_iobase) { 534 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 535 com_kgdb_attached = 1; 536 537 SET(sc->sc_hwflags, COM_HW_KGDB); 538 } 539 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 540 } 541 #endif 542 543 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 544 545 #if NRND > 0 && defined(RND_COM) 546 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 547 RND_TYPE_TTY, 0); 548 #endif 549 550 /* if there are no enable/disable functions, assume the device 551 is always enabled */ 552 if (!sc->enable) 553 sc->enabled = 1; 554 555 com_config(sc); 556 557 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 558 com_power, sc); 559 if (sc->sc_powerhook == NULL) 560 aprint_error("%s: WARNING: unable to establish power hook\n", 561 sc->sc_dev.dv_xname); 562 563 SET(sc->sc_hwflags, COM_HW_DEV_OK); 564 } 565 566 void 567 com_config(struct com_softc *sc) 568 { 569 struct com_regs *regsp = &sc->sc_regs; 570 571 /* Disable interrupts before configuring the device. */ 572 if (sc->sc_type == COM_TYPE_PXA2x0) 573 sc->sc_ier = IER_EUART; 574 else 575 sc->sc_ier = 0; 576 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 577 (void) CSR_READ_1(regsp, COM_REG_IIR); 578 579 #ifdef COM_HAYESP 580 /* Look for a Hayes ESP board. */ 581 if (sc->sc_type == COM_TYPE_HAYESP) { 582 583 /* Set 16550 compatibility mode */ 584 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 585 HAYESP_SETMODE); 586 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 587 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 588 HAYESP_MODE_SCALE); 589 590 /* Set RTS/CTS flow control */ 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 592 HAYESP_SETFLOWTYPE); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_FLOW_RTS); 595 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 596 HAYESP_FLOW_CTS); 597 598 /* Set flow control levels */ 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 600 HAYESP_SETRXFLOW); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 603 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 604 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 605 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 606 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 608 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 609 } 610 #endif 611 612 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 613 com_enable_debugport(sc); 614 } 615 616 int 617 com_detach(struct device *self, int flags) 618 { 619 struct com_softc *sc = (struct com_softc *)self; 620 int maj, mn; 621 622 /* kill the power hook */ 623 if (sc->sc_powerhook != NULL) 624 powerhook_disestablish(sc->sc_powerhook); 625 626 /* locate the major number */ 627 maj = cdevsw_lookup_major(&com_cdevsw); 628 629 /* Nuke the vnodes for any open instances. */ 630 mn = device_unit(self); 631 vdevgone(maj, mn, mn, VCHR); 632 633 mn |= COMDIALOUT_MASK; 634 vdevgone(maj, mn, mn, VCHR); 635 636 if (sc->sc_rbuf == NULL) { 637 /* 638 * Ring buffer allocation failed in the com_attach_subr, 639 * only the tty is allocated, and nothing else. 640 */ 641 ttyfree(sc->sc_tty); 642 return 0; 643 } 644 645 /* Free the receive buffer. */ 646 free(sc->sc_rbuf, M_DEVBUF); 647 648 /* Detach and free the tty. */ 649 tty_detach(sc->sc_tty); 650 ttyfree(sc->sc_tty); 651 652 /* Unhook the soft interrupt handler. */ 653 softintr_disestablish(sc->sc_si); 654 655 #if NRND > 0 && defined(RND_COM) 656 /* Unhook the entropy source. */ 657 rnd_detach_source(&sc->rnd_source); 658 #endif 659 660 return (0); 661 } 662 663 int 664 com_activate(struct device *self, enum devact act) 665 { 666 struct com_softc *sc = (struct com_softc *)self; 667 int s, rv = 0; 668 669 s = splserial(); 670 COM_LOCK(sc); 671 switch (act) { 672 case DVACT_ACTIVATE: 673 rv = EOPNOTSUPP; 674 break; 675 676 case DVACT_DEACTIVATE: 677 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 678 rv = EBUSY; 679 break; 680 } 681 682 if (sc->disable != NULL && sc->enabled != 0) { 683 (*sc->disable)(sc); 684 sc->enabled = 0; 685 } 686 break; 687 } 688 689 COM_UNLOCK(sc); 690 splx(s); 691 return (rv); 692 } 693 694 void 695 com_shutdown(struct com_softc *sc) 696 { 697 struct tty *tp = sc->sc_tty; 698 int s; 699 700 s = splserial(); 701 COM_LOCK(sc); 702 703 /* If we were asserting flow control, then deassert it. */ 704 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 705 com_hwiflow(sc); 706 707 /* Clear any break condition set with TIOCSBRK. */ 708 com_break(sc, 0); 709 710 #ifndef __HAVE_TIMECOUNTER 711 /* Turn off PPS capture on last close. */ 712 sc->sc_ppsmask = 0; 713 sc->ppsparam.mode = 0; 714 #endif /* !__HAVE_TIMECOUNTER */ 715 716 /* 717 * Hang up if necessary. Wait a bit, so the other side has time to 718 * notice even if we immediately open the port again. 719 * Avoid tsleeping above splhigh(). 720 */ 721 if (ISSET(tp->t_cflag, HUPCL)) { 722 com_modem(sc, 0); 723 COM_UNLOCK(sc); 724 splx(s); 725 /* XXX tsleep will only timeout */ 726 (void) tsleep(sc, TTIPRI, ttclos, hz); 727 s = splserial(); 728 COM_LOCK(sc); 729 } 730 731 /* Turn off interrupts. */ 732 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 733 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 734 if (sc->sc_type == COM_TYPE_PXA2x0) 735 sc->sc_ier |= IER_ERXTOUT; 736 } else 737 sc->sc_ier = 0; 738 739 if (sc->sc_type == COM_TYPE_PXA2x0) 740 sc->sc_ier |= IER_EUART; 741 742 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 743 744 if (sc->disable) { 745 #ifdef DIAGNOSTIC 746 if (!sc->enabled) 747 panic("com_shutdown: not enabled?"); 748 #endif 749 (*sc->disable)(sc); 750 sc->enabled = 0; 751 } 752 COM_UNLOCK(sc); 753 splx(s); 754 } 755 756 int 757 comopen(dev_t dev, int flag, int mode, struct lwp *l) 758 { 759 struct com_softc *sc; 760 struct tty *tp; 761 int s, s2; 762 int error; 763 764 sc = device_lookup(&com_cd, COMUNIT(dev)); 765 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 766 sc->sc_rbuf == NULL) 767 return (ENXIO); 768 769 if (!device_is_active(&sc->sc_dev)) 770 return (ENXIO); 771 772 #ifdef KGDB 773 /* 774 * If this is the kgdb port, no other use is permitted. 775 */ 776 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 777 return (EBUSY); 778 #endif 779 780 tp = sc->sc_tty; 781 782 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 783 return (EBUSY); 784 785 s = spltty(); 786 787 /* 788 * Do the following iff this is a first open. 789 */ 790 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 791 struct termios t; 792 793 tp->t_dev = dev; 794 795 s2 = splserial(); 796 COM_LOCK(sc); 797 798 if (sc->enable) { 799 if ((*sc->enable)(sc)) { 800 COM_UNLOCK(sc); 801 splx(s2); 802 splx(s); 803 printf("%s: device enable failed\n", 804 sc->sc_dev.dv_xname); 805 return (EIO); 806 } 807 sc->enabled = 1; 808 com_config(sc); 809 } 810 811 /* Turn on interrupts. */ 812 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 813 if (sc->sc_type == COM_TYPE_PXA2x0) 814 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 815 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 816 817 /* Fetch the current modem control status, needed later. */ 818 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 819 820 /* Clear PPS capture state on first open. */ 821 #ifdef __HAVE_TIMECOUNTER 822 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 823 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 824 pps_init(&sc->sc_pps_state); 825 #else /* !__HAVE_TIMECOUNTER */ 826 sc->sc_ppsmask = 0; 827 sc->ppsparam.mode = 0; 828 #endif /* !__HAVE_TIMECOUNTER */ 829 830 COM_UNLOCK(sc); 831 splx(s2); 832 833 /* 834 * Initialize the termios status to the defaults. Add in the 835 * sticky bits from TIOCSFLAGS. 836 */ 837 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 838 t.c_ospeed = comconsrate; 839 t.c_cflag = comconscflag; 840 } else { 841 t.c_ospeed = TTYDEF_SPEED; 842 t.c_cflag = TTYDEF_CFLAG; 843 } 844 t.c_ispeed = t.c_ospeed; 845 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 846 SET(t.c_cflag, CLOCAL); 847 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 848 SET(t.c_cflag, CRTSCTS); 849 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 850 SET(t.c_cflag, MDMBUF); 851 /* Make sure comparam() will do something. */ 852 tp->t_ospeed = 0; 853 (void) comparam(tp, &t); 854 tp->t_iflag = TTYDEF_IFLAG; 855 tp->t_oflag = TTYDEF_OFLAG; 856 tp->t_lflag = TTYDEF_LFLAG; 857 ttychars(tp); 858 ttsetwater(tp); 859 860 s2 = splserial(); 861 COM_LOCK(sc); 862 863 /* 864 * Turn on DTR. We must always do this, even if carrier is not 865 * present, because otherwise we'd have to use TIOCSDTR 866 * immediately after setting CLOCAL, which applications do not 867 * expect. We always assert DTR while the device is open 868 * unless explicitly requested to deassert it. 869 */ 870 com_modem(sc, 1); 871 872 /* Clear the input ring, and unblock. */ 873 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 874 sc->sc_rbavail = com_rbuf_size; 875 com_iflush(sc); 876 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 877 com_hwiflow(sc); 878 879 #ifdef COM_DEBUG 880 if (com_debug) 881 comstatus(sc, "comopen "); 882 #endif 883 884 COM_UNLOCK(sc); 885 splx(s2); 886 } 887 888 splx(s); 889 890 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 891 if (error) 892 goto bad; 893 894 error = (*tp->t_linesw->l_open)(dev, tp); 895 if (error) 896 goto bad; 897 898 return (0); 899 900 bad: 901 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 902 /* 903 * We failed to open the device, and nobody else had it opened. 904 * Clean up the state as appropriate. 905 */ 906 com_shutdown(sc); 907 } 908 909 return (error); 910 } 911 912 int 913 comclose(dev_t dev, int flag, int mode, struct lwp *l) 914 { 915 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 916 struct tty *tp = sc->sc_tty; 917 918 /* XXX This is for cons.c. */ 919 if (!ISSET(tp->t_state, TS_ISOPEN)) 920 return (0); 921 922 (*tp->t_linesw->l_close)(tp, flag); 923 ttyclose(tp); 924 925 if (COM_ISALIVE(sc) == 0) 926 return (0); 927 928 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 929 /* 930 * Although we got a last close, the device may still be in 931 * use; e.g. if this was the dialout node, and there are still 932 * processes waiting for carrier on the non-dialout node. 933 */ 934 com_shutdown(sc); 935 } 936 937 return (0); 938 } 939 940 int 941 comread(dev_t dev, struct uio *uio, int flag) 942 { 943 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 944 struct tty *tp = sc->sc_tty; 945 946 if (COM_ISALIVE(sc) == 0) 947 return (EIO); 948 949 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 950 } 951 952 int 953 comwrite(dev_t dev, struct uio *uio, int flag) 954 { 955 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 956 struct tty *tp = sc->sc_tty; 957 958 if (COM_ISALIVE(sc) == 0) 959 return (EIO); 960 961 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 962 } 963 964 int 965 compoll(dev_t dev, int events, struct lwp *l) 966 { 967 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 968 struct tty *tp = sc->sc_tty; 969 970 if (COM_ISALIVE(sc) == 0) 971 return (POLLHUP); 972 973 return ((*tp->t_linesw->l_poll)(tp, events, l)); 974 } 975 976 struct tty * 977 comtty(dev_t dev) 978 { 979 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 980 struct tty *tp = sc->sc_tty; 981 982 return (tp); 983 } 984 985 int 986 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 987 { 988 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 989 struct tty *tp = sc->sc_tty; 990 int error; 991 int s; 992 993 if (COM_ISALIVE(sc) == 0) 994 return (EIO); 995 996 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 997 if (error != EPASSTHROUGH) 998 return (error); 999 1000 error = ttioctl(tp, cmd, data, flag, l); 1001 if (error != EPASSTHROUGH) 1002 return (error); 1003 1004 error = 0; 1005 switch (cmd) { 1006 case TIOCSFLAGS: 1007 error = kauth_authorize_device_tty(l->l_cred, 1008 KAUTH_DEVICE_TTY_PRIVSET, tp); 1009 break; 1010 default: 1011 /* nothing */ 1012 break; 1013 } 1014 if (error) { 1015 return error; 1016 } 1017 1018 s = splserial(); 1019 COM_LOCK(sc); 1020 1021 switch (cmd) { 1022 case TIOCSBRK: 1023 com_break(sc, 1); 1024 break; 1025 1026 case TIOCCBRK: 1027 com_break(sc, 0); 1028 break; 1029 1030 case TIOCSDTR: 1031 com_modem(sc, 1); 1032 break; 1033 1034 case TIOCCDTR: 1035 com_modem(sc, 0); 1036 break; 1037 1038 case TIOCGFLAGS: 1039 *(int *)data = sc->sc_swflags; 1040 break; 1041 1042 case TIOCSFLAGS: 1043 sc->sc_swflags = *(int *)data; 1044 break; 1045 1046 case TIOCMSET: 1047 case TIOCMBIS: 1048 case TIOCMBIC: 1049 tiocm_to_com(sc, cmd, *(int *)data); 1050 break; 1051 1052 case TIOCMGET: 1053 *(int *)data = com_to_tiocm(sc); 1054 break; 1055 1056 #ifdef __HAVE_TIMECOUNTER 1057 case PPS_IOC_CREATE: 1058 case PPS_IOC_DESTROY: 1059 case PPS_IOC_GETPARAMS: 1060 case PPS_IOC_SETPARAMS: 1061 case PPS_IOC_GETCAP: 1062 case PPS_IOC_FETCH: 1063 #ifdef PPS_SYNC 1064 case PPS_IOC_KCBIND: 1065 #endif 1066 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1067 break; 1068 #else /* !__HAVE_TIMECOUNTER */ 1069 case PPS_IOC_CREATE: 1070 break; 1071 1072 case PPS_IOC_DESTROY: 1073 break; 1074 1075 case PPS_IOC_GETPARAMS: { 1076 pps_params_t *pp; 1077 pp = (pps_params_t *)data; 1078 *pp = sc->ppsparam; 1079 break; 1080 } 1081 1082 case PPS_IOC_SETPARAMS: { 1083 pps_params_t *pp; 1084 int mode; 1085 pp = (pps_params_t *)data; 1086 if (pp->mode & ~ppscap) { 1087 error = EINVAL; 1088 break; 1089 } 1090 sc->ppsparam = *pp; 1091 /* 1092 * Compute msr masks from user-specified timestamp state. 1093 */ 1094 mode = sc->ppsparam.mode; 1095 switch (mode & PPS_CAPTUREBOTH) { 1096 case 0: 1097 sc->sc_ppsmask = 0; 1098 break; 1099 1100 case PPS_CAPTUREASSERT: 1101 sc->sc_ppsmask = MSR_DCD; 1102 sc->sc_ppsassert = MSR_DCD; 1103 sc->sc_ppsclear = -1; 1104 break; 1105 1106 case PPS_CAPTURECLEAR: 1107 sc->sc_ppsmask = MSR_DCD; 1108 sc->sc_ppsassert = -1; 1109 sc->sc_ppsclear = 0; 1110 break; 1111 1112 case PPS_CAPTUREBOTH: 1113 sc->sc_ppsmask = MSR_DCD; 1114 sc->sc_ppsassert = MSR_DCD; 1115 sc->sc_ppsclear = 0; 1116 break; 1117 1118 default: 1119 error = EINVAL; 1120 break; 1121 } 1122 break; 1123 } 1124 1125 case PPS_IOC_GETCAP: 1126 *(int*)data = ppscap; 1127 break; 1128 1129 case PPS_IOC_FETCH: { 1130 pps_info_t *pi; 1131 pi = (pps_info_t *)data; 1132 *pi = sc->ppsinfo; 1133 break; 1134 } 1135 1136 #ifdef PPS_SYNC 1137 case PPS_IOC_KCBIND: { 1138 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1139 1140 if (edge == 0) { 1141 /* 1142 * remove binding for this source; ignore 1143 * the request if this is not the current 1144 * hardpps source 1145 */ 1146 if (pps_kc_hardpps_source == sc) { 1147 pps_kc_hardpps_source = NULL; 1148 pps_kc_hardpps_mode = 0; 1149 } 1150 } else { 1151 /* 1152 * bind hardpps to this source, replacing any 1153 * previously specified source or edges 1154 */ 1155 pps_kc_hardpps_source = sc; 1156 pps_kc_hardpps_mode = edge; 1157 } 1158 break; 1159 } 1160 #endif /* PPS_SYNC */ 1161 #endif /* !__HAVE_TIMECOUNTER */ 1162 1163 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1164 #ifdef __HAVE_TIMECOUNTER 1165 #ifndef PPS_TRAILING_EDGE 1166 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1167 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1168 #else 1169 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1170 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1171 #endif 1172 #else /* !__HAVE_TIMECOUNTER */ 1173 /* 1174 * Some GPS clocks models use the falling rather than 1175 * rising edge as the on-the-second signal. 1176 * The old API has no way to specify PPS polarity. 1177 */ 1178 sc->sc_ppsmask = MSR_DCD; 1179 #ifndef PPS_TRAILING_EDGE 1180 sc->sc_ppsassert = MSR_DCD; 1181 sc->sc_ppsclear = -1; 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->ppsinfo.assert_timestamp); 1184 #else 1185 sc->sc_ppsassert = -1; 1186 sc->sc_ppsclear = 0; 1187 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1188 &sc->ppsinfo.clear_timestamp); 1189 #endif 1190 #endif /* !__HAVE_TIMECOUNTER */ 1191 break; 1192 1193 default: 1194 error = EPASSTHROUGH; 1195 break; 1196 } 1197 1198 COM_UNLOCK(sc); 1199 splx(s); 1200 1201 #ifdef COM_DEBUG 1202 if (com_debug) 1203 comstatus(sc, "comioctl "); 1204 #endif 1205 1206 return (error); 1207 } 1208 1209 integrate void 1210 com_schedrx(struct com_softc *sc) 1211 { 1212 1213 sc->sc_rx_ready = 1; 1214 1215 /* Wake up the poller. */ 1216 softintr_schedule(sc->sc_si); 1217 } 1218 1219 void 1220 com_break(struct com_softc *sc, int onoff) 1221 { 1222 1223 if (onoff) 1224 SET(sc->sc_lcr, LCR_SBREAK); 1225 else 1226 CLR(sc->sc_lcr, LCR_SBREAK); 1227 1228 if (!sc->sc_heldchange) { 1229 if (sc->sc_tx_busy) { 1230 sc->sc_heldtbc = sc->sc_tbc; 1231 sc->sc_tbc = 0; 1232 sc->sc_heldchange = 1; 1233 } else 1234 com_loadchannelregs(sc); 1235 } 1236 } 1237 1238 void 1239 com_modem(struct com_softc *sc, int onoff) 1240 { 1241 1242 if (sc->sc_mcr_dtr == 0) 1243 return; 1244 1245 if (onoff) 1246 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1247 else 1248 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1249 1250 if (!sc->sc_heldchange) { 1251 if (sc->sc_tx_busy) { 1252 sc->sc_heldtbc = sc->sc_tbc; 1253 sc->sc_tbc = 0; 1254 sc->sc_heldchange = 1; 1255 } else 1256 com_loadchannelregs(sc); 1257 } 1258 } 1259 1260 void 1261 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1262 { 1263 u_char combits; 1264 1265 combits = 0; 1266 if (ISSET(ttybits, TIOCM_DTR)) 1267 SET(combits, MCR_DTR); 1268 if (ISSET(ttybits, TIOCM_RTS)) 1269 SET(combits, MCR_RTS); 1270 1271 switch (how) { 1272 case TIOCMBIC: 1273 CLR(sc->sc_mcr, combits); 1274 break; 1275 1276 case TIOCMBIS: 1277 SET(sc->sc_mcr, combits); 1278 break; 1279 1280 case TIOCMSET: 1281 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1282 SET(sc->sc_mcr, combits); 1283 break; 1284 } 1285 1286 if (!sc->sc_heldchange) { 1287 if (sc->sc_tx_busy) { 1288 sc->sc_heldtbc = sc->sc_tbc; 1289 sc->sc_tbc = 0; 1290 sc->sc_heldchange = 1; 1291 } else 1292 com_loadchannelregs(sc); 1293 } 1294 } 1295 1296 int 1297 com_to_tiocm(struct com_softc *sc) 1298 { 1299 u_char combits; 1300 int ttybits = 0; 1301 1302 combits = sc->sc_mcr; 1303 if (ISSET(combits, MCR_DTR)) 1304 SET(ttybits, TIOCM_DTR); 1305 if (ISSET(combits, MCR_RTS)) 1306 SET(ttybits, TIOCM_RTS); 1307 1308 combits = sc->sc_msr; 1309 if (ISSET(combits, MSR_DCD)) 1310 SET(ttybits, TIOCM_CD); 1311 if (ISSET(combits, MSR_CTS)) 1312 SET(ttybits, TIOCM_CTS); 1313 if (ISSET(combits, MSR_DSR)) 1314 SET(ttybits, TIOCM_DSR); 1315 if (ISSET(combits, MSR_RI | MSR_TERI)) 1316 SET(ttybits, TIOCM_RI); 1317 1318 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1319 SET(ttybits, TIOCM_LE); 1320 1321 return (ttybits); 1322 } 1323 1324 static u_char 1325 cflag2lcr(tcflag_t cflag) 1326 { 1327 u_char lcr = 0; 1328 1329 switch (ISSET(cflag, CSIZE)) { 1330 case CS5: 1331 SET(lcr, LCR_5BITS); 1332 break; 1333 case CS6: 1334 SET(lcr, LCR_6BITS); 1335 break; 1336 case CS7: 1337 SET(lcr, LCR_7BITS); 1338 break; 1339 case CS8: 1340 SET(lcr, LCR_8BITS); 1341 break; 1342 } 1343 if (ISSET(cflag, PARENB)) { 1344 SET(lcr, LCR_PENAB); 1345 if (!ISSET(cflag, PARODD)) 1346 SET(lcr, LCR_PEVEN); 1347 } 1348 if (ISSET(cflag, CSTOPB)) 1349 SET(lcr, LCR_STOPB); 1350 1351 return (lcr); 1352 } 1353 1354 int 1355 comparam(struct tty *tp, struct termios *t) 1356 { 1357 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1358 int ospeed; 1359 u_char lcr; 1360 int s; 1361 1362 if (COM_ISALIVE(sc) == 0) 1363 return (EIO); 1364 1365 #ifdef COM_HAYESP 1366 if (sc->sc_type == COM_TYPE_HAYESP) { 1367 int prescaler, speed; 1368 1369 /* 1370 * Calculate UART clock prescaler. It should be in 1371 * range of 0 .. 3. 1372 */ 1373 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1374 prescaler++, speed /= 2) 1375 if ((ospeed = comspeed(speed, sc->sc_frequency, 1376 sc->sc_type)) > 0) 1377 break; 1378 1379 if (prescaler == 4) 1380 return (EINVAL); 1381 sc->sc_prescaler = prescaler; 1382 } else 1383 #endif 1384 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1385 1386 /* Check requested parameters. */ 1387 if (ospeed < 0) 1388 return (EINVAL); 1389 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1390 return (EINVAL); 1391 1392 /* 1393 * For the console, always force CLOCAL and !HUPCL, so that the port 1394 * is always active. 1395 */ 1396 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1397 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1398 SET(t->c_cflag, CLOCAL); 1399 CLR(t->c_cflag, HUPCL); 1400 } 1401 1402 /* 1403 * If there were no changes, don't do anything. This avoids dropping 1404 * input and improves performance when all we did was frob things like 1405 * VMIN and VTIME. 1406 */ 1407 if (tp->t_ospeed == t->c_ospeed && 1408 tp->t_cflag == t->c_cflag) 1409 return (0); 1410 1411 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1412 1413 s = splserial(); 1414 COM_LOCK(sc); 1415 1416 sc->sc_lcr = lcr; 1417 1418 /* 1419 * If we're not in a mode that assumes a connection is present, then 1420 * ignore carrier changes. 1421 */ 1422 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1423 sc->sc_msr_dcd = 0; 1424 else 1425 sc->sc_msr_dcd = MSR_DCD; 1426 /* 1427 * Set the flow control pins depending on the current flow control 1428 * mode. 1429 */ 1430 if (ISSET(t->c_cflag, CRTSCTS)) { 1431 sc->sc_mcr_dtr = MCR_DTR; 1432 sc->sc_mcr_rts = MCR_RTS; 1433 sc->sc_msr_cts = MSR_CTS; 1434 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1435 } else if (ISSET(t->c_cflag, MDMBUF)) { 1436 /* 1437 * For DTR/DCD flow control, make sure we don't toggle DTR for 1438 * carrier detection. 1439 */ 1440 sc->sc_mcr_dtr = 0; 1441 sc->sc_mcr_rts = MCR_DTR; 1442 sc->sc_msr_cts = MSR_DCD; 1443 sc->sc_efr = 0; 1444 } else { 1445 /* 1446 * If no flow control, then always set RTS. This will make 1447 * the other side happy if it mistakenly thinks we're doing 1448 * RTS/CTS flow control. 1449 */ 1450 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1451 sc->sc_mcr_rts = 0; 1452 sc->sc_msr_cts = 0; 1453 sc->sc_efr = 0; 1454 if (ISSET(sc->sc_mcr, MCR_DTR)) 1455 SET(sc->sc_mcr, MCR_RTS); 1456 else 1457 CLR(sc->sc_mcr, MCR_RTS); 1458 } 1459 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1460 1461 #if 0 1462 if (ospeed == 0) 1463 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1464 else 1465 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1466 #endif 1467 1468 sc->sc_dlbl = ospeed; 1469 sc->sc_dlbh = ospeed >> 8; 1470 1471 /* 1472 * Set the FIFO threshold based on the receive speed. 1473 * 1474 * * If it's a low speed, it's probably a mouse or some other 1475 * interactive device, so set the threshold low. 1476 * * If it's a high speed, trim the trigger level down to prevent 1477 * overflows. 1478 * * Otherwise set it a bit higher. 1479 */ 1480 if (sc->sc_type == COM_TYPE_HAYESP) 1481 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1482 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1483 sc->sc_fifo = FIFO_ENABLE | 1484 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1485 else 1486 sc->sc_fifo = 0; 1487 1488 /* And copy to tty. */ 1489 tp->t_ispeed = t->c_ospeed; 1490 tp->t_ospeed = t->c_ospeed; 1491 tp->t_cflag = t->c_cflag; 1492 1493 if (!sc->sc_heldchange) { 1494 if (sc->sc_tx_busy) { 1495 sc->sc_heldtbc = sc->sc_tbc; 1496 sc->sc_tbc = 0; 1497 sc->sc_heldchange = 1; 1498 } else 1499 com_loadchannelregs(sc); 1500 } 1501 1502 if (!ISSET(t->c_cflag, CHWFLOW)) { 1503 /* Disable the high water mark. */ 1504 sc->sc_r_hiwat = 0; 1505 sc->sc_r_lowat = 0; 1506 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1507 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1508 com_schedrx(sc); 1509 } 1510 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1511 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1512 com_hwiflow(sc); 1513 } 1514 } else { 1515 sc->sc_r_hiwat = com_rbuf_hiwat; 1516 sc->sc_r_lowat = com_rbuf_lowat; 1517 } 1518 1519 COM_UNLOCK(sc); 1520 splx(s); 1521 1522 /* 1523 * Update the tty layer's idea of the carrier bit, in case we changed 1524 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1525 * explicit request. 1526 */ 1527 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1528 1529 #ifdef COM_DEBUG 1530 if (com_debug) 1531 comstatus(sc, "comparam "); 1532 #endif 1533 1534 if (!ISSET(t->c_cflag, CHWFLOW)) { 1535 if (sc->sc_tx_stopped) { 1536 sc->sc_tx_stopped = 0; 1537 comstart(tp); 1538 } 1539 } 1540 1541 return (0); 1542 } 1543 1544 void 1545 com_iflush(struct com_softc *sc) 1546 { 1547 struct com_regs *regsp = &sc->sc_regs; 1548 #ifdef DIAGNOSTIC 1549 int reg; 1550 #endif 1551 int timo; 1552 1553 #ifdef DIAGNOSTIC 1554 reg = 0xffff; 1555 #endif 1556 timo = 50000; 1557 /* flush any pending I/O */ 1558 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1559 && --timo) 1560 #ifdef DIAGNOSTIC 1561 reg = 1562 #else 1563 (void) 1564 #endif 1565 CSR_READ_1(regsp, COM_REG_RXDATA); 1566 #ifdef DIAGNOSTIC 1567 if (!timo) 1568 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1569 reg); 1570 #endif 1571 } 1572 1573 void 1574 com_loadchannelregs(struct com_softc *sc) 1575 { 1576 struct com_regs *regsp = &sc->sc_regs; 1577 1578 /* XXXXX necessary? */ 1579 com_iflush(sc); 1580 1581 if (sc->sc_type == COM_TYPE_PXA2x0) 1582 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1583 else 1584 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1585 1586 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1587 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1588 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1589 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1590 } 1591 } 1592 if (sc->sc_type == COM_TYPE_AU1x00) { 1593 /* alchemy has single separate 16-bit clock divisor register */ 1594 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1595 (sc->sc_dlbh << 8)); 1596 } else { 1597 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1598 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1599 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1600 } 1601 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1602 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1603 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1604 #ifdef COM_HAYESP 1605 if (sc->sc_type == COM_TYPE_HAYESP) { 1606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1607 HAYESP_SETPRESCALER); 1608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1609 sc->sc_prescaler); 1610 } 1611 #endif 1612 1613 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1614 } 1615 1616 int 1617 comhwiflow(struct tty *tp, int block) 1618 { 1619 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1620 int s; 1621 1622 if (COM_ISALIVE(sc) == 0) 1623 return (0); 1624 1625 if (sc->sc_mcr_rts == 0) 1626 return (0); 1627 1628 s = splserial(); 1629 COM_LOCK(sc); 1630 1631 if (block) { 1632 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1633 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1634 com_hwiflow(sc); 1635 } 1636 } else { 1637 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1638 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1639 com_schedrx(sc); 1640 } 1641 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1642 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1643 com_hwiflow(sc); 1644 } 1645 } 1646 1647 COM_UNLOCK(sc); 1648 splx(s); 1649 return (1); 1650 } 1651 1652 /* 1653 * (un)block input via hw flowcontrol 1654 */ 1655 void 1656 com_hwiflow(struct com_softc *sc) 1657 { 1658 struct com_regs *regsp= &sc->sc_regs; 1659 1660 if (sc->sc_mcr_rts == 0) 1661 return; 1662 1663 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1664 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1665 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1666 } else { 1667 SET(sc->sc_mcr, sc->sc_mcr_rts); 1668 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1669 } 1670 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1671 } 1672 1673 1674 void 1675 comstart(struct tty *tp) 1676 { 1677 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1678 struct com_regs *regsp = &sc->sc_regs; 1679 int s; 1680 1681 if (COM_ISALIVE(sc) == 0) 1682 return; 1683 1684 s = spltty(); 1685 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1686 goto out; 1687 if (sc->sc_tx_stopped) 1688 goto out; 1689 1690 if (tp->t_outq.c_cc <= tp->t_lowat) { 1691 if (ISSET(tp->t_state, TS_ASLEEP)) { 1692 CLR(tp->t_state, TS_ASLEEP); 1693 wakeup(&tp->t_outq); 1694 } 1695 selwakeup(&tp->t_wsel); 1696 if (tp->t_outq.c_cc == 0) 1697 goto out; 1698 } 1699 1700 /* Grab the first contiguous region of buffer space. */ 1701 { 1702 u_char *tba; 1703 int tbc; 1704 1705 tba = tp->t_outq.c_cf; 1706 tbc = ndqb(&tp->t_outq, 0); 1707 1708 (void)splserial(); 1709 COM_LOCK(sc); 1710 1711 sc->sc_tba = tba; 1712 sc->sc_tbc = tbc; 1713 } 1714 1715 SET(tp->t_state, TS_BUSY); 1716 sc->sc_tx_busy = 1; 1717 1718 /* Enable transmit completion interrupts if necessary. */ 1719 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1720 SET(sc->sc_ier, IER_ETXRDY); 1721 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1722 } 1723 1724 /* Output the first chunk of the contiguous buffer. */ 1725 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1726 u_int n; 1727 1728 n = sc->sc_tbc; 1729 if (n > sc->sc_fifolen) 1730 n = sc->sc_fifolen; 1731 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1732 sc->sc_tbc -= n; 1733 sc->sc_tba += n; 1734 } 1735 1736 COM_UNLOCK(sc); 1737 out: 1738 splx(s); 1739 return; 1740 } 1741 1742 /* 1743 * Stop output on a line. 1744 */ 1745 void 1746 comstop(struct tty *tp, int flag) 1747 { 1748 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1749 int s; 1750 1751 s = splserial(); 1752 COM_LOCK(sc); 1753 if (ISSET(tp->t_state, TS_BUSY)) { 1754 /* Stop transmitting at the next chunk. */ 1755 sc->sc_tbc = 0; 1756 sc->sc_heldtbc = 0; 1757 if (!ISSET(tp->t_state, TS_TTSTOP)) 1758 SET(tp->t_state, TS_FLUSH); 1759 } 1760 COM_UNLOCK(sc); 1761 splx(s); 1762 } 1763 1764 void 1765 comdiag(void *arg) 1766 { 1767 struct com_softc *sc = arg; 1768 int overflows, floods; 1769 int s; 1770 1771 s = splserial(); 1772 COM_LOCK(sc); 1773 overflows = sc->sc_overflows; 1774 sc->sc_overflows = 0; 1775 floods = sc->sc_floods; 1776 sc->sc_floods = 0; 1777 sc->sc_errors = 0; 1778 COM_UNLOCK(sc); 1779 splx(s); 1780 1781 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1782 sc->sc_dev.dv_xname, 1783 overflows, overflows == 1 ? "" : "s", 1784 floods, floods == 1 ? "" : "s"); 1785 } 1786 1787 integrate void 1788 com_rxsoft(struct com_softc *sc, struct tty *tp) 1789 { 1790 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1791 u_char *get, *end; 1792 u_int cc, scc; 1793 u_char lsr; 1794 int code; 1795 int s; 1796 1797 end = sc->sc_ebuf; 1798 get = sc->sc_rbget; 1799 scc = cc = com_rbuf_size - sc->sc_rbavail; 1800 1801 if (cc == com_rbuf_size) { 1802 sc->sc_floods++; 1803 if (sc->sc_errors++ == 0) 1804 callout_reset(&sc->sc_diag_callout, 60 * hz, 1805 comdiag, sc); 1806 } 1807 1808 /* If not yet open, drop the entire buffer content here */ 1809 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1810 get += cc << 1; 1811 if (get >= end) 1812 get -= com_rbuf_size << 1; 1813 cc = 0; 1814 } 1815 while (cc) { 1816 code = get[0]; 1817 lsr = get[1]; 1818 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1819 if (ISSET(lsr, LSR_OE)) { 1820 sc->sc_overflows++; 1821 if (sc->sc_errors++ == 0) 1822 callout_reset(&sc->sc_diag_callout, 1823 60 * hz, comdiag, sc); 1824 } 1825 if (ISSET(lsr, LSR_BI | LSR_FE)) 1826 SET(code, TTY_FE); 1827 if (ISSET(lsr, LSR_PE)) 1828 SET(code, TTY_PE); 1829 } 1830 if ((*rint)(code, tp) == -1) { 1831 /* 1832 * The line discipline's buffer is out of space. 1833 */ 1834 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1835 /* 1836 * We're either not using flow control, or the 1837 * line discipline didn't tell us to block for 1838 * some reason. Either way, we have no way to 1839 * know when there's more space available, so 1840 * just drop the rest of the data. 1841 */ 1842 get += cc << 1; 1843 if (get >= end) 1844 get -= com_rbuf_size << 1; 1845 cc = 0; 1846 } else { 1847 /* 1848 * Don't schedule any more receive processing 1849 * until the line discipline tells us there's 1850 * space available (through comhwiflow()). 1851 * Leave the rest of the data in the input 1852 * buffer. 1853 */ 1854 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1855 } 1856 break; 1857 } 1858 get += 2; 1859 if (get >= end) 1860 get = sc->sc_rbuf; 1861 cc--; 1862 } 1863 1864 if (cc != scc) { 1865 sc->sc_rbget = get; 1866 s = splserial(); 1867 COM_LOCK(sc); 1868 1869 cc = sc->sc_rbavail += scc - cc; 1870 /* Buffers should be ok again, release possible block. */ 1871 if (cc >= sc->sc_r_lowat) { 1872 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1873 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1874 SET(sc->sc_ier, IER_ERXRDY); 1875 #ifdef COM_PXA2X0 1876 if (sc->sc_type == COM_TYPE_PXA2x0) 1877 SET(sc->sc_ier, IER_ERXTOUT); 1878 #endif 1879 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1880 } 1881 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1882 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1883 com_hwiflow(sc); 1884 } 1885 } 1886 COM_UNLOCK(sc); 1887 splx(s); 1888 } 1889 } 1890 1891 integrate void 1892 com_txsoft(struct com_softc *sc, struct tty *tp) 1893 { 1894 1895 CLR(tp->t_state, TS_BUSY); 1896 if (ISSET(tp->t_state, TS_FLUSH)) 1897 CLR(tp->t_state, TS_FLUSH); 1898 else 1899 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1900 (*tp->t_linesw->l_start)(tp); 1901 } 1902 1903 integrate void 1904 com_stsoft(struct com_softc *sc, struct tty *tp) 1905 { 1906 u_char msr, delta; 1907 int s; 1908 1909 s = splserial(); 1910 COM_LOCK(sc); 1911 msr = sc->sc_msr; 1912 delta = sc->sc_msr_delta; 1913 sc->sc_msr_delta = 0; 1914 COM_UNLOCK(sc); 1915 splx(s); 1916 1917 if (ISSET(delta, sc->sc_msr_dcd)) { 1918 /* 1919 * Inform the tty layer that carrier detect changed. 1920 */ 1921 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1922 } 1923 1924 if (ISSET(delta, sc->sc_msr_cts)) { 1925 /* Block or unblock output according to flow control. */ 1926 if (ISSET(msr, sc->sc_msr_cts)) { 1927 sc->sc_tx_stopped = 0; 1928 (*tp->t_linesw->l_start)(tp); 1929 } else { 1930 sc->sc_tx_stopped = 1; 1931 } 1932 } 1933 1934 #ifdef COM_DEBUG 1935 if (com_debug) 1936 comstatus(sc, "com_stsoft"); 1937 #endif 1938 } 1939 1940 void 1941 comsoft(void *arg) 1942 { 1943 struct com_softc *sc = arg; 1944 struct tty *tp; 1945 1946 if (COM_ISALIVE(sc) == 0) 1947 return; 1948 1949 tp = sc->sc_tty; 1950 1951 if (sc->sc_rx_ready) { 1952 sc->sc_rx_ready = 0; 1953 com_rxsoft(sc, tp); 1954 } 1955 1956 if (sc->sc_st_check) { 1957 sc->sc_st_check = 0; 1958 com_stsoft(sc, tp); 1959 } 1960 1961 if (sc->sc_tx_done) { 1962 sc->sc_tx_done = 0; 1963 com_txsoft(sc, tp); 1964 } 1965 } 1966 1967 int 1968 comintr(void *arg) 1969 { 1970 struct com_softc *sc = arg; 1971 struct com_regs *regsp = &sc->sc_regs; 1972 1973 u_char *put, *end; 1974 u_int cc; 1975 u_char lsr, iir; 1976 1977 if (COM_ISALIVE(sc) == 0) 1978 return (0); 1979 1980 COM_LOCK(sc); 1981 iir = CSR_READ_1(regsp, COM_REG_IIR); 1982 if (ISSET(iir, IIR_NOPEND)) { 1983 COM_UNLOCK(sc); 1984 return (0); 1985 } 1986 1987 end = sc->sc_ebuf; 1988 put = sc->sc_rbput; 1989 cc = sc->sc_rbavail; 1990 1991 again: do { 1992 u_char msr, delta; 1993 1994 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1995 if (ISSET(lsr, LSR_BI)) { 1996 int cn_trapped = 0; 1997 1998 cn_check_magic(sc->sc_tty->t_dev, 1999 CNC_BREAK, com_cnm_state); 2000 if (cn_trapped) 2001 continue; 2002 #if defined(KGDB) && !defined(DDB) 2003 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2004 kgdb_connect(1); 2005 continue; 2006 } 2007 #endif 2008 } 2009 2010 if (ISSET(lsr, LSR_RCV_MASK) && 2011 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2012 while (cc > 0) { 2013 int cn_trapped = 0; 2014 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2015 put[1] = lsr; 2016 cn_check_magic(sc->sc_tty->t_dev, 2017 put[0], com_cnm_state); 2018 if (cn_trapped) 2019 goto next; 2020 put += 2; 2021 if (put >= end) 2022 put = sc->sc_rbuf; 2023 cc--; 2024 next: 2025 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2026 if (!ISSET(lsr, LSR_RCV_MASK)) 2027 break; 2028 } 2029 2030 /* 2031 * Current string of incoming characters ended because 2032 * no more data was available or we ran out of space. 2033 * Schedule a receive event if any data was received. 2034 * If we're out of space, turn off receive interrupts. 2035 */ 2036 sc->sc_rbput = put; 2037 sc->sc_rbavail = cc; 2038 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2039 sc->sc_rx_ready = 1; 2040 2041 /* 2042 * See if we are in danger of overflowing a buffer. If 2043 * so, use hardware flow control to ease the pressure. 2044 */ 2045 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2046 cc < sc->sc_r_hiwat) { 2047 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2048 com_hwiflow(sc); 2049 } 2050 2051 /* 2052 * If we're out of space, disable receive interrupts 2053 * until the queue has drained a bit. 2054 */ 2055 if (!cc) { 2056 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2057 #ifdef COM_PXA2X0 2058 if (sc->sc_type == COM_TYPE_PXA2x0) 2059 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2060 else 2061 #endif 2062 CLR(sc->sc_ier, IER_ERXRDY); 2063 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2064 } 2065 } else { 2066 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2067 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2068 continue; 2069 } 2070 } 2071 2072 msr = CSR_READ_1(regsp, COM_REG_MSR); 2073 delta = msr ^ sc->sc_msr; 2074 sc->sc_msr = msr; 2075 #ifdef __HAVE_TIMECOUNTER 2076 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2077 (delta & MSR_DCD)) { 2078 pps_capture(&sc->sc_pps_state); 2079 pps_event(&sc->sc_pps_state, 2080 (msr & MSR_DCD) ? 2081 PPS_CAPTUREASSERT : 2082 PPS_CAPTURECLEAR); 2083 } 2084 #else /* !__HAVE_TIMECOUNTER */ 2085 /* 2086 * Pulse-per-second (PSS) signals on edge of DCD? 2087 * Process these even if line discipline is ignoring DCD. 2088 */ 2089 if (delta & sc->sc_ppsmask) { 2090 struct timeval tv; 2091 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2092 /* XXX nanotime() */ 2093 microtime(&tv); 2094 TIMEVAL_TO_TIMESPEC(&tv, 2095 &sc->ppsinfo.assert_timestamp); 2096 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2097 timespecadd(&sc->ppsinfo.assert_timestamp, 2098 &sc->ppsparam.assert_offset, 2099 &sc->ppsinfo.assert_timestamp); 2100 } 2101 2102 #ifdef PPS_SYNC 2103 if (pps_kc_hardpps_source == sc && 2104 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2105 hardpps(&tv, tv.tv_usec); 2106 } 2107 #endif 2108 sc->ppsinfo.assert_sequence++; 2109 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2110 2111 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2112 /* XXX nanotime() */ 2113 microtime(&tv); 2114 TIMEVAL_TO_TIMESPEC(&tv, 2115 &sc->ppsinfo.clear_timestamp); 2116 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2117 timespecadd(&sc->ppsinfo.clear_timestamp, 2118 &sc->ppsparam.clear_offset, 2119 &sc->ppsinfo.clear_timestamp); 2120 } 2121 2122 #ifdef PPS_SYNC 2123 if (pps_kc_hardpps_source == sc && 2124 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2125 hardpps(&tv, tv.tv_usec); 2126 } 2127 #endif 2128 sc->ppsinfo.clear_sequence++; 2129 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2130 } 2131 } 2132 #endif /* !__HAVE_TIMECOUNTER */ 2133 2134 /* 2135 * Process normal status changes 2136 */ 2137 if (ISSET(delta, sc->sc_msr_mask)) { 2138 SET(sc->sc_msr_delta, delta); 2139 2140 /* 2141 * Stop output immediately if we lose the output 2142 * flow control signal or carrier detect. 2143 */ 2144 if (ISSET(~msr, sc->sc_msr_mask)) { 2145 sc->sc_tbc = 0; 2146 sc->sc_heldtbc = 0; 2147 #ifdef COM_DEBUG 2148 if (com_debug) 2149 comstatus(sc, "comintr "); 2150 #endif 2151 } 2152 2153 sc->sc_st_check = 1; 2154 } 2155 } while (!ISSET((iir = 2156 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2157 /* 2158 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2159 * by IIR read, so we can't do this way: `process all interrupts, 2160 * then do TX if possble'. 2161 */ 2162 (iir & IIR_IMASK) != IIR_TXRDY); 2163 2164 /* 2165 * Read LSR again, since there may be an interrupt between 2166 * the last LSR read and IIR read above. 2167 */ 2168 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2169 2170 /* 2171 * See if data can be transmitted as well. 2172 * Schedule tx done event if no data left 2173 * and tty was marked busy. 2174 */ 2175 if (ISSET(lsr, LSR_TXRDY)) { 2176 /* 2177 * If we've delayed a parameter change, do it now, and restart 2178 * output. 2179 */ 2180 if (sc->sc_heldchange) { 2181 com_loadchannelregs(sc); 2182 sc->sc_heldchange = 0; 2183 sc->sc_tbc = sc->sc_heldtbc; 2184 sc->sc_heldtbc = 0; 2185 } 2186 2187 /* Output the next chunk of the contiguous buffer, if any. */ 2188 if (sc->sc_tbc > 0) { 2189 u_int n; 2190 2191 n = sc->sc_tbc; 2192 if (n > sc->sc_fifolen) 2193 n = sc->sc_fifolen; 2194 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2195 sc->sc_tbc -= n; 2196 sc->sc_tba += n; 2197 } else { 2198 /* Disable transmit completion interrupts if necessary. */ 2199 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2200 CLR(sc->sc_ier, IER_ETXRDY); 2201 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2202 } 2203 if (sc->sc_tx_busy) { 2204 sc->sc_tx_busy = 0; 2205 sc->sc_tx_done = 1; 2206 } 2207 } 2208 } 2209 2210 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2211 goto again; 2212 2213 COM_UNLOCK(sc); 2214 2215 /* Wake up the poller. */ 2216 softintr_schedule(sc->sc_si); 2217 2218 #if NRND > 0 && defined(RND_COM) 2219 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2220 #endif 2221 2222 return (1); 2223 } 2224 2225 /* 2226 * The following functions are polled getc and putc routines, shared 2227 * by the console and kgdb glue. 2228 * 2229 * The read-ahead code is so that you can detect pending in-band 2230 * cn_magic in polled mode while doing output rather than having to 2231 * wait until the kernel decides it needs input. 2232 */ 2233 2234 #define MAX_READAHEAD 20 2235 static int com_readahead[MAX_READAHEAD]; 2236 static int com_readaheadcount = 0; 2237 2238 int 2239 com_common_getc(dev_t dev, struct com_regs *regsp) 2240 { 2241 int s = splserial(); 2242 u_char stat, c; 2243 2244 /* got a character from reading things earlier */ 2245 if (com_readaheadcount > 0) { 2246 int i; 2247 2248 c = com_readahead[0]; 2249 for (i = 1; i < com_readaheadcount; i++) { 2250 com_readahead[i-1] = com_readahead[i]; 2251 } 2252 com_readaheadcount--; 2253 splx(s); 2254 return (c); 2255 } 2256 2257 /* block until a character becomes available */ 2258 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2259 ; 2260 2261 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2262 stat = CSR_READ_1(regsp, COM_REG_IIR); 2263 { 2264 int cn_trapped = 0; /* unused */ 2265 #ifdef DDB 2266 extern int db_active; 2267 if (!db_active) 2268 #endif 2269 cn_check_magic(dev, c, com_cnm_state); 2270 } 2271 splx(s); 2272 return (c); 2273 } 2274 2275 void 2276 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2277 { 2278 int s = splserial(); 2279 int cin, stat, timo; 2280 2281 if (com_readaheadcount < MAX_READAHEAD 2282 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2283 int cn_trapped = 0; 2284 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2285 stat = CSR_READ_1(regsp, COM_REG_IIR); 2286 cn_check_magic(dev, cin, com_cnm_state); 2287 com_readahead[com_readaheadcount++] = cin; 2288 } 2289 2290 /* wait for any pending transmission to finish */ 2291 timo = 150000; 2292 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2293 continue; 2294 2295 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2296 COM_BARRIER(regsp, BR | BW); 2297 2298 splx(s); 2299 } 2300 2301 /* 2302 * Initialize UART for use as console or KGDB line. 2303 */ 2304 int 2305 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2306 tcflag_t cflag) 2307 { 2308 2309 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2310 ®sp->cr_ioh)) 2311 return (ENOMEM); /* ??? */ 2312 2313 rate = comspeed(rate, frequency, type); 2314 if (type != COM_TYPE_AU1x00) { 2315 /* no EFR on alchemy */ 2316 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2317 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2318 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2319 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2320 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2321 } else { 2322 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2323 } 2324 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2325 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2326 CSR_WRITE_1(regsp, COM_REG_FIFO, 2327 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2328 #ifdef COM_PXA2X0 2329 if (type == COM_TYPE_PXA2x0) 2330 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2331 else 2332 #endif 2333 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2334 2335 return (0); 2336 } 2337 2338 /* 2339 * Following are all routines needed for COM to act as console 2340 */ 2341 struct consdev comcons = { 2342 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2343 NODEV, CN_NORMAL 2344 }; 2345 2346 2347 int 2348 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2349 tcflag_t cflag) 2350 { 2351 int res; 2352 2353 comconsregs = *regsp; 2354 2355 res = cominit(&comconsregs, rate, frequency, type, cflag); 2356 if (res) 2357 return (res); 2358 2359 cn_tab = &comcons; 2360 cn_init_magic(&com_cnm_state); 2361 cn_set_magic("\047\001"); /* default magic is BREAK */ 2362 2363 comconsrate = rate; 2364 comconscflag = cflag; 2365 2366 return (0); 2367 } 2368 2369 int 2370 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2371 int type, tcflag_t cflag) 2372 { 2373 struct com_regs regs; 2374 2375 memset(®s, 0, sizeof regs); 2376 regs.cr_iot = iot; 2377 regs.cr_iobase = iobase; 2378 regs.cr_nports = COM_NPORTS; 2379 #ifdef COM_REGMAP 2380 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2381 #endif 2382 2383 return comcnattach1(®s, rate, frequency, type, cflag); 2384 } 2385 2386 int 2387 comcngetc(dev_t dev) 2388 { 2389 2390 return (com_common_getc(dev, &comconsregs)); 2391 } 2392 2393 /* 2394 * Console kernel output character routine. 2395 */ 2396 void 2397 comcnputc(dev_t dev, int c) 2398 { 2399 2400 com_common_putc(dev, &comconsregs, c); 2401 } 2402 2403 void 2404 comcnpollc(dev_t dev, int on) 2405 { 2406 2407 } 2408 2409 #ifdef KGDB 2410 int 2411 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2412 tcflag_t cflag) 2413 { 2414 int res; 2415 2416 if (regsp->cr_iot == comconsregs.cr_iot && 2417 regsp->cr_iobase == comconsregs.cr_iobase) { 2418 #if !defined(DDB) 2419 return (EBUSY); /* cannot share with console */ 2420 #else 2421 comkgdbregs = *regsp; 2422 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2423 #endif 2424 } else { 2425 comkgdbregs = *regsp; 2426 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2427 if (res) 2428 return (res); 2429 2430 /* 2431 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2432 * expects this to be initialized 2433 */ 2434 cn_init_magic(&com_cnm_state); 2435 cn_set_magic("\047\001"); 2436 } 2437 2438 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2439 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2440 2441 return (0); 2442 } 2443 2444 int 2445 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2446 int frequency, int type, tcflag_t cflag) 2447 { 2448 struct com_regs regs; 2449 2450 regs.cr_iot = iot; 2451 regs.cr_nports = COM_NPORTS; 2452 regs.cr_iobase = iobase; 2453 #ifdef COM_REGMAP 2454 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2455 #endif 2456 2457 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2458 } 2459 2460 /* ARGSUSED */ 2461 int 2462 com_kgdb_getc(void *arg) 2463 { 2464 2465 return (com_common_getc(NODEV, &comkgdbregs)); 2466 } 2467 2468 /* ARGSUSED */ 2469 void 2470 com_kgdb_putc(void *arg, int c) 2471 { 2472 2473 com_common_putc(NODEV, &comkgdbregs, c); 2474 } 2475 #endif /* KGDB */ 2476 2477 /* helper function to identify the com ports used by 2478 console or KGDB (and not yet autoconf attached) */ 2479 int 2480 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2481 { 2482 bus_space_handle_t help; 2483 2484 if (!comconsattached && 2485 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2486 help = comconsregs.cr_ioh; 2487 #ifdef KGDB 2488 else if (!com_kgdb_attached && 2489 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2490 help = comkgdbregs.cr_ioh; 2491 #endif 2492 else 2493 return (0); 2494 2495 if (ioh) 2496 *ioh = help; 2497 return (1); 2498 } 2499 2500 /* 2501 * this routine exists to serve as a shutdown hook for systems that 2502 * have firmware which doesn't interact properly with a com device in 2503 * FIFO mode. 2504 */ 2505 void 2506 com_cleanup(void *arg) 2507 { 2508 struct com_softc *sc = arg; 2509 2510 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2511 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2512 } 2513 2514 void 2515 com_power(int why, void *arg) 2516 { 2517 struct com_softc *sc = arg; 2518 int s; 2519 2520 s = splserial(); 2521 switch (why) { 2522 case PWR_SUSPEND: 2523 case PWR_STANDBY: 2524 /* XXX should we do something to stop the device? */ 2525 break; 2526 case PWR_RESUME: 2527 com_loadchannelregs(sc); 2528 break; 2529 case PWR_SOFTSUSPEND: 2530 case PWR_SOFTSTANDBY: 2531 case PWR_SOFTRESUME: 2532 break; 2533 } 2534 splx(s); 2535 } 2536
Indexes created Thu Sep 25 16:09:42 GMT 2025