com.c revision 1.262.2.1
1 /* $NetBSD: com.c,v 1.262.2.1 2007/10/29 02:12:51 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.262.2.1 2007/10/29 02:12:51 matt Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 126 #include <machine/intr.h> 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 195 integrate void com_rxsoft(struct com_softc *, struct tty *); 196 integrate void com_txsoft(struct com_softc *, struct tty *); 197 integrate void com_stsoft(struct com_softc *, struct tty *); 198 integrate void com_schedrx(struct com_softc *); 199 void comdiag(void *); 200 201 extern struct cfdriver com_cd; 202 203 dev_type_open(comopen); 204 dev_type_close(comclose); 205 dev_type_read(comread); 206 dev_type_write(comwrite); 207 dev_type_ioctl(comioctl); 208 dev_type_stop(comstop); 209 dev_type_tty(comtty); 210 dev_type_poll(compoll); 211 212 const struct cdevsw com_cdevsw = { 213 comopen, comclose, comread, comwrite, comioctl, 214 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 215 }; 216 217 /* 218 * Make this an option variable one can patch. 219 * But be warned: this must be a power of 2! 220 */ 221 u_int com_rbuf_size = COM_RING_SIZE; 222 223 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 224 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 225 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 226 227 static struct com_regs comconsregs; 228 static int comconsattached; 229 static int comconsrate; 230 static tcflag_t comconscflag; 231 static struct cnm_state com_cnm_state; 232 233 #ifndef __HAVE_TIMECOUNTER 234 static int ppscap = 235 PPS_TSFMT_TSPEC | 236 PPS_CAPTUREASSERT | 237 PPS_CAPTURECLEAR | 238 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 239 #endif /* !__HAVE_TIMECOUNTER */ 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_16550 { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 256 257 const bus_size_t com_std_map[16] = COM_REG_16550; 258 #endif /* COM_REGMAP */ 259 260 #define COMUNIT_MASK 0x7ffff 261 #define COMDIALOUT_MASK 0x80000 262 263 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 264 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active(&(sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 #define COM_LOCK(sc) simple_lock(&(sc)->sc_lock) 275 #define COM_UNLOCK(sc) simple_unlock(&(sc)->sc_lock) 276 277 /*ARGSUSED*/ 278 int 279 comspeed(long speed, long frequency, int type) 280 { 281 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 282 283 int x, err; 284 int divisor = 16; 285 286 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 287 divisor = 13; 288 } 289 290 #if 0 291 if (speed == 0) 292 return (0); 293 #endif 294 if (speed <= 0) 295 return (-1); 296 x = divrnd(frequency / divisor, speed); 297 if (x <= 0) 298 return (-1); 299 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 300 if (err < 0) 301 err = -err; 302 if (err > COM_TOLERANCE) 303 return (-1); 304 return (x); 305 306 #undef divrnd 307 } 308 309 #ifdef COM_DEBUG 310 int com_debug = 0; 311 312 void comstatus(struct com_softc *, const char *); 313 void 314 comstatus(struct com_softc *sc, const char *str) 315 { 316 struct tty *tp = sc->sc_tty; 317 318 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 319 sc->sc_dev.dv_xname, str, 320 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 322 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 324 sc->sc_tx_stopped ? '+' : '-'); 325 326 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 327 sc->sc_dev.dv_xname, str, 328 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 329 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 330 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 331 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 332 sc->sc_rx_flags); 333 } 334 #endif 335 336 int 337 com_probe_subr(struct com_regs *regs) 338 { 339 340 /* force access to id reg */ 341 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 342 CSR_WRITE_1(regs, COM_REG_IIR, 0); 343 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 344 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 345 return (0); 346 347 return (1); 348 } 349 350 int 351 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 352 { 353 struct com_regs regs; 354 355 regs.cr_iot = iot; 356 regs.cr_ioh = ioh; 357 #ifdef COM_REGMAP 358 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 359 #endif 360 361 return com_probe_subr(®s); 362 } 363 364 static void 365 com_enable_debugport(struct com_softc *sc) 366 { 367 /* Turn on line break interrupt, set carrier. */ 368 sc->sc_ier = IER_ERXRDY; 369 if (sc->sc_type == COM_TYPE_PXA2x0) 370 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 371 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 372 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 373 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 374 } 375 376 void 377 com_attach_subr(struct com_softc *sc) 378 { 379 struct com_regs *regsp = &sc->sc_regs; 380 struct tty *tp; 381 #ifdef COM_16650 382 u_int8_t lcr; 383 #endif 384 const char *fifo_msg = NULL; 385 386 aprint_naive("\n"); 387 388 callout_init(&sc->sc_diag_callout, 0); 389 simple_lock_init(&sc->sc_lock); 390 391 /* Disable interrupts before configuring the device. */ 392 if (sc->sc_type == COM_TYPE_PXA2x0) 393 sc->sc_ier = IER_EUART; 394 else 395 sc->sc_ier = 0; 396 397 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 398 399 if (regsp->cr_iot == comconsregs.cr_iot && 400 regsp->cr_iobase == comconsregs.cr_iobase) { 401 comconsattached = 1; 402 403 /* Make sure the console is always "hardwired". */ 404 delay(10000); /* wait for output to finish */ 405 SET(sc->sc_hwflags, COM_HW_CONSOLE); 406 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 407 } 408 409 /* Probe for FIFO */ 410 switch (sc->sc_type) { 411 case COM_TYPE_HAYESP: 412 goto fifodone; 413 414 case COM_TYPE_AU1x00: 415 sc->sc_fifolen = 16; 416 fifo_msg = "Au1X00 UART, working fifo"; 417 SET(sc->sc_hwflags, COM_HW_FIFO); 418 goto fifodelay; 419 420 case COM_TYPE_OMAP: 421 sc->sc_fifolen = 64; 422 fifo_msg = "OMAP UART, working fifo"; 423 SET(sc->sc_hwflags, COM_HW_FIFO); 424 goto fifodelay; 425 } 426 427 sc->sc_fifolen = 1; 428 /* look for a NS 16550AF UART with FIFOs */ 429 CSR_WRITE_1(regsp, COM_REG_FIFO, 430 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 431 delay(100); 432 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 433 == IIR_FIFO_MASK) 434 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 435 == FIFO_TRIGGER_14) { 436 SET(sc->sc_hwflags, COM_HW_FIFO); 437 438 #ifdef COM_16650 439 /* 440 * IIR changes into the EFR if LCR is set to LCR_EERS 441 * on 16650s. We also know IIR != 0 at this point. 442 * Write 0 into the EFR, and read it. If the result 443 * is 0, we have a 16650. 444 * 445 * Older 16650s were broken; the test to detect them 446 * is taken from the Linux driver. Apparently 447 * setting DLAB enable gives access to the EFR on 448 * these chips. 449 */ 450 lcr = CSR_READ_1(regsp, COM_REG_LCR); 451 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 452 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 453 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 454 CSR_WRITE_1(regsp, COM_REG_LCR, 455 lcr | LCR_DLAB); 456 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 457 CLR(sc->sc_hwflags, COM_HW_FIFO); 458 sc->sc_fifolen = 0; 459 } else { 460 SET(sc->sc_hwflags, COM_HW_FLOW); 461 sc->sc_fifolen = 32; 462 } 463 } else 464 #endif 465 sc->sc_fifolen = 16; 466 467 #ifdef COM_16650 468 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 469 if (sc->sc_fifolen == 0) 470 fifo_msg = "st16650, broken fifo"; 471 else if (sc->sc_fifolen == 32) 472 fifo_msg = "st16650a, working fifo"; 473 else 474 #endif 475 fifo_msg = "ns16550a, working fifo"; 476 } else 477 fifo_msg = "ns16550, broken fifo"; 478 else 479 fifo_msg = "ns8250 or ns16450, no fifo"; 480 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 481 fifodelay: 482 /* 483 * Some chips will clear down both Tx and Rx FIFOs when zero is 484 * written to com_fifo. If this chip is the console, writing zero 485 * results in some of the chip/FIFO description being lost, so delay 486 * printing it until now. 487 */ 488 delay(10); 489 aprint_normal(": %s\n", fifo_msg); 490 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 491 sc->sc_fifolen = 1; 492 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 493 } 494 495 fifodone: 496 497 tp = ttymalloc(); 498 tp->t_oproc = comstart; 499 tp->t_param = comparam; 500 tp->t_hwiflow = comhwiflow; 501 502 sc->sc_tty = tp; 503 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 504 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 505 sc->sc_rbavail = com_rbuf_size; 506 if (sc->sc_rbuf == NULL) { 507 aprint_error("%s: unable to allocate ring buffer\n", 508 sc->sc_dev.dv_xname); 509 return; 510 } 511 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 512 513 tty_attach(tp); 514 515 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 516 SET(sc->sc_mcr, MCR_IENABLE); 517 518 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 519 int maj; 520 521 /* locate the major number */ 522 maj = cdevsw_lookup_major(&com_cdevsw); 523 524 tp->t_dev = cn_tab->cn_dev = makedev(maj, 525 device_unit(&sc->sc_dev)); 526 527 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 528 } 529 530 #ifdef KGDB 531 /* 532 * Allow kgdb to "take over" this port. If this is 533 * not the console and is the kgdb device, it has 534 * exclusive use. If it's the console _and_ the 535 * kgdb device, it doesn't. 536 */ 537 if (regsp->cr_iot == comkgdbregs.cr_iot && 538 regsp->cr_iobase == comkgdbregs.cr_iobase) { 539 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 540 com_kgdb_attached = 1; 541 542 SET(sc->sc_hwflags, COM_HW_KGDB); 543 } 544 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 545 } 546 #endif 547 548 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, comsoft, sc); 549 550 #if NRND > 0 && defined(RND_COM) 551 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 552 RND_TYPE_TTY, 0); 553 #endif 554 555 /* if there are no enable/disable functions, assume the device 556 is always enabled */ 557 if (!sc->enable) 558 sc->enabled = 1; 559 560 com_config(sc); 561 562 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 563 com_power, sc); 564 if (sc->sc_powerhook == NULL) 565 aprint_error("%s: WARNING: unable to establish power hook\n", 566 sc->sc_dev.dv_xname); 567 568 SET(sc->sc_hwflags, COM_HW_DEV_OK); 569 } 570 571 void 572 com_config(struct com_softc *sc) 573 { 574 struct com_regs *regsp = &sc->sc_regs; 575 576 /* Disable interrupts before configuring the device. */ 577 if (sc->sc_type == COM_TYPE_PXA2x0) 578 sc->sc_ier = IER_EUART; 579 else 580 sc->sc_ier = 0; 581 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 582 (void) CSR_READ_1(regsp, COM_REG_IIR); 583 584 #ifdef COM_HAYESP 585 /* Look for a Hayes ESP board. */ 586 if (sc->sc_type == COM_TYPE_HAYESP) { 587 588 /* Set 16550 compatibility mode */ 589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 590 HAYESP_SETMODE); 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 592 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 593 HAYESP_MODE_SCALE); 594 595 /* Set RTS/CTS flow control */ 596 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 597 HAYESP_SETFLOWTYPE); 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 599 HAYESP_FLOW_RTS); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_FLOW_CTS); 602 603 /* Set flow control levels */ 604 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 605 HAYESP_SETRXFLOW); 606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 607 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 609 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 611 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 613 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 614 } 615 #endif 616 617 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 618 com_enable_debugport(sc); 619 } 620 621 int 622 com_detach(struct device *self, int flags) 623 { 624 struct com_softc *sc = (struct com_softc *)self; 625 int maj, mn; 626 627 /* kill the power hook */ 628 if (sc->sc_powerhook != NULL) 629 powerhook_disestablish(sc->sc_powerhook); 630 631 /* locate the major number */ 632 maj = cdevsw_lookup_major(&com_cdevsw); 633 634 /* Nuke the vnodes for any open instances. */ 635 mn = device_unit(self); 636 vdevgone(maj, mn, mn, VCHR); 637 638 mn |= COMDIALOUT_MASK; 639 vdevgone(maj, mn, mn, VCHR); 640 641 if (sc->sc_rbuf == NULL) { 642 /* 643 * Ring buffer allocation failed in the com_attach_subr, 644 * only the tty is allocated, and nothing else. 645 */ 646 ttyfree(sc->sc_tty); 647 return 0; 648 } 649 650 /* Free the receive buffer. */ 651 free(sc->sc_rbuf, M_DEVBUF); 652 653 /* Detach and free the tty. */ 654 tty_detach(sc->sc_tty); 655 ttyfree(sc->sc_tty); 656 657 /* Unhook the soft interrupt handler. */ 658 softintr_disestablish(sc->sc_si); 659 660 #if NRND > 0 && defined(RND_COM) 661 /* Unhook the entropy source. */ 662 rnd_detach_source(&sc->rnd_source); 663 #endif 664 665 return (0); 666 } 667 668 int 669 com_activate(struct device *self, enum devact act) 670 { 671 struct com_softc *sc = (struct com_softc *)self; 672 int s, rv = 0; 673 674 s = splserial(); 675 COM_LOCK(sc); 676 switch (act) { 677 case DVACT_ACTIVATE: 678 rv = EOPNOTSUPP; 679 break; 680 681 case DVACT_DEACTIVATE: 682 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 683 rv = EBUSY; 684 break; 685 } 686 687 if (sc->disable != NULL && sc->enabled != 0) { 688 (*sc->disable)(sc); 689 sc->enabled = 0; 690 } 691 break; 692 } 693 694 COM_UNLOCK(sc); 695 if (sc->sc_type == COM_TYPE_OMAP) { 696 /* enable but mode is based on speed */ 697 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 698 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_13X); 699 } else { 700 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_16X); 701 } 702 } 703 splx(s); 704 return (rv); 705 } 706 707 void 708 com_shutdown(struct com_softc *sc) 709 { 710 struct tty *tp = sc->sc_tty; 711 int s; 712 713 s = splserial(); 714 COM_LOCK(sc); 715 716 /* If we were asserting flow control, then deassert it. */ 717 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 718 com_hwiflow(sc); 719 720 /* Clear any break condition set with TIOCSBRK. */ 721 com_break(sc, 0); 722 723 #ifndef __HAVE_TIMECOUNTER 724 /* Turn off PPS capture on last close. */ 725 sc->sc_ppsmask = 0; 726 sc->ppsparam.mode = 0; 727 #endif /* !__HAVE_TIMECOUNTER */ 728 729 /* 730 * Hang up if necessary. Wait a bit, so the other side has time to 731 * notice even if we immediately open the port again. 732 * Avoid tsleeping above splhigh(). 733 */ 734 if (ISSET(tp->t_cflag, HUPCL)) { 735 com_modem(sc, 0); 736 COM_UNLOCK(sc); 737 splx(s); 738 /* XXX tsleep will only timeout */ 739 (void) tsleep(sc, TTIPRI, ttclos, hz); 740 s = splserial(); 741 COM_LOCK(sc); 742 } 743 744 /* Turn off interrupts. */ 745 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 746 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 747 if (sc->sc_type == COM_TYPE_PXA2x0) 748 sc->sc_ier |= IER_ERXTOUT; 749 } else 750 sc->sc_ier = 0; 751 752 if (sc->sc_type == COM_TYPE_PXA2x0) 753 sc->sc_ier |= IER_EUART; 754 755 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 756 757 if (sc->disable) { 758 #ifdef DIAGNOSTIC 759 if (!sc->enabled) 760 panic("com_shutdown: not enabled?"); 761 #endif 762 (*sc->disable)(sc); 763 sc->enabled = 0; 764 } 765 COM_UNLOCK(sc); 766 splx(s); 767 } 768 769 int 770 comopen(dev_t dev, int flag, int mode, struct lwp *l) 771 { 772 struct com_softc *sc; 773 struct tty *tp; 774 int s, s2; 775 int error; 776 777 sc = device_lookup(&com_cd, COMUNIT(dev)); 778 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 779 sc->sc_rbuf == NULL) 780 return (ENXIO); 781 782 if (!device_is_active(&sc->sc_dev)) 783 return (ENXIO); 784 785 #ifdef KGDB 786 /* 787 * If this is the kgdb port, no other use is permitted. 788 */ 789 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 790 return (EBUSY); 791 #endif 792 793 tp = sc->sc_tty; 794 795 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 796 return (EBUSY); 797 798 s = spltty(); 799 800 /* 801 * Do the following iff this is a first open. 802 */ 803 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 804 struct termios t; 805 806 tp->t_dev = dev; 807 808 s2 = splserial(); 809 COM_LOCK(sc); 810 811 if (sc->enable) { 812 if ((*sc->enable)(sc)) { 813 COM_UNLOCK(sc); 814 splx(s2); 815 splx(s); 816 printf("%s: device enable failed\n", 817 sc->sc_dev.dv_xname); 818 return (EIO); 819 } 820 sc->enabled = 1; 821 com_config(sc); 822 } 823 824 /* Turn on interrupts. */ 825 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 826 if (sc->sc_type == COM_TYPE_PXA2x0) 827 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 828 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 829 830 /* Fetch the current modem control status, needed later. */ 831 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 832 833 /* Clear PPS capture state on first open. */ 834 #ifdef __HAVE_TIMECOUNTER 835 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 836 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 837 pps_init(&sc->sc_pps_state); 838 #else /* !__HAVE_TIMECOUNTER */ 839 sc->sc_ppsmask = 0; 840 sc->ppsparam.mode = 0; 841 #endif /* !__HAVE_TIMECOUNTER */ 842 843 COM_UNLOCK(sc); 844 splx(s2); 845 846 /* 847 * Initialize the termios status to the defaults. Add in the 848 * sticky bits from TIOCSFLAGS. 849 */ 850 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 851 t.c_ospeed = comconsrate; 852 t.c_cflag = comconscflag; 853 } else { 854 t.c_ospeed = TTYDEF_SPEED; 855 t.c_cflag = TTYDEF_CFLAG; 856 } 857 t.c_ispeed = t.c_ospeed; 858 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 859 SET(t.c_cflag, CLOCAL); 860 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 861 SET(t.c_cflag, CRTSCTS); 862 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 863 SET(t.c_cflag, MDMBUF); 864 /* Make sure comparam() will do something. */ 865 tp->t_ospeed = 0; 866 (void) comparam(tp, &t); 867 tp->t_iflag = TTYDEF_IFLAG; 868 tp->t_oflag = TTYDEF_OFLAG; 869 tp->t_lflag = TTYDEF_LFLAG; 870 ttychars(tp); 871 ttsetwater(tp); 872 873 s2 = splserial(); 874 COM_LOCK(sc); 875 876 /* 877 * Turn on DTR. We must always do this, even if carrier is not 878 * present, because otherwise we'd have to use TIOCSDTR 879 * immediately after setting CLOCAL, which applications do not 880 * expect. We always assert DTR while the device is open 881 * unless explicitly requested to deassert it. 882 */ 883 com_modem(sc, 1); 884 885 /* Clear the input ring, and unblock. */ 886 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 887 sc->sc_rbavail = com_rbuf_size; 888 com_iflush(sc); 889 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 890 com_hwiflow(sc); 891 892 #ifdef COM_DEBUG 893 if (com_debug) 894 comstatus(sc, "comopen "); 895 #endif 896 897 COM_UNLOCK(sc); 898 splx(s2); 899 } 900 901 splx(s); 902 903 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 904 if (error) 905 goto bad; 906 907 error = (*tp->t_linesw->l_open)(dev, tp); 908 if (error) 909 goto bad; 910 911 return (0); 912 913 bad: 914 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 915 /* 916 * We failed to open the device, and nobody else had it opened. 917 * Clean up the state as appropriate. 918 */ 919 com_shutdown(sc); 920 } 921 922 return (error); 923 } 924 925 int 926 comclose(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 929 struct tty *tp = sc->sc_tty; 930 931 /* XXX This is for cons.c. */ 932 if (!ISSET(tp->t_state, TS_ISOPEN)) 933 return (0); 934 935 (*tp->t_linesw->l_close)(tp, flag); 936 ttyclose(tp); 937 938 if (COM_ISALIVE(sc) == 0) 939 return (0); 940 941 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 942 /* 943 * Although we got a last close, the device may still be in 944 * use; e.g. if this was the dialout node, and there are still 945 * processes waiting for carrier on the non-dialout node. 946 */ 947 com_shutdown(sc); 948 } 949 950 return (0); 951 } 952 953 int 954 comread(dev_t dev, struct uio *uio, int flag) 955 { 956 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 957 struct tty *tp = sc->sc_tty; 958 959 if (COM_ISALIVE(sc) == 0) 960 return (EIO); 961 962 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 963 } 964 965 int 966 comwrite(dev_t dev, struct uio *uio, int flag) 967 { 968 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 969 struct tty *tp = sc->sc_tty; 970 971 if (COM_ISALIVE(sc) == 0) 972 return (EIO); 973 974 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 975 } 976 977 int 978 compoll(dev_t dev, int events, struct lwp *l) 979 { 980 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 981 struct tty *tp = sc->sc_tty; 982 983 if (COM_ISALIVE(sc) == 0) 984 return (POLLHUP); 985 986 return ((*tp->t_linesw->l_poll)(tp, events, l)); 987 } 988 989 struct tty * 990 comtty(dev_t dev) 991 { 992 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 993 struct tty *tp = sc->sc_tty; 994 995 return (tp); 996 } 997 998 int 999 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1000 { 1001 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 1002 struct tty *tp = sc->sc_tty; 1003 int error; 1004 int s; 1005 1006 if (COM_ISALIVE(sc) == 0) 1007 return (EIO); 1008 1009 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1010 if (error != EPASSTHROUGH) 1011 return (error); 1012 1013 error = ttioctl(tp, cmd, data, flag, l); 1014 if (error != EPASSTHROUGH) 1015 return (error); 1016 1017 error = 0; 1018 switch (cmd) { 1019 case TIOCSFLAGS: 1020 error = kauth_authorize_device_tty(l->l_cred, 1021 KAUTH_DEVICE_TTY_PRIVSET, tp); 1022 break; 1023 default: 1024 /* nothing */ 1025 break; 1026 } 1027 if (error) { 1028 return error; 1029 } 1030 1031 s = splserial(); 1032 COM_LOCK(sc); 1033 1034 switch (cmd) { 1035 case TIOCSBRK: 1036 com_break(sc, 1); 1037 break; 1038 1039 case TIOCCBRK: 1040 com_break(sc, 0); 1041 break; 1042 1043 case TIOCSDTR: 1044 com_modem(sc, 1); 1045 break; 1046 1047 case TIOCCDTR: 1048 com_modem(sc, 0); 1049 break; 1050 1051 case TIOCGFLAGS: 1052 *(int *)data = sc->sc_swflags; 1053 break; 1054 1055 case TIOCSFLAGS: 1056 sc->sc_swflags = *(int *)data; 1057 break; 1058 1059 case TIOCMSET: 1060 case TIOCMBIS: 1061 case TIOCMBIC: 1062 tiocm_to_com(sc, cmd, *(int *)data); 1063 break; 1064 1065 case TIOCMGET: 1066 *(int *)data = com_to_tiocm(sc); 1067 break; 1068 1069 #ifdef __HAVE_TIMECOUNTER 1070 case PPS_IOC_CREATE: 1071 case PPS_IOC_DESTROY: 1072 case PPS_IOC_GETPARAMS: 1073 case PPS_IOC_SETPARAMS: 1074 case PPS_IOC_GETCAP: 1075 case PPS_IOC_FETCH: 1076 #ifdef PPS_SYNC 1077 case PPS_IOC_KCBIND: 1078 #endif 1079 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1080 break; 1081 #else /* !__HAVE_TIMECOUNTER */ 1082 case PPS_IOC_CREATE: 1083 break; 1084 1085 case PPS_IOC_DESTROY: 1086 break; 1087 1088 case PPS_IOC_GETPARAMS: { 1089 pps_params_t *pp; 1090 pp = (pps_params_t *)data; 1091 *pp = sc->ppsparam; 1092 break; 1093 } 1094 1095 case PPS_IOC_SETPARAMS: { 1096 pps_params_t *pp; 1097 int mode; 1098 pp = (pps_params_t *)data; 1099 if (pp->mode & ~ppscap) { 1100 error = EINVAL; 1101 break; 1102 } 1103 sc->ppsparam = *pp; 1104 /* 1105 * Compute msr masks from user-specified timestamp state. 1106 */ 1107 mode = sc->ppsparam.mode; 1108 switch (mode & PPS_CAPTUREBOTH) { 1109 case 0: 1110 sc->sc_ppsmask = 0; 1111 break; 1112 1113 case PPS_CAPTUREASSERT: 1114 sc->sc_ppsmask = MSR_DCD; 1115 sc->sc_ppsassert = MSR_DCD; 1116 sc->sc_ppsclear = -1; 1117 break; 1118 1119 case PPS_CAPTURECLEAR: 1120 sc->sc_ppsmask = MSR_DCD; 1121 sc->sc_ppsassert = -1; 1122 sc->sc_ppsclear = 0; 1123 break; 1124 1125 case PPS_CAPTUREBOTH: 1126 sc->sc_ppsmask = MSR_DCD; 1127 sc->sc_ppsassert = MSR_DCD; 1128 sc->sc_ppsclear = 0; 1129 break; 1130 1131 default: 1132 error = EINVAL; 1133 break; 1134 } 1135 break; 1136 } 1137 1138 case PPS_IOC_GETCAP: 1139 *(int*)data = ppscap; 1140 break; 1141 1142 case PPS_IOC_FETCH: { 1143 pps_info_t *pi; 1144 pi = (pps_info_t *)data; 1145 *pi = sc->ppsinfo; 1146 break; 1147 } 1148 1149 #ifdef PPS_SYNC 1150 case PPS_IOC_KCBIND: { 1151 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1152 1153 if (edge == 0) { 1154 /* 1155 * remove binding for this source; ignore 1156 * the request if this is not the current 1157 * hardpps source 1158 */ 1159 if (pps_kc_hardpps_source == sc) { 1160 pps_kc_hardpps_source = NULL; 1161 pps_kc_hardpps_mode = 0; 1162 } 1163 } else { 1164 /* 1165 * bind hardpps to this source, replacing any 1166 * previously specified source or edges 1167 */ 1168 pps_kc_hardpps_source = sc; 1169 pps_kc_hardpps_mode = edge; 1170 } 1171 break; 1172 } 1173 #endif /* PPS_SYNC */ 1174 #endif /* !__HAVE_TIMECOUNTER */ 1175 1176 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1177 #ifdef __HAVE_TIMECOUNTER 1178 #ifndef PPS_TRAILING_EDGE 1179 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1180 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1181 #else 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1184 #endif 1185 #else /* !__HAVE_TIMECOUNTER */ 1186 /* 1187 * Some GPS clocks models use the falling rather than 1188 * rising edge as the on-the-second signal. 1189 * The old API has no way to specify PPS polarity. 1190 */ 1191 sc->sc_ppsmask = MSR_DCD; 1192 #ifndef PPS_TRAILING_EDGE 1193 sc->sc_ppsassert = MSR_DCD; 1194 sc->sc_ppsclear = -1; 1195 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1196 &sc->ppsinfo.assert_timestamp); 1197 #else 1198 sc->sc_ppsassert = -1; 1199 sc->sc_ppsclear = 0; 1200 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1201 &sc->ppsinfo.clear_timestamp); 1202 #endif 1203 #endif /* !__HAVE_TIMECOUNTER */ 1204 break; 1205 1206 default: 1207 error = EPASSTHROUGH; 1208 break; 1209 } 1210 1211 COM_UNLOCK(sc); 1212 splx(s); 1213 1214 #ifdef COM_DEBUG 1215 if (com_debug) 1216 comstatus(sc, "comioctl "); 1217 #endif 1218 1219 return (error); 1220 } 1221 1222 integrate void 1223 com_schedrx(struct com_softc *sc) 1224 { 1225 1226 sc->sc_rx_ready = 1; 1227 1228 /* Wake up the poller. */ 1229 softintr_schedule(sc->sc_si); 1230 } 1231 1232 void 1233 com_break(struct com_softc *sc, int onoff) 1234 { 1235 1236 if (onoff) 1237 SET(sc->sc_lcr, LCR_SBREAK); 1238 else 1239 CLR(sc->sc_lcr, LCR_SBREAK); 1240 1241 if (!sc->sc_heldchange) { 1242 if (sc->sc_tx_busy) { 1243 sc->sc_heldtbc = sc->sc_tbc; 1244 sc->sc_tbc = 0; 1245 sc->sc_heldchange = 1; 1246 } else 1247 com_loadchannelregs(sc); 1248 } 1249 } 1250 1251 void 1252 com_modem(struct com_softc *sc, int onoff) 1253 { 1254 1255 if (sc->sc_mcr_dtr == 0) 1256 return; 1257 1258 if (onoff) 1259 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1260 else 1261 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1262 1263 if (!sc->sc_heldchange) { 1264 if (sc->sc_tx_busy) { 1265 sc->sc_heldtbc = sc->sc_tbc; 1266 sc->sc_tbc = 0; 1267 sc->sc_heldchange = 1; 1268 } else 1269 com_loadchannelregs(sc); 1270 } 1271 } 1272 1273 void 1274 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1275 { 1276 u_char combits; 1277 1278 combits = 0; 1279 if (ISSET(ttybits, TIOCM_DTR)) 1280 SET(combits, MCR_DTR); 1281 if (ISSET(ttybits, TIOCM_RTS)) 1282 SET(combits, MCR_RTS); 1283 1284 switch (how) { 1285 case TIOCMBIC: 1286 CLR(sc->sc_mcr, combits); 1287 break; 1288 1289 case TIOCMBIS: 1290 SET(sc->sc_mcr, combits); 1291 break; 1292 1293 case TIOCMSET: 1294 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1295 SET(sc->sc_mcr, combits); 1296 break; 1297 } 1298 1299 if (!sc->sc_heldchange) { 1300 if (sc->sc_tx_busy) { 1301 sc->sc_heldtbc = sc->sc_tbc; 1302 sc->sc_tbc = 0; 1303 sc->sc_heldchange = 1; 1304 } else 1305 com_loadchannelregs(sc); 1306 } 1307 } 1308 1309 int 1310 com_to_tiocm(struct com_softc *sc) 1311 { 1312 u_char combits; 1313 int ttybits = 0; 1314 1315 combits = sc->sc_mcr; 1316 if (ISSET(combits, MCR_DTR)) 1317 SET(ttybits, TIOCM_DTR); 1318 if (ISSET(combits, MCR_RTS)) 1319 SET(ttybits, TIOCM_RTS); 1320 1321 combits = sc->sc_msr; 1322 if (ISSET(combits, MSR_DCD)) 1323 SET(ttybits, TIOCM_CD); 1324 if (ISSET(combits, MSR_CTS)) 1325 SET(ttybits, TIOCM_CTS); 1326 if (ISSET(combits, MSR_DSR)) 1327 SET(ttybits, TIOCM_DSR); 1328 if (ISSET(combits, MSR_RI | MSR_TERI)) 1329 SET(ttybits, TIOCM_RI); 1330 1331 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1332 SET(ttybits, TIOCM_LE); 1333 1334 return (ttybits); 1335 } 1336 1337 static u_char 1338 cflag2lcr(tcflag_t cflag) 1339 { 1340 u_char lcr = 0; 1341 1342 switch (ISSET(cflag, CSIZE)) { 1343 case CS5: 1344 SET(lcr, LCR_5BITS); 1345 break; 1346 case CS6: 1347 SET(lcr, LCR_6BITS); 1348 break; 1349 case CS7: 1350 SET(lcr, LCR_7BITS); 1351 break; 1352 case CS8: 1353 SET(lcr, LCR_8BITS); 1354 break; 1355 } 1356 if (ISSET(cflag, PARENB)) { 1357 SET(lcr, LCR_PENAB); 1358 if (!ISSET(cflag, PARODD)) 1359 SET(lcr, LCR_PEVEN); 1360 } 1361 if (ISSET(cflag, CSTOPB)) 1362 SET(lcr, LCR_STOPB); 1363 1364 return (lcr); 1365 } 1366 1367 int 1368 comparam(struct tty *tp, struct termios *t) 1369 { 1370 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1371 int ospeed; 1372 u_char lcr; 1373 int s; 1374 1375 if (COM_ISALIVE(sc) == 0) 1376 return (EIO); 1377 1378 #ifdef COM_HAYESP 1379 if (sc->sc_type == COM_TYPE_HAYESP) { 1380 int prescaler, speed; 1381 1382 /* 1383 * Calculate UART clock prescaler. It should be in 1384 * range of 0 .. 3. 1385 */ 1386 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1387 prescaler++, speed /= 2) 1388 if ((ospeed = comspeed(speed, sc->sc_frequency, 1389 sc->sc_type)) > 0) 1390 break; 1391 1392 if (prescaler == 4) 1393 return (EINVAL); 1394 sc->sc_prescaler = prescaler; 1395 } else 1396 #endif 1397 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1398 1399 /* Check requested parameters. */ 1400 if (ospeed < 0) 1401 return (EINVAL); 1402 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1403 return (EINVAL); 1404 1405 /* 1406 * For the console, always force CLOCAL and !HUPCL, so that the port 1407 * is always active. 1408 */ 1409 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1410 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1411 SET(t->c_cflag, CLOCAL); 1412 CLR(t->c_cflag, HUPCL); 1413 } 1414 1415 /* 1416 * If there were no changes, don't do anything. This avoids dropping 1417 * input and improves performance when all we did was frob things like 1418 * VMIN and VTIME. 1419 */ 1420 if (tp->t_ospeed == t->c_ospeed && 1421 tp->t_cflag == t->c_cflag) 1422 return (0); 1423 1424 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1425 1426 s = splserial(); 1427 COM_LOCK(sc); 1428 1429 sc->sc_lcr = lcr; 1430 1431 /* 1432 * If we're not in a mode that assumes a connection is present, then 1433 * ignore carrier changes. 1434 */ 1435 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1436 sc->sc_msr_dcd = 0; 1437 else 1438 sc->sc_msr_dcd = MSR_DCD; 1439 /* 1440 * Set the flow control pins depending on the current flow control 1441 * mode. 1442 */ 1443 if (ISSET(t->c_cflag, CRTSCTS)) { 1444 sc->sc_mcr_dtr = MCR_DTR; 1445 sc->sc_mcr_rts = MCR_RTS; 1446 sc->sc_msr_cts = MSR_CTS; 1447 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1448 } else if (ISSET(t->c_cflag, MDMBUF)) { 1449 /* 1450 * For DTR/DCD flow control, make sure we don't toggle DTR for 1451 * carrier detection. 1452 */ 1453 sc->sc_mcr_dtr = 0; 1454 sc->sc_mcr_rts = MCR_DTR; 1455 sc->sc_msr_cts = MSR_DCD; 1456 sc->sc_efr = 0; 1457 } else { 1458 /* 1459 * If no flow control, then always set RTS. This will make 1460 * the other side happy if it mistakenly thinks we're doing 1461 * RTS/CTS flow control. 1462 */ 1463 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1464 sc->sc_mcr_rts = 0; 1465 sc->sc_msr_cts = 0; 1466 sc->sc_efr = 0; 1467 if (ISSET(sc->sc_mcr, MCR_DTR)) 1468 SET(sc->sc_mcr, MCR_RTS); 1469 else 1470 CLR(sc->sc_mcr, MCR_RTS); 1471 } 1472 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1473 1474 #if 0 1475 if (ospeed == 0) 1476 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1477 else 1478 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1479 #endif 1480 1481 sc->sc_dlbl = ospeed; 1482 sc->sc_dlbh = ospeed >> 8; 1483 1484 /* 1485 * Set the FIFO threshold based on the receive speed. 1486 * 1487 * * If it's a low speed, it's probably a mouse or some other 1488 * interactive device, so set the threshold low. 1489 * * If it's a high speed, trim the trigger level down to prevent 1490 * overflows. 1491 * * Otherwise set it a bit higher. 1492 */ 1493 if (sc->sc_type == COM_TYPE_HAYESP) 1494 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1495 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1496 sc->sc_fifo = FIFO_ENABLE | 1497 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1498 else 1499 sc->sc_fifo = 0; 1500 1501 /* And copy to tty. */ 1502 tp->t_ispeed = t->c_ospeed; 1503 tp->t_ospeed = t->c_ospeed; 1504 tp->t_cflag = t->c_cflag; 1505 1506 if (!sc->sc_heldchange) { 1507 if (sc->sc_tx_busy) { 1508 sc->sc_heldtbc = sc->sc_tbc; 1509 sc->sc_tbc = 0; 1510 sc->sc_heldchange = 1; 1511 } else 1512 com_loadchannelregs(sc); 1513 } 1514 1515 if (!ISSET(t->c_cflag, CHWFLOW)) { 1516 /* Disable the high water mark. */ 1517 sc->sc_r_hiwat = 0; 1518 sc->sc_r_lowat = 0; 1519 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1520 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1521 com_schedrx(sc); 1522 } 1523 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1524 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1525 com_hwiflow(sc); 1526 } 1527 } else { 1528 sc->sc_r_hiwat = com_rbuf_hiwat; 1529 sc->sc_r_lowat = com_rbuf_lowat; 1530 } 1531 1532 COM_UNLOCK(sc); 1533 splx(s); 1534 1535 /* 1536 * Update the tty layer's idea of the carrier bit, in case we changed 1537 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1538 * explicit request. 1539 */ 1540 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1541 1542 #ifdef COM_DEBUG 1543 if (com_debug) 1544 comstatus(sc, "comparam "); 1545 #endif 1546 1547 if (!ISSET(t->c_cflag, CHWFLOW)) { 1548 if (sc->sc_tx_stopped) { 1549 sc->sc_tx_stopped = 0; 1550 comstart(tp); 1551 } 1552 } 1553 1554 return (0); 1555 } 1556 1557 void 1558 com_iflush(struct com_softc *sc) 1559 { 1560 struct com_regs *regsp = &sc->sc_regs; 1561 #ifdef DIAGNOSTIC 1562 int reg; 1563 #endif 1564 int timo; 1565 1566 #ifdef DIAGNOSTIC 1567 reg = 0xffff; 1568 #endif 1569 timo = 50000; 1570 /* flush any pending I/O */ 1571 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1572 && --timo) 1573 #ifdef DIAGNOSTIC 1574 reg = 1575 #else 1576 (void) 1577 #endif 1578 CSR_READ_1(regsp, COM_REG_RXDATA); 1579 #ifdef DIAGNOSTIC 1580 if (!timo) 1581 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1582 reg); 1583 #endif 1584 } 1585 1586 void 1587 com_loadchannelregs(struct com_softc *sc) 1588 { 1589 struct com_regs *regsp = &sc->sc_regs; 1590 1591 /* XXXXX necessary? */ 1592 com_iflush(sc); 1593 1594 if (sc->sc_type == COM_TYPE_PXA2x0) 1595 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1596 else 1597 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1598 1599 if (sc->sc_type == COM_TYPE_OMAP) { 1600 /* disable before changing settings */ 1601 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1602 } 1603 1604 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1605 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1606 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1607 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1608 } 1609 } 1610 if (sc->sc_type == COM_TYPE_AU1x00) { 1611 /* alchemy has single separate 16-bit clock divisor register */ 1612 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1613 (sc->sc_dlbh << 8)); 1614 } else { 1615 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1616 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1617 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1618 } 1619 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1620 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1621 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1622 #ifdef COM_HAYESP 1623 if (sc->sc_type == COM_TYPE_HAYESP) { 1624 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1625 HAYESP_SETPRESCALER); 1626 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1627 sc->sc_prescaler); 1628 } 1629 #endif 1630 if (sc->sc_type == COM_TYPE_OMAP) { 1631 /* setup the fifos. the FCR value is not used as long 1632 as SCR[6] and SCR[7] are 0, which they are at reset 1633 and we never touch the SCR register */ 1634 uint8_t rx_fifo_trig = 40; 1635 uint8_t tx_fifo_trig = 60; 1636 uint8_t rx_start = 8; 1637 uint8_t rx_halt = 60; 1638 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1639 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1640 1641 /* enable access to TCR & TLR */ 1642 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1643 1644 /* write tcr and tlr values */ 1645 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1646 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1647 1648 /* disable access to TCR & TLR */ 1649 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1650 1651 /* enable again, but mode is based on speed */ 1652 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1653 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1654 } else { 1655 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1656 } 1657 } 1658 1659 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1660 } 1661 1662 int 1663 comhwiflow(struct tty *tp, int block) 1664 { 1665 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1666 int s; 1667 1668 if (COM_ISALIVE(sc) == 0) 1669 return (0); 1670 1671 if (sc->sc_mcr_rts == 0) 1672 return (0); 1673 1674 s = splserial(); 1675 COM_LOCK(sc); 1676 1677 if (block) { 1678 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1679 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1680 com_hwiflow(sc); 1681 } 1682 } else { 1683 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1684 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1685 com_schedrx(sc); 1686 } 1687 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1688 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1689 com_hwiflow(sc); 1690 } 1691 } 1692 1693 COM_UNLOCK(sc); 1694 splx(s); 1695 return (1); 1696 } 1697 1698 /* 1699 * (un)block input via hw flowcontrol 1700 */ 1701 void 1702 com_hwiflow(struct com_softc *sc) 1703 { 1704 struct com_regs *regsp= &sc->sc_regs; 1705 1706 if (sc->sc_mcr_rts == 0) 1707 return; 1708 1709 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1710 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1711 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1712 } else { 1713 SET(sc->sc_mcr, sc->sc_mcr_rts); 1714 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1715 } 1716 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1717 } 1718 1719 1720 void 1721 comstart(struct tty *tp) 1722 { 1723 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1724 struct com_regs *regsp = &sc->sc_regs; 1725 int s; 1726 1727 if (COM_ISALIVE(sc) == 0) 1728 return; 1729 1730 s = spltty(); 1731 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1732 goto out; 1733 if (sc->sc_tx_stopped) 1734 goto out; 1735 1736 if (tp->t_outq.c_cc <= tp->t_lowat) { 1737 if (ISSET(tp->t_state, TS_ASLEEP)) { 1738 CLR(tp->t_state, TS_ASLEEP); 1739 wakeup(&tp->t_outq); 1740 } 1741 selwakeup(&tp->t_wsel); 1742 if (tp->t_outq.c_cc == 0) 1743 goto out; 1744 } 1745 1746 /* Grab the first contiguous region of buffer space. */ 1747 { 1748 u_char *tba; 1749 int tbc; 1750 1751 tba = tp->t_outq.c_cf; 1752 tbc = ndqb(&tp->t_outq, 0); 1753 1754 (void)splserial(); 1755 COM_LOCK(sc); 1756 1757 sc->sc_tba = tba; 1758 sc->sc_tbc = tbc; 1759 } 1760 1761 SET(tp->t_state, TS_BUSY); 1762 sc->sc_tx_busy = 1; 1763 1764 /* Enable transmit completion interrupts if necessary. */ 1765 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1766 SET(sc->sc_ier, IER_ETXRDY); 1767 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1768 } 1769 1770 /* Output the first chunk of the contiguous buffer. */ 1771 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1772 u_int n; 1773 1774 n = sc->sc_tbc; 1775 if (n > sc->sc_fifolen) 1776 n = sc->sc_fifolen; 1777 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1778 sc->sc_tbc -= n; 1779 sc->sc_tba += n; 1780 } 1781 1782 COM_UNLOCK(sc); 1783 out: 1784 splx(s); 1785 return; 1786 } 1787 1788 /* 1789 * Stop output on a line. 1790 */ 1791 void 1792 comstop(struct tty *tp, int flag) 1793 { 1794 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1795 int s; 1796 1797 s = splserial(); 1798 COM_LOCK(sc); 1799 if (ISSET(tp->t_state, TS_BUSY)) { 1800 /* Stop transmitting at the next chunk. */ 1801 sc->sc_tbc = 0; 1802 sc->sc_heldtbc = 0; 1803 if (!ISSET(tp->t_state, TS_TTSTOP)) 1804 SET(tp->t_state, TS_FLUSH); 1805 } 1806 COM_UNLOCK(sc); 1807 splx(s); 1808 } 1809 1810 void 1811 comdiag(void *arg) 1812 { 1813 struct com_softc *sc = arg; 1814 int overflows, floods; 1815 int s; 1816 1817 s = splserial(); 1818 COM_LOCK(sc); 1819 overflows = sc->sc_overflows; 1820 sc->sc_overflows = 0; 1821 floods = sc->sc_floods; 1822 sc->sc_floods = 0; 1823 sc->sc_errors = 0; 1824 COM_UNLOCK(sc); 1825 splx(s); 1826 1827 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1828 sc->sc_dev.dv_xname, 1829 overflows, overflows == 1 ? "" : "s", 1830 floods, floods == 1 ? "" : "s"); 1831 } 1832 1833 integrate void 1834 com_rxsoft(struct com_softc *sc, struct tty *tp) 1835 { 1836 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1837 u_char *get, *end; 1838 u_int cc, scc; 1839 u_char lsr; 1840 int code; 1841 int s; 1842 1843 end = sc->sc_ebuf; 1844 get = sc->sc_rbget; 1845 scc = cc = com_rbuf_size - sc->sc_rbavail; 1846 1847 if (cc == com_rbuf_size) { 1848 sc->sc_floods++; 1849 if (sc->sc_errors++ == 0) 1850 callout_reset(&sc->sc_diag_callout, 60 * hz, 1851 comdiag, sc); 1852 } 1853 1854 /* If not yet open, drop the entire buffer content here */ 1855 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1856 get += cc << 1; 1857 if (get >= end) 1858 get -= com_rbuf_size << 1; 1859 cc = 0; 1860 } 1861 while (cc) { 1862 code = get[0]; 1863 lsr = get[1]; 1864 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1865 if (ISSET(lsr, LSR_OE)) { 1866 sc->sc_overflows++; 1867 if (sc->sc_errors++ == 0) 1868 callout_reset(&sc->sc_diag_callout, 1869 60 * hz, comdiag, sc); 1870 } 1871 if (ISSET(lsr, LSR_BI | LSR_FE)) 1872 SET(code, TTY_FE); 1873 if (ISSET(lsr, LSR_PE)) 1874 SET(code, TTY_PE); 1875 } 1876 if ((*rint)(code, tp) == -1) { 1877 /* 1878 * The line discipline's buffer is out of space. 1879 */ 1880 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1881 /* 1882 * We're either not using flow control, or the 1883 * line discipline didn't tell us to block for 1884 * some reason. Either way, we have no way to 1885 * know when there's more space available, so 1886 * just drop the rest of the data. 1887 */ 1888 get += cc << 1; 1889 if (get >= end) 1890 get -= com_rbuf_size << 1; 1891 cc = 0; 1892 } else { 1893 /* 1894 * Don't schedule any more receive processing 1895 * until the line discipline tells us there's 1896 * space available (through comhwiflow()). 1897 * Leave the rest of the data in the input 1898 * buffer. 1899 */ 1900 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1901 } 1902 break; 1903 } 1904 get += 2; 1905 if (get >= end) 1906 get = sc->sc_rbuf; 1907 cc--; 1908 } 1909 1910 if (cc != scc) { 1911 sc->sc_rbget = get; 1912 s = splserial(); 1913 COM_LOCK(sc); 1914 1915 cc = sc->sc_rbavail += scc - cc; 1916 /* Buffers should be ok again, release possible block. */ 1917 if (cc >= sc->sc_r_lowat) { 1918 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1919 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1920 SET(sc->sc_ier, IER_ERXRDY); 1921 #ifdef COM_PXA2X0 1922 if (sc->sc_type == COM_TYPE_PXA2x0) 1923 SET(sc->sc_ier, IER_ERXTOUT); 1924 #endif 1925 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1926 } 1927 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1928 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1929 com_hwiflow(sc); 1930 } 1931 } 1932 COM_UNLOCK(sc); 1933 splx(s); 1934 } 1935 } 1936 1937 integrate void 1938 com_txsoft(struct com_softc *sc, struct tty *tp) 1939 { 1940 1941 CLR(tp->t_state, TS_BUSY); 1942 if (ISSET(tp->t_state, TS_FLUSH)) 1943 CLR(tp->t_state, TS_FLUSH); 1944 else 1945 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1946 (*tp->t_linesw->l_start)(tp); 1947 } 1948 1949 integrate void 1950 com_stsoft(struct com_softc *sc, struct tty *tp) 1951 { 1952 u_char msr, delta; 1953 int s; 1954 1955 s = splserial(); 1956 COM_LOCK(sc); 1957 msr = sc->sc_msr; 1958 delta = sc->sc_msr_delta; 1959 sc->sc_msr_delta = 0; 1960 COM_UNLOCK(sc); 1961 splx(s); 1962 1963 if (ISSET(delta, sc->sc_msr_dcd)) { 1964 /* 1965 * Inform the tty layer that carrier detect changed. 1966 */ 1967 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1968 } 1969 1970 if (ISSET(delta, sc->sc_msr_cts)) { 1971 /* Block or unblock output according to flow control. */ 1972 if (ISSET(msr, sc->sc_msr_cts)) { 1973 sc->sc_tx_stopped = 0; 1974 (*tp->t_linesw->l_start)(tp); 1975 } else { 1976 sc->sc_tx_stopped = 1; 1977 } 1978 } 1979 1980 #ifdef COM_DEBUG 1981 if (com_debug) 1982 comstatus(sc, "com_stsoft"); 1983 #endif 1984 } 1985 1986 void 1987 comsoft(void *arg) 1988 { 1989 struct com_softc *sc = arg; 1990 struct tty *tp; 1991 1992 if (COM_ISALIVE(sc) == 0) 1993 return; 1994 1995 tp = sc->sc_tty; 1996 1997 if (sc->sc_rx_ready) { 1998 sc->sc_rx_ready = 0; 1999 com_rxsoft(sc, tp); 2000 } 2001 2002 if (sc->sc_st_check) { 2003 sc->sc_st_check = 0; 2004 com_stsoft(sc, tp); 2005 } 2006 2007 if (sc->sc_tx_done) { 2008 sc->sc_tx_done = 0; 2009 com_txsoft(sc, tp); 2010 } 2011 } 2012 2013 int 2014 comintr(void *arg) 2015 { 2016 struct com_softc *sc = arg; 2017 struct com_regs *regsp = &sc->sc_regs; 2018 2019 u_char *put, *end; 2020 u_int cc; 2021 u_char lsr, iir; 2022 2023 if (COM_ISALIVE(sc) == 0) 2024 return (0); 2025 2026 COM_LOCK(sc); 2027 iir = CSR_READ_1(regsp, COM_REG_IIR); 2028 if (ISSET(iir, IIR_NOPEND)) { 2029 COM_UNLOCK(sc); 2030 return (0); 2031 } 2032 2033 end = sc->sc_ebuf; 2034 put = sc->sc_rbput; 2035 cc = sc->sc_rbavail; 2036 2037 again: do { 2038 u_char msr, delta; 2039 2040 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2041 if (ISSET(lsr, LSR_BI)) { 2042 int cn_trapped = 0; 2043 2044 cn_check_magic(sc->sc_tty->t_dev, 2045 CNC_BREAK, com_cnm_state); 2046 if (cn_trapped) 2047 continue; 2048 #if defined(KGDB) && !defined(DDB) 2049 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2050 kgdb_connect(1); 2051 continue; 2052 } 2053 #endif 2054 } 2055 2056 if (ISSET(lsr, LSR_RCV_MASK) && 2057 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2058 while (cc > 0) { 2059 int cn_trapped = 0; 2060 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2061 put[1] = lsr; 2062 cn_check_magic(sc->sc_tty->t_dev, 2063 put[0], com_cnm_state); 2064 if (cn_trapped) 2065 goto next; 2066 put += 2; 2067 if (put >= end) 2068 put = sc->sc_rbuf; 2069 cc--; 2070 next: 2071 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2072 if (!ISSET(lsr, LSR_RCV_MASK)) 2073 break; 2074 } 2075 2076 /* 2077 * Current string of incoming characters ended because 2078 * no more data was available or we ran out of space. 2079 * Schedule a receive event if any data was received. 2080 * If we're out of space, turn off receive interrupts. 2081 */ 2082 sc->sc_rbput = put; 2083 sc->sc_rbavail = cc; 2084 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2085 sc->sc_rx_ready = 1; 2086 2087 /* 2088 * See if we are in danger of overflowing a buffer. If 2089 * so, use hardware flow control to ease the pressure. 2090 */ 2091 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2092 cc < sc->sc_r_hiwat) { 2093 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2094 com_hwiflow(sc); 2095 } 2096 2097 /* 2098 * If we're out of space, disable receive interrupts 2099 * until the queue has drained a bit. 2100 */ 2101 if (!cc) { 2102 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2103 #ifdef COM_PXA2X0 2104 if (sc->sc_type == COM_TYPE_PXA2x0) 2105 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2106 else 2107 #endif 2108 CLR(sc->sc_ier, IER_ERXRDY); 2109 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2110 } 2111 } else { 2112 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2113 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2114 continue; 2115 } 2116 } 2117 2118 msr = CSR_READ_1(regsp, COM_REG_MSR); 2119 delta = msr ^ sc->sc_msr; 2120 sc->sc_msr = msr; 2121 #ifdef __HAVE_TIMECOUNTER 2122 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2123 (delta & MSR_DCD)) { 2124 pps_capture(&sc->sc_pps_state); 2125 pps_event(&sc->sc_pps_state, 2126 (msr & MSR_DCD) ? 2127 PPS_CAPTUREASSERT : 2128 PPS_CAPTURECLEAR); 2129 } 2130 #else /* !__HAVE_TIMECOUNTER */ 2131 /* 2132 * Pulse-per-second (PSS) signals on edge of DCD? 2133 * Process these even if line discipline is ignoring DCD. 2134 */ 2135 if (delta & sc->sc_ppsmask) { 2136 struct timeval tv; 2137 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2138 /* XXX nanotime() */ 2139 microtime(&tv); 2140 TIMEVAL_TO_TIMESPEC(&tv, 2141 &sc->ppsinfo.assert_timestamp); 2142 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2143 timespecadd(&sc->ppsinfo.assert_timestamp, 2144 &sc->ppsparam.assert_offset, 2145 &sc->ppsinfo.assert_timestamp); 2146 } 2147 2148 #ifdef PPS_SYNC 2149 if (pps_kc_hardpps_source == sc && 2150 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2151 hardpps(&tv, tv.tv_usec); 2152 } 2153 #endif 2154 sc->ppsinfo.assert_sequence++; 2155 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2156 2157 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2158 /* XXX nanotime() */ 2159 microtime(&tv); 2160 TIMEVAL_TO_TIMESPEC(&tv, 2161 &sc->ppsinfo.clear_timestamp); 2162 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2163 timespecadd(&sc->ppsinfo.clear_timestamp, 2164 &sc->ppsparam.clear_offset, 2165 &sc->ppsinfo.clear_timestamp); 2166 } 2167 2168 #ifdef PPS_SYNC 2169 if (pps_kc_hardpps_source == sc && 2170 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2171 hardpps(&tv, tv.tv_usec); 2172 } 2173 #endif 2174 sc->ppsinfo.clear_sequence++; 2175 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2176 } 2177 } 2178 #endif /* !__HAVE_TIMECOUNTER */ 2179 2180 /* 2181 * Process normal status changes 2182 */ 2183 if (ISSET(delta, sc->sc_msr_mask)) { 2184 SET(sc->sc_msr_delta, delta); 2185 2186 /* 2187 * Stop output immediately if we lose the output 2188 * flow control signal or carrier detect. 2189 */ 2190 if (ISSET(~msr, sc->sc_msr_mask)) { 2191 sc->sc_tbc = 0; 2192 sc->sc_heldtbc = 0; 2193 #ifdef COM_DEBUG 2194 if (com_debug) 2195 comstatus(sc, "comintr "); 2196 #endif 2197 } 2198 2199 sc->sc_st_check = 1; 2200 } 2201 } while (!ISSET((iir = 2202 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2203 /* 2204 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2205 * by IIR read, so we can't do this way: `process all interrupts, 2206 * then do TX if possble'. 2207 */ 2208 (iir & IIR_IMASK) != IIR_TXRDY); 2209 2210 /* 2211 * Read LSR again, since there may be an interrupt between 2212 * the last LSR read and IIR read above. 2213 */ 2214 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2215 2216 /* 2217 * See if data can be transmitted as well. 2218 * Schedule tx done event if no data left 2219 * and tty was marked busy. 2220 */ 2221 if (ISSET(lsr, LSR_TXRDY)) { 2222 /* 2223 * If we've delayed a parameter change, do it now, and restart 2224 * output. 2225 */ 2226 if (sc->sc_heldchange) { 2227 com_loadchannelregs(sc); 2228 sc->sc_heldchange = 0; 2229 sc->sc_tbc = sc->sc_heldtbc; 2230 sc->sc_heldtbc = 0; 2231 } 2232 2233 /* Output the next chunk of the contiguous buffer, if any. */ 2234 if (sc->sc_tbc > 0) { 2235 u_int n; 2236 2237 n = sc->sc_tbc; 2238 if (n > sc->sc_fifolen) 2239 n = sc->sc_fifolen; 2240 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2241 sc->sc_tbc -= n; 2242 sc->sc_tba += n; 2243 } else { 2244 /* Disable transmit completion interrupts if necessary. */ 2245 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2246 CLR(sc->sc_ier, IER_ETXRDY); 2247 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2248 } 2249 if (sc->sc_tx_busy) { 2250 sc->sc_tx_busy = 0; 2251 sc->sc_tx_done = 1; 2252 } 2253 } 2254 } 2255 2256 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2257 goto again; 2258 2259 COM_UNLOCK(sc); 2260 2261 /* Wake up the poller. */ 2262 softintr_schedule(sc->sc_si); 2263 2264 #if NRND > 0 && defined(RND_COM) 2265 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2266 #endif 2267 2268 return (1); 2269 } 2270 2271 /* 2272 * The following functions are polled getc and putc routines, shared 2273 * by the console and kgdb glue. 2274 * 2275 * The read-ahead code is so that you can detect pending in-band 2276 * cn_magic in polled mode while doing output rather than having to 2277 * wait until the kernel decides it needs input. 2278 */ 2279 2280 #define MAX_READAHEAD 20 2281 static int com_readahead[MAX_READAHEAD]; 2282 static int com_readaheadcount = 0; 2283 2284 int 2285 com_common_getc(dev_t dev, struct com_regs *regsp) 2286 { 2287 int s = splserial(); 2288 u_char stat, c; 2289 2290 /* got a character from reading things earlier */ 2291 if (com_readaheadcount > 0) { 2292 int i; 2293 2294 c = com_readahead[0]; 2295 for (i = 1; i < com_readaheadcount; i++) { 2296 com_readahead[i-1] = com_readahead[i]; 2297 } 2298 com_readaheadcount--; 2299 splx(s); 2300 return (c); 2301 } 2302 2303 /* block until a character becomes available */ 2304 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2305 ; 2306 2307 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2308 stat = CSR_READ_1(regsp, COM_REG_IIR); 2309 { 2310 int cn_trapped = 0; /* unused */ 2311 #ifdef DDB 2312 extern int db_active; 2313 if (!db_active) 2314 #endif 2315 cn_check_magic(dev, c, com_cnm_state); 2316 } 2317 splx(s); 2318 return (c); 2319 } 2320 2321 void 2322 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2323 { 2324 int s = splserial(); 2325 int cin, stat, timo; 2326 2327 if (com_readaheadcount < MAX_READAHEAD 2328 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2329 int cn_trapped = 0; 2330 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2331 stat = CSR_READ_1(regsp, COM_REG_IIR); 2332 cn_check_magic(dev, cin, com_cnm_state); 2333 com_readahead[com_readaheadcount++] = cin; 2334 } 2335 2336 /* wait for any pending transmission to finish */ 2337 timo = 150000; 2338 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2339 continue; 2340 2341 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2342 COM_BARRIER(regsp, BR | BW); 2343 2344 splx(s); 2345 } 2346 2347 /* 2348 * Initialize UART for use as console or KGDB line. 2349 */ 2350 int 2351 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2352 tcflag_t cflag) 2353 { 2354 2355 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2356 ®sp->cr_ioh)) 2357 return (ENOMEM); /* ??? */ 2358 2359 if (type == COM_TYPE_OMAP) { 2360 /* disable before changing settings */ 2361 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2362 } 2363 2364 rate = comspeed(rate, frequency, type); 2365 if (type != COM_TYPE_AU1x00) { 2366 /* no EFR on alchemy */ 2367 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2368 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2369 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2370 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2371 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2372 } else { 2373 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2374 } 2375 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2376 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2377 CSR_WRITE_1(regsp, COM_REG_FIFO, 2378 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2379 2380 if (type == COM_TYPE_OMAP) { 2381 /* setup the fifos. the FCR value is not used as long 2382 as SCR[6] and SCR[7] are 0, which they are at reset 2383 and we never touch the SCR register */ 2384 uint8_t rx_fifo_trig = 40; 2385 uint8_t tx_fifo_trig = 60; 2386 uint8_t rx_start = 8; 2387 uint8_t rx_halt = 60; 2388 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2389 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2390 2391 /* enable access to TCR & TLR */ 2392 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2393 2394 /* write tcr and tlr values */ 2395 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2396 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2397 2398 /* disable access to TCR & TLR */ 2399 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2400 2401 /* enable again, but mode is based on speed */ 2402 if (rate > 230400) { 2403 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2404 } else { 2405 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2406 } 2407 } 2408 2409 #ifdef COM_PXA2X0 2410 if (type == COM_TYPE_PXA2x0) 2411 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2412 else 2413 #endif 2414 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2415 2416 return (0); 2417 } 2418 2419 /* 2420 * Following are all routines needed for COM to act as console 2421 */ 2422 struct consdev comcons = { 2423 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2424 NODEV, CN_NORMAL 2425 }; 2426 2427 2428 int 2429 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2430 tcflag_t cflag) 2431 { 2432 int res; 2433 2434 comconsregs = *regsp; 2435 2436 res = cominit(&comconsregs, rate, frequency, type, cflag); 2437 if (res) 2438 return (res); 2439 2440 cn_tab = &comcons; 2441 cn_init_magic(&com_cnm_state); 2442 cn_set_magic("\047\001"); /* default magic is BREAK */ 2443 2444 comconsrate = rate; 2445 comconscflag = cflag; 2446 2447 return (0); 2448 } 2449 2450 int 2451 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2452 int type, tcflag_t cflag) 2453 { 2454 struct com_regs regs; 2455 2456 memset(®s, 0, sizeof regs); 2457 regs.cr_iot = iot; 2458 regs.cr_iobase = iobase; 2459 regs.cr_nports = COM_NPORTS; 2460 #ifdef COM_REGMAP 2461 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2462 #endif 2463 2464 return comcnattach1(®s, rate, frequency, type, cflag); 2465 } 2466 2467 int 2468 comcngetc(dev_t dev) 2469 { 2470 2471 return (com_common_getc(dev, &comconsregs)); 2472 } 2473 2474 /* 2475 * Console kernel output character routine. 2476 */ 2477 void 2478 comcnputc(dev_t dev, int c) 2479 { 2480 2481 com_common_putc(dev, &comconsregs, c); 2482 } 2483 2484 void 2485 comcnpollc(dev_t dev, int on) 2486 { 2487 2488 } 2489 2490 #ifdef KGDB 2491 int 2492 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2493 tcflag_t cflag) 2494 { 2495 int res; 2496 2497 if (regsp->cr_iot == comconsregs.cr_iot && 2498 regsp->cr_iobase == comconsregs.cr_iobase) { 2499 #if !defined(DDB) 2500 return (EBUSY); /* cannot share with console */ 2501 #else 2502 comkgdbregs = *regsp; 2503 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2504 #endif 2505 } else { 2506 comkgdbregs = *regsp; 2507 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2508 if (res) 2509 return (res); 2510 2511 /* 2512 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2513 * expects this to be initialized 2514 */ 2515 cn_init_magic(&com_cnm_state); 2516 cn_set_magic("\047\001"); 2517 } 2518 2519 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2520 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2521 2522 return (0); 2523 } 2524 2525 int 2526 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2527 int frequency, int type, tcflag_t cflag) 2528 { 2529 struct com_regs regs; 2530 2531 regs.cr_iot = iot; 2532 regs.cr_nports = COM_NPORTS; 2533 regs.cr_iobase = iobase; 2534 #ifdef COM_REGMAP 2535 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2536 #endif 2537 2538 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2539 } 2540 2541 /* ARGSUSED */ 2542 int 2543 com_kgdb_getc(void *arg) 2544 { 2545 2546 return (com_common_getc(NODEV, &comkgdbregs)); 2547 } 2548 2549 /* ARGSUSED */ 2550 void 2551 com_kgdb_putc(void *arg, int c) 2552 { 2553 2554 com_common_putc(NODEV, &comkgdbregs, c); 2555 } 2556 #endif /* KGDB */ 2557 2558 /* helper function to identify the com ports used by 2559 console or KGDB (and not yet autoconf attached) */ 2560 int 2561 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2562 { 2563 bus_space_handle_t help; 2564 2565 if (!comconsattached && 2566 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2567 help = comconsregs.cr_ioh; 2568 #ifdef KGDB 2569 else if (!com_kgdb_attached && 2570 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2571 help = comkgdbregs.cr_ioh; 2572 #endif 2573 else 2574 return (0); 2575 2576 if (ioh) 2577 *ioh = help; 2578 return (1); 2579 } 2580 2581 /* 2582 * this routine exists to serve as a shutdown hook for systems that 2583 * have firmware which doesn't interact properly with a com device in 2584 * FIFO mode. 2585 */ 2586 void 2587 com_cleanup(void *arg) 2588 { 2589 struct com_softc *sc = arg; 2590 2591 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2592 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2593 } 2594 2595 void 2596 com_power(int why, void *arg) 2597 { 2598 struct com_softc *sc = arg; 2599 int s; 2600 2601 s = splserial(); 2602 switch (why) { 2603 case PWR_SUSPEND: 2604 case PWR_STANDBY: 2605 /* XXX should we do something to stop the device? */ 2606 break; 2607 case PWR_RESUME: 2608 com_loadchannelregs(sc); 2609 break; 2610 case PWR_SOFTSUSPEND: 2611 case PWR_SOFTSTANDBY: 2612 case PWR_SOFTRESUME: 2613 break; 2614 } 2615 splx(s); 2616 } 2617
Indexes created Mon Oct 20 01:09:56 GMT 2025