com.c revision 1.262.2.2
1 /* $NetBSD: com.c,v 1.262.2.2 2007/11/06 23:26:29 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.262.2.2 2007/11/06 23:26:29 matt Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 integrate void com_rxsoft(struct com_softc *, struct tty *); 195 integrate void com_txsoft(struct com_softc *, struct tty *); 196 integrate void com_stsoft(struct com_softc *, struct tty *); 197 integrate void com_schedrx(struct com_softc *); 198 void comdiag(void *); 199 200 extern struct cfdriver com_cd; 201 202 dev_type_open(comopen); 203 dev_type_close(comclose); 204 dev_type_read(comread); 205 dev_type_write(comwrite); 206 dev_type_ioctl(comioctl); 207 dev_type_stop(comstop); 208 dev_type_tty(comtty); 209 dev_type_poll(compoll); 210 211 const struct cdevsw com_cdevsw = { 212 comopen, comclose, comread, comwrite, comioctl, 213 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 214 }; 215 216 /* 217 * Make this an option variable one can patch. 218 * But be warned: this must be a power of 2! 219 */ 220 u_int com_rbuf_size = COM_RING_SIZE; 221 222 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 223 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 224 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 225 226 static struct com_regs comconsregs; 227 static int comconsattached; 228 static int comconsrate; 229 static tcflag_t comconscflag; 230 static struct cnm_state com_cnm_state; 231 232 #ifndef __HAVE_TIMECOUNTER 233 static int ppscap = 234 PPS_TSFMT_TSPEC | 235 PPS_CAPTUREASSERT | 236 PPS_CAPTURECLEAR | 237 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 238 #endif /* !__HAVE_TIMECOUNTER */ 239 240 #ifdef KGDB 241 #include <sys/kgdb.h> 242 243 static struct com_regs comkgdbregs; 244 static int com_kgdb_attached; 245 246 int com_kgdb_getc(void *); 247 void com_kgdb_putc(void *, int); 248 #endif /* KGDB */ 249 250 #ifdef COM_REGMAP 251 /* initializer for typical 16550-ish hardware */ 252 #define COM_REG_16550 { \ 253 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 254 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 255 256 const bus_size_t com_std_map[16] = COM_REG_16550; 257 #endif /* COM_REGMAP */ 258 259 #define COMUNIT_MASK 0x7ffff 260 #define COMDIALOUT_MASK 0x80000 261 262 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 263 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 264 265 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 266 device_is_active(&(sc)->sc_dev)) 267 268 #define BR BUS_SPACE_BARRIER_READ 269 #define BW BUS_SPACE_BARRIER_WRITE 270 #define COM_BARRIER(r, f) \ 271 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 272 273 /*ARGSUSED*/ 274 int 275 comspeed(long speed, long frequency, int type) 276 { 277 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 278 279 int x, err; 280 int divisor = 16; 281 282 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 283 divisor = 13; 284 } 285 286 #if 0 287 if (speed == 0) 288 return (0); 289 #endif 290 if (speed <= 0) 291 return (-1); 292 x = divrnd(frequency / divisor, speed); 293 if (x <= 0) 294 return (-1); 295 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 296 if (err < 0) 297 err = -err; 298 if (err > COM_TOLERANCE) 299 return (-1); 300 return (x); 301 302 #undef divrnd 303 } 304 305 #ifdef COM_DEBUG 306 int com_debug = 0; 307 308 void comstatus(struct com_softc *, const char *); 309 void 310 comstatus(struct com_softc *sc, const char *str) 311 { 312 struct tty *tp = sc->sc_tty; 313 314 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 315 sc->sc_dev.dv_xname, str, 316 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 317 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 318 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 319 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 320 sc->sc_tx_stopped ? '+' : '-'); 321 322 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 323 sc->sc_dev.dv_xname, str, 324 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 325 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 326 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 327 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 328 sc->sc_rx_flags); 329 } 330 #endif 331 332 int 333 com_probe_subr(struct com_regs *regs) 334 { 335 336 /* force access to id reg */ 337 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 338 CSR_WRITE_1(regs, COM_REG_IIR, 0); 339 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 340 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 341 return (0); 342 343 return (1); 344 } 345 346 int 347 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 348 { 349 struct com_regs regs; 350 351 regs.cr_iot = iot; 352 regs.cr_ioh = ioh; 353 #ifdef COM_REGMAP 354 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 355 #endif 356 357 return com_probe_subr(®s); 358 } 359 360 /* 361 * No locking in this routine; it is only called during attach, 362 * or with the port already locked. 363 */ 364 static void 365 com_enable_debugport(struct com_softc *sc) 366 { 367 368 /* Turn on line break interrupt, set carrier. */ 369 sc->sc_ier = IER_ERXRDY; 370 if (sc->sc_type == COM_TYPE_PXA2x0) 371 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 372 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 373 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 374 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 375 } 376 377 void 378 com_attach_subr(struct com_softc *sc) 379 { 380 struct com_regs *regsp = &sc->sc_regs; 381 struct tty *tp; 382 #ifdef COM_16650 383 u_int8_t lcr; 384 #endif 385 const char *fifo_msg = NULL; 386 387 aprint_naive("\n"); 388 389 callout_init(&sc->sc_diag_callout, 0); 390 mutex_init(&sc->sc_lock, MUTEX_SPIN, IPL_SERIAL); 391 392 /* Disable interrupts before configuring the device. */ 393 if (sc->sc_type == COM_TYPE_PXA2x0) 394 sc->sc_ier = IER_EUART; 395 else 396 sc->sc_ier = 0; 397 398 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 399 400 if (regsp->cr_iot == comconsregs.cr_iot && 401 regsp->cr_iobase == comconsregs.cr_iobase) { 402 comconsattached = 1; 403 404 /* Make sure the console is always "hardwired". */ 405 delay(10000); /* wait for output to finish */ 406 SET(sc->sc_hwflags, COM_HW_CONSOLE); 407 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 408 } 409 410 /* Probe for FIFO */ 411 switch (sc->sc_type) { 412 case COM_TYPE_HAYESP: 413 goto fifodone; 414 415 case COM_TYPE_AU1x00: 416 sc->sc_fifolen = 16; 417 fifo_msg = "Au1X00 UART, working fifo"; 418 SET(sc->sc_hwflags, COM_HW_FIFO); 419 goto fifodelay; 420 421 case COM_TYPE_OMAP: 422 sc->sc_fifolen = 64; 423 fifo_msg = "OMAP UART, working fifo"; 424 SET(sc->sc_hwflags, COM_HW_FIFO); 425 goto fifodelay; 426 } 427 428 sc->sc_fifolen = 1; 429 /* look for a NS 16550AF UART with FIFOs */ 430 CSR_WRITE_1(regsp, COM_REG_FIFO, 431 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 432 delay(100); 433 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 434 == IIR_FIFO_MASK) 435 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 436 == FIFO_TRIGGER_14) { 437 SET(sc->sc_hwflags, COM_HW_FIFO); 438 439 #ifdef COM_16650 440 /* 441 * IIR changes into the EFR if LCR is set to LCR_EERS 442 * on 16650s. We also know IIR != 0 at this point. 443 * Write 0 into the EFR, and read it. If the result 444 * is 0, we have a 16650. 445 * 446 * Older 16650s were broken; the test to detect them 447 * is taken from the Linux driver. Apparently 448 * setting DLAB enable gives access to the EFR on 449 * these chips. 450 */ 451 lcr = CSR_READ_1(regsp, COM_REG_LCR); 452 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 453 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 454 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 455 CSR_WRITE_1(regsp, COM_REG_LCR, 456 lcr | LCR_DLAB); 457 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 458 CLR(sc->sc_hwflags, COM_HW_FIFO); 459 sc->sc_fifolen = 0; 460 } else { 461 SET(sc->sc_hwflags, COM_HW_FLOW); 462 sc->sc_fifolen = 32; 463 } 464 } else 465 #endif 466 sc->sc_fifolen = 16; 467 468 #ifdef COM_16650 469 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 470 if (sc->sc_fifolen == 0) 471 fifo_msg = "st16650, broken fifo"; 472 else if (sc->sc_fifolen == 32) 473 fifo_msg = "st16650a, working fifo"; 474 else 475 #endif 476 fifo_msg = "ns16550a, working fifo"; 477 } else 478 fifo_msg = "ns16550, broken fifo"; 479 else 480 fifo_msg = "ns8250 or ns16450, no fifo"; 481 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 482 fifodelay: 483 /* 484 * Some chips will clear down both Tx and Rx FIFOs when zero is 485 * written to com_fifo. If this chip is the console, writing zero 486 * results in some of the chip/FIFO description being lost, so delay 487 * printing it until now. 488 */ 489 delay(10); 490 aprint_normal(": %s\n", fifo_msg); 491 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 492 sc->sc_fifolen = 1; 493 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 494 } 495 496 fifodone: 497 498 tp = ttymalloc(); 499 tp->t_oproc = comstart; 500 tp->t_param = comparam; 501 tp->t_hwiflow = comhwiflow; 502 503 sc->sc_tty = tp; 504 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 505 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 506 sc->sc_rbavail = com_rbuf_size; 507 if (sc->sc_rbuf == NULL) { 508 aprint_error("%s: unable to allocate ring buffer\n", 509 sc->sc_dev.dv_xname); 510 return; 511 } 512 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 513 514 tty_attach(tp); 515 516 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 517 SET(sc->sc_mcr, MCR_IENABLE); 518 519 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 520 int maj; 521 522 /* locate the major number */ 523 maj = cdevsw_lookup_major(&com_cdevsw); 524 525 tp->t_dev = cn_tab->cn_dev = makedev(maj, 526 device_unit(&sc->sc_dev)); 527 528 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 529 } 530 531 #ifdef KGDB 532 /* 533 * Allow kgdb to "take over" this port. If this is 534 * not the console and is the kgdb device, it has 535 * exclusive use. If it's the console _and_ the 536 * kgdb device, it doesn't. 537 */ 538 if (regsp->cr_iot == comkgdbregs.cr_iot && 539 regsp->cr_iobase == comkgdbregs.cr_iobase) { 540 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 541 com_kgdb_attached = 1; 542 543 SET(sc->sc_hwflags, COM_HW_KGDB); 544 } 545 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 546 } 547 #endif 548 549 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 550 551 #if NRND > 0 && defined(RND_COM) 552 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 553 RND_TYPE_TTY, 0); 554 #endif 555 556 /* if there are no enable/disable functions, assume the device 557 is always enabled */ 558 if (!sc->enable) 559 sc->enabled = 1; 560 561 com_config(sc); 562 563 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 564 com_power, sc); 565 if (sc->sc_powerhook == NULL) 566 aprint_error("%s: WARNING: unable to establish power hook\n", 567 sc->sc_dev.dv_xname); 568 569 SET(sc->sc_hwflags, COM_HW_DEV_OK); 570 } 571 572 void 573 com_config(struct com_softc *sc) 574 { 575 struct com_regs *regsp = &sc->sc_regs; 576 577 /* Disable interrupts before configuring the device. */ 578 if (sc->sc_type == COM_TYPE_PXA2x0) 579 sc->sc_ier = IER_EUART; 580 else 581 sc->sc_ier = 0; 582 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 583 (void) CSR_READ_1(regsp, COM_REG_IIR); 584 585 #ifdef COM_HAYESP 586 /* Look for a Hayes ESP board. */ 587 if (sc->sc_type == COM_TYPE_HAYESP) { 588 589 /* Set 16550 compatibility mode */ 590 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 591 HAYESP_SETMODE); 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 593 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 594 HAYESP_MODE_SCALE); 595 596 /* Set RTS/CTS flow control */ 597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 598 HAYESP_SETFLOWTYPE); 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 600 HAYESP_FLOW_RTS); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_FLOW_CTS); 603 604 /* Set flow control levels */ 605 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 606 HAYESP_SETRXFLOW); 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 608 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 613 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 614 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 615 } 616 #endif 617 618 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 619 com_enable_debugport(sc); 620 } 621 622 int 623 com_detach(struct device *self, int flags) 624 { 625 struct com_softc *sc = (struct com_softc *)self; 626 int maj, mn; 627 628 /* kill the power hook */ 629 if (sc->sc_powerhook != NULL) 630 powerhook_disestablish(sc->sc_powerhook); 631 632 /* locate the major number */ 633 maj = cdevsw_lookup_major(&com_cdevsw); 634 635 /* Nuke the vnodes for any open instances. */ 636 mn = device_unit(self); 637 vdevgone(maj, mn, mn, VCHR); 638 639 mn |= COMDIALOUT_MASK; 640 vdevgone(maj, mn, mn, VCHR); 641 642 if (sc->sc_rbuf == NULL) { 643 /* 644 * Ring buffer allocation failed in the com_attach_subr, 645 * only the tty is allocated, and nothing else. 646 */ 647 ttyfree(sc->sc_tty); 648 return 0; 649 } 650 651 /* Free the receive buffer. */ 652 free(sc->sc_rbuf, M_DEVBUF); 653 654 /* Detach and free the tty. */ 655 tty_detach(sc->sc_tty); 656 ttyfree(sc->sc_tty); 657 658 /* Unhook the soft interrupt handler. */ 659 softint_disestablish(sc->sc_si); 660 661 #if NRND > 0 && defined(RND_COM) 662 /* Unhook the entropy source. */ 663 rnd_detach_source(&sc->rnd_source); 664 #endif 665 666 return (0); 667 } 668 669 int 670 com_activate(struct device *self, enum devact act) 671 { 672 struct com_softc *sc = (struct com_softc *)self; 673 int rv = 0; 674 675 mutex_spin_enter(&sc->sc_lock); 676 switch (act) { 677 case DVACT_ACTIVATE: 678 rv = EOPNOTSUPP; 679 break; 680 681 case DVACT_DEACTIVATE: 682 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 683 rv = EBUSY; 684 break; 685 } 686 687 if (sc->disable != NULL && sc->enabled != 0) { 688 (*sc->disable)(sc); 689 sc->enabled = 0; 690 } 691 break; 692 } 693 694 if (sc->sc_type == COM_TYPE_OMAP) { 695 /* enable but mode is based on speed */ 696 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 697 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_13X); 698 } else { 699 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_16X); 700 } 701 } 702 mutex_spin_exit(&sc->sc_lock); 703 return (rv); 704 } 705 706 void 707 com_shutdown(struct com_softc *sc) 708 { 709 struct tty *tp = sc->sc_tty; 710 711 mutex_spin_enter(&sc->sc_lock); 712 713 /* If we were asserting flow control, then deassert it. */ 714 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 715 com_hwiflow(sc); 716 717 /* Clear any break condition set with TIOCSBRK. */ 718 com_break(sc, 0); 719 720 #ifndef __HAVE_TIMECOUNTER 721 /* Turn off PPS capture on last close. */ 722 sc->sc_ppsmask = 0; 723 sc->ppsparam.mode = 0; 724 #endif /* !__HAVE_TIMECOUNTER */ 725 726 /* 727 * Hang up if necessary. Wait a bit, so the other side has time to 728 * notice even if we immediately open the port again. 729 * Avoid tsleeping above splhigh(). 730 */ 731 if (ISSET(tp->t_cflag, HUPCL)) { 732 com_modem(sc, 0); 733 mutex_spin_exit(&sc->sc_lock); 734 /* XXX will only timeout */ 735 (void) kpause(ttclos, false, hz, NULL); 736 mutex_spin_enter(&sc->sc_lock); 737 } 738 739 /* Turn off interrupts. */ 740 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 741 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 742 if (sc->sc_type == COM_TYPE_PXA2x0) 743 sc->sc_ier |= IER_ERXTOUT; 744 } else 745 sc->sc_ier = 0; 746 747 if (sc->sc_type == COM_TYPE_PXA2x0) 748 sc->sc_ier |= IER_EUART; 749 750 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 751 752 if (sc->disable) { 753 #ifdef DIAGNOSTIC 754 if (!sc->enabled) 755 panic("com_shutdown: not enabled?"); 756 #endif 757 (*sc->disable)(sc); 758 sc->enabled = 0; 759 } 760 mutex_spin_exit(&sc->sc_lock); 761 } 762 763 int 764 comopen(dev_t dev, int flag, int mode, struct lwp *l) 765 { 766 struct com_softc *sc; 767 struct tty *tp; 768 int s; 769 int error; 770 771 sc = device_lookup(&com_cd, COMUNIT(dev)); 772 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 773 sc->sc_rbuf == NULL) 774 return (ENXIO); 775 776 if (!device_is_active(&sc->sc_dev)) 777 return (ENXIO); 778 779 #ifdef KGDB 780 /* 781 * If this is the kgdb port, no other use is permitted. 782 */ 783 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 784 return (EBUSY); 785 #endif 786 787 tp = sc->sc_tty; 788 789 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 790 return (EBUSY); 791 792 s = spltty(); 793 794 /* 795 * Do the following iff this is a first open. 796 */ 797 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 798 struct termios t; 799 800 tp->t_dev = dev; 801 802 mutex_spin_enter(&sc->sc_lock); 803 804 if (sc->enable) { 805 if ((*sc->enable)(sc)) { 806 mutex_spin_exit(&sc->sc_lock); 807 splx(s); 808 printf("%s: device enable failed\n", 809 sc->sc_dev.dv_xname); 810 return (EIO); 811 } 812 sc->enabled = 1; 813 com_config(sc); 814 } 815 816 /* Turn on interrupts. */ 817 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 818 if (sc->sc_type == COM_TYPE_PXA2x0) 819 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 820 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 821 822 /* Fetch the current modem control status, needed later. */ 823 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 824 825 /* Clear PPS capture state on first open. */ 826 #ifdef __HAVE_TIMECOUNTER 827 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 828 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 829 pps_init(&sc->sc_pps_state); 830 #else /* !__HAVE_TIMECOUNTER */ 831 sc->sc_ppsmask = 0; 832 sc->ppsparam.mode = 0; 833 #endif /* !__HAVE_TIMECOUNTER */ 834 835 mutex_spin_exit(&sc->sc_lock); 836 837 /* 838 * Initialize the termios status to the defaults. Add in the 839 * sticky bits from TIOCSFLAGS. 840 */ 841 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 842 t.c_ospeed = comconsrate; 843 t.c_cflag = comconscflag; 844 } else { 845 t.c_ospeed = TTYDEF_SPEED; 846 t.c_cflag = TTYDEF_CFLAG; 847 } 848 t.c_ispeed = t.c_ospeed; 849 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 850 SET(t.c_cflag, CLOCAL); 851 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 852 SET(t.c_cflag, CRTSCTS); 853 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 854 SET(t.c_cflag, MDMBUF); 855 /* Make sure comparam() will do something. */ 856 tp->t_ospeed = 0; 857 (void) comparam(tp, &t); 858 tp->t_iflag = TTYDEF_IFLAG; 859 tp->t_oflag = TTYDEF_OFLAG; 860 tp->t_lflag = TTYDEF_LFLAG; 861 ttychars(tp); 862 ttsetwater(tp); 863 864 mutex_spin_enter(&sc->sc_lock); 865 866 /* 867 * Turn on DTR. We must always do this, even if carrier is not 868 * present, because otherwise we'd have to use TIOCSDTR 869 * immediately after setting CLOCAL, which applications do not 870 * expect. We always assert DTR while the device is open 871 * unless explicitly requested to deassert it. 872 */ 873 com_modem(sc, 1); 874 875 /* Clear the input ring, and unblock. */ 876 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 877 sc->sc_rbavail = com_rbuf_size; 878 com_iflush(sc); 879 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 880 com_hwiflow(sc); 881 882 #ifdef COM_DEBUG 883 if (com_debug) 884 comstatus(sc, "comopen "); 885 #endif 886 887 mutex_spin_exit(&sc->sc_lock); 888 } 889 890 splx(s); 891 892 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 893 if (error) 894 goto bad; 895 896 error = (*tp->t_linesw->l_open)(dev, tp); 897 if (error) 898 goto bad; 899 900 return (0); 901 902 bad: 903 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 904 /* 905 * We failed to open the device, and nobody else had it opened. 906 * Clean up the state as appropriate. 907 */ 908 com_shutdown(sc); 909 } 910 911 return (error); 912 } 913 914 int 915 comclose(dev_t dev, int flag, int mode, struct lwp *l) 916 { 917 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 918 struct tty *tp = sc->sc_tty; 919 920 /* XXX This is for cons.c. */ 921 if (!ISSET(tp->t_state, TS_ISOPEN)) 922 return (0); 923 924 (*tp->t_linesw->l_close)(tp, flag); 925 ttyclose(tp); 926 927 if (COM_ISALIVE(sc) == 0) 928 return (0); 929 930 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 931 /* 932 * Although we got a last close, the device may still be in 933 * use; e.g. if this was the dialout node, and there are still 934 * processes waiting for carrier on the non-dialout node. 935 */ 936 com_shutdown(sc); 937 } 938 939 return (0); 940 } 941 942 int 943 comread(dev_t dev, struct uio *uio, int flag) 944 { 945 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 946 struct tty *tp = sc->sc_tty; 947 948 if (COM_ISALIVE(sc) == 0) 949 return (EIO); 950 951 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 952 } 953 954 int 955 comwrite(dev_t dev, struct uio *uio, int flag) 956 { 957 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 958 struct tty *tp = sc->sc_tty; 959 960 if (COM_ISALIVE(sc) == 0) 961 return (EIO); 962 963 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 964 } 965 966 int 967 compoll(dev_t dev, int events, struct lwp *l) 968 { 969 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 970 struct tty *tp = sc->sc_tty; 971 972 if (COM_ISALIVE(sc) == 0) 973 return (POLLHUP); 974 975 return ((*tp->t_linesw->l_poll)(tp, events, l)); 976 } 977 978 struct tty * 979 comtty(dev_t dev) 980 { 981 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 982 struct tty *tp = sc->sc_tty; 983 984 return (tp); 985 } 986 987 int 988 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 989 { 990 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 991 struct tty *tp = sc->sc_tty; 992 int error; 993 994 if (COM_ISALIVE(sc) == 0) 995 return (EIO); 996 997 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 998 if (error != EPASSTHROUGH) 999 return (error); 1000 1001 error = ttioctl(tp, cmd, data, flag, l); 1002 if (error != EPASSTHROUGH) 1003 return (error); 1004 1005 error = 0; 1006 switch (cmd) { 1007 case TIOCSFLAGS: 1008 error = kauth_authorize_device_tty(l->l_cred, 1009 KAUTH_DEVICE_TTY_PRIVSET, tp); 1010 break; 1011 default: 1012 /* nothing */ 1013 break; 1014 } 1015 if (error) { 1016 return error; 1017 } 1018 1019 mutex_spin_enter(&sc->sc_lock); 1020 1021 switch (cmd) { 1022 case TIOCSBRK: 1023 com_break(sc, 1); 1024 break; 1025 1026 case TIOCCBRK: 1027 com_break(sc, 0); 1028 break; 1029 1030 case TIOCSDTR: 1031 com_modem(sc, 1); 1032 break; 1033 1034 case TIOCCDTR: 1035 com_modem(sc, 0); 1036 break; 1037 1038 case TIOCGFLAGS: 1039 *(int *)data = sc->sc_swflags; 1040 break; 1041 1042 case TIOCSFLAGS: 1043 sc->sc_swflags = *(int *)data; 1044 break; 1045 1046 case TIOCMSET: 1047 case TIOCMBIS: 1048 case TIOCMBIC: 1049 tiocm_to_com(sc, cmd, *(int *)data); 1050 break; 1051 1052 case TIOCMGET: 1053 *(int *)data = com_to_tiocm(sc); 1054 break; 1055 1056 #ifdef __HAVE_TIMECOUNTER 1057 case PPS_IOC_CREATE: 1058 case PPS_IOC_DESTROY: 1059 case PPS_IOC_GETPARAMS: 1060 case PPS_IOC_SETPARAMS: 1061 case PPS_IOC_GETCAP: 1062 case PPS_IOC_FETCH: 1063 #ifdef PPS_SYNC 1064 case PPS_IOC_KCBIND: 1065 #endif 1066 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1067 break; 1068 #else /* !__HAVE_TIMECOUNTER */ 1069 case PPS_IOC_CREATE: 1070 break; 1071 1072 case PPS_IOC_DESTROY: 1073 break; 1074 1075 case PPS_IOC_GETPARAMS: { 1076 pps_params_t *pp; 1077 pp = (pps_params_t *)data; 1078 *pp = sc->ppsparam; 1079 break; 1080 } 1081 1082 case PPS_IOC_SETPARAMS: { 1083 pps_params_t *pp; 1084 int mode; 1085 pp = (pps_params_t *)data; 1086 if (pp->mode & ~ppscap) { 1087 error = EINVAL; 1088 break; 1089 } 1090 sc->ppsparam = *pp; 1091 /* 1092 * Compute msr masks from user-specified timestamp state. 1093 */ 1094 mode = sc->ppsparam.mode; 1095 switch (mode & PPS_CAPTUREBOTH) { 1096 case 0: 1097 sc->sc_ppsmask = 0; 1098 break; 1099 1100 case PPS_CAPTUREASSERT: 1101 sc->sc_ppsmask = MSR_DCD; 1102 sc->sc_ppsassert = MSR_DCD; 1103 sc->sc_ppsclear = -1; 1104 break; 1105 1106 case PPS_CAPTURECLEAR: 1107 sc->sc_ppsmask = MSR_DCD; 1108 sc->sc_ppsassert = -1; 1109 sc->sc_ppsclear = 0; 1110 break; 1111 1112 case PPS_CAPTUREBOTH: 1113 sc->sc_ppsmask = MSR_DCD; 1114 sc->sc_ppsassert = MSR_DCD; 1115 sc->sc_ppsclear = 0; 1116 break; 1117 1118 default: 1119 error = EINVAL; 1120 break; 1121 } 1122 break; 1123 } 1124 1125 case PPS_IOC_GETCAP: 1126 *(int*)data = ppscap; 1127 break; 1128 1129 case PPS_IOC_FETCH: { 1130 pps_info_t *pi; 1131 pi = (pps_info_t *)data; 1132 *pi = sc->ppsinfo; 1133 break; 1134 } 1135 1136 #ifdef PPS_SYNC 1137 case PPS_IOC_KCBIND: { 1138 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1139 1140 if (edge == 0) { 1141 /* 1142 * remove binding for this source; ignore 1143 * the request if this is not the current 1144 * hardpps source 1145 */ 1146 if (pps_kc_hardpps_source == sc) { 1147 pps_kc_hardpps_source = NULL; 1148 pps_kc_hardpps_mode = 0; 1149 } 1150 } else { 1151 /* 1152 * bind hardpps to this source, replacing any 1153 * previously specified source or edges 1154 */ 1155 pps_kc_hardpps_source = sc; 1156 pps_kc_hardpps_mode = edge; 1157 } 1158 break; 1159 } 1160 #endif /* PPS_SYNC */ 1161 #endif /* !__HAVE_TIMECOUNTER */ 1162 1163 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1164 #ifdef __HAVE_TIMECOUNTER 1165 #ifndef PPS_TRAILING_EDGE 1166 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1167 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1168 #else 1169 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1170 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1171 #endif 1172 #else /* !__HAVE_TIMECOUNTER */ 1173 /* 1174 * Some GPS clocks models use the falling rather than 1175 * rising edge as the on-the-second signal. 1176 * The old API has no way to specify PPS polarity. 1177 */ 1178 sc->sc_ppsmask = MSR_DCD; 1179 #ifndef PPS_TRAILING_EDGE 1180 sc->sc_ppsassert = MSR_DCD; 1181 sc->sc_ppsclear = -1; 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->ppsinfo.assert_timestamp); 1184 #else 1185 sc->sc_ppsassert = -1; 1186 sc->sc_ppsclear = 0; 1187 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1188 &sc->ppsinfo.clear_timestamp); 1189 #endif 1190 #endif /* !__HAVE_TIMECOUNTER */ 1191 break; 1192 1193 default: 1194 error = EPASSTHROUGH; 1195 break; 1196 } 1197 1198 mutex_spin_exit(&sc->sc_lock); 1199 1200 #ifdef COM_DEBUG 1201 if (com_debug) 1202 comstatus(sc, "comioctl "); 1203 #endif 1204 1205 return (error); 1206 } 1207 1208 integrate void 1209 com_schedrx(struct com_softc *sc) 1210 { 1211 1212 sc->sc_rx_ready = 1; 1213 1214 /* Wake up the poller. */ 1215 softint_schedule(sc->sc_si); 1216 } 1217 1218 void 1219 com_break(struct com_softc *sc, int onoff) 1220 { 1221 1222 if (onoff) 1223 SET(sc->sc_lcr, LCR_SBREAK); 1224 else 1225 CLR(sc->sc_lcr, LCR_SBREAK); 1226 1227 if (!sc->sc_heldchange) { 1228 if (sc->sc_tx_busy) { 1229 sc->sc_heldtbc = sc->sc_tbc; 1230 sc->sc_tbc = 0; 1231 sc->sc_heldchange = 1; 1232 } else 1233 com_loadchannelregs(sc); 1234 } 1235 } 1236 1237 void 1238 com_modem(struct com_softc *sc, int onoff) 1239 { 1240 1241 if (sc->sc_mcr_dtr == 0) 1242 return; 1243 1244 if (onoff) 1245 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1246 else 1247 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1248 1249 if (!sc->sc_heldchange) { 1250 if (sc->sc_tx_busy) { 1251 sc->sc_heldtbc = sc->sc_tbc; 1252 sc->sc_tbc = 0; 1253 sc->sc_heldchange = 1; 1254 } else 1255 com_loadchannelregs(sc); 1256 } 1257 } 1258 1259 void 1260 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1261 { 1262 u_char combits; 1263 1264 combits = 0; 1265 if (ISSET(ttybits, TIOCM_DTR)) 1266 SET(combits, MCR_DTR); 1267 if (ISSET(ttybits, TIOCM_RTS)) 1268 SET(combits, MCR_RTS); 1269 1270 switch (how) { 1271 case TIOCMBIC: 1272 CLR(sc->sc_mcr, combits); 1273 break; 1274 1275 case TIOCMBIS: 1276 SET(sc->sc_mcr, combits); 1277 break; 1278 1279 case TIOCMSET: 1280 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1281 SET(sc->sc_mcr, combits); 1282 break; 1283 } 1284 1285 if (!sc->sc_heldchange) { 1286 if (sc->sc_tx_busy) { 1287 sc->sc_heldtbc = sc->sc_tbc; 1288 sc->sc_tbc = 0; 1289 sc->sc_heldchange = 1; 1290 } else 1291 com_loadchannelregs(sc); 1292 } 1293 } 1294 1295 int 1296 com_to_tiocm(struct com_softc *sc) 1297 { 1298 u_char combits; 1299 int ttybits = 0; 1300 1301 combits = sc->sc_mcr; 1302 if (ISSET(combits, MCR_DTR)) 1303 SET(ttybits, TIOCM_DTR); 1304 if (ISSET(combits, MCR_RTS)) 1305 SET(ttybits, TIOCM_RTS); 1306 1307 combits = sc->sc_msr; 1308 if (ISSET(combits, MSR_DCD)) 1309 SET(ttybits, TIOCM_CD); 1310 if (ISSET(combits, MSR_CTS)) 1311 SET(ttybits, TIOCM_CTS); 1312 if (ISSET(combits, MSR_DSR)) 1313 SET(ttybits, TIOCM_DSR); 1314 if (ISSET(combits, MSR_RI | MSR_TERI)) 1315 SET(ttybits, TIOCM_RI); 1316 1317 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1318 SET(ttybits, TIOCM_LE); 1319 1320 return (ttybits); 1321 } 1322 1323 static u_char 1324 cflag2lcr(tcflag_t cflag) 1325 { 1326 u_char lcr = 0; 1327 1328 switch (ISSET(cflag, CSIZE)) { 1329 case CS5: 1330 SET(lcr, LCR_5BITS); 1331 break; 1332 case CS6: 1333 SET(lcr, LCR_6BITS); 1334 break; 1335 case CS7: 1336 SET(lcr, LCR_7BITS); 1337 break; 1338 case CS8: 1339 SET(lcr, LCR_8BITS); 1340 break; 1341 } 1342 if (ISSET(cflag, PARENB)) { 1343 SET(lcr, LCR_PENAB); 1344 if (!ISSET(cflag, PARODD)) 1345 SET(lcr, LCR_PEVEN); 1346 } 1347 if (ISSET(cflag, CSTOPB)) 1348 SET(lcr, LCR_STOPB); 1349 1350 return (lcr); 1351 } 1352 1353 int 1354 comparam(struct tty *tp, struct termios *t) 1355 { 1356 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1357 int ospeed; 1358 u_char lcr; 1359 1360 if (COM_ISALIVE(sc) == 0) 1361 return (EIO); 1362 1363 #ifdef COM_HAYESP 1364 if (sc->sc_type == COM_TYPE_HAYESP) { 1365 int prescaler, speed; 1366 1367 /* 1368 * Calculate UART clock prescaler. It should be in 1369 * range of 0 .. 3. 1370 */ 1371 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1372 prescaler++, speed /= 2) 1373 if ((ospeed = comspeed(speed, sc->sc_frequency, 1374 sc->sc_type)) > 0) 1375 break; 1376 1377 if (prescaler == 4) 1378 return (EINVAL); 1379 sc->sc_prescaler = prescaler; 1380 } else 1381 #endif 1382 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1383 1384 /* Check requested parameters. */ 1385 if (ospeed < 0) 1386 return (EINVAL); 1387 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1388 return (EINVAL); 1389 1390 /* 1391 * For the console, always force CLOCAL and !HUPCL, so that the port 1392 * is always active. 1393 */ 1394 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1395 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1396 SET(t->c_cflag, CLOCAL); 1397 CLR(t->c_cflag, HUPCL); 1398 } 1399 1400 /* 1401 * If there were no changes, don't do anything. This avoids dropping 1402 * input and improves performance when all we did was frob things like 1403 * VMIN and VTIME. 1404 */ 1405 if (tp->t_ospeed == t->c_ospeed && 1406 tp->t_cflag == t->c_cflag) 1407 return (0); 1408 1409 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1410 1411 mutex_spin_enter(&sc->sc_lock); 1412 1413 sc->sc_lcr = lcr; 1414 1415 /* 1416 * If we're not in a mode that assumes a connection is present, then 1417 * ignore carrier changes. 1418 */ 1419 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1420 sc->sc_msr_dcd = 0; 1421 else 1422 sc->sc_msr_dcd = MSR_DCD; 1423 /* 1424 * Set the flow control pins depending on the current flow control 1425 * mode. 1426 */ 1427 if (ISSET(t->c_cflag, CRTSCTS)) { 1428 sc->sc_mcr_dtr = MCR_DTR; 1429 sc->sc_mcr_rts = MCR_RTS; 1430 sc->sc_msr_cts = MSR_CTS; 1431 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1432 } else if (ISSET(t->c_cflag, MDMBUF)) { 1433 /* 1434 * For DTR/DCD flow control, make sure we don't toggle DTR for 1435 * carrier detection. 1436 */ 1437 sc->sc_mcr_dtr = 0; 1438 sc->sc_mcr_rts = MCR_DTR; 1439 sc->sc_msr_cts = MSR_DCD; 1440 sc->sc_efr = 0; 1441 } else { 1442 /* 1443 * If no flow control, then always set RTS. This will make 1444 * the other side happy if it mistakenly thinks we're doing 1445 * RTS/CTS flow control. 1446 */ 1447 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1448 sc->sc_mcr_rts = 0; 1449 sc->sc_msr_cts = 0; 1450 sc->sc_efr = 0; 1451 if (ISSET(sc->sc_mcr, MCR_DTR)) 1452 SET(sc->sc_mcr, MCR_RTS); 1453 else 1454 CLR(sc->sc_mcr, MCR_RTS); 1455 } 1456 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1457 1458 #if 0 1459 if (ospeed == 0) 1460 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1461 else 1462 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1463 #endif 1464 1465 sc->sc_dlbl = ospeed; 1466 sc->sc_dlbh = ospeed >> 8; 1467 1468 /* 1469 * Set the FIFO threshold based on the receive speed. 1470 * 1471 * * If it's a low speed, it's probably a mouse or some other 1472 * interactive device, so set the threshold low. 1473 * * If it's a high speed, trim the trigger level down to prevent 1474 * overflows. 1475 * * Otherwise set it a bit higher. 1476 */ 1477 if (sc->sc_type == COM_TYPE_HAYESP) 1478 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1479 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1480 sc->sc_fifo = FIFO_ENABLE | 1481 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1482 else 1483 sc->sc_fifo = 0; 1484 1485 /* And copy to tty. */ 1486 tp->t_ispeed = t->c_ospeed; 1487 tp->t_ospeed = t->c_ospeed; 1488 tp->t_cflag = t->c_cflag; 1489 1490 if (!sc->sc_heldchange) { 1491 if (sc->sc_tx_busy) { 1492 sc->sc_heldtbc = sc->sc_tbc; 1493 sc->sc_tbc = 0; 1494 sc->sc_heldchange = 1; 1495 } else 1496 com_loadchannelregs(sc); 1497 } 1498 1499 if (!ISSET(t->c_cflag, CHWFLOW)) { 1500 /* Disable the high water mark. */ 1501 sc->sc_r_hiwat = 0; 1502 sc->sc_r_lowat = 0; 1503 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1504 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1505 com_schedrx(sc); 1506 } 1507 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1508 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1509 com_hwiflow(sc); 1510 } 1511 } else { 1512 sc->sc_r_hiwat = com_rbuf_hiwat; 1513 sc->sc_r_lowat = com_rbuf_lowat; 1514 } 1515 1516 mutex_spin_exit(&sc->sc_lock); 1517 1518 /* 1519 * Update the tty layer's idea of the carrier bit, in case we changed 1520 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1521 * explicit request. 1522 */ 1523 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1524 1525 #ifdef COM_DEBUG 1526 if (com_debug) 1527 comstatus(sc, "comparam "); 1528 #endif 1529 1530 if (!ISSET(t->c_cflag, CHWFLOW)) { 1531 if (sc->sc_tx_stopped) { 1532 sc->sc_tx_stopped = 0; 1533 comstart(tp); 1534 } 1535 } 1536 1537 return (0); 1538 } 1539 1540 void 1541 com_iflush(struct com_softc *sc) 1542 { 1543 struct com_regs *regsp = &sc->sc_regs; 1544 #ifdef DIAGNOSTIC 1545 int reg; 1546 #endif 1547 int timo; 1548 1549 #ifdef DIAGNOSTIC 1550 reg = 0xffff; 1551 #endif 1552 timo = 50000; 1553 /* flush any pending I/O */ 1554 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1555 && --timo) 1556 #ifdef DIAGNOSTIC 1557 reg = 1558 #else 1559 (void) 1560 #endif 1561 CSR_READ_1(regsp, COM_REG_RXDATA); 1562 #ifdef DIAGNOSTIC 1563 if (!timo) 1564 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1565 reg); 1566 #endif 1567 } 1568 1569 void 1570 com_loadchannelregs(struct com_softc *sc) 1571 { 1572 struct com_regs *regsp = &sc->sc_regs; 1573 1574 /* XXXXX necessary? */ 1575 com_iflush(sc); 1576 1577 if (sc->sc_type == COM_TYPE_PXA2x0) 1578 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1579 else 1580 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1581 1582 if (sc->sc_type == COM_TYPE_OMAP) { 1583 /* disable before changing settings */ 1584 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1585 } 1586 1587 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1588 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1589 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1590 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1591 } 1592 } 1593 if (sc->sc_type == COM_TYPE_AU1x00) { 1594 /* alchemy has single separate 16-bit clock divisor register */ 1595 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1596 (sc->sc_dlbh << 8)); 1597 } else { 1598 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1599 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1600 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1601 } 1602 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1603 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1604 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1605 #ifdef COM_HAYESP 1606 if (sc->sc_type == COM_TYPE_HAYESP) { 1607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1608 HAYESP_SETPRESCALER); 1609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1610 sc->sc_prescaler); 1611 } 1612 #endif 1613 if (sc->sc_type == COM_TYPE_OMAP) { 1614 /* setup the fifos. the FCR value is not used as long 1615 as SCR[6] and SCR[7] are 0, which they are at reset 1616 and we never touch the SCR register */ 1617 uint8_t rx_fifo_trig = 40; 1618 uint8_t tx_fifo_trig = 60; 1619 uint8_t rx_start = 8; 1620 uint8_t rx_halt = 60; 1621 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1622 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1623 1624 /* enable access to TCR & TLR */ 1625 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1626 1627 /* write tcr and tlr values */ 1628 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1629 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1630 1631 /* disable access to TCR & TLR */ 1632 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1633 1634 /* enable again, but mode is based on speed */ 1635 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1636 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1637 } else { 1638 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1639 } 1640 } 1641 1642 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1643 } 1644 1645 int 1646 comhwiflow(struct tty *tp, int block) 1647 { 1648 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1649 1650 if (COM_ISALIVE(sc) == 0) 1651 return (0); 1652 1653 if (sc->sc_mcr_rts == 0) 1654 return (0); 1655 1656 mutex_spin_enter(&sc->sc_lock); 1657 1658 if (block) { 1659 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1660 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1661 com_hwiflow(sc); 1662 } 1663 } else { 1664 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1665 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1666 com_schedrx(sc); 1667 } 1668 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1669 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1670 com_hwiflow(sc); 1671 } 1672 } 1673 1674 mutex_spin_exit(&sc->sc_lock); 1675 return (1); 1676 } 1677 1678 /* 1679 * (un)block input via hw flowcontrol 1680 */ 1681 void 1682 com_hwiflow(struct com_softc *sc) 1683 { 1684 struct com_regs *regsp= &sc->sc_regs; 1685 1686 if (sc->sc_mcr_rts == 0) 1687 return; 1688 1689 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1690 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1691 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1692 } else { 1693 SET(sc->sc_mcr, sc->sc_mcr_rts); 1694 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1695 } 1696 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1697 } 1698 1699 1700 void 1701 comstart(struct tty *tp) 1702 { 1703 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1704 struct com_regs *regsp = &sc->sc_regs; 1705 int s; 1706 1707 if (COM_ISALIVE(sc) == 0) 1708 return; 1709 1710 s = spltty(); 1711 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1712 goto out; 1713 if (sc->sc_tx_stopped) 1714 goto out; 1715 1716 if (tp->t_outq.c_cc <= tp->t_lowat) { 1717 if (ISSET(tp->t_state, TS_ASLEEP)) { 1718 CLR(tp->t_state, TS_ASLEEP); 1719 wakeup(&tp->t_outq); 1720 } 1721 selwakeup(&tp->t_wsel); 1722 if (tp->t_outq.c_cc == 0) 1723 goto out; 1724 } 1725 1726 /* Grab the first contiguous region of buffer space. */ 1727 { 1728 u_char *tba; 1729 int tbc; 1730 1731 tba = tp->t_outq.c_cf; 1732 tbc = ndqb(&tp->t_outq, 0); 1733 1734 mutex_spin_enter(&sc->sc_lock); 1735 1736 sc->sc_tba = tba; 1737 sc->sc_tbc = tbc; 1738 } 1739 1740 SET(tp->t_state, TS_BUSY); 1741 sc->sc_tx_busy = 1; 1742 1743 /* Enable transmit completion interrupts if necessary. */ 1744 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1745 SET(sc->sc_ier, IER_ETXRDY); 1746 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1747 } 1748 1749 /* Output the first chunk of the contiguous buffer. */ 1750 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1751 u_int n; 1752 1753 n = sc->sc_tbc; 1754 if (n > sc->sc_fifolen) 1755 n = sc->sc_fifolen; 1756 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1757 sc->sc_tbc -= n; 1758 sc->sc_tba += n; 1759 } 1760 1761 mutex_spin_exit(&sc->sc_lock); 1762 out: 1763 splx(s); 1764 return; 1765 } 1766 1767 /* 1768 * Stop output on a line. 1769 */ 1770 void 1771 comstop(struct tty *tp, int flag) 1772 { 1773 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1774 1775 mutex_spin_enter(&sc->sc_lock); 1776 if (ISSET(tp->t_state, TS_BUSY)) { 1777 /* Stop transmitting at the next chunk. */ 1778 sc->sc_tbc = 0; 1779 sc->sc_heldtbc = 0; 1780 if (!ISSET(tp->t_state, TS_TTSTOP)) 1781 SET(tp->t_state, TS_FLUSH); 1782 } 1783 mutex_spin_exit(&sc->sc_lock); 1784 } 1785 1786 void 1787 comdiag(void *arg) 1788 { 1789 struct com_softc *sc = arg; 1790 int overflows, floods; 1791 1792 mutex_spin_enter(&sc->sc_lock); 1793 overflows = sc->sc_overflows; 1794 sc->sc_overflows = 0; 1795 floods = sc->sc_floods; 1796 sc->sc_floods = 0; 1797 sc->sc_errors = 0; 1798 mutex_spin_exit(&sc->sc_lock); 1799 1800 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1801 sc->sc_dev.dv_xname, 1802 overflows, overflows == 1 ? "" : "s", 1803 floods, floods == 1 ? "" : "s"); 1804 } 1805 1806 integrate void 1807 com_rxsoft(struct com_softc *sc, struct tty *tp) 1808 { 1809 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1810 u_char *get, *end; 1811 u_int cc, scc; 1812 u_char lsr; 1813 int code; 1814 1815 end = sc->sc_ebuf; 1816 get = sc->sc_rbget; 1817 scc = cc = com_rbuf_size - sc->sc_rbavail; 1818 1819 if (cc == com_rbuf_size) { 1820 sc->sc_floods++; 1821 if (sc->sc_errors++ == 0) 1822 callout_reset(&sc->sc_diag_callout, 60 * hz, 1823 comdiag, sc); 1824 } 1825 1826 /* If not yet open, drop the entire buffer content here */ 1827 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1828 get += cc << 1; 1829 if (get >= end) 1830 get -= com_rbuf_size << 1; 1831 cc = 0; 1832 } 1833 while (cc) { 1834 code = get[0]; 1835 lsr = get[1]; 1836 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1837 if (ISSET(lsr, LSR_OE)) { 1838 sc->sc_overflows++; 1839 if (sc->sc_errors++ == 0) 1840 callout_reset(&sc->sc_diag_callout, 1841 60 * hz, comdiag, sc); 1842 } 1843 if (ISSET(lsr, LSR_BI | LSR_FE)) 1844 SET(code, TTY_FE); 1845 if (ISSET(lsr, LSR_PE)) 1846 SET(code, TTY_PE); 1847 } 1848 if ((*rint)(code, tp) == -1) { 1849 /* 1850 * The line discipline's buffer is out of space. 1851 */ 1852 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1853 /* 1854 * We're either not using flow control, or the 1855 * line discipline didn't tell us to block for 1856 * some reason. Either way, we have no way to 1857 * know when there's more space available, so 1858 * just drop the rest of the data. 1859 */ 1860 get += cc << 1; 1861 if (get >= end) 1862 get -= com_rbuf_size << 1; 1863 cc = 0; 1864 } else { 1865 /* 1866 * Don't schedule any more receive processing 1867 * until the line discipline tells us there's 1868 * space available (through comhwiflow()). 1869 * Leave the rest of the data in the input 1870 * buffer. 1871 */ 1872 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1873 } 1874 break; 1875 } 1876 get += 2; 1877 if (get >= end) 1878 get = sc->sc_rbuf; 1879 cc--; 1880 } 1881 1882 if (cc != scc) { 1883 sc->sc_rbget = get; 1884 mutex_spin_enter(&sc->sc_lock); 1885 1886 cc = sc->sc_rbavail += scc - cc; 1887 /* Buffers should be ok again, release possible block. */ 1888 if (cc >= sc->sc_r_lowat) { 1889 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1890 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1891 SET(sc->sc_ier, IER_ERXRDY); 1892 #ifdef COM_PXA2X0 1893 if (sc->sc_type == COM_TYPE_PXA2x0) 1894 SET(sc->sc_ier, IER_ERXTOUT); 1895 #endif 1896 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1897 } 1898 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1899 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1900 com_hwiflow(sc); 1901 } 1902 } 1903 mutex_spin_exit(&sc->sc_lock); 1904 } 1905 } 1906 1907 integrate void 1908 com_txsoft(struct com_softc *sc, struct tty *tp) 1909 { 1910 1911 CLR(tp->t_state, TS_BUSY); 1912 if (ISSET(tp->t_state, TS_FLUSH)) 1913 CLR(tp->t_state, TS_FLUSH); 1914 else 1915 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1916 (*tp->t_linesw->l_start)(tp); 1917 } 1918 1919 integrate void 1920 com_stsoft(struct com_softc *sc, struct tty *tp) 1921 { 1922 u_char msr, delta; 1923 1924 mutex_spin_enter(&sc->sc_lock); 1925 msr = sc->sc_msr; 1926 delta = sc->sc_msr_delta; 1927 sc->sc_msr_delta = 0; 1928 mutex_spin_exit(&sc->sc_lock); 1929 1930 if (ISSET(delta, sc->sc_msr_dcd)) { 1931 /* 1932 * Inform the tty layer that carrier detect changed. 1933 */ 1934 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1935 } 1936 1937 if (ISSET(delta, sc->sc_msr_cts)) { 1938 /* Block or unblock output according to flow control. */ 1939 if (ISSET(msr, sc->sc_msr_cts)) { 1940 sc->sc_tx_stopped = 0; 1941 (*tp->t_linesw->l_start)(tp); 1942 } else { 1943 sc->sc_tx_stopped = 1; 1944 } 1945 } 1946 1947 #ifdef COM_DEBUG 1948 if (com_debug) 1949 comstatus(sc, "com_stsoft"); 1950 #endif 1951 } 1952 1953 void 1954 comsoft(void *arg) 1955 { 1956 struct com_softc *sc = arg; 1957 struct tty *tp; 1958 1959 if (COM_ISALIVE(sc) == 0) 1960 return; 1961 1962 tp = sc->sc_tty; 1963 1964 if (sc->sc_rx_ready) { 1965 sc->sc_rx_ready = 0; 1966 com_rxsoft(sc, tp); 1967 } 1968 1969 if (sc->sc_st_check) { 1970 sc->sc_st_check = 0; 1971 com_stsoft(sc, tp); 1972 } 1973 1974 if (sc->sc_tx_done) { 1975 sc->sc_tx_done = 0; 1976 com_txsoft(sc, tp); 1977 } 1978 } 1979 1980 int 1981 comintr(void *arg) 1982 { 1983 struct com_softc *sc = arg; 1984 struct com_regs *regsp = &sc->sc_regs; 1985 1986 u_char *put, *end; 1987 u_int cc; 1988 u_char lsr, iir; 1989 1990 if (COM_ISALIVE(sc) == 0) 1991 return (0); 1992 1993 mutex_spin_enter(&sc->sc_lock); 1994 iir = CSR_READ_1(regsp, COM_REG_IIR); 1995 if (ISSET(iir, IIR_NOPEND)) { 1996 mutex_spin_exit(&sc->sc_lock); 1997 return (0); 1998 } 1999 2000 end = sc->sc_ebuf; 2001 put = sc->sc_rbput; 2002 cc = sc->sc_rbavail; 2003 2004 again: do { 2005 u_char msr, delta; 2006 2007 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2008 if (ISSET(lsr, LSR_BI)) { 2009 int cn_trapped = 0; 2010 2011 cn_check_magic(sc->sc_tty->t_dev, 2012 CNC_BREAK, com_cnm_state); 2013 if (cn_trapped) 2014 continue; 2015 #if defined(KGDB) && !defined(DDB) 2016 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2017 kgdb_connect(1); 2018 continue; 2019 } 2020 #endif 2021 } 2022 2023 if (ISSET(lsr, LSR_RCV_MASK) && 2024 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2025 while (cc > 0) { 2026 int cn_trapped = 0; 2027 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2028 put[1] = lsr; 2029 cn_check_magic(sc->sc_tty->t_dev, 2030 put[0], com_cnm_state); 2031 if (cn_trapped) 2032 goto next; 2033 put += 2; 2034 if (put >= end) 2035 put = sc->sc_rbuf; 2036 cc--; 2037 next: 2038 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2039 if (!ISSET(lsr, LSR_RCV_MASK)) 2040 break; 2041 } 2042 2043 /* 2044 * Current string of incoming characters ended because 2045 * no more data was available or we ran out of space. 2046 * Schedule a receive event if any data was received. 2047 * If we're out of space, turn off receive interrupts. 2048 */ 2049 sc->sc_rbput = put; 2050 sc->sc_rbavail = cc; 2051 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2052 sc->sc_rx_ready = 1; 2053 2054 /* 2055 * See if we are in danger of overflowing a buffer. If 2056 * so, use hardware flow control to ease the pressure. 2057 */ 2058 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2059 cc < sc->sc_r_hiwat) { 2060 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2061 com_hwiflow(sc); 2062 } 2063 2064 /* 2065 * If we're out of space, disable receive interrupts 2066 * until the queue has drained a bit. 2067 */ 2068 if (!cc) { 2069 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2070 #ifdef COM_PXA2X0 2071 if (sc->sc_type == COM_TYPE_PXA2x0) 2072 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2073 else 2074 #endif 2075 CLR(sc->sc_ier, IER_ERXRDY); 2076 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2077 } 2078 } else { 2079 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2080 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2081 continue; 2082 } 2083 } 2084 2085 msr = CSR_READ_1(regsp, COM_REG_MSR); 2086 delta = msr ^ sc->sc_msr; 2087 sc->sc_msr = msr; 2088 #ifdef __HAVE_TIMECOUNTER 2089 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2090 (delta & MSR_DCD)) { 2091 pps_capture(&sc->sc_pps_state); 2092 pps_event(&sc->sc_pps_state, 2093 (msr & MSR_DCD) ? 2094 PPS_CAPTUREASSERT : 2095 PPS_CAPTURECLEAR); 2096 } 2097 #else /* !__HAVE_TIMECOUNTER */ 2098 /* 2099 * Pulse-per-second (PSS) signals on edge of DCD? 2100 * Process these even if line discipline is ignoring DCD. 2101 */ 2102 if (delta & sc->sc_ppsmask) { 2103 struct timeval tv; 2104 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2105 /* XXX nanotime() */ 2106 microtime(&tv); 2107 TIMEVAL_TO_TIMESPEC(&tv, 2108 &sc->ppsinfo.assert_timestamp); 2109 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2110 timespecadd(&sc->ppsinfo.assert_timestamp, 2111 &sc->ppsparam.assert_offset, 2112 &sc->ppsinfo.assert_timestamp); 2113 } 2114 2115 #ifdef PPS_SYNC 2116 if (pps_kc_hardpps_source == sc && 2117 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2118 hardpps(&tv, tv.tv_usec); 2119 } 2120 #endif 2121 sc->ppsinfo.assert_sequence++; 2122 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2123 2124 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2125 /* XXX nanotime() */ 2126 microtime(&tv); 2127 TIMEVAL_TO_TIMESPEC(&tv, 2128 &sc->ppsinfo.clear_timestamp); 2129 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2130 timespecadd(&sc->ppsinfo.clear_timestamp, 2131 &sc->ppsparam.clear_offset, 2132 &sc->ppsinfo.clear_timestamp); 2133 } 2134 2135 #ifdef PPS_SYNC 2136 if (pps_kc_hardpps_source == sc && 2137 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2138 hardpps(&tv, tv.tv_usec); 2139 } 2140 #endif 2141 sc->ppsinfo.clear_sequence++; 2142 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2143 } 2144 } 2145 #endif /* !__HAVE_TIMECOUNTER */ 2146 2147 /* 2148 * Process normal status changes 2149 */ 2150 if (ISSET(delta, sc->sc_msr_mask)) { 2151 SET(sc->sc_msr_delta, delta); 2152 2153 /* 2154 * Stop output immediately if we lose the output 2155 * flow control signal or carrier detect. 2156 */ 2157 if (ISSET(~msr, sc->sc_msr_mask)) { 2158 sc->sc_tbc = 0; 2159 sc->sc_heldtbc = 0; 2160 #ifdef COM_DEBUG 2161 if (com_debug) 2162 comstatus(sc, "comintr "); 2163 #endif 2164 } 2165 2166 sc->sc_st_check = 1; 2167 } 2168 } while (!ISSET((iir = 2169 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2170 /* 2171 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2172 * by IIR read, so we can't do this way: `process all interrupts, 2173 * then do TX if possble'. 2174 */ 2175 (iir & IIR_IMASK) != IIR_TXRDY); 2176 2177 /* 2178 * Read LSR again, since there may be an interrupt between 2179 * the last LSR read and IIR read above. 2180 */ 2181 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2182 2183 /* 2184 * See if data can be transmitted as well. 2185 * Schedule tx done event if no data left 2186 * and tty was marked busy. 2187 */ 2188 if (ISSET(lsr, LSR_TXRDY)) { 2189 /* 2190 * If we've delayed a parameter change, do it now, and restart 2191 * output. 2192 */ 2193 if (sc->sc_heldchange) { 2194 com_loadchannelregs(sc); 2195 sc->sc_heldchange = 0; 2196 sc->sc_tbc = sc->sc_heldtbc; 2197 sc->sc_heldtbc = 0; 2198 } 2199 2200 /* Output the next chunk of the contiguous buffer, if any. */ 2201 if (sc->sc_tbc > 0) { 2202 u_int n; 2203 2204 n = sc->sc_tbc; 2205 if (n > sc->sc_fifolen) 2206 n = sc->sc_fifolen; 2207 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2208 sc->sc_tbc -= n; 2209 sc->sc_tba += n; 2210 } else { 2211 /* Disable transmit completion interrupts if necessary. */ 2212 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2213 CLR(sc->sc_ier, IER_ETXRDY); 2214 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2215 } 2216 if (sc->sc_tx_busy) { 2217 sc->sc_tx_busy = 0; 2218 sc->sc_tx_done = 1; 2219 } 2220 } 2221 } 2222 2223 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2224 goto again; 2225 2226 mutex_spin_exit(&sc->sc_lock); 2227 2228 /* Wake up the poller. */ 2229 softint_schedule(sc->sc_si); 2230 2231 #if NRND > 0 && defined(RND_COM) 2232 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2233 #endif 2234 2235 return (1); 2236 } 2237 2238 /* 2239 * The following functions are polled getc and putc routines, shared 2240 * by the console and kgdb glue. 2241 * 2242 * The read-ahead code is so that you can detect pending in-band 2243 * cn_magic in polled mode while doing output rather than having to 2244 * wait until the kernel decides it needs input. 2245 */ 2246 2247 #define MAX_READAHEAD 20 2248 static int com_readahead[MAX_READAHEAD]; 2249 static int com_readaheadcount = 0; 2250 2251 int 2252 com_common_getc(dev_t dev, struct com_regs *regsp) 2253 { 2254 int s = splserial(); 2255 u_char stat, c; 2256 2257 /* got a character from reading things earlier */ 2258 if (com_readaheadcount > 0) { 2259 int i; 2260 2261 c = com_readahead[0]; 2262 for (i = 1; i < com_readaheadcount; i++) { 2263 com_readahead[i-1] = com_readahead[i]; 2264 } 2265 com_readaheadcount--; 2266 splx(s); 2267 return (c); 2268 } 2269 2270 /* block until a character becomes available */ 2271 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2272 ; 2273 2274 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2275 stat = CSR_READ_1(regsp, COM_REG_IIR); 2276 { 2277 int cn_trapped = 0; /* unused */ 2278 #ifdef DDB 2279 extern int db_active; 2280 if (!db_active) 2281 #endif 2282 cn_check_magic(dev, c, com_cnm_state); 2283 } 2284 splx(s); 2285 return (c); 2286 } 2287 2288 void 2289 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2290 { 2291 int s = splserial(); 2292 int cin, stat, timo; 2293 2294 if (com_readaheadcount < MAX_READAHEAD 2295 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2296 int cn_trapped = 0; 2297 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2298 stat = CSR_READ_1(regsp, COM_REG_IIR); 2299 cn_check_magic(dev, cin, com_cnm_state); 2300 com_readahead[com_readaheadcount++] = cin; 2301 } 2302 2303 /* wait for any pending transmission to finish */ 2304 timo = 150000; 2305 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2306 continue; 2307 2308 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2309 COM_BARRIER(regsp, BR | BW); 2310 2311 splx(s); 2312 } 2313 2314 /* 2315 * Initialize UART for use as console or KGDB line. 2316 */ 2317 int 2318 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2319 tcflag_t cflag) 2320 { 2321 2322 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2323 ®sp->cr_ioh)) 2324 return (ENOMEM); /* ??? */ 2325 2326 if (type == COM_TYPE_OMAP) { 2327 /* disable before changing settings */ 2328 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2329 } 2330 2331 rate = comspeed(rate, frequency, type); 2332 if (type != COM_TYPE_AU1x00) { 2333 /* no EFR on alchemy */ 2334 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2335 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2336 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2337 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2338 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2339 } else { 2340 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2341 } 2342 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2343 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2344 CSR_WRITE_1(regsp, COM_REG_FIFO, 2345 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2346 2347 if (type == COM_TYPE_OMAP) { 2348 /* setup the fifos. the FCR value is not used as long 2349 as SCR[6] and SCR[7] are 0, which they are at reset 2350 and we never touch the SCR register */ 2351 uint8_t rx_fifo_trig = 40; 2352 uint8_t tx_fifo_trig = 60; 2353 uint8_t rx_start = 8; 2354 uint8_t rx_halt = 60; 2355 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2356 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2357 2358 /* enable access to TCR & TLR */ 2359 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2360 2361 /* write tcr and tlr values */ 2362 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2363 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2364 2365 /* disable access to TCR & TLR */ 2366 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2367 2368 /* enable again, but mode is based on speed */ 2369 if (rate > 230400) { 2370 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2371 } else { 2372 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2373 } 2374 } 2375 2376 #ifdef COM_PXA2X0 2377 if (type == COM_TYPE_PXA2x0) 2378 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2379 else 2380 #endif 2381 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2382 2383 return (0); 2384 } 2385 2386 /* 2387 * Following are all routines needed for COM to act as console 2388 */ 2389 struct consdev comcons = { 2390 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2391 NODEV, CN_NORMAL 2392 }; 2393 2394 2395 int 2396 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2397 tcflag_t cflag) 2398 { 2399 int res; 2400 2401 comconsregs = *regsp; 2402 2403 res = cominit(&comconsregs, rate, frequency, type, cflag); 2404 if (res) 2405 return (res); 2406 2407 cn_tab = &comcons; 2408 cn_init_magic(&com_cnm_state); 2409 cn_set_magic("\047\001"); /* default magic is BREAK */ 2410 2411 comconsrate = rate; 2412 comconscflag = cflag; 2413 2414 return (0); 2415 } 2416 2417 int 2418 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2419 int type, tcflag_t cflag) 2420 { 2421 struct com_regs regs; 2422 2423 memset(®s, 0, sizeof regs); 2424 regs.cr_iot = iot; 2425 regs.cr_iobase = iobase; 2426 regs.cr_nports = COM_NPORTS; 2427 #ifdef COM_REGMAP 2428 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2429 #endif 2430 2431 return comcnattach1(®s, rate, frequency, type, cflag); 2432 } 2433 2434 int 2435 comcngetc(dev_t dev) 2436 { 2437 2438 return (com_common_getc(dev, &comconsregs)); 2439 } 2440 2441 /* 2442 * Console kernel output character routine. 2443 */ 2444 void 2445 comcnputc(dev_t dev, int c) 2446 { 2447 2448 com_common_putc(dev, &comconsregs, c); 2449 } 2450 2451 void 2452 comcnpollc(dev_t dev, int on) 2453 { 2454 2455 } 2456 2457 #ifdef KGDB 2458 int 2459 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2460 tcflag_t cflag) 2461 { 2462 int res; 2463 2464 if (regsp->cr_iot == comconsregs.cr_iot && 2465 regsp->cr_iobase == comconsregs.cr_iobase) { 2466 #if !defined(DDB) 2467 return (EBUSY); /* cannot share with console */ 2468 #else 2469 comkgdbregs = *regsp; 2470 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2471 #endif 2472 } else { 2473 comkgdbregs = *regsp; 2474 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2475 if (res) 2476 return (res); 2477 2478 /* 2479 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2480 * expects this to be initialized 2481 */ 2482 cn_init_magic(&com_cnm_state); 2483 cn_set_magic("\047\001"); 2484 } 2485 2486 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2487 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2488 2489 return (0); 2490 } 2491 2492 int 2493 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2494 int frequency, int type, tcflag_t cflag) 2495 { 2496 struct com_regs regs; 2497 2498 regs.cr_iot = iot; 2499 regs.cr_nports = COM_NPORTS; 2500 regs.cr_iobase = iobase; 2501 #ifdef COM_REGMAP 2502 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2503 #endif 2504 2505 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2506 } 2507 2508 /* ARGSUSED */ 2509 int 2510 com_kgdb_getc(void *arg) 2511 { 2512 2513 return (com_common_getc(NODEV, &comkgdbregs)); 2514 } 2515 2516 /* ARGSUSED */ 2517 void 2518 com_kgdb_putc(void *arg, int c) 2519 { 2520 2521 com_common_putc(NODEV, &comkgdbregs, c); 2522 } 2523 #endif /* KGDB */ 2524 2525 /* helper function to identify the com ports used by 2526 console or KGDB (and not yet autoconf attached) */ 2527 int 2528 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2529 { 2530 bus_space_handle_t help; 2531 2532 if (!comconsattached && 2533 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2534 help = comconsregs.cr_ioh; 2535 #ifdef KGDB 2536 else if (!com_kgdb_attached && 2537 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2538 help = comkgdbregs.cr_ioh; 2539 #endif 2540 else 2541 return (0); 2542 2543 if (ioh) 2544 *ioh = help; 2545 return (1); 2546 } 2547 2548 /* 2549 * this routine exists to serve as a shutdown hook for systems that 2550 * have firmware which doesn't interact properly with a com device in 2551 * FIFO mode. 2552 */ 2553 void 2554 com_cleanup(void *arg) 2555 { 2556 struct com_softc *sc = arg; 2557 2558 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2559 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2560 } 2561 2562 void 2563 com_power(int why, void *arg) 2564 { 2565 struct com_softc *sc = arg; 2566 2567 mutex_spin_enter(&sc->sc_lock); 2568 switch (why) { 2569 case PWR_SUSPEND: 2570 case PWR_STANDBY: 2571 /* XXX should we do something to stop the device? */ 2572 break; 2573 case PWR_RESUME: 2574 com_loadchannelregs(sc); 2575 break; 2576 case PWR_SOFTSUSPEND: 2577 case PWR_SOFTSTANDBY: 2578 case PWR_SOFTRESUME: 2579 break; 2580 } 2581 mutex_spin_exit(&sc->sc_lock); 2582 } 2583
Indexes created Tue Oct 21 06:10:07 GMT 2025