com.c revision 1.262.2.3
1 /* $NetBSD: com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 182 int com_common_getc(dev_t, struct com_regs *); 183 void com_common_putc(dev_t, struct com_regs *, int); 184 185 int cominit(struct com_regs *, int, int, int, tcflag_t); 186 187 int comcngetc(dev_t); 188 void comcnputc(dev_t, int); 189 void comcnpollc(dev_t, int); 190 191 #define integrate static inline 192 void comsoft(void *); 193 integrate void com_rxsoft(struct com_softc *, struct tty *); 194 integrate void com_txsoft(struct com_softc *, struct tty *); 195 integrate void com_stsoft(struct com_softc *, struct tty *); 196 integrate void com_schedrx(struct com_softc *); 197 void comdiag(void *); 198 199 extern struct cfdriver com_cd; 200 201 dev_type_open(comopen); 202 dev_type_close(comclose); 203 dev_type_read(comread); 204 dev_type_write(comwrite); 205 dev_type_ioctl(comioctl); 206 dev_type_stop(comstop); 207 dev_type_tty(comtty); 208 dev_type_poll(compoll); 209 210 const struct cdevsw com_cdevsw = { 211 comopen, comclose, comread, comwrite, comioctl, 212 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static struct com_regs comconsregs; 226 static int comconsattached; 227 static int comconsrate; 228 static tcflag_t comconscflag; 229 static struct cnm_state com_cnm_state; 230 231 #ifndef __HAVE_TIMECOUNTER 232 static int ppscap = 233 PPS_TSFMT_TSPEC | 234 PPS_CAPTUREASSERT | 235 PPS_CAPTURECLEAR | 236 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 237 #endif /* !__HAVE_TIMECOUNTER */ 238 239 #ifdef KGDB 240 #include <sys/kgdb.h> 241 242 static struct com_regs comkgdbregs; 243 static int com_kgdb_attached; 244 245 int com_kgdb_getc(void *); 246 void com_kgdb_putc(void *, int); 247 #endif /* KGDB */ 248 249 #ifdef COM_REGMAP 250 /* initializer for typical 16550-ish hardware */ 251 #define COM_REG_16550 { \ 252 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 253 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 254 255 const bus_size_t com_std_map[16] = COM_REG_16550; 256 #endif /* COM_REGMAP */ 257 258 #define COMUNIT_MASK 0x7ffff 259 #define COMDIALOUT_MASK 0x80000 260 261 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 262 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 263 264 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 265 device_is_active(&(sc)->sc_dev)) 266 267 #define BR BUS_SPACE_BARRIER_READ 268 #define BW BUS_SPACE_BARRIER_WRITE 269 #define COM_BARRIER(r, f) \ 270 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 271 272 /*ARGSUSED*/ 273 int 274 comspeed(long speed, long frequency, int type) 275 { 276 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 277 278 int x, err; 279 int divisor = 16; 280 281 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 282 divisor = 13; 283 } 284 285 #if 0 286 if (speed == 0) 287 return (0); 288 #endif 289 if (speed <= 0) 290 return (-1); 291 x = divrnd(frequency / divisor, speed); 292 if (x <= 0) 293 return (-1); 294 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 295 if (err < 0) 296 err = -err; 297 if (err > COM_TOLERANCE) 298 return (-1); 299 return (x); 300 301 #undef divrnd 302 } 303 304 #ifdef COM_DEBUG 305 int com_debug = 0; 306 307 void comstatus(struct com_softc *, const char *); 308 void 309 comstatus(struct com_softc *sc, const char *str) 310 { 311 struct tty *tp = sc->sc_tty; 312 313 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 314 sc->sc_dev.dv_xname, str, 315 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 316 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 317 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 318 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 319 sc->sc_tx_stopped ? '+' : '-'); 320 321 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 322 sc->sc_dev.dv_xname, str, 323 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 324 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 325 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 326 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 327 sc->sc_rx_flags); 328 } 329 #endif 330 331 int 332 com_probe_subr(struct com_regs *regs) 333 { 334 335 /* force access to id reg */ 336 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 337 CSR_WRITE_1(regs, COM_REG_IIR, 0); 338 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 339 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 340 return (0); 341 342 return (1); 343 } 344 345 int 346 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 347 { 348 struct com_regs regs; 349 350 regs.cr_iot = iot; 351 regs.cr_ioh = ioh; 352 #ifdef COM_REGMAP 353 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 354 #endif 355 356 return com_probe_subr(®s); 357 } 358 359 /* 360 * No locking in this routine; it is only called during attach, 361 * or with the port already locked. 362 */ 363 static void 364 com_enable_debugport(struct com_softc *sc) 365 { 366 367 /* Turn on line break interrupt, set carrier. */ 368 sc->sc_ier = IER_ERXRDY; 369 if (sc->sc_type == COM_TYPE_PXA2x0) 370 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 371 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 372 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 373 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 374 } 375 376 void 377 com_attach_subr(struct com_softc *sc) 378 { 379 struct com_regs *regsp = &sc->sc_regs; 380 struct tty *tp; 381 #ifdef COM_16650 382 u_int8_t lcr; 383 #endif 384 const char *fifo_msg = NULL; 385 386 aprint_naive("\n"); 387 388 callout_init(&sc->sc_diag_callout, 0); 389 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 390 391 /* Disable interrupts before configuring the device. */ 392 if (sc->sc_type == COM_TYPE_PXA2x0) 393 sc->sc_ier = IER_EUART; 394 else 395 sc->sc_ier = 0; 396 397 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 398 399 if (regsp->cr_iot == comconsregs.cr_iot && 400 regsp->cr_iobase == comconsregs.cr_iobase) { 401 comconsattached = 1; 402 403 /* Make sure the console is always "hardwired". */ 404 delay(10000); /* wait for output to finish */ 405 SET(sc->sc_hwflags, COM_HW_CONSOLE); 406 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 407 } 408 409 /* Probe for FIFO */ 410 switch (sc->sc_type) { 411 case COM_TYPE_HAYESP: 412 goto fifodone; 413 414 case COM_TYPE_AU1x00: 415 sc->sc_fifolen = 16; 416 fifo_msg = "Au1X00 UART, working fifo"; 417 SET(sc->sc_hwflags, COM_HW_FIFO); 418 goto fifodelay; 419 420 case COM_TYPE_OMAP: 421 sc->sc_fifolen = 64; 422 fifo_msg = "OMAP UART, working fifo"; 423 SET(sc->sc_hwflags, COM_HW_FIFO); 424 goto fifodelay; 425 } 426 427 sc->sc_fifolen = 1; 428 /* look for a NS 16550AF UART with FIFOs */ 429 CSR_WRITE_1(regsp, COM_REG_FIFO, 430 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 431 delay(100); 432 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 433 == IIR_FIFO_MASK) 434 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 435 == FIFO_TRIGGER_14) { 436 SET(sc->sc_hwflags, COM_HW_FIFO); 437 438 #ifdef COM_16650 439 /* 440 * IIR changes into the EFR if LCR is set to LCR_EERS 441 * on 16650s. We also know IIR != 0 at this point. 442 * Write 0 into the EFR, and read it. If the result 443 * is 0, we have a 16650. 444 * 445 * Older 16650s were broken; the test to detect them 446 * is taken from the Linux driver. Apparently 447 * setting DLAB enable gives access to the EFR on 448 * these chips. 449 */ 450 lcr = CSR_READ_1(regsp, COM_REG_LCR); 451 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 452 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 453 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 454 CSR_WRITE_1(regsp, COM_REG_LCR, 455 lcr | LCR_DLAB); 456 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 457 CLR(sc->sc_hwflags, COM_HW_FIFO); 458 sc->sc_fifolen = 0; 459 } else { 460 SET(sc->sc_hwflags, COM_HW_FLOW); 461 sc->sc_fifolen = 32; 462 } 463 } else 464 #endif 465 sc->sc_fifolen = 16; 466 467 #ifdef COM_16650 468 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 469 if (sc->sc_fifolen == 0) 470 fifo_msg = "st16650, broken fifo"; 471 else if (sc->sc_fifolen == 32) 472 fifo_msg = "st16650a, working fifo"; 473 else 474 #endif 475 fifo_msg = "ns16550a, working fifo"; 476 } else 477 fifo_msg = "ns16550, broken fifo"; 478 else 479 fifo_msg = "ns8250 or ns16450, no fifo"; 480 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 481 fifodelay: 482 /* 483 * Some chips will clear down both Tx and Rx FIFOs when zero is 484 * written to com_fifo. If this chip is the console, writing zero 485 * results in some of the chip/FIFO description being lost, so delay 486 * printing it until now. 487 */ 488 delay(10); 489 aprint_normal(": %s\n", fifo_msg); 490 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 491 sc->sc_fifolen = 1; 492 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 493 } 494 495 fifodone: 496 497 tp = ttymalloc(); 498 tp->t_oproc = comstart; 499 tp->t_param = comparam; 500 tp->t_hwiflow = comhwiflow; 501 502 sc->sc_tty = tp; 503 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 504 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 505 sc->sc_rbavail = com_rbuf_size; 506 if (sc->sc_rbuf == NULL) { 507 aprint_error("%s: unable to allocate ring buffer\n", 508 sc->sc_dev.dv_xname); 509 return; 510 } 511 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 512 513 tty_attach(tp); 514 515 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 516 SET(sc->sc_mcr, MCR_IENABLE); 517 518 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 519 int maj; 520 521 /* locate the major number */ 522 maj = cdevsw_lookup_major(&com_cdevsw); 523 524 tp->t_dev = cn_tab->cn_dev = makedev(maj, 525 device_unit(&sc->sc_dev)); 526 527 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 528 } 529 530 #ifdef KGDB 531 /* 532 * Allow kgdb to "take over" this port. If this is 533 * not the console and is the kgdb device, it has 534 * exclusive use. If it's the console _and_ the 535 * kgdb device, it doesn't. 536 */ 537 if (regsp->cr_iot == comkgdbregs.cr_iot && 538 regsp->cr_iobase == comkgdbregs.cr_iobase) { 539 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 540 com_kgdb_attached = 1; 541 542 SET(sc->sc_hwflags, COM_HW_KGDB); 543 } 544 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 545 } 546 #endif 547 548 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 549 550 #if NRND > 0 && defined(RND_COM) 551 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 552 RND_TYPE_TTY, 0); 553 #endif 554 555 /* if there are no enable/disable functions, assume the device 556 is always enabled */ 557 if (!sc->enable) 558 sc->enabled = 1; 559 560 com_config(sc); 561 562 SET(sc->sc_hwflags, COM_HW_DEV_OK); 563 } 564 565 void 566 com_config(struct com_softc *sc) 567 { 568 struct com_regs *regsp = &sc->sc_regs; 569 570 /* Disable interrupts before configuring the device. */ 571 if (sc->sc_type == COM_TYPE_PXA2x0) 572 sc->sc_ier = IER_EUART; 573 else 574 sc->sc_ier = 0; 575 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 576 (void) CSR_READ_1(regsp, COM_REG_IIR); 577 578 #ifdef COM_HAYESP 579 /* Look for a Hayes ESP board. */ 580 if (sc->sc_type == COM_TYPE_HAYESP) { 581 582 /* Set 16550 compatibility mode */ 583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 584 HAYESP_SETMODE); 585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 586 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 587 HAYESP_MODE_SCALE); 588 589 /* Set RTS/CTS flow control */ 590 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 591 HAYESP_SETFLOWTYPE); 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 593 HAYESP_FLOW_RTS); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_FLOW_CTS); 596 597 /* Set flow control levels */ 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 599 HAYESP_SETRXFLOW); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 604 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 605 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 607 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 608 } 609 #endif 610 611 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 612 com_enable_debugport(sc); 613 } 614 615 int 616 com_detach(struct device *self, int flags) 617 { 618 struct com_softc *sc = (struct com_softc *)self; 619 int maj, mn; 620 621 /* locate the major number */ 622 maj = cdevsw_lookup_major(&com_cdevsw); 623 624 /* Nuke the vnodes for any open instances. */ 625 mn = device_unit(self); 626 vdevgone(maj, mn, mn, VCHR); 627 628 mn |= COMDIALOUT_MASK; 629 vdevgone(maj, mn, mn, VCHR); 630 631 if (sc->sc_rbuf == NULL) { 632 /* 633 * Ring buffer allocation failed in the com_attach_subr, 634 * only the tty is allocated, and nothing else. 635 */ 636 ttyfree(sc->sc_tty); 637 return 0; 638 } 639 640 /* Free the receive buffer. */ 641 free(sc->sc_rbuf, M_DEVBUF); 642 643 /* Detach and free the tty. */ 644 tty_detach(sc->sc_tty); 645 ttyfree(sc->sc_tty); 646 647 /* Unhook the soft interrupt handler. */ 648 softint_disestablish(sc->sc_si); 649 650 #if NRND > 0 && defined(RND_COM) 651 /* Unhook the entropy source. */ 652 rnd_detach_source(&sc->rnd_source); 653 #endif 654 655 return (0); 656 } 657 658 int 659 com_activate(struct device *self, enum devact act) 660 { 661 struct com_softc *sc = (struct com_softc *)self; 662 int rv = 0; 663 664 switch (act) { 665 case DVACT_ACTIVATE: 666 rv = EOPNOTSUPP; 667 break; 668 669 case DVACT_DEACTIVATE: 670 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 671 rv = EBUSY; 672 break; 673 } 674 675 if (sc->disable != NULL && sc->enabled != 0) { 676 (*sc->disable)(sc); 677 sc->enabled = 0; 678 } 679 break; 680 } 681 682 if (sc->sc_type == COM_TYPE_OMAP) { 683 /* enable but mode is based on speed */ 684 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 685 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_13X); 686 } else { 687 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_16X); 688 } 689 } 690 mutex_spin_exit(&sc->sc_lock); 691 return (rv); 692 } 693 694 void 695 com_shutdown(struct com_softc *sc) 696 { 697 struct tty *tp = sc->sc_tty; 698 699 mutex_spin_enter(&sc->sc_lock); 700 701 /* If we were asserting flow control, then deassert it. */ 702 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 703 com_hwiflow(sc); 704 705 /* Clear any break condition set with TIOCSBRK. */ 706 com_break(sc, 0); 707 708 #ifndef __HAVE_TIMECOUNTER 709 /* Turn off PPS capture on last close. */ 710 sc->sc_ppsmask = 0; 711 sc->ppsparam.mode = 0; 712 #endif /* !__HAVE_TIMECOUNTER */ 713 714 /* 715 * Hang up if necessary. Wait a bit, so the other side has time to 716 * notice even if we immediately open the port again. 717 * Avoid tsleeping above splhigh(). 718 */ 719 if (ISSET(tp->t_cflag, HUPCL)) { 720 com_modem(sc, 0); 721 mutex_spin_exit(&sc->sc_lock); 722 /* XXX will only timeout */ 723 (void) kpause(ttclos, false, hz, NULL); 724 mutex_spin_enter(&sc->sc_lock); 725 } 726 727 /* Turn off interrupts. */ 728 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 729 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 730 if (sc->sc_type == COM_TYPE_PXA2x0) 731 sc->sc_ier |= IER_ERXTOUT; 732 } else 733 sc->sc_ier = 0; 734 735 if (sc->sc_type == COM_TYPE_PXA2x0) 736 sc->sc_ier |= IER_EUART; 737 738 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 739 740 mutex_spin_exit(&sc->sc_lock); 741 742 if (sc->disable) { 743 #ifdef DIAGNOSTIC 744 if (!sc->enabled) 745 panic("com_shutdown: not enabled?"); 746 #endif 747 (*sc->disable)(sc); 748 sc->enabled = 0; 749 } 750 } 751 752 int 753 comopen(dev_t dev, int flag, int mode, struct lwp *l) 754 { 755 struct com_softc *sc; 756 struct tty *tp; 757 int s; 758 int error; 759 760 sc = device_lookup(&com_cd, COMUNIT(dev)); 761 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 762 sc->sc_rbuf == NULL) 763 return (ENXIO); 764 765 if (!device_is_active(&sc->sc_dev)) 766 return (ENXIO); 767 768 #ifdef KGDB 769 /* 770 * If this is the kgdb port, no other use is permitted. 771 */ 772 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 773 return (EBUSY); 774 #endif 775 776 tp = sc->sc_tty; 777 778 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 779 return (EBUSY); 780 781 s = spltty(); 782 783 /* 784 * Do the following iff this is a first open. 785 */ 786 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 787 struct termios t; 788 789 tp->t_dev = dev; 790 791 792 if (sc->enable) { 793 if ((*sc->enable)(sc)) { 794 splx(s); 795 printf("%s: device enable failed\n", 796 sc->sc_dev.dv_xname); 797 return (EIO); 798 } 799 mutex_spin_enter(&sc->sc_lock); 800 sc->enabled = 1; 801 com_config(sc); 802 } else { 803 mutex_spin_enter(&sc->sc_lock); 804 } 805 806 /* Turn on interrupts. */ 807 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 808 if (sc->sc_type == COM_TYPE_PXA2x0) 809 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 810 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 811 812 /* Fetch the current modem control status, needed later. */ 813 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 814 815 /* Clear PPS capture state on first open. */ 816 #ifdef __HAVE_TIMECOUNTER 817 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 818 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 819 pps_init(&sc->sc_pps_state); 820 #else /* !__HAVE_TIMECOUNTER */ 821 sc->sc_ppsmask = 0; 822 sc->ppsparam.mode = 0; 823 #endif /* !__HAVE_TIMECOUNTER */ 824 825 mutex_spin_exit(&sc->sc_lock); 826 827 /* 828 * Initialize the termios status to the defaults. Add in the 829 * sticky bits from TIOCSFLAGS. 830 */ 831 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 832 t.c_ospeed = comconsrate; 833 t.c_cflag = comconscflag; 834 } else { 835 t.c_ospeed = TTYDEF_SPEED; 836 t.c_cflag = TTYDEF_CFLAG; 837 } 838 t.c_ispeed = t.c_ospeed; 839 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 840 SET(t.c_cflag, CLOCAL); 841 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 842 SET(t.c_cflag, CRTSCTS); 843 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 844 SET(t.c_cflag, MDMBUF); 845 /* Make sure comparam() will do something. */ 846 tp->t_ospeed = 0; 847 (void) comparam(tp, &t); 848 tp->t_iflag = TTYDEF_IFLAG; 849 tp->t_oflag = TTYDEF_OFLAG; 850 tp->t_lflag = TTYDEF_LFLAG; 851 ttychars(tp); 852 ttsetwater(tp); 853 854 mutex_spin_enter(&sc->sc_lock); 855 856 /* 857 * Turn on DTR. We must always do this, even if carrier is not 858 * present, because otherwise we'd have to use TIOCSDTR 859 * immediately after setting CLOCAL, which applications do not 860 * expect. We always assert DTR while the device is open 861 * unless explicitly requested to deassert it. 862 */ 863 com_modem(sc, 1); 864 865 /* Clear the input ring, and unblock. */ 866 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 867 sc->sc_rbavail = com_rbuf_size; 868 com_iflush(sc); 869 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 870 com_hwiflow(sc); 871 872 #ifdef COM_DEBUG 873 if (com_debug) 874 comstatus(sc, "comopen "); 875 #endif 876 877 mutex_spin_exit(&sc->sc_lock); 878 } 879 880 splx(s); 881 882 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 883 if (error) 884 goto bad; 885 886 error = (*tp->t_linesw->l_open)(dev, tp); 887 if (error) 888 goto bad; 889 890 return (0); 891 892 bad: 893 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 894 /* 895 * We failed to open the device, and nobody else had it opened. 896 * Clean up the state as appropriate. 897 */ 898 com_shutdown(sc); 899 } 900 901 return (error); 902 } 903 904 int 905 comclose(dev_t dev, int flag, int mode, struct lwp *l) 906 { 907 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 908 struct tty *tp = sc->sc_tty; 909 910 /* XXX This is for cons.c. */ 911 if (!ISSET(tp->t_state, TS_ISOPEN)) 912 return (0); 913 914 (*tp->t_linesw->l_close)(tp, flag); 915 ttyclose(tp); 916 917 if (COM_ISALIVE(sc) == 0) 918 return (0); 919 920 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 921 /* 922 * Although we got a last close, the device may still be in 923 * use; e.g. if this was the dialout node, and there are still 924 * processes waiting for carrier on the non-dialout node. 925 */ 926 com_shutdown(sc); 927 } 928 929 return (0); 930 } 931 932 int 933 comread(dev_t dev, struct uio *uio, int flag) 934 { 935 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 936 struct tty *tp = sc->sc_tty; 937 938 if (COM_ISALIVE(sc) == 0) 939 return (EIO); 940 941 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 942 } 943 944 int 945 comwrite(dev_t dev, struct uio *uio, int flag) 946 { 947 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 948 struct tty *tp = sc->sc_tty; 949 950 if (COM_ISALIVE(sc) == 0) 951 return (EIO); 952 953 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 954 } 955 956 int 957 compoll(dev_t dev, int events, struct lwp *l) 958 { 959 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 960 struct tty *tp = sc->sc_tty; 961 962 if (COM_ISALIVE(sc) == 0) 963 return (POLLHUP); 964 965 return ((*tp->t_linesw->l_poll)(tp, events, l)); 966 } 967 968 struct tty * 969 comtty(dev_t dev) 970 { 971 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 972 struct tty *tp = sc->sc_tty; 973 974 return (tp); 975 } 976 977 int 978 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 979 { 980 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 981 struct tty *tp = sc->sc_tty; 982 int error; 983 984 if (COM_ISALIVE(sc) == 0) 985 return (EIO); 986 987 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 988 if (error != EPASSTHROUGH) 989 return (error); 990 991 error = ttioctl(tp, cmd, data, flag, l); 992 if (error != EPASSTHROUGH) 993 return (error); 994 995 error = 0; 996 switch (cmd) { 997 case TIOCSFLAGS: 998 error = kauth_authorize_device_tty(l->l_cred, 999 KAUTH_DEVICE_TTY_PRIVSET, tp); 1000 break; 1001 default: 1002 /* nothing */ 1003 break; 1004 } 1005 if (error) { 1006 return error; 1007 } 1008 1009 mutex_spin_enter(&sc->sc_lock); 1010 1011 switch (cmd) { 1012 case TIOCSBRK: 1013 com_break(sc, 1); 1014 break; 1015 1016 case TIOCCBRK: 1017 com_break(sc, 0); 1018 break; 1019 1020 case TIOCSDTR: 1021 com_modem(sc, 1); 1022 break; 1023 1024 case TIOCCDTR: 1025 com_modem(sc, 0); 1026 break; 1027 1028 case TIOCGFLAGS: 1029 *(int *)data = sc->sc_swflags; 1030 break; 1031 1032 case TIOCSFLAGS: 1033 sc->sc_swflags = *(int *)data; 1034 break; 1035 1036 case TIOCMSET: 1037 case TIOCMBIS: 1038 case TIOCMBIC: 1039 tiocm_to_com(sc, cmd, *(int *)data); 1040 break; 1041 1042 case TIOCMGET: 1043 *(int *)data = com_to_tiocm(sc); 1044 break; 1045 1046 #ifdef __HAVE_TIMECOUNTER 1047 case PPS_IOC_CREATE: 1048 case PPS_IOC_DESTROY: 1049 case PPS_IOC_GETPARAMS: 1050 case PPS_IOC_SETPARAMS: 1051 case PPS_IOC_GETCAP: 1052 case PPS_IOC_FETCH: 1053 #ifdef PPS_SYNC 1054 case PPS_IOC_KCBIND: 1055 #endif 1056 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1057 break; 1058 #else /* !__HAVE_TIMECOUNTER */ 1059 case PPS_IOC_CREATE: 1060 break; 1061 1062 case PPS_IOC_DESTROY: 1063 break; 1064 1065 case PPS_IOC_GETPARAMS: { 1066 pps_params_t *pp; 1067 pp = (pps_params_t *)data; 1068 *pp = sc->ppsparam; 1069 break; 1070 } 1071 1072 case PPS_IOC_SETPARAMS: { 1073 pps_params_t *pp; 1074 int mode; 1075 pp = (pps_params_t *)data; 1076 if (pp->mode & ~ppscap) { 1077 error = EINVAL; 1078 break; 1079 } 1080 sc->ppsparam = *pp; 1081 /* 1082 * Compute msr masks from user-specified timestamp state. 1083 */ 1084 mode = sc->ppsparam.mode; 1085 switch (mode & PPS_CAPTUREBOTH) { 1086 case 0: 1087 sc->sc_ppsmask = 0; 1088 break; 1089 1090 case PPS_CAPTUREASSERT: 1091 sc->sc_ppsmask = MSR_DCD; 1092 sc->sc_ppsassert = MSR_DCD; 1093 sc->sc_ppsclear = -1; 1094 break; 1095 1096 case PPS_CAPTURECLEAR: 1097 sc->sc_ppsmask = MSR_DCD; 1098 sc->sc_ppsassert = -1; 1099 sc->sc_ppsclear = 0; 1100 break; 1101 1102 case PPS_CAPTUREBOTH: 1103 sc->sc_ppsmask = MSR_DCD; 1104 sc->sc_ppsassert = MSR_DCD; 1105 sc->sc_ppsclear = 0; 1106 break; 1107 1108 default: 1109 error = EINVAL; 1110 break; 1111 } 1112 break; 1113 } 1114 1115 case PPS_IOC_GETCAP: 1116 *(int*)data = ppscap; 1117 break; 1118 1119 case PPS_IOC_FETCH: { 1120 pps_info_t *pi; 1121 pi = (pps_info_t *)data; 1122 *pi = sc->ppsinfo; 1123 break; 1124 } 1125 1126 #ifdef PPS_SYNC 1127 case PPS_IOC_KCBIND: { 1128 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1129 1130 if (edge == 0) { 1131 /* 1132 * remove binding for this source; ignore 1133 * the request if this is not the current 1134 * hardpps source 1135 */ 1136 if (pps_kc_hardpps_source == sc) { 1137 pps_kc_hardpps_source = NULL; 1138 pps_kc_hardpps_mode = 0; 1139 } 1140 } else { 1141 /* 1142 * bind hardpps to this source, replacing any 1143 * previously specified source or edges 1144 */ 1145 pps_kc_hardpps_source = sc; 1146 pps_kc_hardpps_mode = edge; 1147 } 1148 break; 1149 } 1150 #endif /* PPS_SYNC */ 1151 #endif /* !__HAVE_TIMECOUNTER */ 1152 1153 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1154 #ifdef __HAVE_TIMECOUNTER 1155 #ifndef PPS_TRAILING_EDGE 1156 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1157 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1158 #else 1159 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1160 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1161 #endif 1162 #else /* !__HAVE_TIMECOUNTER */ 1163 /* 1164 * Some GPS clocks models use the falling rather than 1165 * rising edge as the on-the-second signal. 1166 * The old API has no way to specify PPS polarity. 1167 */ 1168 sc->sc_ppsmask = MSR_DCD; 1169 #ifndef PPS_TRAILING_EDGE 1170 sc->sc_ppsassert = MSR_DCD; 1171 sc->sc_ppsclear = -1; 1172 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1173 &sc->ppsinfo.assert_timestamp); 1174 #else 1175 sc->sc_ppsassert = -1; 1176 sc->sc_ppsclear = 0; 1177 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1178 &sc->ppsinfo.clear_timestamp); 1179 #endif 1180 #endif /* !__HAVE_TIMECOUNTER */ 1181 break; 1182 1183 default: 1184 error = EPASSTHROUGH; 1185 break; 1186 } 1187 1188 mutex_spin_exit(&sc->sc_lock); 1189 1190 #ifdef COM_DEBUG 1191 if (com_debug) 1192 comstatus(sc, "comioctl "); 1193 #endif 1194 1195 return (error); 1196 } 1197 1198 integrate void 1199 com_schedrx(struct com_softc *sc) 1200 { 1201 1202 sc->sc_rx_ready = 1; 1203 1204 /* Wake up the poller. */ 1205 softint_schedule(sc->sc_si); 1206 } 1207 1208 void 1209 com_break(struct com_softc *sc, int onoff) 1210 { 1211 1212 if (onoff) 1213 SET(sc->sc_lcr, LCR_SBREAK); 1214 else 1215 CLR(sc->sc_lcr, LCR_SBREAK); 1216 1217 if (!sc->sc_heldchange) { 1218 if (sc->sc_tx_busy) { 1219 sc->sc_heldtbc = sc->sc_tbc; 1220 sc->sc_tbc = 0; 1221 sc->sc_heldchange = 1; 1222 } else 1223 com_loadchannelregs(sc); 1224 } 1225 } 1226 1227 void 1228 com_modem(struct com_softc *sc, int onoff) 1229 { 1230 1231 if (sc->sc_mcr_dtr == 0) 1232 return; 1233 1234 if (onoff) 1235 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1236 else 1237 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1238 1239 if (!sc->sc_heldchange) { 1240 if (sc->sc_tx_busy) { 1241 sc->sc_heldtbc = sc->sc_tbc; 1242 sc->sc_tbc = 0; 1243 sc->sc_heldchange = 1; 1244 } else 1245 com_loadchannelregs(sc); 1246 } 1247 } 1248 1249 void 1250 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1251 { 1252 u_char combits; 1253 1254 combits = 0; 1255 if (ISSET(ttybits, TIOCM_DTR)) 1256 SET(combits, MCR_DTR); 1257 if (ISSET(ttybits, TIOCM_RTS)) 1258 SET(combits, MCR_RTS); 1259 1260 switch (how) { 1261 case TIOCMBIC: 1262 CLR(sc->sc_mcr, combits); 1263 break; 1264 1265 case TIOCMBIS: 1266 SET(sc->sc_mcr, combits); 1267 break; 1268 1269 case TIOCMSET: 1270 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1271 SET(sc->sc_mcr, combits); 1272 break; 1273 } 1274 1275 if (!sc->sc_heldchange) { 1276 if (sc->sc_tx_busy) { 1277 sc->sc_heldtbc = sc->sc_tbc; 1278 sc->sc_tbc = 0; 1279 sc->sc_heldchange = 1; 1280 } else 1281 com_loadchannelregs(sc); 1282 } 1283 } 1284 1285 int 1286 com_to_tiocm(struct com_softc *sc) 1287 { 1288 u_char combits; 1289 int ttybits = 0; 1290 1291 combits = sc->sc_mcr; 1292 if (ISSET(combits, MCR_DTR)) 1293 SET(ttybits, TIOCM_DTR); 1294 if (ISSET(combits, MCR_RTS)) 1295 SET(ttybits, TIOCM_RTS); 1296 1297 combits = sc->sc_msr; 1298 if (ISSET(combits, MSR_DCD)) 1299 SET(ttybits, TIOCM_CD); 1300 if (ISSET(combits, MSR_CTS)) 1301 SET(ttybits, TIOCM_CTS); 1302 if (ISSET(combits, MSR_DSR)) 1303 SET(ttybits, TIOCM_DSR); 1304 if (ISSET(combits, MSR_RI | MSR_TERI)) 1305 SET(ttybits, TIOCM_RI); 1306 1307 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1308 SET(ttybits, TIOCM_LE); 1309 1310 return (ttybits); 1311 } 1312 1313 static u_char 1314 cflag2lcr(tcflag_t cflag) 1315 { 1316 u_char lcr = 0; 1317 1318 switch (ISSET(cflag, CSIZE)) { 1319 case CS5: 1320 SET(lcr, LCR_5BITS); 1321 break; 1322 case CS6: 1323 SET(lcr, LCR_6BITS); 1324 break; 1325 case CS7: 1326 SET(lcr, LCR_7BITS); 1327 break; 1328 case CS8: 1329 SET(lcr, LCR_8BITS); 1330 break; 1331 } 1332 if (ISSET(cflag, PARENB)) { 1333 SET(lcr, LCR_PENAB); 1334 if (!ISSET(cflag, PARODD)) 1335 SET(lcr, LCR_PEVEN); 1336 } 1337 if (ISSET(cflag, CSTOPB)) 1338 SET(lcr, LCR_STOPB); 1339 1340 return (lcr); 1341 } 1342 1343 int 1344 comparam(struct tty *tp, struct termios *t) 1345 { 1346 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1347 int ospeed; 1348 u_char lcr; 1349 1350 if (COM_ISALIVE(sc) == 0) 1351 return (EIO); 1352 1353 #ifdef COM_HAYESP 1354 if (sc->sc_type == COM_TYPE_HAYESP) { 1355 int prescaler, speed; 1356 1357 /* 1358 * Calculate UART clock prescaler. It should be in 1359 * range of 0 .. 3. 1360 */ 1361 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1362 prescaler++, speed /= 2) 1363 if ((ospeed = comspeed(speed, sc->sc_frequency, 1364 sc->sc_type)) > 0) 1365 break; 1366 1367 if (prescaler == 4) 1368 return (EINVAL); 1369 sc->sc_prescaler = prescaler; 1370 } else 1371 #endif 1372 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1373 1374 /* Check requested parameters. */ 1375 if (ospeed < 0) 1376 return (EINVAL); 1377 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1378 return (EINVAL); 1379 1380 /* 1381 * For the console, always force CLOCAL and !HUPCL, so that the port 1382 * is always active. 1383 */ 1384 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1385 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1386 SET(t->c_cflag, CLOCAL); 1387 CLR(t->c_cflag, HUPCL); 1388 } 1389 1390 /* 1391 * If there were no changes, don't do anything. This avoids dropping 1392 * input and improves performance when all we did was frob things like 1393 * VMIN and VTIME. 1394 */ 1395 if (tp->t_ospeed == t->c_ospeed && 1396 tp->t_cflag == t->c_cflag) 1397 return (0); 1398 1399 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1400 1401 mutex_spin_enter(&sc->sc_lock); 1402 1403 sc->sc_lcr = lcr; 1404 1405 /* 1406 * If we're not in a mode that assumes a connection is present, then 1407 * ignore carrier changes. 1408 */ 1409 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1410 sc->sc_msr_dcd = 0; 1411 else 1412 sc->sc_msr_dcd = MSR_DCD; 1413 /* 1414 * Set the flow control pins depending on the current flow control 1415 * mode. 1416 */ 1417 if (ISSET(t->c_cflag, CRTSCTS)) { 1418 sc->sc_mcr_dtr = MCR_DTR; 1419 sc->sc_mcr_rts = MCR_RTS; 1420 sc->sc_msr_cts = MSR_CTS; 1421 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1422 } else if (ISSET(t->c_cflag, MDMBUF)) { 1423 /* 1424 * For DTR/DCD flow control, make sure we don't toggle DTR for 1425 * carrier detection. 1426 */ 1427 sc->sc_mcr_dtr = 0; 1428 sc->sc_mcr_rts = MCR_DTR; 1429 sc->sc_msr_cts = MSR_DCD; 1430 sc->sc_efr = 0; 1431 } else { 1432 /* 1433 * If no flow control, then always set RTS. This will make 1434 * the other side happy if it mistakenly thinks we're doing 1435 * RTS/CTS flow control. 1436 */ 1437 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1438 sc->sc_mcr_rts = 0; 1439 sc->sc_msr_cts = 0; 1440 sc->sc_efr = 0; 1441 if (ISSET(sc->sc_mcr, MCR_DTR)) 1442 SET(sc->sc_mcr, MCR_RTS); 1443 else 1444 CLR(sc->sc_mcr, MCR_RTS); 1445 } 1446 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1447 1448 #if 0 1449 if (ospeed == 0) 1450 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1451 else 1452 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1453 #endif 1454 1455 sc->sc_dlbl = ospeed; 1456 sc->sc_dlbh = ospeed >> 8; 1457 1458 /* 1459 * Set the FIFO threshold based on the receive speed. 1460 * 1461 * * If it's a low speed, it's probably a mouse or some other 1462 * interactive device, so set the threshold low. 1463 * * If it's a high speed, trim the trigger level down to prevent 1464 * overflows. 1465 * * Otherwise set it a bit higher. 1466 */ 1467 if (sc->sc_type == COM_TYPE_HAYESP) 1468 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1469 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1470 sc->sc_fifo = FIFO_ENABLE | 1471 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1472 else 1473 sc->sc_fifo = 0; 1474 1475 /* And copy to tty. */ 1476 tp->t_ispeed = t->c_ospeed; 1477 tp->t_ospeed = t->c_ospeed; 1478 tp->t_cflag = t->c_cflag; 1479 1480 if (!sc->sc_heldchange) { 1481 if (sc->sc_tx_busy) { 1482 sc->sc_heldtbc = sc->sc_tbc; 1483 sc->sc_tbc = 0; 1484 sc->sc_heldchange = 1; 1485 } else 1486 com_loadchannelregs(sc); 1487 } 1488 1489 if (!ISSET(t->c_cflag, CHWFLOW)) { 1490 /* Disable the high water mark. */ 1491 sc->sc_r_hiwat = 0; 1492 sc->sc_r_lowat = 0; 1493 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1494 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1495 com_schedrx(sc); 1496 } 1497 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1498 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1499 com_hwiflow(sc); 1500 } 1501 } else { 1502 sc->sc_r_hiwat = com_rbuf_hiwat; 1503 sc->sc_r_lowat = com_rbuf_lowat; 1504 } 1505 1506 mutex_spin_exit(&sc->sc_lock); 1507 1508 /* 1509 * Update the tty layer's idea of the carrier bit, in case we changed 1510 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1511 * explicit request. 1512 */ 1513 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1514 1515 #ifdef COM_DEBUG 1516 if (com_debug) 1517 comstatus(sc, "comparam "); 1518 #endif 1519 1520 if (!ISSET(t->c_cflag, CHWFLOW)) { 1521 if (sc->sc_tx_stopped) { 1522 sc->sc_tx_stopped = 0; 1523 comstart(tp); 1524 } 1525 } 1526 1527 return (0); 1528 } 1529 1530 void 1531 com_iflush(struct com_softc *sc) 1532 { 1533 struct com_regs *regsp = &sc->sc_regs; 1534 #ifdef DIAGNOSTIC 1535 int reg; 1536 #endif 1537 int timo; 1538 1539 #ifdef DIAGNOSTIC 1540 reg = 0xffff; 1541 #endif 1542 timo = 50000; 1543 /* flush any pending I/O */ 1544 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1545 && --timo) 1546 #ifdef DIAGNOSTIC 1547 reg = 1548 #else 1549 (void) 1550 #endif 1551 CSR_READ_1(regsp, COM_REG_RXDATA); 1552 #ifdef DIAGNOSTIC 1553 if (!timo) 1554 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1555 reg); 1556 #endif 1557 } 1558 1559 void 1560 com_loadchannelregs(struct com_softc *sc) 1561 { 1562 struct com_regs *regsp = &sc->sc_regs; 1563 1564 /* XXXXX necessary? */ 1565 com_iflush(sc); 1566 1567 if (sc->sc_type == COM_TYPE_PXA2x0) 1568 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1569 else 1570 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1571 1572 if (sc->sc_type == COM_TYPE_OMAP) { 1573 /* disable before changing settings */ 1574 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1575 } 1576 1577 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1578 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1579 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1580 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1581 } 1582 } 1583 if (sc->sc_type == COM_TYPE_AU1x00) { 1584 /* alchemy has single separate 16-bit clock divisor register */ 1585 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1586 (sc->sc_dlbh << 8)); 1587 } else { 1588 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1589 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1590 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1591 } 1592 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1593 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1594 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1595 #ifdef COM_HAYESP 1596 if (sc->sc_type == COM_TYPE_HAYESP) { 1597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1598 HAYESP_SETPRESCALER); 1599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1600 sc->sc_prescaler); 1601 } 1602 #endif 1603 if (sc->sc_type == COM_TYPE_OMAP) { 1604 /* setup the fifos. the FCR value is not used as long 1605 as SCR[6] and SCR[7] are 0, which they are at reset 1606 and we never touch the SCR register */ 1607 uint8_t rx_fifo_trig = 40; 1608 uint8_t tx_fifo_trig = 60; 1609 uint8_t rx_start = 8; 1610 uint8_t rx_halt = 60; 1611 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1612 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1613 1614 /* enable access to TCR & TLR */ 1615 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1616 1617 /* write tcr and tlr values */ 1618 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1619 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1620 1621 /* disable access to TCR & TLR */ 1622 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1623 1624 /* enable again, but mode is based on speed */ 1625 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1626 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1627 } else { 1628 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1629 } 1630 } 1631 1632 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1633 } 1634 1635 int 1636 comhwiflow(struct tty *tp, int block) 1637 { 1638 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1639 1640 if (COM_ISALIVE(sc) == 0) 1641 return (0); 1642 1643 if (sc->sc_mcr_rts == 0) 1644 return (0); 1645 1646 mutex_spin_enter(&sc->sc_lock); 1647 1648 if (block) { 1649 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1650 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1651 com_hwiflow(sc); 1652 } 1653 } else { 1654 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1655 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1656 com_schedrx(sc); 1657 } 1658 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1659 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1660 com_hwiflow(sc); 1661 } 1662 } 1663 1664 mutex_spin_exit(&sc->sc_lock); 1665 return (1); 1666 } 1667 1668 /* 1669 * (un)block input via hw flowcontrol 1670 */ 1671 void 1672 com_hwiflow(struct com_softc *sc) 1673 { 1674 struct com_regs *regsp= &sc->sc_regs; 1675 1676 if (sc->sc_mcr_rts == 0) 1677 return; 1678 1679 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1680 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1681 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1682 } else { 1683 SET(sc->sc_mcr, sc->sc_mcr_rts); 1684 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1685 } 1686 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1687 } 1688 1689 1690 void 1691 comstart(struct tty *tp) 1692 { 1693 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1694 struct com_regs *regsp = &sc->sc_regs; 1695 int s; 1696 1697 if (COM_ISALIVE(sc) == 0) 1698 return; 1699 1700 s = spltty(); 1701 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1702 goto out; 1703 if (sc->sc_tx_stopped) 1704 goto out; 1705 if (!ttypull(tp)) 1706 goto out; 1707 1708 /* Grab the first contiguous region of buffer space. */ 1709 { 1710 u_char *tba; 1711 int tbc; 1712 1713 tba = tp->t_outq.c_cf; 1714 tbc = ndqb(&tp->t_outq, 0); 1715 1716 mutex_spin_enter(&sc->sc_lock); 1717 1718 sc->sc_tba = tba; 1719 sc->sc_tbc = tbc; 1720 } 1721 1722 SET(tp->t_state, TS_BUSY); 1723 sc->sc_tx_busy = 1; 1724 1725 /* Enable transmit completion interrupts if necessary. */ 1726 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1727 SET(sc->sc_ier, IER_ETXRDY); 1728 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1729 } 1730 1731 /* Output the first chunk of the contiguous buffer. */ 1732 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1733 u_int n; 1734 1735 n = sc->sc_tbc; 1736 if (n > sc->sc_fifolen) 1737 n = sc->sc_fifolen; 1738 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1739 sc->sc_tbc -= n; 1740 sc->sc_tba += n; 1741 } 1742 1743 mutex_spin_exit(&sc->sc_lock); 1744 out: 1745 splx(s); 1746 return; 1747 } 1748 1749 /* 1750 * Stop output on a line. 1751 */ 1752 void 1753 comstop(struct tty *tp, int flag) 1754 { 1755 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1756 1757 mutex_spin_enter(&sc->sc_lock); 1758 if (ISSET(tp->t_state, TS_BUSY)) { 1759 /* Stop transmitting at the next chunk. */ 1760 sc->sc_tbc = 0; 1761 sc->sc_heldtbc = 0; 1762 if (!ISSET(tp->t_state, TS_TTSTOP)) 1763 SET(tp->t_state, TS_FLUSH); 1764 } 1765 mutex_spin_exit(&sc->sc_lock); 1766 } 1767 1768 void 1769 comdiag(void *arg) 1770 { 1771 struct com_softc *sc = arg; 1772 int overflows, floods; 1773 1774 mutex_spin_enter(&sc->sc_lock); 1775 overflows = sc->sc_overflows; 1776 sc->sc_overflows = 0; 1777 floods = sc->sc_floods; 1778 sc->sc_floods = 0; 1779 sc->sc_errors = 0; 1780 mutex_spin_exit(&sc->sc_lock); 1781 1782 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1783 sc->sc_dev.dv_xname, 1784 overflows, overflows == 1 ? "" : "s", 1785 floods, floods == 1 ? "" : "s"); 1786 } 1787 1788 integrate void 1789 com_rxsoft(struct com_softc *sc, struct tty *tp) 1790 { 1791 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1792 u_char *get, *end; 1793 u_int cc, scc; 1794 u_char lsr; 1795 int code; 1796 1797 end = sc->sc_ebuf; 1798 get = sc->sc_rbget; 1799 scc = cc = com_rbuf_size - sc->sc_rbavail; 1800 1801 if (cc == com_rbuf_size) { 1802 sc->sc_floods++; 1803 if (sc->sc_errors++ == 0) 1804 callout_reset(&sc->sc_diag_callout, 60 * hz, 1805 comdiag, sc); 1806 } 1807 1808 /* If not yet open, drop the entire buffer content here */ 1809 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1810 get += cc << 1; 1811 if (get >= end) 1812 get -= com_rbuf_size << 1; 1813 cc = 0; 1814 } 1815 while (cc) { 1816 code = get[0]; 1817 lsr = get[1]; 1818 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1819 if (ISSET(lsr, LSR_OE)) { 1820 sc->sc_overflows++; 1821 if (sc->sc_errors++ == 0) 1822 callout_reset(&sc->sc_diag_callout, 1823 60 * hz, comdiag, sc); 1824 } 1825 if (ISSET(lsr, LSR_BI | LSR_FE)) 1826 SET(code, TTY_FE); 1827 if (ISSET(lsr, LSR_PE)) 1828 SET(code, TTY_PE); 1829 } 1830 if ((*rint)(code, tp) == -1) { 1831 /* 1832 * The line discipline's buffer is out of space. 1833 */ 1834 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1835 /* 1836 * We're either not using flow control, or the 1837 * line discipline didn't tell us to block for 1838 * some reason. Either way, we have no way to 1839 * know when there's more space available, so 1840 * just drop the rest of the data. 1841 */ 1842 get += cc << 1; 1843 if (get >= end) 1844 get -= com_rbuf_size << 1; 1845 cc = 0; 1846 } else { 1847 /* 1848 * Don't schedule any more receive processing 1849 * until the line discipline tells us there's 1850 * space available (through comhwiflow()). 1851 * Leave the rest of the data in the input 1852 * buffer. 1853 */ 1854 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1855 } 1856 break; 1857 } 1858 get += 2; 1859 if (get >= end) 1860 get = sc->sc_rbuf; 1861 cc--; 1862 } 1863 1864 if (cc != scc) { 1865 sc->sc_rbget = get; 1866 mutex_spin_enter(&sc->sc_lock); 1867 1868 cc = sc->sc_rbavail += scc - cc; 1869 /* Buffers should be ok again, release possible block. */ 1870 if (cc >= sc->sc_r_lowat) { 1871 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1872 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1873 SET(sc->sc_ier, IER_ERXRDY); 1874 #ifdef COM_PXA2X0 1875 if (sc->sc_type == COM_TYPE_PXA2x0) 1876 SET(sc->sc_ier, IER_ERXTOUT); 1877 #endif 1878 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1879 } 1880 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1881 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1882 com_hwiflow(sc); 1883 } 1884 } 1885 mutex_spin_exit(&sc->sc_lock); 1886 } 1887 } 1888 1889 integrate void 1890 com_txsoft(struct com_softc *sc, struct tty *tp) 1891 { 1892 1893 CLR(tp->t_state, TS_BUSY); 1894 if (ISSET(tp->t_state, TS_FLUSH)) 1895 CLR(tp->t_state, TS_FLUSH); 1896 else 1897 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1898 (*tp->t_linesw->l_start)(tp); 1899 } 1900 1901 integrate void 1902 com_stsoft(struct com_softc *sc, struct tty *tp) 1903 { 1904 u_char msr, delta; 1905 1906 mutex_spin_enter(&sc->sc_lock); 1907 msr = sc->sc_msr; 1908 delta = sc->sc_msr_delta; 1909 sc->sc_msr_delta = 0; 1910 mutex_spin_exit(&sc->sc_lock); 1911 1912 if (ISSET(delta, sc->sc_msr_dcd)) { 1913 /* 1914 * Inform the tty layer that carrier detect changed. 1915 */ 1916 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1917 } 1918 1919 if (ISSET(delta, sc->sc_msr_cts)) { 1920 /* Block or unblock output according to flow control. */ 1921 if (ISSET(msr, sc->sc_msr_cts)) { 1922 sc->sc_tx_stopped = 0; 1923 (*tp->t_linesw->l_start)(tp); 1924 } else { 1925 sc->sc_tx_stopped = 1; 1926 } 1927 } 1928 1929 #ifdef COM_DEBUG 1930 if (com_debug) 1931 comstatus(sc, "com_stsoft"); 1932 #endif 1933 } 1934 1935 void 1936 comsoft(void *arg) 1937 { 1938 struct com_softc *sc = arg; 1939 struct tty *tp; 1940 1941 if (COM_ISALIVE(sc) == 0) 1942 return; 1943 1944 tp = sc->sc_tty; 1945 1946 if (sc->sc_rx_ready) { 1947 sc->sc_rx_ready = 0; 1948 com_rxsoft(sc, tp); 1949 } 1950 1951 if (sc->sc_st_check) { 1952 sc->sc_st_check = 0; 1953 com_stsoft(sc, tp); 1954 } 1955 1956 if (sc->sc_tx_done) { 1957 sc->sc_tx_done = 0; 1958 com_txsoft(sc, tp); 1959 } 1960 } 1961 1962 int 1963 comintr(void *arg) 1964 { 1965 struct com_softc *sc = arg; 1966 struct com_regs *regsp = &sc->sc_regs; 1967 1968 u_char *put, *end; 1969 u_int cc; 1970 u_char lsr, iir; 1971 1972 if (COM_ISALIVE(sc) == 0) 1973 return (0); 1974 1975 mutex_spin_enter(&sc->sc_lock); 1976 iir = CSR_READ_1(regsp, COM_REG_IIR); 1977 if (ISSET(iir, IIR_NOPEND)) { 1978 mutex_spin_exit(&sc->sc_lock); 1979 return (0); 1980 } 1981 1982 end = sc->sc_ebuf; 1983 put = sc->sc_rbput; 1984 cc = sc->sc_rbavail; 1985 1986 again: do { 1987 u_char msr, delta; 1988 1989 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1990 if (ISSET(lsr, LSR_BI)) { 1991 int cn_trapped = 0; 1992 1993 cn_check_magic(sc->sc_tty->t_dev, 1994 CNC_BREAK, com_cnm_state); 1995 if (cn_trapped) 1996 continue; 1997 #if defined(KGDB) && !defined(DDB) 1998 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1999 kgdb_connect(1); 2000 continue; 2001 } 2002 #endif 2003 } 2004 2005 if (ISSET(lsr, LSR_RCV_MASK) && 2006 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2007 while (cc > 0) { 2008 int cn_trapped = 0; 2009 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2010 put[1] = lsr; 2011 cn_check_magic(sc->sc_tty->t_dev, 2012 put[0], com_cnm_state); 2013 if (cn_trapped) 2014 goto next; 2015 put += 2; 2016 if (put >= end) 2017 put = sc->sc_rbuf; 2018 cc--; 2019 next: 2020 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2021 if (!ISSET(lsr, LSR_RCV_MASK)) 2022 break; 2023 } 2024 2025 /* 2026 * Current string of incoming characters ended because 2027 * no more data was available or we ran out of space. 2028 * Schedule a receive event if any data was received. 2029 * If we're out of space, turn off receive interrupts. 2030 */ 2031 sc->sc_rbput = put; 2032 sc->sc_rbavail = cc; 2033 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2034 sc->sc_rx_ready = 1; 2035 2036 /* 2037 * See if we are in danger of overflowing a buffer. If 2038 * so, use hardware flow control to ease the pressure. 2039 */ 2040 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2041 cc < sc->sc_r_hiwat) { 2042 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2043 com_hwiflow(sc); 2044 } 2045 2046 /* 2047 * If we're out of space, disable receive interrupts 2048 * until the queue has drained a bit. 2049 */ 2050 if (!cc) { 2051 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2052 #ifdef COM_PXA2X0 2053 if (sc->sc_type == COM_TYPE_PXA2x0) 2054 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2055 else 2056 #endif 2057 CLR(sc->sc_ier, IER_ERXRDY); 2058 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2059 } 2060 } else { 2061 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2062 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2063 continue; 2064 } 2065 } 2066 2067 msr = CSR_READ_1(regsp, COM_REG_MSR); 2068 delta = msr ^ sc->sc_msr; 2069 sc->sc_msr = msr; 2070 #ifdef __HAVE_TIMECOUNTER 2071 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2072 (delta & MSR_DCD)) { 2073 pps_capture(&sc->sc_pps_state); 2074 pps_event(&sc->sc_pps_state, 2075 (msr & MSR_DCD) ? 2076 PPS_CAPTUREASSERT : 2077 PPS_CAPTURECLEAR); 2078 } 2079 #else /* !__HAVE_TIMECOUNTER */ 2080 /* 2081 * Pulse-per-second (PSS) signals on edge of DCD? 2082 * Process these even if line discipline is ignoring DCD. 2083 */ 2084 if (delta & sc->sc_ppsmask) { 2085 struct timeval tv; 2086 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2087 /* XXX nanotime() */ 2088 microtime(&tv); 2089 TIMEVAL_TO_TIMESPEC(&tv, 2090 &sc->ppsinfo.assert_timestamp); 2091 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2092 timespecadd(&sc->ppsinfo.assert_timestamp, 2093 &sc->ppsparam.assert_offset, 2094 &sc->ppsinfo.assert_timestamp); 2095 } 2096 2097 #ifdef PPS_SYNC 2098 if (pps_kc_hardpps_source == sc && 2099 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2100 hardpps(&tv, tv.tv_usec); 2101 } 2102 #endif 2103 sc->ppsinfo.assert_sequence++; 2104 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2105 2106 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2107 /* XXX nanotime() */ 2108 microtime(&tv); 2109 TIMEVAL_TO_TIMESPEC(&tv, 2110 &sc->ppsinfo.clear_timestamp); 2111 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2112 timespecadd(&sc->ppsinfo.clear_timestamp, 2113 &sc->ppsparam.clear_offset, 2114 &sc->ppsinfo.clear_timestamp); 2115 } 2116 2117 #ifdef PPS_SYNC 2118 if (pps_kc_hardpps_source == sc && 2119 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2120 hardpps(&tv, tv.tv_usec); 2121 } 2122 #endif 2123 sc->ppsinfo.clear_sequence++; 2124 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2125 } 2126 } 2127 #endif /* !__HAVE_TIMECOUNTER */ 2128 2129 /* 2130 * Process normal status changes 2131 */ 2132 if (ISSET(delta, sc->sc_msr_mask)) { 2133 SET(sc->sc_msr_delta, delta); 2134 2135 /* 2136 * Stop output immediately if we lose the output 2137 * flow control signal or carrier detect. 2138 */ 2139 if (ISSET(~msr, sc->sc_msr_mask)) { 2140 sc->sc_tbc = 0; 2141 sc->sc_heldtbc = 0; 2142 #ifdef COM_DEBUG 2143 if (com_debug) 2144 comstatus(sc, "comintr "); 2145 #endif 2146 } 2147 2148 sc->sc_st_check = 1; 2149 } 2150 } while (!ISSET((iir = 2151 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2152 /* 2153 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2154 * by IIR read, so we can't do this way: `process all interrupts, 2155 * then do TX if possble'. 2156 */ 2157 (iir & IIR_IMASK) != IIR_TXRDY); 2158 2159 /* 2160 * Read LSR again, since there may be an interrupt between 2161 * the last LSR read and IIR read above. 2162 */ 2163 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2164 2165 /* 2166 * See if data can be transmitted as well. 2167 * Schedule tx done event if no data left 2168 * and tty was marked busy. 2169 */ 2170 if (ISSET(lsr, LSR_TXRDY)) { 2171 /* 2172 * If we've delayed a parameter change, do it now, and restart 2173 * output. 2174 */ 2175 if (sc->sc_heldchange) { 2176 com_loadchannelregs(sc); 2177 sc->sc_heldchange = 0; 2178 sc->sc_tbc = sc->sc_heldtbc; 2179 sc->sc_heldtbc = 0; 2180 } 2181 2182 /* Output the next chunk of the contiguous buffer, if any. */ 2183 if (sc->sc_tbc > 0) { 2184 u_int n; 2185 2186 n = sc->sc_tbc; 2187 if (n > sc->sc_fifolen) 2188 n = sc->sc_fifolen; 2189 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2190 sc->sc_tbc -= n; 2191 sc->sc_tba += n; 2192 } else { 2193 /* Disable transmit completion interrupts if necessary. */ 2194 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2195 CLR(sc->sc_ier, IER_ETXRDY); 2196 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2197 } 2198 if (sc->sc_tx_busy) { 2199 sc->sc_tx_busy = 0; 2200 sc->sc_tx_done = 1; 2201 } 2202 } 2203 } 2204 2205 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2206 goto again; 2207 2208 mutex_spin_exit(&sc->sc_lock); 2209 2210 /* Wake up the poller. */ 2211 softint_schedule(sc->sc_si); 2212 2213 #if NRND > 0 && defined(RND_COM) 2214 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2215 #endif 2216 2217 return (1); 2218 } 2219 2220 /* 2221 * The following functions are polled getc and putc routines, shared 2222 * by the console and kgdb glue. 2223 * 2224 * The read-ahead code is so that you can detect pending in-band 2225 * cn_magic in polled mode while doing output rather than having to 2226 * wait until the kernel decides it needs input. 2227 */ 2228 2229 #define MAX_READAHEAD 20 2230 static int com_readahead[MAX_READAHEAD]; 2231 static int com_readaheadcount = 0; 2232 2233 int 2234 com_common_getc(dev_t dev, struct com_regs *regsp) 2235 { 2236 int s = splserial(); 2237 u_char stat, c; 2238 2239 /* got a character from reading things earlier */ 2240 if (com_readaheadcount > 0) { 2241 int i; 2242 2243 c = com_readahead[0]; 2244 for (i = 1; i < com_readaheadcount; i++) { 2245 com_readahead[i-1] = com_readahead[i]; 2246 } 2247 com_readaheadcount--; 2248 splx(s); 2249 return (c); 2250 } 2251 2252 /* block until a character becomes available */ 2253 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2254 ; 2255 2256 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2257 stat = CSR_READ_1(regsp, COM_REG_IIR); 2258 { 2259 int cn_trapped = 0; /* unused */ 2260 #ifdef DDB 2261 extern int db_active; 2262 if (!db_active) 2263 #endif 2264 cn_check_magic(dev, c, com_cnm_state); 2265 } 2266 splx(s); 2267 return (c); 2268 } 2269 2270 void 2271 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2272 { 2273 int s = splserial(); 2274 int cin, stat, timo; 2275 2276 if (com_readaheadcount < MAX_READAHEAD 2277 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2278 int cn_trapped = 0; 2279 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2280 stat = CSR_READ_1(regsp, COM_REG_IIR); 2281 cn_check_magic(dev, cin, com_cnm_state); 2282 com_readahead[com_readaheadcount++] = cin; 2283 } 2284 2285 /* wait for any pending transmission to finish */ 2286 timo = 150000; 2287 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2288 continue; 2289 2290 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2291 COM_BARRIER(regsp, BR | BW); 2292 2293 splx(s); 2294 } 2295 2296 /* 2297 * Initialize UART for use as console or KGDB line. 2298 */ 2299 int 2300 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2301 tcflag_t cflag) 2302 { 2303 2304 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2305 ®sp->cr_ioh)) 2306 return (ENOMEM); /* ??? */ 2307 2308 if (type == COM_TYPE_OMAP) { 2309 /* disable before changing settings */ 2310 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2311 } 2312 2313 rate = comspeed(rate, frequency, type); 2314 if (type != COM_TYPE_AU1x00) { 2315 /* no EFR on alchemy */ 2316 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2317 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2318 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2319 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2320 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2321 } else { 2322 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2323 } 2324 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2325 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2326 CSR_WRITE_1(regsp, COM_REG_FIFO, 2327 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2328 2329 if (type == COM_TYPE_OMAP) { 2330 /* setup the fifos. the FCR value is not used as long 2331 as SCR[6] and SCR[7] are 0, which they are at reset 2332 and we never touch the SCR register */ 2333 uint8_t rx_fifo_trig = 40; 2334 uint8_t tx_fifo_trig = 60; 2335 uint8_t rx_start = 8; 2336 uint8_t rx_halt = 60; 2337 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2338 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2339 2340 /* enable access to TCR & TLR */ 2341 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2342 2343 /* write tcr and tlr values */ 2344 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2345 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2346 2347 /* disable access to TCR & TLR */ 2348 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2349 2350 /* enable again, but mode is based on speed */ 2351 if (rate > 230400) { 2352 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2353 } else { 2354 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2355 } 2356 } 2357 2358 #ifdef COM_PXA2X0 2359 if (type == COM_TYPE_PXA2x0) 2360 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2361 else 2362 #endif 2363 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2364 2365 return (0); 2366 } 2367 2368 /* 2369 * Following are all routines needed for COM to act as console 2370 */ 2371 struct consdev comcons = { 2372 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2373 NODEV, CN_NORMAL 2374 }; 2375 2376 2377 int 2378 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2379 tcflag_t cflag) 2380 { 2381 int res; 2382 2383 comconsregs = *regsp; 2384 2385 res = cominit(&comconsregs, rate, frequency, type, cflag); 2386 if (res) 2387 return (res); 2388 2389 cn_tab = &comcons; 2390 cn_init_magic(&com_cnm_state); 2391 cn_set_magic("\047\001"); /* default magic is BREAK */ 2392 2393 comconsrate = rate; 2394 comconscflag = cflag; 2395 2396 return (0); 2397 } 2398 2399 int 2400 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2401 int type, tcflag_t cflag) 2402 { 2403 struct com_regs regs; 2404 2405 memset(®s, 0, sizeof regs); 2406 regs.cr_iot = iot; 2407 regs.cr_iobase = iobase; 2408 regs.cr_nports = COM_NPORTS; 2409 #ifdef COM_REGMAP 2410 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2411 #endif 2412 2413 return comcnattach1(®s, rate, frequency, type, cflag); 2414 } 2415 2416 int 2417 comcngetc(dev_t dev) 2418 { 2419 2420 return (com_common_getc(dev, &comconsregs)); 2421 } 2422 2423 /* 2424 * Console kernel output character routine. 2425 */ 2426 void 2427 comcnputc(dev_t dev, int c) 2428 { 2429 2430 com_common_putc(dev, &comconsregs, c); 2431 } 2432 2433 void 2434 comcnpollc(dev_t dev, int on) 2435 { 2436 2437 } 2438 2439 #ifdef KGDB 2440 int 2441 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2442 tcflag_t cflag) 2443 { 2444 int res; 2445 2446 if (regsp->cr_iot == comconsregs.cr_iot && 2447 regsp->cr_iobase == comconsregs.cr_iobase) { 2448 #if !defined(DDB) 2449 return (EBUSY); /* cannot share with console */ 2450 #else 2451 comkgdbregs = *regsp; 2452 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2453 #endif 2454 } else { 2455 comkgdbregs = *regsp; 2456 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2457 if (res) 2458 return (res); 2459 2460 /* 2461 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2462 * expects this to be initialized 2463 */ 2464 cn_init_magic(&com_cnm_state); 2465 cn_set_magic("\047\001"); 2466 } 2467 2468 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2469 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2470 2471 return (0); 2472 } 2473 2474 int 2475 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2476 int frequency, int type, tcflag_t cflag) 2477 { 2478 struct com_regs regs; 2479 2480 regs.cr_iot = iot; 2481 regs.cr_nports = COM_NPORTS; 2482 regs.cr_iobase = iobase; 2483 #ifdef COM_REGMAP 2484 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2485 #endif 2486 2487 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2488 } 2489 2490 /* ARGSUSED */ 2491 int 2492 com_kgdb_getc(void *arg) 2493 { 2494 2495 return (com_common_getc(NODEV, &comkgdbregs)); 2496 } 2497 2498 /* ARGSUSED */ 2499 void 2500 com_kgdb_putc(void *arg, int c) 2501 { 2502 2503 com_common_putc(NODEV, &comkgdbregs, c); 2504 } 2505 #endif /* KGDB */ 2506 2507 /* helper function to identify the com ports used by 2508 console or KGDB (and not yet autoconf attached) */ 2509 int 2510 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2511 { 2512 bus_space_handle_t help; 2513 2514 if (!comconsattached && 2515 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2516 help = comconsregs.cr_ioh; 2517 #ifdef KGDB 2518 else if (!com_kgdb_attached && 2519 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2520 help = comkgdbregs.cr_ioh; 2521 #endif 2522 else 2523 return (0); 2524 2525 if (ioh) 2526 *ioh = help; 2527 return (1); 2528 } 2529 2530 /* 2531 * this routine exists to serve as a shutdown hook for systems that 2532 * have firmware which doesn't interact properly with a com device in 2533 * FIFO mode. 2534 */ 2535 void 2536 com_cleanup(void *arg) 2537 { 2538 struct com_softc *sc = arg; 2539 2540 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2541 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2542 } 2543 2544 bool 2545 com_resume(device_t dev) 2546 { 2547 struct com_softc *sc = device_private(dev); 2548 2549 mutex_spin_enter(&sc->sc_lock); 2550 com_loadchannelregs(sc); 2551 mutex_spin_exit(&sc->sc_lock); 2552 2553 return true; 2554 } 2555
Indexes created Wed Oct 22 13:09:56 GMT 2025