com.c revision 1.262.2.4
1 /* com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 182 int com_common_getc(dev_t, struct com_regs *); 183 void com_common_putc(dev_t, struct com_regs *, int); 184 185 int cominit(struct com_regs *, int, int, int, tcflag_t); 186 187 int comcngetc(dev_t); 188 void comcnputc(dev_t, int); 189 void comcnpollc(dev_t, int); 190 191 #define integrate static inline 192 void comsoft(void *); 193 integrate void com_rxsoft(struct com_softc *, struct tty *); 194 integrate void com_txsoft(struct com_softc *, struct tty *); 195 integrate void com_stsoft(struct com_softc *, struct tty *); 196 integrate void com_schedrx(struct com_softc *); 197 void comdiag(void *); 198 199 extern struct cfdriver com_cd; 200 201 dev_type_open(comopen); 202 dev_type_close(comclose); 203 dev_type_read(comread); 204 dev_type_write(comwrite); 205 dev_type_ioctl(comioctl); 206 dev_type_stop(comstop); 207 dev_type_tty(comtty); 208 dev_type_poll(compoll); 209 210 const struct cdevsw com_cdevsw = { 211 comopen, comclose, comread, comwrite, comioctl, 212 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static struct com_regs comconsregs; 226 static int comconsattached; 227 static int comconsrate; 228 static tcflag_t comconscflag; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 #ifdef COM_REGMAP 242 /* initializer for typical 16550-ish hardware */ 243 #define COM_REG_16550 { \ 244 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 245 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 246 247 const bus_size_t com_std_map[16] = COM_REG_16550; 248 #endif /* COM_REGMAP */ 249 250 #define COMUNIT_MASK 0x7ffff 251 #define COMDIALOUT_MASK 0x80000 252 253 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 254 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 255 256 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 257 device_is_active((sc)->sc_dev)) 258 259 #define BR BUS_SPACE_BARRIER_READ 260 #define BW BUS_SPACE_BARRIER_WRITE 261 #define COM_BARRIER(r, f) \ 262 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 263 264 /*ARGSUSED*/ 265 int 266 comspeed(long speed, long frequency, int type) 267 { 268 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 269 270 int x, err; 271 int divisor = 16; 272 273 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 274 divisor = 13; 275 } 276 277 #if 0 278 if (speed == 0) 279 return (0); 280 #endif 281 if (speed <= 0) 282 return (-1); 283 x = divrnd(frequency / divisor, speed); 284 if (x <= 0) 285 return (-1); 286 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 287 if (err < 0) 288 err = -err; 289 if (err > COM_TOLERANCE) 290 return (-1); 291 return (x); 292 293 #undef divrnd 294 } 295 296 #ifdef COM_DEBUG 297 int com_debug = 0; 298 299 void comstatus(struct com_softc *, const char *); 300 void 301 comstatus(struct com_softc *sc, const char *str) 302 { 303 struct tty *tp = sc->sc_tty; 304 305 aprint_normal_dev(sc->sc_dev, 306 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 307 str, 308 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 309 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 310 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 311 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 312 sc->sc_tx_stopped ? '+' : '-'); 313 314 aprint_normal_dev(sc->sc_dev, 315 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 316 str, 317 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 318 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 319 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 320 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 321 sc->sc_rx_flags); 322 } 323 #endif 324 325 int 326 com_probe_subr(struct com_regs *regs) 327 { 328 329 /* force access to id reg */ 330 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 331 CSR_WRITE_1(regs, COM_REG_IIR, 0); 332 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 333 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 334 return (0); 335 336 return (1); 337 } 338 339 int 340 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 341 { 342 struct com_regs regs; 343 344 regs.cr_iot = iot; 345 regs.cr_ioh = ioh; 346 #ifdef COM_REGMAP 347 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 348 #endif 349 350 return com_probe_subr(®s); 351 } 352 353 /* 354 * No locking in this routine; it is only called during attach, 355 * or with the port already locked. 356 */ 357 static void 358 com_enable_debugport(struct com_softc *sc) 359 { 360 361 /* Turn on line break interrupt, set carrier. */ 362 sc->sc_ier = IER_ERXRDY; 363 if (sc->sc_type == COM_TYPE_PXA2x0) 364 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 365 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 366 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 367 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 368 } 369 370 void 371 com_attach_subr(struct com_softc *sc) 372 { 373 struct com_regs *regsp = &sc->sc_regs; 374 struct tty *tp; 375 #ifdef COM_16650 376 u_int8_t lcr; 377 #endif 378 const char *fifo_msg = NULL; 379 380 aprint_naive("\n"); 381 382 callout_init(&sc->sc_diag_callout, 0); 383 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 384 385 /* Disable interrupts before configuring the device. */ 386 if (sc->sc_type == COM_TYPE_PXA2x0) 387 sc->sc_ier = IER_EUART; 388 else 389 sc->sc_ier = 0; 390 391 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 392 393 if (regsp->cr_iot == comconsregs.cr_iot && 394 regsp->cr_iobase == comconsregs.cr_iobase) { 395 comconsattached = 1; 396 397 /* Make sure the console is always "hardwired". */ 398 delay(10000); /* wait for output to finish */ 399 SET(sc->sc_hwflags, COM_HW_CONSOLE); 400 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 401 } 402 403 /* Probe for FIFO */ 404 switch (sc->sc_type) { 405 case COM_TYPE_HAYESP: 406 goto fifodone; 407 408 case COM_TYPE_AU1x00: 409 sc->sc_fifolen = 16; 410 fifo_msg = "Au1X00 UART, working fifo"; 411 SET(sc->sc_hwflags, COM_HW_FIFO); 412 goto fifodelay; 413 414 case COM_TYPE_OMAP: 415 sc->sc_fifolen = 64; 416 fifo_msg = "OMAP UART, working fifo"; 417 SET(sc->sc_hwflags, COM_HW_FIFO); 418 goto fifodelay; 419 } 420 421 sc->sc_fifolen = 1; 422 /* look for a NS 16550AF UART with FIFOs */ 423 CSR_WRITE_1(regsp, COM_REG_FIFO, 424 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 425 delay(100); 426 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 427 == IIR_FIFO_MASK) 428 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 429 == FIFO_TRIGGER_14) { 430 SET(sc->sc_hwflags, COM_HW_FIFO); 431 432 #ifdef COM_16650 433 /* 434 * IIR changes into the EFR if LCR is set to LCR_EERS 435 * on 16650s. We also know IIR != 0 at this point. 436 * Write 0 into the EFR, and read it. If the result 437 * is 0, we have a 16650. 438 * 439 * Older 16650s were broken; the test to detect them 440 * is taken from the Linux driver. Apparently 441 * setting DLAB enable gives access to the EFR on 442 * these chips. 443 */ 444 lcr = CSR_READ_1(regsp, COM_REG_LCR); 445 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 446 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 447 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 448 CSR_WRITE_1(regsp, COM_REG_LCR, 449 lcr | LCR_DLAB); 450 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 451 CLR(sc->sc_hwflags, COM_HW_FIFO); 452 sc->sc_fifolen = 0; 453 } else { 454 SET(sc->sc_hwflags, COM_HW_FLOW); 455 sc->sc_fifolen = 32; 456 } 457 } else 458 #endif 459 sc->sc_fifolen = 16; 460 461 #ifdef COM_16650 462 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 463 if (sc->sc_fifolen == 0) 464 fifo_msg = "st16650, broken fifo"; 465 else if (sc->sc_fifolen == 32) 466 fifo_msg = "st16650a, working fifo"; 467 else 468 #endif 469 fifo_msg = "ns16550a, working fifo"; 470 } else 471 fifo_msg = "ns16550, broken fifo"; 472 else 473 fifo_msg = "ns8250 or ns16450, no fifo"; 474 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 475 fifodelay: 476 /* 477 * Some chips will clear down both Tx and Rx FIFOs when zero is 478 * written to com_fifo. If this chip is the console, writing zero 479 * results in some of the chip/FIFO description being lost, so delay 480 * printing it until now. 481 */ 482 delay(10); 483 aprint_normal(": %s\n", fifo_msg); 484 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 485 sc->sc_fifolen = 1; 486 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 487 } 488 489 fifodone: 490 491 tp = ttymalloc(); 492 tp->t_oproc = comstart; 493 tp->t_param = comparam; 494 tp->t_hwiflow = comhwiflow; 495 496 sc->sc_tty = tp; 497 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 498 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 499 sc->sc_rbavail = com_rbuf_size; 500 if (sc->sc_rbuf == NULL) { 501 aprint_error_dev(sc->sc_dev, 502 "unable to allocate ring buffer\n"); 503 return; 504 } 505 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 506 507 tty_attach(tp); 508 509 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 510 SET(sc->sc_mcr, MCR_IENABLE); 511 512 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 513 int maj; 514 515 /* locate the major number */ 516 maj = cdevsw_lookup_major(&com_cdevsw); 517 518 tp->t_dev = cn_tab->cn_dev = makedev(maj, 519 device_unit(sc->sc_dev)); 520 521 aprint_normal_dev(sc->sc_dev, "console\n"); 522 } 523 524 #ifdef KGDB 525 /* 526 * Allow kgdb to "take over" this port. If this is 527 * not the console and is the kgdb device, it has 528 * exclusive use. If it's the console _and_ the 529 * kgdb device, it doesn't. 530 */ 531 if (regsp->cr_iot == comkgdbregs.cr_iot && 532 regsp->cr_iobase == comkgdbregs.cr_iobase) { 533 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 534 com_kgdb_attached = 1; 535 536 SET(sc->sc_hwflags, COM_HW_KGDB); 537 } 538 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 539 } 540 #endif 541 542 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 543 544 #if NRND > 0 && defined(RND_COM) 545 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 546 RND_TYPE_TTY, 0); 547 #endif 548 549 /* if there are no enable/disable functions, assume the device 550 is always enabled */ 551 if (!sc->enable) 552 sc->enabled = 1; 553 554 com_config(sc); 555 556 SET(sc->sc_hwflags, COM_HW_DEV_OK); 557 } 558 559 void 560 com_config(struct com_softc *sc) 561 { 562 struct com_regs *regsp = &sc->sc_regs; 563 564 /* Disable interrupts before configuring the device. */ 565 if (sc->sc_type == COM_TYPE_PXA2x0) 566 sc->sc_ier = IER_EUART; 567 else 568 sc->sc_ier = 0; 569 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 570 (void) CSR_READ_1(regsp, COM_REG_IIR); 571 572 #ifdef COM_HAYESP 573 /* Look for a Hayes ESP board. */ 574 if (sc->sc_type == COM_TYPE_HAYESP) { 575 576 /* Set 16550 compatibility mode */ 577 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 578 HAYESP_SETMODE); 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 580 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 581 HAYESP_MODE_SCALE); 582 583 /* Set RTS/CTS flow control */ 584 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 585 HAYESP_SETFLOWTYPE); 586 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 587 HAYESP_FLOW_RTS); 588 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 589 HAYESP_FLOW_CTS); 590 591 /* Set flow control levels */ 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 593 HAYESP_SETRXFLOW); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 596 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 597 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 599 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 602 } 603 #endif 604 605 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 606 com_enable_debugport(sc); 607 } 608 609 int 610 com_detach(device_t self, int flags) 611 { 612 struct com_softc *sc = device_private(self); 613 int maj, mn; 614 615 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 616 return EBUSY; 617 618 /* locate the major number */ 619 maj = cdevsw_lookup_major(&com_cdevsw); 620 621 /* Nuke the vnodes for any open instances. */ 622 mn = device_unit(self); 623 vdevgone(maj, mn, mn, VCHR); 624 625 mn |= COMDIALOUT_MASK; 626 vdevgone(maj, mn, mn, VCHR); 627 628 if (sc->sc_rbuf == NULL) { 629 /* 630 * Ring buffer allocation failed in the com_attach_subr, 631 * only the tty is allocated, and nothing else. 632 */ 633 ttyfree(sc->sc_tty); 634 return 0; 635 } 636 637 /* Free the receive buffer. */ 638 free(sc->sc_rbuf, M_DEVBUF); 639 640 /* Detach and free the tty. */ 641 tty_detach(sc->sc_tty); 642 ttyfree(sc->sc_tty); 643 644 /* Unhook the soft interrupt handler. */ 645 softint_disestablish(sc->sc_si); 646 647 #if NRND > 0 && defined(RND_COM) 648 /* Unhook the entropy source. */ 649 rnd_detach_source(&sc->rnd_source); 650 #endif 651 callout_destroy(&sc->sc_diag_callout); 652 653 /* Destroy the lock. */ 654 mutex_destroy(&sc->sc_lock); 655 656 return (0); 657 } 658 659 int 660 com_activate(device_t self, enum devact act) 661 { 662 struct com_softc *sc = device_private(self); 663 int rv = 0; 664 665 switch (act) { 666 case DVACT_ACTIVATE: 667 rv = EOPNOTSUPP; 668 break; 669 670 case DVACT_DEACTIVATE: 671 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 672 rv = EBUSY; 673 break; 674 } 675 676 if (sc->disable != NULL && sc->enabled != 0) { 677 (*sc->disable)(sc); 678 sc->enabled = 0; 679 } 680 break; 681 } 682 683 if (sc->sc_type == COM_TYPE_OMAP) { 684 /* enable but mode is based on speed */ 685 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 686 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_13X); 687 } else { 688 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_16X); 689 } 690 } 691 mutex_spin_exit(&sc->sc_lock); 692 return (rv); 693 } 694 695 void 696 com_shutdown(struct com_softc *sc) 697 { 698 struct tty *tp = sc->sc_tty; 699 700 mutex_spin_enter(&sc->sc_lock); 701 702 /* If we were asserting flow control, then deassert it. */ 703 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 704 com_hwiflow(sc); 705 706 /* Clear any break condition set with TIOCSBRK. */ 707 com_break(sc, 0); 708 709 /* 710 * Hang up if necessary. Wait a bit, so the other side has time to 711 * notice even if we immediately open the port again. 712 * Avoid tsleeping above splhigh(). 713 */ 714 if (ISSET(tp->t_cflag, HUPCL)) { 715 com_modem(sc, 0); 716 mutex_spin_exit(&sc->sc_lock); 717 /* XXX will only timeout */ 718 (void) kpause(ttclos, false, hz, NULL); 719 mutex_spin_enter(&sc->sc_lock); 720 } 721 722 /* Turn off interrupts. */ 723 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 724 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 725 if (sc->sc_type == COM_TYPE_PXA2x0) 726 sc->sc_ier |= IER_ERXTOUT; 727 } else 728 sc->sc_ier = 0; 729 730 if (sc->sc_type == COM_TYPE_PXA2x0) 731 sc->sc_ier |= IER_EUART; 732 733 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 734 735 mutex_spin_exit(&sc->sc_lock); 736 737 if (sc->disable) { 738 #ifdef DIAGNOSTIC 739 if (!sc->enabled) 740 panic("com_shutdown: not enabled?"); 741 #endif 742 (*sc->disable)(sc); 743 sc->enabled = 0; 744 } 745 } 746 747 int 748 comopen(dev_t dev, int flag, int mode, struct lwp *l) 749 { 750 struct com_softc *sc; 751 struct tty *tp; 752 int s; 753 int error; 754 755 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 756 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 757 sc->sc_rbuf == NULL) 758 return (ENXIO); 759 760 if (!device_is_active(sc->sc_dev)) 761 return (ENXIO); 762 763 #ifdef KGDB 764 /* 765 * If this is the kgdb port, no other use is permitted. 766 */ 767 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 768 return (EBUSY); 769 #endif 770 771 tp = sc->sc_tty; 772 773 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 774 return (EBUSY); 775 776 s = spltty(); 777 778 /* 779 * Do the following iff this is a first open. 780 */ 781 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 782 struct termios t; 783 784 tp->t_dev = dev; 785 786 787 if (sc->enable) { 788 if ((*sc->enable)(sc)) { 789 splx(s); 790 aprint_error_dev(sc->sc_dev, 791 "device enable failed\n"); 792 return (EIO); 793 } 794 mutex_spin_enter(&sc->sc_lock); 795 sc->enabled = 1; 796 com_config(sc); 797 } else { 798 mutex_spin_enter(&sc->sc_lock); 799 } 800 801 /* Turn on interrupts. */ 802 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 803 if (sc->sc_type == COM_TYPE_PXA2x0) 804 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 805 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 806 807 /* Fetch the current modem control status, needed later. */ 808 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 809 810 /* Clear PPS capture state on first open. */ 811 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 812 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 813 pps_init(&sc->sc_pps_state); 814 815 mutex_spin_exit(&sc->sc_lock); 816 817 /* 818 * Initialize the termios status to the defaults. Add in the 819 * sticky bits from TIOCSFLAGS. 820 */ 821 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 822 t.c_ospeed = comconsrate; 823 t.c_cflag = comconscflag; 824 } else { 825 t.c_ospeed = TTYDEF_SPEED; 826 t.c_cflag = TTYDEF_CFLAG; 827 } 828 t.c_ispeed = t.c_ospeed; 829 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 830 SET(t.c_cflag, CLOCAL); 831 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 832 SET(t.c_cflag, CRTSCTS); 833 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 834 SET(t.c_cflag, MDMBUF); 835 /* Make sure comparam() will do something. */ 836 tp->t_ospeed = 0; 837 (void) comparam(tp, &t); 838 tp->t_iflag = TTYDEF_IFLAG; 839 tp->t_oflag = TTYDEF_OFLAG; 840 tp->t_lflag = TTYDEF_LFLAG; 841 ttychars(tp); 842 ttsetwater(tp); 843 844 mutex_spin_enter(&sc->sc_lock); 845 846 /* 847 * Turn on DTR. We must always do this, even if carrier is not 848 * present, because otherwise we'd have to use TIOCSDTR 849 * immediately after setting CLOCAL, which applications do not 850 * expect. We always assert DTR while the device is open 851 * unless explicitly requested to deassert it. 852 */ 853 com_modem(sc, 1); 854 855 /* Clear the input ring, and unblock. */ 856 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 857 sc->sc_rbavail = com_rbuf_size; 858 com_iflush(sc); 859 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 860 com_hwiflow(sc); 861 862 #ifdef COM_DEBUG 863 if (com_debug) 864 comstatus(sc, "comopen "); 865 #endif 866 867 mutex_spin_exit(&sc->sc_lock); 868 } 869 870 splx(s); 871 872 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 873 if (error) 874 goto bad; 875 876 error = (*tp->t_linesw->l_open)(dev, tp); 877 if (error) 878 goto bad; 879 880 return (0); 881 882 bad: 883 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 884 /* 885 * We failed to open the device, and nobody else had it opened. 886 * Clean up the state as appropriate. 887 */ 888 com_shutdown(sc); 889 } 890 891 return (error); 892 } 893 894 int 895 comclose(dev_t dev, int flag, int mode, struct lwp *l) 896 { 897 struct com_softc *sc = 898 device_lookup_private(&com_cd, COMUNIT(dev)); 899 struct tty *tp = sc->sc_tty; 900 901 /* XXX This is for cons.c. */ 902 if (!ISSET(tp->t_state, TS_ISOPEN)) 903 return (0); 904 905 (*tp->t_linesw->l_close)(tp, flag); 906 ttyclose(tp); 907 908 if (COM_ISALIVE(sc) == 0) 909 return (0); 910 911 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 912 /* 913 * Although we got a last close, the device may still be in 914 * use; e.g. if this was the dialout node, and there are still 915 * processes waiting for carrier on the non-dialout node. 916 */ 917 com_shutdown(sc); 918 } 919 920 return (0); 921 } 922 923 int 924 comread(dev_t dev, struct uio *uio, int flag) 925 { 926 struct com_softc *sc = 927 device_lookup_private(&com_cd, COMUNIT(dev)); 928 struct tty *tp = sc->sc_tty; 929 930 if (COM_ISALIVE(sc) == 0) 931 return (EIO); 932 933 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 934 } 935 936 int 937 comwrite(dev_t dev, struct uio *uio, int flag) 938 { 939 struct com_softc *sc = 940 device_lookup_private(&com_cd, COMUNIT(dev)); 941 struct tty *tp = sc->sc_tty; 942 943 if (COM_ISALIVE(sc) == 0) 944 return (EIO); 945 946 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 947 } 948 949 int 950 compoll(dev_t dev, int events, struct lwp *l) 951 { 952 struct com_softc *sc = 953 device_lookup_private(&com_cd, COMUNIT(dev)); 954 struct tty *tp = sc->sc_tty; 955 956 if (COM_ISALIVE(sc) == 0) 957 return (POLLHUP); 958 959 return ((*tp->t_linesw->l_poll)(tp, events, l)); 960 } 961 962 struct tty * 963 comtty(dev_t dev) 964 { 965 struct com_softc *sc = 966 device_lookup_private(&com_cd, COMUNIT(dev)); 967 struct tty *tp = sc->sc_tty; 968 969 return (tp); 970 } 971 972 int 973 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 974 { 975 struct com_softc *sc; 976 struct tty *tp; 977 int error; 978 979 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 980 if (sc == NULL) 981 return ENXIO; 982 if (COM_ISALIVE(sc) == 0) 983 return (EIO); 984 985 tp = sc->sc_tty; 986 987 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 988 if (error != EPASSTHROUGH) 989 return (error); 990 991 error = ttioctl(tp, cmd, data, flag, l); 992 if (error != EPASSTHROUGH) 993 return (error); 994 995 error = 0; 996 switch (cmd) { 997 case TIOCSFLAGS: 998 error = kauth_authorize_device_tty(l->l_cred, 999 KAUTH_DEVICE_TTY_PRIVSET, tp); 1000 break; 1001 default: 1002 /* nothing */ 1003 break; 1004 } 1005 if (error) { 1006 return error; 1007 } 1008 1009 mutex_spin_enter(&sc->sc_lock); 1010 1011 switch (cmd) { 1012 case TIOCSBRK: 1013 com_break(sc, 1); 1014 break; 1015 1016 case TIOCCBRK: 1017 com_break(sc, 0); 1018 break; 1019 1020 case TIOCSDTR: 1021 com_modem(sc, 1); 1022 break; 1023 1024 case TIOCCDTR: 1025 com_modem(sc, 0); 1026 break; 1027 1028 case TIOCGFLAGS: 1029 *(int *)data = sc->sc_swflags; 1030 break; 1031 1032 case TIOCSFLAGS: 1033 sc->sc_swflags = *(int *)data; 1034 break; 1035 1036 case TIOCMSET: 1037 case TIOCMBIS: 1038 case TIOCMBIC: 1039 tiocm_to_com(sc, cmd, *(int *)data); 1040 break; 1041 1042 case TIOCMGET: 1043 *(int *)data = com_to_tiocm(sc); 1044 break; 1045 1046 case PPS_IOC_CREATE: 1047 case PPS_IOC_DESTROY: 1048 case PPS_IOC_GETPARAMS: 1049 case PPS_IOC_SETPARAMS: 1050 case PPS_IOC_GETCAP: 1051 case PPS_IOC_FETCH: 1052 #ifdef PPS_SYNC 1053 case PPS_IOC_KCBIND: 1054 #endif 1055 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1056 break; 1057 1058 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1059 #ifndef PPS_TRAILING_EDGE 1060 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1061 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1062 #else 1063 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1064 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1065 #endif 1066 break; 1067 1068 default: 1069 error = EPASSTHROUGH; 1070 break; 1071 } 1072 1073 mutex_spin_exit(&sc->sc_lock); 1074 1075 #ifdef COM_DEBUG 1076 if (com_debug) 1077 comstatus(sc, "comioctl "); 1078 #endif 1079 1080 return (error); 1081 } 1082 1083 integrate void 1084 com_schedrx(struct com_softc *sc) 1085 { 1086 1087 sc->sc_rx_ready = 1; 1088 1089 /* Wake up the poller. */ 1090 softint_schedule(sc->sc_si); 1091 } 1092 1093 void 1094 com_break(struct com_softc *sc, int onoff) 1095 { 1096 1097 if (onoff) 1098 SET(sc->sc_lcr, LCR_SBREAK); 1099 else 1100 CLR(sc->sc_lcr, LCR_SBREAK); 1101 1102 if (!sc->sc_heldchange) { 1103 if (sc->sc_tx_busy) { 1104 sc->sc_heldtbc = sc->sc_tbc; 1105 sc->sc_tbc = 0; 1106 sc->sc_heldchange = 1; 1107 } else 1108 com_loadchannelregs(sc); 1109 } 1110 } 1111 1112 void 1113 com_modem(struct com_softc *sc, int onoff) 1114 { 1115 1116 if (sc->sc_mcr_dtr == 0) 1117 return; 1118 1119 if (onoff) 1120 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1121 else 1122 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1123 1124 if (!sc->sc_heldchange) { 1125 if (sc->sc_tx_busy) { 1126 sc->sc_heldtbc = sc->sc_tbc; 1127 sc->sc_tbc = 0; 1128 sc->sc_heldchange = 1; 1129 } else 1130 com_loadchannelregs(sc); 1131 } 1132 } 1133 1134 void 1135 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1136 { 1137 u_char combits; 1138 1139 combits = 0; 1140 if (ISSET(ttybits, TIOCM_DTR)) 1141 SET(combits, MCR_DTR); 1142 if (ISSET(ttybits, TIOCM_RTS)) 1143 SET(combits, MCR_RTS); 1144 1145 switch (how) { 1146 case TIOCMBIC: 1147 CLR(sc->sc_mcr, combits); 1148 break; 1149 1150 case TIOCMBIS: 1151 SET(sc->sc_mcr, combits); 1152 break; 1153 1154 case TIOCMSET: 1155 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1156 SET(sc->sc_mcr, combits); 1157 break; 1158 } 1159 1160 if (!sc->sc_heldchange) { 1161 if (sc->sc_tx_busy) { 1162 sc->sc_heldtbc = sc->sc_tbc; 1163 sc->sc_tbc = 0; 1164 sc->sc_heldchange = 1; 1165 } else 1166 com_loadchannelregs(sc); 1167 } 1168 } 1169 1170 int 1171 com_to_tiocm(struct com_softc *sc) 1172 { 1173 u_char combits; 1174 int ttybits = 0; 1175 1176 combits = sc->sc_mcr; 1177 if (ISSET(combits, MCR_DTR)) 1178 SET(ttybits, TIOCM_DTR); 1179 if (ISSET(combits, MCR_RTS)) 1180 SET(ttybits, TIOCM_RTS); 1181 1182 combits = sc->sc_msr; 1183 if (ISSET(combits, MSR_DCD)) 1184 SET(ttybits, TIOCM_CD); 1185 if (ISSET(combits, MSR_CTS)) 1186 SET(ttybits, TIOCM_CTS); 1187 if (ISSET(combits, MSR_DSR)) 1188 SET(ttybits, TIOCM_DSR); 1189 if (ISSET(combits, MSR_RI | MSR_TERI)) 1190 SET(ttybits, TIOCM_RI); 1191 1192 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1193 SET(ttybits, TIOCM_LE); 1194 1195 return (ttybits); 1196 } 1197 1198 static u_char 1199 cflag2lcr(tcflag_t cflag) 1200 { 1201 u_char lcr = 0; 1202 1203 switch (ISSET(cflag, CSIZE)) { 1204 case CS5: 1205 SET(lcr, LCR_5BITS); 1206 break; 1207 case CS6: 1208 SET(lcr, LCR_6BITS); 1209 break; 1210 case CS7: 1211 SET(lcr, LCR_7BITS); 1212 break; 1213 case CS8: 1214 SET(lcr, LCR_8BITS); 1215 break; 1216 } 1217 if (ISSET(cflag, PARENB)) { 1218 SET(lcr, LCR_PENAB); 1219 if (!ISSET(cflag, PARODD)) 1220 SET(lcr, LCR_PEVEN); 1221 } 1222 if (ISSET(cflag, CSTOPB)) 1223 SET(lcr, LCR_STOPB); 1224 1225 return (lcr); 1226 } 1227 1228 int 1229 comparam(struct tty *tp, struct termios *t) 1230 { 1231 struct com_softc *sc = 1232 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1233 int ospeed; 1234 u_char lcr; 1235 1236 if (COM_ISALIVE(sc) == 0) 1237 return (EIO); 1238 1239 #ifdef COM_HAYESP 1240 if (sc->sc_type == COM_TYPE_HAYESP) { 1241 int prescaler, speed; 1242 1243 /* 1244 * Calculate UART clock prescaler. It should be in 1245 * range of 0 .. 3. 1246 */ 1247 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1248 prescaler++, speed /= 2) 1249 if ((ospeed = comspeed(speed, sc->sc_frequency, 1250 sc->sc_type)) > 0) 1251 break; 1252 1253 if (prescaler == 4) 1254 return (EINVAL); 1255 sc->sc_prescaler = prescaler; 1256 } else 1257 #endif 1258 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1259 1260 /* Check requested parameters. */ 1261 if (ospeed < 0) 1262 return (EINVAL); 1263 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1264 return (EINVAL); 1265 1266 /* 1267 * For the console, always force CLOCAL and !HUPCL, so that the port 1268 * is always active. 1269 */ 1270 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1271 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1272 SET(t->c_cflag, CLOCAL); 1273 CLR(t->c_cflag, HUPCL); 1274 } 1275 1276 /* 1277 * If there were no changes, don't do anything. This avoids dropping 1278 * input and improves performance when all we did was frob things like 1279 * VMIN and VTIME. 1280 */ 1281 if (tp->t_ospeed == t->c_ospeed && 1282 tp->t_cflag == t->c_cflag) 1283 return (0); 1284 1285 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1286 1287 mutex_spin_enter(&sc->sc_lock); 1288 1289 sc->sc_lcr = lcr; 1290 1291 /* 1292 * If we're not in a mode that assumes a connection is present, then 1293 * ignore carrier changes. 1294 */ 1295 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1296 sc->sc_msr_dcd = 0; 1297 else 1298 sc->sc_msr_dcd = MSR_DCD; 1299 /* 1300 * Set the flow control pins depending on the current flow control 1301 * mode. 1302 */ 1303 if (ISSET(t->c_cflag, CRTSCTS)) { 1304 sc->sc_mcr_dtr = MCR_DTR; 1305 sc->sc_mcr_rts = MCR_RTS; 1306 sc->sc_msr_cts = MSR_CTS; 1307 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1308 } else if (ISSET(t->c_cflag, MDMBUF)) { 1309 /* 1310 * For DTR/DCD flow control, make sure we don't toggle DTR for 1311 * carrier detection. 1312 */ 1313 sc->sc_mcr_dtr = 0; 1314 sc->sc_mcr_rts = MCR_DTR; 1315 sc->sc_msr_cts = MSR_DCD; 1316 sc->sc_efr = 0; 1317 } else { 1318 /* 1319 * If no flow control, then always set RTS. This will make 1320 * the other side happy if it mistakenly thinks we're doing 1321 * RTS/CTS flow control. 1322 */ 1323 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1324 sc->sc_mcr_rts = 0; 1325 sc->sc_msr_cts = 0; 1326 sc->sc_efr = 0; 1327 if (ISSET(sc->sc_mcr, MCR_DTR)) 1328 SET(sc->sc_mcr, MCR_RTS); 1329 else 1330 CLR(sc->sc_mcr, MCR_RTS); 1331 } 1332 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1333 1334 #if 0 1335 if (ospeed == 0) 1336 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1337 else 1338 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1339 #endif 1340 1341 sc->sc_dlbl = ospeed; 1342 sc->sc_dlbh = ospeed >> 8; 1343 1344 /* 1345 * Set the FIFO threshold based on the receive speed. 1346 * 1347 * * If it's a low speed, it's probably a mouse or some other 1348 * interactive device, so set the threshold low. 1349 * * If it's a high speed, trim the trigger level down to prevent 1350 * overflows. 1351 * * Otherwise set it a bit higher. 1352 */ 1353 if (sc->sc_type == COM_TYPE_HAYESP) 1354 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1355 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1356 sc->sc_fifo = FIFO_ENABLE | 1357 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1358 else 1359 sc->sc_fifo = 0; 1360 1361 /* And copy to tty. */ 1362 tp->t_ispeed = t->c_ospeed; 1363 tp->t_ospeed = t->c_ospeed; 1364 tp->t_cflag = t->c_cflag; 1365 1366 if (!sc->sc_heldchange) { 1367 if (sc->sc_tx_busy) { 1368 sc->sc_heldtbc = sc->sc_tbc; 1369 sc->sc_tbc = 0; 1370 sc->sc_heldchange = 1; 1371 } else 1372 com_loadchannelregs(sc); 1373 } 1374 1375 if (!ISSET(t->c_cflag, CHWFLOW)) { 1376 /* Disable the high water mark. */ 1377 sc->sc_r_hiwat = 0; 1378 sc->sc_r_lowat = 0; 1379 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1380 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1381 com_schedrx(sc); 1382 } 1383 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1384 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1385 com_hwiflow(sc); 1386 } 1387 } else { 1388 sc->sc_r_hiwat = com_rbuf_hiwat; 1389 sc->sc_r_lowat = com_rbuf_lowat; 1390 } 1391 1392 mutex_spin_exit(&sc->sc_lock); 1393 1394 /* 1395 * Update the tty layer's idea of the carrier bit, in case we changed 1396 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1397 * explicit request. 1398 */ 1399 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1400 1401 #ifdef COM_DEBUG 1402 if (com_debug) 1403 comstatus(sc, "comparam "); 1404 #endif 1405 1406 if (!ISSET(t->c_cflag, CHWFLOW)) { 1407 if (sc->sc_tx_stopped) { 1408 sc->sc_tx_stopped = 0; 1409 comstart(tp); 1410 } 1411 } 1412 1413 return (0); 1414 } 1415 1416 void 1417 com_iflush(struct com_softc *sc) 1418 { 1419 struct com_regs *regsp = &sc->sc_regs; 1420 #ifdef DIAGNOSTIC 1421 int reg; 1422 #endif 1423 int timo; 1424 1425 #ifdef DIAGNOSTIC 1426 reg = 0xffff; 1427 #endif 1428 timo = 50000; 1429 /* flush any pending I/O */ 1430 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1431 && --timo) 1432 #ifdef DIAGNOSTIC 1433 reg = 1434 #else 1435 (void) 1436 #endif 1437 CSR_READ_1(regsp, COM_REG_RXDATA); 1438 #ifdef DIAGNOSTIC 1439 if (!timo) 1440 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1441 #endif 1442 } 1443 1444 void 1445 com_loadchannelregs(struct com_softc *sc) 1446 { 1447 struct com_regs *regsp = &sc->sc_regs; 1448 1449 /* XXXXX necessary? */ 1450 com_iflush(sc); 1451 1452 if (sc->sc_type == COM_TYPE_PXA2x0) 1453 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1454 else 1455 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1456 1457 if (sc->sc_type == COM_TYPE_OMAP) { 1458 /* disable before changing settings */ 1459 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1460 } 1461 1462 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1463 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1464 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1465 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1466 } 1467 } 1468 if (sc->sc_type == COM_TYPE_AU1x00) { 1469 /* alchemy has single separate 16-bit clock divisor register */ 1470 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1471 (sc->sc_dlbh << 8)); 1472 } else { 1473 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1474 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1475 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1476 } 1477 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1478 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1479 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1480 #ifdef COM_HAYESP 1481 if (sc->sc_type == COM_TYPE_HAYESP) { 1482 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1483 HAYESP_SETPRESCALER); 1484 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1485 sc->sc_prescaler); 1486 } 1487 #endif 1488 if (sc->sc_type == COM_TYPE_OMAP) { 1489 /* setup the fifos. the FCR value is not used as long 1490 as SCR[6] and SCR[7] are 0, which they are at reset 1491 and we never touch the SCR register */ 1492 uint8_t rx_fifo_trig = 40; 1493 uint8_t tx_fifo_trig = 60; 1494 uint8_t rx_start = 8; 1495 uint8_t rx_halt = 60; 1496 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1497 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1498 1499 /* enable access to TCR & TLR */ 1500 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1501 1502 /* write tcr and tlr values */ 1503 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1504 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1505 1506 /* disable access to TCR & TLR */ 1507 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1508 1509 /* enable again, but mode is based on speed */ 1510 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1511 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1512 } else { 1513 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1514 } 1515 } 1516 1517 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1518 } 1519 1520 int 1521 comhwiflow(struct tty *tp, int block) 1522 { 1523 struct com_softc *sc = 1524 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1525 1526 if (COM_ISALIVE(sc) == 0) 1527 return (0); 1528 1529 if (sc->sc_mcr_rts == 0) 1530 return (0); 1531 1532 mutex_spin_enter(&sc->sc_lock); 1533 1534 if (block) { 1535 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1536 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1537 com_hwiflow(sc); 1538 } 1539 } else { 1540 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1541 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1542 com_schedrx(sc); 1543 } 1544 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1545 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1546 com_hwiflow(sc); 1547 } 1548 } 1549 1550 mutex_spin_exit(&sc->sc_lock); 1551 return (1); 1552 } 1553 1554 /* 1555 * (un)block input via hw flowcontrol 1556 */ 1557 void 1558 com_hwiflow(struct com_softc *sc) 1559 { 1560 struct com_regs *regsp= &sc->sc_regs; 1561 1562 if (sc->sc_mcr_rts == 0) 1563 return; 1564 1565 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1566 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1567 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1568 } else { 1569 SET(sc->sc_mcr, sc->sc_mcr_rts); 1570 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1571 } 1572 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1573 } 1574 1575 1576 void 1577 comstart(struct tty *tp) 1578 { 1579 struct com_softc *sc = 1580 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1581 struct com_regs *regsp = &sc->sc_regs; 1582 int s; 1583 1584 if (COM_ISALIVE(sc) == 0) 1585 return; 1586 1587 s = spltty(); 1588 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1589 goto out; 1590 if (sc->sc_tx_stopped) 1591 goto out; 1592 if (!ttypull(tp)) 1593 goto out; 1594 1595 /* Grab the first contiguous region of buffer space. */ 1596 { 1597 u_char *tba; 1598 int tbc; 1599 1600 tba = tp->t_outq.c_cf; 1601 tbc = ndqb(&tp->t_outq, 0); 1602 1603 mutex_spin_enter(&sc->sc_lock); 1604 1605 sc->sc_tba = tba; 1606 sc->sc_tbc = tbc; 1607 } 1608 1609 SET(tp->t_state, TS_BUSY); 1610 sc->sc_tx_busy = 1; 1611 1612 /* Enable transmit completion interrupts if necessary. */ 1613 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1614 SET(sc->sc_ier, IER_ETXRDY); 1615 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1616 } 1617 1618 /* Output the first chunk of the contiguous buffer. */ 1619 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1620 u_int n; 1621 1622 n = sc->sc_tbc; 1623 if (n > sc->sc_fifolen) 1624 n = sc->sc_fifolen; 1625 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1626 sc->sc_tbc -= n; 1627 sc->sc_tba += n; 1628 } 1629 1630 mutex_spin_exit(&sc->sc_lock); 1631 out: 1632 splx(s); 1633 return; 1634 } 1635 1636 /* 1637 * Stop output on a line. 1638 */ 1639 void 1640 comstop(struct tty *tp, int flag) 1641 { 1642 struct com_softc *sc = 1643 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1644 1645 mutex_spin_enter(&sc->sc_lock); 1646 if (ISSET(tp->t_state, TS_BUSY)) { 1647 /* Stop transmitting at the next chunk. */ 1648 sc->sc_tbc = 0; 1649 sc->sc_heldtbc = 0; 1650 if (!ISSET(tp->t_state, TS_TTSTOP)) 1651 SET(tp->t_state, TS_FLUSH); 1652 } 1653 mutex_spin_exit(&sc->sc_lock); 1654 } 1655 1656 void 1657 comdiag(void *arg) 1658 { 1659 struct com_softc *sc = arg; 1660 int overflows, floods; 1661 1662 mutex_spin_enter(&sc->sc_lock); 1663 overflows = sc->sc_overflows; 1664 sc->sc_overflows = 0; 1665 floods = sc->sc_floods; 1666 sc->sc_floods = 0; 1667 sc->sc_errors = 0; 1668 mutex_spin_exit(&sc->sc_lock); 1669 1670 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1671 device_xname(sc->sc_dev), 1672 overflows, overflows == 1 ? "" : "s", 1673 floods, floods == 1 ? "" : "s"); 1674 } 1675 1676 integrate void 1677 com_rxsoft(struct com_softc *sc, struct tty *tp) 1678 { 1679 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1680 u_char *get, *end; 1681 u_int cc, scc; 1682 u_char lsr; 1683 int code; 1684 1685 end = sc->sc_ebuf; 1686 get = sc->sc_rbget; 1687 scc = cc = com_rbuf_size - sc->sc_rbavail; 1688 1689 if (cc == com_rbuf_size) { 1690 sc->sc_floods++; 1691 if (sc->sc_errors++ == 0) 1692 callout_reset(&sc->sc_diag_callout, 60 * hz, 1693 comdiag, sc); 1694 } 1695 1696 /* If not yet open, drop the entire buffer content here */ 1697 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1698 get += cc << 1; 1699 if (get >= end) 1700 get -= com_rbuf_size << 1; 1701 cc = 0; 1702 } 1703 while (cc) { 1704 code = get[0]; 1705 lsr = get[1]; 1706 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1707 if (ISSET(lsr, LSR_OE)) { 1708 sc->sc_overflows++; 1709 if (sc->sc_errors++ == 0) 1710 callout_reset(&sc->sc_diag_callout, 1711 60 * hz, comdiag, sc); 1712 } 1713 if (ISSET(lsr, LSR_BI | LSR_FE)) 1714 SET(code, TTY_FE); 1715 if (ISSET(lsr, LSR_PE)) 1716 SET(code, TTY_PE); 1717 } 1718 if ((*rint)(code, tp) == -1) { 1719 /* 1720 * The line discipline's buffer is out of space. 1721 */ 1722 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1723 /* 1724 * We're either not using flow control, or the 1725 * line discipline didn't tell us to block for 1726 * some reason. Either way, we have no way to 1727 * know when there's more space available, so 1728 * just drop the rest of the data. 1729 */ 1730 get += cc << 1; 1731 if (get >= end) 1732 get -= com_rbuf_size << 1; 1733 cc = 0; 1734 } else { 1735 /* 1736 * Don't schedule any more receive processing 1737 * until the line discipline tells us there's 1738 * space available (through comhwiflow()). 1739 * Leave the rest of the data in the input 1740 * buffer. 1741 */ 1742 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1743 } 1744 break; 1745 } 1746 get += 2; 1747 if (get >= end) 1748 get = sc->sc_rbuf; 1749 cc--; 1750 } 1751 1752 if (cc != scc) { 1753 sc->sc_rbget = get; 1754 mutex_spin_enter(&sc->sc_lock); 1755 1756 cc = sc->sc_rbavail += scc - cc; 1757 /* Buffers should be ok again, release possible block. */ 1758 if (cc >= sc->sc_r_lowat) { 1759 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1760 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1761 SET(sc->sc_ier, IER_ERXRDY); 1762 #ifdef COM_PXA2X0 1763 if (sc->sc_type == COM_TYPE_PXA2x0) 1764 SET(sc->sc_ier, IER_ERXTOUT); 1765 #endif 1766 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1767 } 1768 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1769 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1770 com_hwiflow(sc); 1771 } 1772 } 1773 mutex_spin_exit(&sc->sc_lock); 1774 } 1775 } 1776 1777 integrate void 1778 com_txsoft(struct com_softc *sc, struct tty *tp) 1779 { 1780 1781 CLR(tp->t_state, TS_BUSY); 1782 if (ISSET(tp->t_state, TS_FLUSH)) 1783 CLR(tp->t_state, TS_FLUSH); 1784 else 1785 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1786 (*tp->t_linesw->l_start)(tp); 1787 } 1788 1789 integrate void 1790 com_stsoft(struct com_softc *sc, struct tty *tp) 1791 { 1792 u_char msr, delta; 1793 1794 mutex_spin_enter(&sc->sc_lock); 1795 msr = sc->sc_msr; 1796 delta = sc->sc_msr_delta; 1797 sc->sc_msr_delta = 0; 1798 mutex_spin_exit(&sc->sc_lock); 1799 1800 if (ISSET(delta, sc->sc_msr_dcd)) { 1801 /* 1802 * Inform the tty layer that carrier detect changed. 1803 */ 1804 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1805 } 1806 1807 if (ISSET(delta, sc->sc_msr_cts)) { 1808 /* Block or unblock output according to flow control. */ 1809 if (ISSET(msr, sc->sc_msr_cts)) { 1810 sc->sc_tx_stopped = 0; 1811 (*tp->t_linesw->l_start)(tp); 1812 } else { 1813 sc->sc_tx_stopped = 1; 1814 } 1815 } 1816 1817 #ifdef COM_DEBUG 1818 if (com_debug) 1819 comstatus(sc, "com_stsoft"); 1820 #endif 1821 } 1822 1823 void 1824 comsoft(void *arg) 1825 { 1826 struct com_softc *sc = arg; 1827 struct tty *tp; 1828 1829 if (COM_ISALIVE(sc) == 0) 1830 return; 1831 1832 tp = sc->sc_tty; 1833 1834 if (sc->sc_rx_ready) { 1835 sc->sc_rx_ready = 0; 1836 com_rxsoft(sc, tp); 1837 } 1838 1839 if (sc->sc_st_check) { 1840 sc->sc_st_check = 0; 1841 com_stsoft(sc, tp); 1842 } 1843 1844 if (sc->sc_tx_done) { 1845 sc->sc_tx_done = 0; 1846 com_txsoft(sc, tp); 1847 } 1848 } 1849 1850 int 1851 comintr(void *arg) 1852 { 1853 struct com_softc *sc = arg; 1854 struct com_regs *regsp = &sc->sc_regs; 1855 1856 u_char *put, *end; 1857 u_int cc; 1858 u_char lsr, iir; 1859 1860 if (COM_ISALIVE(sc) == 0) 1861 return (0); 1862 1863 mutex_spin_enter(&sc->sc_lock); 1864 iir = CSR_READ_1(regsp, COM_REG_IIR); 1865 if (ISSET(iir, IIR_NOPEND)) { 1866 mutex_spin_exit(&sc->sc_lock); 1867 return (0); 1868 } 1869 1870 end = sc->sc_ebuf; 1871 put = sc->sc_rbput; 1872 cc = sc->sc_rbavail; 1873 1874 again: do { 1875 u_char msr, delta; 1876 1877 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1878 if (ISSET(lsr, LSR_BI)) { 1879 int cn_trapped = 0; 1880 1881 cn_check_magic(sc->sc_tty->t_dev, 1882 CNC_BREAK, com_cnm_state); 1883 if (cn_trapped) 1884 continue; 1885 #if defined(KGDB) && !defined(DDB) 1886 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1887 kgdb_connect(1); 1888 continue; 1889 } 1890 #endif 1891 } 1892 1893 if (ISSET(lsr, LSR_RCV_MASK) && 1894 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1895 while (cc > 0) { 1896 int cn_trapped = 0; 1897 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1898 put[1] = lsr; 1899 cn_check_magic(sc->sc_tty->t_dev, 1900 put[0], com_cnm_state); 1901 if (cn_trapped) 1902 goto next; 1903 put += 2; 1904 if (put >= end) 1905 put = sc->sc_rbuf; 1906 cc--; 1907 next: 1908 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1909 if (!ISSET(lsr, LSR_RCV_MASK)) 1910 break; 1911 } 1912 1913 /* 1914 * Current string of incoming characters ended because 1915 * no more data was available or we ran out of space. 1916 * Schedule a receive event if any data was received. 1917 * If we're out of space, turn off receive interrupts. 1918 */ 1919 sc->sc_rbput = put; 1920 sc->sc_rbavail = cc; 1921 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1922 sc->sc_rx_ready = 1; 1923 1924 /* 1925 * See if we are in danger of overflowing a buffer. If 1926 * so, use hardware flow control to ease the pressure. 1927 */ 1928 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1929 cc < sc->sc_r_hiwat) { 1930 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1931 com_hwiflow(sc); 1932 } 1933 1934 /* 1935 * If we're out of space, disable receive interrupts 1936 * until the queue has drained a bit. 1937 */ 1938 if (!cc) { 1939 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1940 #ifdef COM_PXA2X0 1941 if (sc->sc_type == COM_TYPE_PXA2x0) 1942 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1943 else 1944 #endif 1945 CLR(sc->sc_ier, IER_ERXRDY); 1946 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1947 } 1948 } else { 1949 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1950 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1951 continue; 1952 } 1953 } 1954 1955 msr = CSR_READ_1(regsp, COM_REG_MSR); 1956 delta = msr ^ sc->sc_msr; 1957 sc->sc_msr = msr; 1958 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1959 (delta & MSR_DCD)) { 1960 pps_capture(&sc->sc_pps_state); 1961 pps_event(&sc->sc_pps_state, 1962 (msr & MSR_DCD) ? 1963 PPS_CAPTUREASSERT : 1964 PPS_CAPTURECLEAR); 1965 } 1966 1967 /* 1968 * Process normal status changes 1969 */ 1970 if (ISSET(delta, sc->sc_msr_mask)) { 1971 SET(sc->sc_msr_delta, delta); 1972 1973 /* 1974 * Stop output immediately if we lose the output 1975 * flow control signal or carrier detect. 1976 */ 1977 if (ISSET(~msr, sc->sc_msr_mask)) { 1978 sc->sc_tbc = 0; 1979 sc->sc_heldtbc = 0; 1980 #ifdef COM_DEBUG 1981 if (com_debug) 1982 comstatus(sc, "comintr "); 1983 #endif 1984 } 1985 1986 sc->sc_st_check = 1; 1987 } 1988 } while (!ISSET((iir = 1989 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 1990 /* 1991 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 1992 * by IIR read, so we can't do this way: `process all interrupts, 1993 * then do TX if possble'. 1994 */ 1995 (iir & IIR_IMASK) != IIR_TXRDY); 1996 1997 /* 1998 * Read LSR again, since there may be an interrupt between 1999 * the last LSR read and IIR read above. 2000 */ 2001 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2002 2003 /* 2004 * See if data can be transmitted as well. 2005 * Schedule tx done event if no data left 2006 * and tty was marked busy. 2007 */ 2008 if (ISSET(lsr, LSR_TXRDY)) { 2009 /* 2010 * If we've delayed a parameter change, do it now, and restart 2011 * output. 2012 */ 2013 if (sc->sc_heldchange) { 2014 com_loadchannelregs(sc); 2015 sc->sc_heldchange = 0; 2016 sc->sc_tbc = sc->sc_heldtbc; 2017 sc->sc_heldtbc = 0; 2018 } 2019 2020 /* Output the next chunk of the contiguous buffer, if any. */ 2021 if (sc->sc_tbc > 0) { 2022 u_int n; 2023 2024 n = sc->sc_tbc; 2025 if (n > sc->sc_fifolen) 2026 n = sc->sc_fifolen; 2027 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2028 sc->sc_tbc -= n; 2029 sc->sc_tba += n; 2030 } else { 2031 /* Disable transmit completion interrupts if necessary. */ 2032 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2033 CLR(sc->sc_ier, IER_ETXRDY); 2034 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2035 } 2036 if (sc->sc_tx_busy) { 2037 sc->sc_tx_busy = 0; 2038 sc->sc_tx_done = 1; 2039 } 2040 } 2041 } 2042 2043 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2044 goto again; 2045 2046 mutex_spin_exit(&sc->sc_lock); 2047 2048 /* Wake up the poller. */ 2049 softint_schedule(sc->sc_si); 2050 2051 #if NRND > 0 && defined(RND_COM) 2052 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2053 #endif 2054 2055 return (1); 2056 } 2057 2058 /* 2059 * The following functions are polled getc and putc routines, shared 2060 * by the console and kgdb glue. 2061 * 2062 * The read-ahead code is so that you can detect pending in-band 2063 * cn_magic in polled mode while doing output rather than having to 2064 * wait until the kernel decides it needs input. 2065 */ 2066 2067 #define MAX_READAHEAD 20 2068 static int com_readahead[MAX_READAHEAD]; 2069 static int com_readaheadcount = 0; 2070 2071 int 2072 com_common_getc(dev_t dev, struct com_regs *regsp) 2073 { 2074 int s = splserial(); 2075 u_char stat, c; 2076 2077 /* got a character from reading things earlier */ 2078 if (com_readaheadcount > 0) { 2079 int i; 2080 2081 c = com_readahead[0]; 2082 for (i = 1; i < com_readaheadcount; i++) { 2083 com_readahead[i-1] = com_readahead[i]; 2084 } 2085 com_readaheadcount--; 2086 splx(s); 2087 return (c); 2088 } 2089 2090 /* block until a character becomes available */ 2091 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2092 ; 2093 2094 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2095 stat = CSR_READ_1(regsp, COM_REG_IIR); 2096 { 2097 int cn_trapped = 0; /* unused */ 2098 #ifdef DDB 2099 extern int db_active; 2100 if (!db_active) 2101 #endif 2102 cn_check_magic(dev, c, com_cnm_state); 2103 } 2104 splx(s); 2105 return (c); 2106 } 2107 2108 void 2109 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2110 { 2111 int s = splserial(); 2112 int cin, stat, timo; 2113 2114 if (com_readaheadcount < MAX_READAHEAD 2115 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2116 int cn_trapped = 0; 2117 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2118 stat = CSR_READ_1(regsp, COM_REG_IIR); 2119 cn_check_magic(dev, cin, com_cnm_state); 2120 com_readahead[com_readaheadcount++] = cin; 2121 } 2122 2123 /* wait for any pending transmission to finish */ 2124 timo = 150000; 2125 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2126 continue; 2127 2128 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2129 COM_BARRIER(regsp, BR | BW); 2130 2131 splx(s); 2132 } 2133 2134 /* 2135 * Initialize UART for use as console or KGDB line. 2136 */ 2137 int 2138 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2139 tcflag_t cflag) 2140 { 2141 2142 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2143 ®sp->cr_ioh)) 2144 return (ENOMEM); /* ??? */ 2145 2146 if (type == COM_TYPE_OMAP) { 2147 /* disable before changing settings */ 2148 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2149 } 2150 2151 rate = comspeed(rate, frequency, type); 2152 if (type != COM_TYPE_AU1x00) { 2153 /* no EFR on alchemy */ 2154 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2155 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2156 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2157 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2158 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2159 } else { 2160 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2161 } 2162 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2163 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2164 CSR_WRITE_1(regsp, COM_REG_FIFO, 2165 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2166 2167 if (type == COM_TYPE_OMAP) { 2168 /* setup the fifos. the FCR value is not used as long 2169 as SCR[6] and SCR[7] are 0, which they are at reset 2170 and we never touch the SCR register */ 2171 uint8_t rx_fifo_trig = 40; 2172 uint8_t tx_fifo_trig = 60; 2173 uint8_t rx_start = 8; 2174 uint8_t rx_halt = 60; 2175 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2176 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2177 2178 /* enable access to TCR & TLR */ 2179 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2180 2181 /* write tcr and tlr values */ 2182 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2183 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2184 2185 /* disable access to TCR & TLR */ 2186 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2187 2188 /* enable again, but mode is based on speed */ 2189 if (rate > 230400) { 2190 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2191 } else { 2192 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2193 } 2194 } 2195 2196 #ifdef COM_PXA2X0 2197 if (type == COM_TYPE_PXA2x0) 2198 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2199 else 2200 #endif 2201 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2202 2203 return (0); 2204 } 2205 2206 /* 2207 * Following are all routines needed for COM to act as console 2208 */ 2209 struct consdev comcons = { 2210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2211 NODEV, CN_NORMAL 2212 }; 2213 2214 2215 int 2216 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2217 tcflag_t cflag) 2218 { 2219 int res; 2220 2221 comconsregs = *regsp; 2222 2223 res = cominit(&comconsregs, rate, frequency, type, cflag); 2224 if (res) 2225 return (res); 2226 2227 cn_tab = &comcons; 2228 cn_init_magic(&com_cnm_state); 2229 cn_set_magic("\047\001"); /* default magic is BREAK */ 2230 2231 comconsrate = rate; 2232 comconscflag = cflag; 2233 2234 return (0); 2235 } 2236 2237 int 2238 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2239 int type, tcflag_t cflag) 2240 { 2241 struct com_regs regs; 2242 2243 memset(®s, 0, sizeof regs); 2244 regs.cr_iot = iot; 2245 regs.cr_iobase = iobase; 2246 regs.cr_nports = COM_NPORTS; 2247 #ifdef COM_REGMAP 2248 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2249 #endif 2250 2251 return comcnattach1(®s, rate, frequency, type, cflag); 2252 } 2253 2254 int 2255 comcngetc(dev_t dev) 2256 { 2257 2258 return (com_common_getc(dev, &comconsregs)); 2259 } 2260 2261 /* 2262 * Console kernel output character routine. 2263 */ 2264 void 2265 comcnputc(dev_t dev, int c) 2266 { 2267 2268 com_common_putc(dev, &comconsregs, c); 2269 } 2270 2271 void 2272 comcnpollc(dev_t dev, int on) 2273 { 2274 2275 } 2276 2277 #ifdef KGDB 2278 int 2279 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2280 tcflag_t cflag) 2281 { 2282 int res; 2283 2284 if (regsp->cr_iot == comconsregs.cr_iot && 2285 regsp->cr_iobase == comconsregs.cr_iobase) { 2286 #if !defined(DDB) 2287 return (EBUSY); /* cannot share with console */ 2288 #else 2289 comkgdbregs = *regsp; 2290 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2291 #endif 2292 } else { 2293 comkgdbregs = *regsp; 2294 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2295 if (res) 2296 return (res); 2297 2298 /* 2299 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2300 * expects this to be initialized 2301 */ 2302 cn_init_magic(&com_cnm_state); 2303 cn_set_magic("\047\001"); 2304 } 2305 2306 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2307 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2308 2309 return (0); 2310 } 2311 2312 int 2313 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2314 int frequency, int type, tcflag_t cflag) 2315 { 2316 struct com_regs regs; 2317 2318 regs.cr_iot = iot; 2319 regs.cr_nports = COM_NPORTS; 2320 regs.cr_iobase = iobase; 2321 #ifdef COM_REGMAP 2322 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2323 #endif 2324 2325 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2326 } 2327 2328 /* ARGSUSED */ 2329 int 2330 com_kgdb_getc(void *arg) 2331 { 2332 2333 return (com_common_getc(NODEV, &comkgdbregs)); 2334 } 2335 2336 /* ARGSUSED */ 2337 void 2338 com_kgdb_putc(void *arg, int c) 2339 { 2340 2341 com_common_putc(NODEV, &comkgdbregs, c); 2342 } 2343 #endif /* KGDB */ 2344 2345 /* helper function to identify the com ports used by 2346 console or KGDB (and not yet autoconf attached) */ 2347 int 2348 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2349 { 2350 bus_space_handle_t help; 2351 2352 if (!comconsattached && 2353 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2354 help = comconsregs.cr_ioh; 2355 #ifdef KGDB 2356 else if (!com_kgdb_attached && 2357 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2358 help = comkgdbregs.cr_ioh; 2359 #endif 2360 else 2361 return (0); 2362 2363 if (ioh) 2364 *ioh = help; 2365 return (1); 2366 } 2367 2368 /* 2369 * this routine exists to serve as a shutdown hook for systems that 2370 * have firmware which doesn't interact properly with a com device in 2371 * FIFO mode. 2372 */ 2373 bool 2374 com_cleanup(device_t self, int how) 2375 { 2376 struct com_softc *sc = device_private(self); 2377 2378 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2379 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2380 2381 return true; 2382 } 2383 2384 bool 2385 com_suspend(device_t self PMF_FN_ARGS) 2386 { 2387 struct com_softc *sc = device_private(self); 2388 2389 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2390 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2391 2392 return true; 2393 } 2394 2395 bool 2396 com_resume(device_t self PMF_FN_ARGS) 2397 { 2398 struct com_softc *sc = device_private(self); 2399 2400 mutex_spin_enter(&sc->sc_lock); 2401 com_loadchannelregs(sc); 2402 mutex_spin_exit(&sc->sc_lock); 2403 2404 return true; 2405 } 2406
Indexes created Sat Oct 25 01:09:55 GMT 2025